From 6f172696365d5ac2887c7c08f3f0c5e561121c87 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 2 Jun 2010 14:57:09 -0700 Subject: copied over from other repo. Beginnings of a skeleton fpga image for USRP1-Plus --- usrp2/top/safe_u1plus/.gitignore | 1 + usrp2/top/safe_u1plus/Makefile | 245 +++++++++++++++++++ usrp2/top/safe_u1plus/safe_u1plus.v | 362 ++++++++++++++++++++++++++++ usrp2/top/safe_u1plus/u1plus.ucf | 168 +++++++++++++ usrp2/top/u1_core/.gitignore | 44 ++++ usrp2/top/u1_core/u1_core.v | 455 ++++++++++++++++++++++++++++++++++++ usrp2/top/u1plus/.gitignore | 1 + usrp2/top/u1plus/Makefile | 232 ++++++++++++++++++ usrp2/top/u1plus/timing.ucf | 2 + usrp2/top/u1plus/u1plus.ucf | 203 ++++++++++++++++ usrp2/top/u1plus/u1plus.v | 141 +++++++++++ 11 files changed, 1854 insertions(+) create mode 100644 usrp2/top/safe_u1plus/.gitignore create mode 100644 usrp2/top/safe_u1plus/Makefile create mode 100644 usrp2/top/safe_u1plus/safe_u1plus.v create mode 100644 usrp2/top/safe_u1plus/u1plus.ucf create mode 100644 usrp2/top/u1_core/.gitignore create mode 100755 usrp2/top/u1_core/u1_core.v create mode 100644 usrp2/top/u1plus/.gitignore create mode 100644 usrp2/top/u1plus/Makefile create mode 100644 usrp2/top/u1plus/timing.ucf create mode 100644 usrp2/top/u1plus/u1plus.ucf create mode 100644 usrp2/top/u1plus/u1plus.v diff --git a/usrp2/top/safe_u1plus/.gitignore b/usrp2/top/safe_u1plus/.gitignore new file mode 100644 index 000000000..1b2211df0 --- /dev/null +++ b/usrp2/top/safe_u1plus/.gitignore @@ -0,0 +1 @@ +build* diff --git a/usrp2/top/safe_u1plus/Makefile b/usrp2/top/safe_u1plus/Makefile new file mode 100644 index 000000000..2f000df0f --- /dev/null +++ b/usrp2/top/safe_u1plus/Makefile @@ -0,0 +1,245 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := safe_u1plus +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3s1400a \ +package ft256 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +control_lib/CRC16_D16.v \ +control_lib/atr_controller.v \ +control_lib/bin2gray.v \ +control_lib/dcache.v \ +control_lib/decoder_3_8.v \ +control_lib/dpram32.v \ +control_lib/gray2bin.v \ +control_lib/gray_send.v \ +control_lib/icache.v \ +control_lib/mux4.v \ +control_lib/mux8.v \ +control_lib/nsgpio.v \ +control_lib/ram_2port.v \ +control_lib/ram_harv_cache.v \ +control_lib/ram_loader.v \ +control_lib/setting_reg.v \ +control_lib/settings_bus.v \ +control_lib/srl.v \ +control_lib/system_control.v \ +control_lib/wb_1master.v \ +control_lib/wb_readback_mux.v \ +control_lib/simple_uart.v \ +control_lib/simple_uart_tx.v \ +control_lib/simple_uart_rx.v \ +control_lib/oneshot_2clk.v \ +control_lib/sd_spi.v \ +control_lib/sd_spi_wb.v \ +control_lib/wb_bridge_16_32.v \ +control_lib/reset_sync.v \ +simple_gemac/simple_gemac_wrapper.v \ +simple_gemac/simple_gemac.v \ +simple_gemac/simple_gemac_wb.v \ +simple_gemac/simple_gemac_tx.v \ +simple_gemac/simple_gemac_rx.v \ +simple_gemac/crc.v \ +simple_gemac/delay_line.v \ +simple_gemac/flow_ctrl_tx.v \ +simple_gemac/flow_ctrl_rx.v \ +simple_gemac/address_filter.v \ +simple_gemac/ll8_to_txmac.v \ +simple_gemac/rxmac_to_ll8.v \ +simple_gemac/miim/eth_miim.v \ +simple_gemac/miim/eth_clockgen.v \ +simple_gemac/miim/eth_outputcontrol.v \ +simple_gemac/miim/eth_shiftreg.v \ +control_lib/newfifo/buffer_int.v \ +control_lib/newfifo/buffer_pool.v \ +control_lib/newfifo/fifo_2clock.v \ +control_lib/newfifo/fifo_2clock_cascade.v \ +control_lib/newfifo/ll8_shortfifo.v \ +control_lib/newfifo/ll8_to_fifo36.v \ +control_lib/newfifo/fifo_short.v \ +control_lib/newfifo/fifo_long.v \ +control_lib/newfifo/fifo_cascade.v \ +control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/longfifo.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ +coregen/fifo_xlnx_2Kx36_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.xco \ +coregen/fifo_xlnx_512x36_2clk.v \ +coregen/fifo_xlnx_512x36_2clk.xco \ +coregen/fifo_xlnx_64x36_2clk.v \ +coregen/fifo_xlnx_64x36_2clk.xco \ +extram/wb_zbt16_b.v \ +opencores/8b10b/decode_8b10b.v \ +opencores/8b10b/encode_8b10b.v \ +opencores/aemb/rtl/verilog/aeMB_bpcu.v \ +opencores/aemb/rtl/verilog/aeMB_core_BE.v \ +opencores/aemb/rtl/verilog/aeMB_ctrl.v \ +opencores/aemb/rtl/verilog/aeMB_edk32.v \ +opencores/aemb/rtl/verilog/aeMB_ibuf.v \ +opencores/aemb/rtl/verilog/aeMB_regf.v \ +opencores/aemb/rtl/verilog/aeMB_xecu.v \ +opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_defines.v \ +opencores/i2c/rtl/verilog/i2c_master_top.v \ +opencores/i2c/rtl/verilog/timescale.v \ +opencores/simple_pic/rtl/simple_pic.v \ +opencores/spi/rtl/verilog/spi_clgen.v \ +opencores/spi/rtl/verilog/spi_defines.v \ +opencores/spi/rtl/verilog/spi_shift.v \ +opencores/spi/rtl/verilog/spi_top.v \ +opencores/spi/rtl/verilog/timescale.v \ +sdr_lib/acc.v \ +sdr_lib/add2.v \ +sdr_lib/add2_and_round.v \ +sdr_lib/add2_and_round_reg.v \ +sdr_lib/add2_reg.v \ +sdr_lib/cic_dec_shifter.v \ +sdr_lib/cic_decim.v \ +sdr_lib/cic_int_shifter.v \ +sdr_lib/cic_interp.v \ +sdr_lib/cic_strober.v \ +sdr_lib/clip.v \ +sdr_lib/clip_reg.v \ +sdr_lib/cordic.v \ +sdr_lib/cordic_z24.v \ +sdr_lib/cordic_stage.v \ +sdr_lib/dsp_core_rx.v \ +sdr_lib/dsp_core_tx.v \ +sdr_lib/hb_dec.v \ +sdr_lib/hb_interp.v \ +sdr_lib/round.v \ +sdr_lib/round_reg.v \ +sdr_lib/rx_control.v \ +sdr_lib/rx_dcoffset.v \ +sdr_lib/sign_extend.v \ +sdr_lib/small_hb_dec.v \ +sdr_lib/small_hb_int.v \ +sdr_lib/tx_control.v \ +serdes/serdes.v \ +serdes/serdes_fc_rx.v \ +serdes/serdes_fc_tx.v \ +serdes/serdes_rx.v \ +serdes/serdes_tx.v \ +timing/time_receiver.v \ +timing/time_sender.v \ +timing/time_sync.v \ +timing/timer.v \ +top/u2_core/u2_core.v \ +top/safe_u2plus/u1plus.ucf \ +top/safe_u2plus/safe_u1plus.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +clean: + rm -rf $(BUILD_DIR) + + diff --git a/usrp2/top/safe_u1plus/safe_u1plus.v b/usrp2/top/safe_u1plus/safe_u1plus.v new file mode 100644 index 000000000..38b276000 --- /dev/null +++ b/usrp2/top/safe_u1plus/safe_u1plus.v @@ -0,0 +1,362 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module safe_u2plus + ( + input CLK_FPGA_P, input CLK_FPGA_N, // Diff + + // ADC + //input ADC_clkout_p, //input ADC_clkout_n, + //input ADCA_12_p, //input ADCA_12_n, + //input ADCA_10_p, //input ADCA_10_n, + //input ADCA_8_p, //input ADCA_8_n, + //input ADCA_6_p, //input ADCA_6_n, + //input ADCA_4_p, //input ADCA_4_n, + //input ADCA_2_p, //input ADCA_2_n, + //input ADCA_0_p, //input ADCA_0_n, + //input ADCB_12_p, //input ADCB_12_n, + //input ADCB_10_p, //input ADCB_10_n, + //input ADCB_8_p, //input ADCB_8_n, + //input ADCB_6_p, //input ADCB_6_n, + //input ADCB_4_p, //input ADCB_4_n, + //input ADCB_2_p, //input ADCB_2_n, + //input ADCB_0_p, //input ADCB_0_n, + + // DAC + //output [15:0] DACA, + //output [15:0] DACB, + //input DAC_LOCK, // unused for now + + // DB IO Pins + //inout [15:0] io_tx, + //inout [15:0] io_rx, + + // Misc, debug + output [5:1] leds, // LED4 is shared w/INIT_B + //input FPGA_RESET, + //output [1:0] debug_clk, + //output [31:0] debug, + //output [3:1] TXD, //input [3:1] RXD, // UARTs + ////input [3:0] dipsw, // Forgot DIP Switches... + + // Clock Gen Control + //output [1:0] clk_en, + //output [1:0] clk_sel, + //input CLK_FUNC, // FIXME is an //input to control the 9510 + //input CLK_STATUS, + + //inout SCL, //inout SDA, // I2C + + // PPS + //input PPS_IN, //input PPS2_IN, + + // SPI + //output SEN_CLK, //output SCLK_CLK, //output MOSI_CLK, //input MISO_CLK, + //output SEN_DAC, //output SCLK_DAC, //output MOSI_DAC, //input MISO_DAC, + //output SEN_ADC, //output SCLK_ADC, //output MOSI_ADC, + //output SEN_TX_DB, //output SCLK_TX_DB, //output MOSI_TX_DB, //input MISO_TX_DB, + //output SEN_TX_DAC, //output SCLK_TX_DAC, //output MOSI_TX_DAC, + //output SEN_TX_ADC, //output SCLK_TX_ADC, //output MOSI_TX_ADC, //input MISO_TX_ADC, + //output SEN_RX_DB, //output SCLK_RX_DB, //output MOSI_RX_DB, //input MISO_RX_DB, + //output SEN_RX_DAC, //output SCLK_RX_DAC, //output MOSI_RX_DAC, + //output SEN_RX_ADC, //output SCLK_RX_ADC, //output MOSI_RX_ADC, //input MISO_RX_ADC, + + // GigE PHY + //input CLK_TO_MAC, + + //output reg [7:0] GMII_TXD, + //output reg GMII_TX_EN, + //output reg GMII_TX_ER, + //output GMII_GTX_CLK, + //input GMII_TX_CLK, // 100mbps clk + + //input GMII_RX_CLK, + //input [7:0] GMII_RXD, + //input GMII_RX_DV, + //input GMII_RX_ER, + //input GMII_COL, + //input GMII_CRS, + + //input PHY_INTn, // open drain + //inout MDIO, + //output MDC, + //output PHY_RESETn, + output ETH_LED + + //input POR, + + // Expansion + //input exp_time_in_p, //input exp_time_in_n, // Diff + //output exp_time_out_p, //output exp_time_out_n, // Diff + //input exp_user_in_p, //input exp_user_in_n, // Diff + //output exp_user_out_p, //output exp_user_out_n, // Diff + + // SERDES + //output ser_enable, + //output ser_prbsen, + //output ser_loopen, + //output ser_rx_en, + + //output ser_tx_clk, + //output reg [15:0] ser_t, + //output reg ser_tklsb, + //output reg ser_tkmsb, + + //input ser_rx_clk, + //input [15:0] ser_r, + //input ser_rklsb, + //input ser_rkmsb, + + // SRAM + //inout [35:0] RAM_D, + //output [20:0] RAM_A, + //output [3:0] RAM_BWn, + //output RAM_ZZ, + //output RAM_LDn, + //output RAM_OEn, + //output RAM_WEn, + //output RAM_CENn, + //output RAM_CLK, + + // SPI Flash + //output flash_cs, + //output flash_clk, + //output flash_mosi, + //input flash_miso + ); + + // FPGA-specific pins connections + wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + reg [31:0] ctr; + + always @(posedge clk_fpga) + ctr <= ctr + 1; + + assign {leds,ETH_LED} = ~ctr[29:24]; + + +/* + wire exp_time_in; + IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); + defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_time_out; + OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); + defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; + + wire dcm_rst = 0; + + wire [13:0] adc_a, adc_b; + + capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds + (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), + .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p}, + {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), + .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n}, + {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), + .out({adc_a,adc_b})); + + // Handle Clocks + DCM DCM_INST (.CLKFB(dsp_clk), + .CLKIN(clk_fpga), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(), + .CLK180(), + .CLK270(), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 10.000; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // LEDs are active low outputs + wire [4:0] leds_int; + assign leds = ~leds_int; // drive low to turn on leds + + // SPI + wire miso, mosi, sclk; + + assign {SCLK_CLK,MOSI_CLK} = ~SEN_CLK ? {sclk,mosi} : 2'B0; + assign {SCLK_DAC,MOSI_DAC} = ~SEN_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_ADC,MOSI_ADC} = ~SEN_ADC ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_DAC,MOSI_TX_DAC} = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_ADC,MOSI_TX_ADC} = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_DAC,MOSI_RX_DAC} = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_ADC,MOSI_RX_ADC} = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0; + + assign miso = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) | + (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) | + (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC); + + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; + wire [7:0] GMII_TXD_unreg; + wire GMII_GTX_CLK_int; + + always @(posedge GMII_GTX_CLK_int) + begin + GMII_TX_EN <= GMII_TX_EN_unreg; + GMII_TX_ER <= GMII_TX_ER_unreg; + GMII_TXD <= GMII_TXD_unreg; + end + + OFDDRRSE OFDDRRSE_gmii_inst + (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) + .C0(GMII_GTX_CLK_int), // 0 degree clock input + .C1(~GMII_GTX_CLK_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + + wire ser_tklsb_unreg, ser_tkmsb_unreg; + wire [15:0] ser_t_unreg; + wire ser_tx_clk_int; + + always @(posedge ser_tx_clk_int) + begin + ser_tklsb <= ser_tklsb_unreg; + ser_tkmsb <= ser_tkmsb_unreg; + ser_t <= ser_t_unreg; + end + + assign ser_tx_clk = clk_fpga; + + reg [15:0] ser_r_int; + reg ser_rklsb_int, ser_rkmsb_int; + + always @(posedge ser_rx_clk) + begin + ser_r_int <= ser_r; + ser_rklsb_int <= ser_rklsb; + ser_rkmsb_int <= ser_rkmsb; + end + + u2_core u2_core(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .leds (leds_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_time_in), + .exp_pps_out (exp_time_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .adc_a (adc_a[13:0]), + .adc_ovf_a (adc_ovf_a), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b[13:0]), + .adc_ovf_b (adc_ovf_b), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (DACA[15:0]), + .dac_b (DACB[15:0]), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk_int), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D (RAM_D), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (uart_tx_o), + .uart_rx_i (uart_rx_i), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2) + ); +*/ +endmodule // safe_u2plus diff --git a/usrp2/top/safe_u1plus/u1plus.ucf b/usrp2/top/safe_u1plus/u1plus.ucf new file mode 100644 index 000000000..c3b20b76f --- /dev/null +++ b/usrp2/top/safe_u1plus/u1plus.ucf @@ -0,0 +1,168 @@ +NET "TMS" LOC = "B2" ; +NET "TDO" LOC = "B16" ; +NET "TDI" LOC = "B1" ; +NET "TCK" LOC = "A15" ; +NET "GPIF_D07" LOC = "N12" ; +NET "GPIF_D06" LOC = "P13" ; +NET "GPIF_D05" LOC = "P11" ; +NET "GPIF_RDY3" LOC = "N11" ; +NET "GPIF_RDY2" LOC = "T10" ; +NET "GPIF_RDY1" LOC = "T4" ; +NET "GPIF_RDY0" LOC = "R5" ; +NET "cgen_st_status" LOC = "P6" ; +NET "GPIF_CTL3" LOC = "N5" ; +NET "GPIF_CTL2" LOC = "M11" ; +NET "GPIF_CTL1" LOC = "M9" ; +NET "GPIF_CTL0" LOC = "M7" ; +NET "fpga_cfg_prog_b" LOC = "A2" ; +NET "fpga_cfg_done" LOC = "T15" ; +NET "reset_n" LOC = "D5" ; +NET "fpga_cfg_din" LOC = "T14" ; +NET "fpga_cfg_cclk" LOC = "R14" ; +NET "SDA_FPGA" LOC = "T13" ; +NET "SCL_FPGA" LOC = "R13" ; +NET "fpga_cfg_init_b" LOC = "T12" ; +NET "FX2_PA7_FLAGD" LOC = "P12" ; +NET "mystery_bus_2" LOC = "T11" ; +NET "FX2_PA6_PKTEND" LOC = "R11" ; +NET "FX2_PA2_SLOE" LOC = "P10" ; +NET "GPIF_D15" LOC = "P7" ; +NET "GPIF_D14" LOC = "N8" ; +NET "GPIF_D13" LOC = "T5" ; +NET "GPIF_D12" LOC = "T6" ; +NET "GPIF_D11" LOC = "N6" ; +NET "GPIF_D10" LOC = "P5" ; +NET "GPIF_D09" LOC = "R3" ; +NET "GPIF_D08" LOC = "T3" ; +NET "debug_led2" LOC = "R2" ; +NET "cgen_ref_sel" LOC = "T2" ; +NET "debug_led1" LOC = "N4" ; +NET "debug_led0" LOC = "P4" ; +NET "GPIF_D04" LOC = "R9" ; +NET "GPIF_D03" LOC = "T9" ; +NET "GPIF_D02" LOC = "N9" ; +NET "GPIF_D01" LOC = "P9" ; +NET "GPIF_D00" LOC = "P8" ; +NET "IFCLK" LOC = "T8" ; +NET "CLK_FPGA_P" LOC = "R7" ; +NET "CLK_FPGA_N" LOC = "T7" ; +NET "cgen_sync_b" LOC = "H15" ; +NET "FPGA_TXD" LOC = "H16" ; +NET "debug_00" LOC = "K16" ; +NET "debug_01" LOC = "J16" ; +NET "debug_clk0" LOC = "K15" ; +NET "debug_clk1" LOC = "K14" ; +NET "debug_02" LOC = "C16" ; +NET "debug_03" LOC = "C15" ; +NET "debug_04" LOC = "E13" ; +NET "debug_05" LOC = "D14" ; +NET "debug_06" LOC = "D16" ; +NET "debug_07" LOC = "D15" ; +NET "debug_08" LOC = "E14" ; +NET "debug_09" LOC = "F13" ; +NET "debug_10" LOC = "G13" ; +NET "debug_11" LOC = "F14" ; +NET "debug_12" LOC = "E16" ; +NET "debug_13" LOC = "F15" ; +NET "debug_14" LOC = "H13" ; +NET "debug_15" LOC = "G14" ; +NET "debug_16" LOC = "G16" ; +NET "debug_17" LOC = "F16" ; +NET "debug_18" LOC = "J12" ; +NET "debug_19" LOC = "J13" ; +NET "debug_20" LOC = "L14" ; +NET "debug_21" LOC = "L16" ; +NET "debug_22" LOC = "M15" ; +NET "debug_23" LOC = "M16" ; +NET "debug_24" LOC = "L13" ; +NET "debug_25" LOC = "K13" ; +NET "debug_26" LOC = "P16" ; +NET "debug_27" LOC = "N16" ; +NET "debug_28" LOC = "R15" ; +NET "debug_29" LOC = "P15" ; +NET "debug_30" LOC = "N13" ; +NET "debug_31" LOC = "N14" ; +NET "PPS_IN" LOC = "M14" ; +NET "cgen_st_ld" LOC = "M13" ; +NET "cgen_st_refmon" LOC = "J14" ; +NET "FPGA_RXD" LOC = "H12" ; +NET "DA10" LOC = "A8" ; +NET "DA09" LOC = "B8" ; +NET "DA08" LOC = "C8" ; +NET "DA07" LOC = "D8" ; +NET "DA06" LOC = "C9" ; +NET "DA05" LOC = "A9" ; +NET "DA04" LOC = "C10" ; +NET "DA03" LOC = "D9" ; +NET "SCLK_CODEC" LOC = "K3" ; +NET "TXBLANK" LOC = "K1" ; +NET "TXSYNC" LOC = "J2" ; +NET "TX00" LOC = "J1" ; +NET "TX01" LOC = "H3" ; +NET "TX02" LOC = "J3" ; +NET "TX03" LOC = "G2" ; +NET "TX04" LOC = "H1" ; +NET "TX05" LOC = "N3" ; +NET "TX06" LOC = "M4" ; +NET "TX07" LOC = "R1" ; +NET "TX08" LOC = "P2" ; +NET "TX09" LOC = "P1" ; +NET "TX10" LOC = "M1" ; +NET "TX11" LOC = "N1" ; +NET "TX12" LOC = "M3" ; +NET "TX13" LOC = "L4" ; +NET "io_tx_00" LOC = "K4" ; +NET "io_tx_01" LOC = "L3" ; +NET "io_tx_02" LOC = "L2" ; +NET "io_tx_03" LOC = "F1" ; +NET "io_tx_04" LOC = "F3" ; +NET "io_tx_05" LOC = "G3" ; +NET "io_tx_06" LOC = "E3" ; +NET "io_tx_07" LOC = "E2" ; +NET "io_tx_08" LOC = "E4" ; +NET "io_tx_09" LOC = "F4" ; +NET "io_tx_10" LOC = "D1" ; +NET "io_tx_11" LOC = "E1" ; +NET "io_tx_12" LOC = "D4" ; +NET "io_tx_13" LOC = "D3" ; +NET "io_tx_14" LOC = "C2" ; +NET "io_tx_15" LOC = "C1" ; +NET "MISO_AUX" LOC = "J5" ; +NET "MISO_CODEC" LOC = "G4" ; +NET "MISO_TX_DB" LOC = "J4" ; +NET "SEN_TX_DB" LOC = "N2" ; +NET "MOSI_TX_DB" LOC = "L1" ; +NET "SCLK_TX_DB" LOC = "G1" ; +NET "DA02" LOC = "A3" ; +NET "DA01" LOC = "B3" ; +NET "DA00" LOC = "A4" ; +NET "SEN_RX_DB" LOC = "B4" ; +NET "MOSI_RX_DB" LOC = "A5" ; +NET "SCLK_RX_DB" LOC = "C5" ; +NET "io_rx_00" LOC = "D7" ; +NET "io_rx_01" LOC = "C6" ; +NET "io_rx_02" LOC = "A6" ; +NET "io_rx_03" LOC = "B6" ; +NET "io_rx_04" LOC = "E9" ; +NET "io_rx_05" LOC = "A7" ; +NET "io_rx_06" LOC = "C7" ; +NET "io_rx_07" LOC = "B10" ; +NET "io_rx_08" LOC = "A10" ; +NET "io_rx_09" LOC = "C11" ; +NET "io_rx_10" LOC = "A11" ; +NET "io_rx_11" LOC = "D11" ; +NET "io_rx_12" LOC = "B12" ; +NET "io_rx_13" LOC = "A12" ; +NET "io_rx_14" LOC = "A14" ; +NET "io_rx_15" LOC = "A13" ; +NET "SEN_AUX" LOC = "C12" ; +NET "SCLK_AUX" LOC = "D12" ; +NET "reset_codec" LOC = "B14" ; +NET "SEN_CODEC" LOC = "D13" ; +NET "MOSI_CODEC" LOC = "C13" ; +NET "MISO_RX_DB" LOC = "E6" ; +NET "mystery_bus_1" LOC = "C4" ; +NET "mystery_bus_0" LOC = "E7" ; +NET "RXSYNC" LOC = "D10" ; +NET "DA11" LOC = "B15" ; + diff --git a/usrp2/top/u1_core/.gitignore b/usrp2/top/u1_core/.gitignore new file mode 100644 index 000000000..9728395c1 --- /dev/null +++ b/usrp2/top/u1_core/.gitignore @@ -0,0 +1,44 @@ +*~ +/xst +/_ngo +/_xmsgs +/*.stx +/*.tspec +/*.xml +/*.gyd +/*.ngr +/*.tim +/*.err +/*.lso +/*.bld +/*.cmd_log +/*.ise_ISE_Backup +/*.mfd +/*.vm6 +/*.syr +/*.xst +/*.csv +/*.html +/*.jed +/*.pad +/*.ng* +/*.pnx +/*.rpt +/*.prj +/*_html +/*_log +/*.lfp +/*.bit +/*.bin +/*.vcd +/*.unroutes +/*.drc +/*_map.* +/*_guide.* +/*.twr +/*.twx +/a.out +/*.xpi +/*_pad.txt +/*.bgn +/*.par diff --git a/usrp2/top/u1_core/u1_core.v b/usrp2/top/u1_core/u1_core.v new file mode 100755 index 000000000..24a57936e --- /dev/null +++ b/usrp2/top/u1_core/u1_core.v @@ -0,0 +1,455 @@ +// //////////////////////////////////////////////////////////////////////////////// +// Module Name: u2_core +// //////////////////////////////////////////////////////////////////////////////// + +module u1_core + #(parameter RAM_SIZE=16384) + (input sys_clk, input sys_rst, + input wb_clk, input wb_rst, + + output uart_tx_o, input uart_rx_i, output uart_baud_o, + output [2:0] leds, output [31:0] debug, output [1:0] debug_clk, + + input scl_pad_i, output scl_pad_o, output scl_pad_oen_o, + input sda_pad_i, output sda_pad_o, output sda_pad_oen_o, + + input pps, + output reset_codec, + + input gpif_clk, inout [15:0] gpif_d, input [3:0] gpif_ctl, output [3:0] gpif_rdy, + input [2:0] gpif_misc, + + input [11:0] adc, input rxsync, + output [13:0] dac, output txsync, output txblank, + + // Generic SPI + output sclk, + output mosi, + input miso, + output [3:0] sen, + + // GPIO to DBoards + inout [15:0] io_tx, + inout [15:0] io_rx, + + input sim_mode + ); + + wire [7:0] set_addr; + wire [31:0] set_data; + wire set_stb; + + wire ram_loader_done, ram_loader_rst; + + wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; + wire bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int; + + wire [31:0] debug_gpio_0, debug_gpio_1; + wire [31:0] atr_lines; + + wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp; + + wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; + wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; + wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; + + wire serdes_link_up; + wire epoch; + wire [31:0] irq; + + // /////////////////////////////////////////////////////////////////////////////////////////////// + // Wishbone Single Master INTERCON + localparam dw = 32; // Data bus width + localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space + localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. + + wire [dw-1:0] m0_dat_o, m0_dat_i; + wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, + s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, + s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, + sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o; + wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr; + wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel; + wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack; + wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb; + wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc; + wire m0_err, m0_rty; + wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we; + + wb_1master #(.decode_w(6), + .s0_addr(6'b0000_00),.s0_mask(6'b100000), + .s1_addr(6'b1000_00),.s1_mask(6'b110000), + .s2_addr(6'b1100_00),.s2_mask(6'b111111), + .s3_addr(6'b1100_01),.s3_mask(6'b111111), + .s4_addr(6'b1100_10),.s4_mask(6'b111111), + .s5_addr(6'b1100_11),.s5_mask(6'b111111), + .s6_addr(6'b1101_00),.s6_mask(6'b111111), + .s7_addr(6'b1101_01),.s7_mask(6'b111111), + .s8_addr(6'b1101_10),.s8_mask(6'b111111), + .s9_addr(6'b1101_11),.s9_mask(6'b111111), + .sa_addr(6'b1110_00),.sa_mask(6'b111111), + .sb_addr(6'b1110_01),.sb_mask(6'b111111), + .sc_addr(6'b1110_10),.sc_mask(6'b111111), + .sd_addr(6'b1110_11),.sd_mask(6'b111111), + .se_addr(6'b1111_00),.se_mask(6'b111111), + .sf_addr(6'b1111_01),.sf_mask(6'b111111), + .dw(dw),.aw(aw),.sw(sw)) wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_i(0),.sf_ack_i(0),.sf_err_i(0),.sf_rty_i(0) ); + + // /////////////////////////////////////////////////////////////////// + // RAM Loader + + wire [31:0] ram_loader_dat, iwb_dat; + wire [15:0] ram_loader_adr, iwb_adr; + wire [3:0] ram_loader_sel; + wire ram_loader_stb, ram_loader_we, ram_loader_ack; + wire iwb_ack, iwb_stb; + ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) + ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), + // CPLD Interface + .cfg_clk_i(cpld_clk), + .cfg_data_i(cpld_din), + .start_o(cpld_start_int), + .mode_o(cpld_mode_int), + .done_o(cpld_done_int), + .detached_i(cpld_detached), + // Wishbone Interface + .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), + .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), + .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), + .ram_loader_done_o(ram_loader_done)); + + // ///////////////////////////////////////////////////////////////////////// + // Processor + aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) + aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), + // Instruction Wishbone bus to I-RAM + .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), + .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), + // Data Wishbone bus to system bus fabric + .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), + .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), + // Interrupts and exceptions + .sys_int_i(proc_int),.sys_exc_i(bus_error) ); + + assign bus_error = m0_err | m0_rty; + + // ///////////////////////////////////////////////////////////////////////// + // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone + // I-port connects directly to processor and ram loader + + wire flush_icache; + ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) + sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + + .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), + .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), + .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), + .ram_loader_done_i(ram_loader_done), + + .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), + .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), + + .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), + .flush_icache(flush_icache)); + + setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(flush_icache)); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool, slave #1 + wire rd0_ready_i, rd0_ready_o; + wire rd1_ready_i, rd1_ready_o; + wire rd2_ready_i, rd2_ready_o; + wire rd3_ready_i, rd3_ready_o; + wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; + wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + + wire wr0_ready_i, wr0_ready_o; + wire wr1_ready_i, wr1_ready_o; + wire wr2_ready_i, wr2_ready_o; + wire wr3_ready_i, wr3_ready_o; + wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; + wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + + buffer_pool #(.BUF_SIZE(9), .SET_ADDR(64)) buffer_pool + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .status(status),.sys_int_o(buffer_int), + + .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), + .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), + + // Write Interfaces + .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o), + .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o), + .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o), + .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o), + // Read Interfaces + .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o), + .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o), + .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o), + .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o) + ); + + wire [31:0] status_enc; + priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc)); + + // ///////////////////////////////////////////////////////////////////////// + // SPI -- Slave #2 + spi_top shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), + .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), + .ss_pad_o(sen), + .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // I2C -- Slave #3 + i2c_master_top #(.ARST_LVL(1)) + i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_i[31:8] = 24'd0; + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio( {io_tx,io_rx} ) ); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool Status -- Slave #5 + + reg [31:0] cycle_count; + always @(posedge wb_clk) + if(wb_rst) + cycle_count <= 0; + else + cycle_count <= cycle_count + 1; + + wb_readback_mux buff_pool_status + (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), + .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), + + .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), + .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), + .word08(status),.word09({sim_mode,31'b0}),.word10(32'b0), + .word11(32'b0),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count) + ); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #7 + settings_bus settings_bus + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), + .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), + .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data)); + + assign s7_dat_i = 32'd0; + + // Output control lines + setting_reg #(.my_addr(0)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), + .in(set_data),.out(clock_outs),.changed()); + + // ///////////////////////////////////////////////////////////////////////// + // LEDS + // register 8 determines whether leds are controlled by SW or not + // 1 = controlled by HW, 0 = by SW + // In Rev3 there are only 6 leds, and the highest one is on the ETH connector + + wire [7:0] led_hw = 0; + + setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_sw),.changed()); + setting_reg #(.my_addr(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_src),.changed()); + + assign leds = (led_src & led_hw) | (~led_src & led_sw); + + // ///////////////////////////////////////////////////////////////////////// + // Interrupt Controller, Slave #8 + + assign irq= {{8'b0}, + {8'b0}, + {6'b0, uart_tx_int, uart_rx_int}, + {pps_int,overrun,underrun,1'b0,i2c_int,spi_int,timer_int,buffer_int}}; + + pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]), + .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), + .irq(irq) ); + + // ///////////////////////////////////////////////////////////////////////// + // Master Timer, Slave #9 + + wire [31:0] master_time; + timer timer + (.wb_clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), + .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), + .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); + + // ///////////////////////////////////////////////////////////////////////// + // UART, Slave #10 + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), + .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), + .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), + .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller, Slave #11 + + wire run_rx, run_tx; + reg run_rx_d1; + always @(posedge dsp_clk) + run_rx_d1 <= run_rx; + + atr_controller atr_controller + (.clk_i(wb_clk),.rst_i(wb_rst), + .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), + .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), + .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); + + // ////////////////////////////////////////////////////////////////////////// + // Time Sync, Slave #12 + + reg pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1; + always @(negedge dsp_clk) pps_negedge <= pps; + always @(posedge dsp_clk) pps_posedge <= pps; + always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge; + always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge; + + wire pps_o; + time_sync time_sync + (.wb_clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(sc_cyc),.stb_i(sc_stb),.adr_i(sc_adr[4:2]), + .we_i(sc_we),.dat_i(sc_dat_o),.dat_o(sc_dat_i),.ack_o(sc_ack), + .sys_clk_i(dsp_clk),.master_time_o(master_time), + .pps_posedge(pps_posedge),.pps_negedge(pps_negedge), + .exp_pps_in(),.exp_pps_out(), + .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) ); + + // ///////////////////////////////////////////////////////////////////////// + // DSP + wire [31:0] sample_rx, sample_tx; + wire strobe_rx, strobe_tx; + + rx_control #(.FIFOSIZE(10)) rx_control + (.clk(dsp_clk), .rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .master_time(master_time),.overrun(overrun), + .wr_dat_o(wr1_dat), .wr_flags_o(wr1_flags), .wr_ready_o(wr1_ready_i), .wr_ready_i(wr1_ready_o), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty), + .debug_rx(debug_rx) ); + + dsp_core_rx dsp_core_rx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + tx_control #(.FIFOSIZE(10)) tx_control + (.clk(dsp_clk), .rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .master_time(master_time),.underrun(underrun), + .rd_dat_i(rd1_dat), .rd_flags_i(rd1_flags), .rd_ready_i(rd1_ready_o), .rd_ready_o(rd1_ready_i), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty), + .debug(debug_txc) ); + + dsp_core_tx dsp_core_tx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .dac_a(dac_a),.dac_b(dac_b), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_tx_dsp) ); + + assign dsp_rst = wb_rst; + + // ///////////////////////////////////////////////////////////////////////////////////////// + // CODEC Interface + + assign txblank = 0; + + always @(posedge dsp_clk) + if(tx_strobe) + begin + dac <= dac_a; + txsync <= 0; + end + else + begin + dac <= dac_b; + txsync <= 1; + end + + always @(posedge dsp_clk) + if(rxsync) + begin + adc_a_hold <= adc; + rx_strobe <= 0; + end + else + begin + adc_a <= adc_a_hold; + adc_b <= adc; + rx_strobe <= 1; + end + + // ///////////////////////////////////////////////////////////////////////////////////////// + // Debug Pins + + assign debug_clk[0] = 0; + assign debug_clk[1] = 0; + assign debug = 0; + + +endmodule // u1_core diff --git a/usrp2/top/u1plus/.gitignore b/usrp2/top/u1plus/.gitignore new file mode 100644 index 000000000..1b2211df0 --- /dev/null +++ b/usrp2/top/u1plus/.gitignore @@ -0,0 +1 @@ +build* diff --git a/usrp2/top/u1plus/Makefile b/usrp2/top/u1plus/Makefile new file mode 100644 index 000000000..8a7c7856d --- /dev/null +++ b/usrp2/top/u1plus/Makefile @@ -0,0 +1,232 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := u1plus +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan3A" \ +device XC3S1400A \ +package ft256 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +control_lib/CRC16_D16.v \ +control_lib/atr_controller.v \ +control_lib/bin2gray.v \ +control_lib/dcache.v \ +control_lib/decoder_3_8.v \ +control_lib/dpram32.v \ +control_lib/gray2bin.v \ +control_lib/gray_send.v \ +control_lib/icache.v \ +control_lib/mux4.v \ +control_lib/mux8.v \ +control_lib/nsgpio.v \ +control_lib/ram_2port.v \ +control_lib/ram_harv_cache.v \ +control_lib/ram_loader.v \ +control_lib/setting_reg.v \ +control_lib/settings_bus.v \ +control_lib/srl.v \ +control_lib/system_control.v \ +control_lib/wb_1master.v \ +control_lib/wb_readback_mux.v \ +control_lib/simple_uart.v \ +control_lib/simple_uart_tx.v \ +control_lib/simple_uart_rx.v \ +control_lib/oneshot_2clk.v \ +control_lib/sd_spi.v \ +control_lib/sd_spi_wb.v \ +control_lib/wb_bridge_16_32.v \ +control_lib/reset_sync.v \ +control_lib/newfifo/buffer_int.v \ +control_lib/newfifo/buffer_pool.v \ +control_lib/newfifo/fifo_2clock.v \ +control_lib/newfifo/fifo_2clock_cascade.v \ +control_lib/newfifo/ll8_shortfifo.v \ +control_lib/newfifo/ll8_to_fifo36.v \ +control_lib/newfifo/fifo_short.v \ +control_lib/newfifo/fifo_long.v \ +control_lib/newfifo/fifo_cascade.v \ +control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/longfifo.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ +control_lib/priority_enc.v \ +control_lib/pic.v \ +coregen/fifo_xlnx_2Kx36_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.xco \ +coregen/fifo_xlnx_512x36_2clk.v \ +coregen/fifo_xlnx_512x36_2clk.xco \ +coregen/fifo_xlnx_64x36_2clk.v \ +coregen/fifo_xlnx_64x36_2clk.xco \ +extram/wb_zbt16_b.v \ +opencores/8b10b/decode_8b10b.v \ +opencores/8b10b/encode_8b10b.v \ +opencores/aemb/rtl/verilog/aeMB_bpcu.v \ +opencores/aemb/rtl/verilog/aeMB_core_BE.v \ +opencores/aemb/rtl/verilog/aeMB_ctrl.v \ +opencores/aemb/rtl/verilog/aeMB_edk32.v \ +opencores/aemb/rtl/verilog/aeMB_ibuf.v \ +opencores/aemb/rtl/verilog/aeMB_regf.v \ +opencores/aemb/rtl/verilog/aeMB_xecu.v \ +opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_defines.v \ +opencores/i2c/rtl/verilog/i2c_master_top.v \ +opencores/i2c/rtl/verilog/timescale.v \ +opencores/simple_pic/rtl/simple_pic.v \ +opencores/spi/rtl/verilog/spi_clgen.v \ +opencores/spi/rtl/verilog/spi_defines.v \ +opencores/spi/rtl/verilog/spi_shift.v \ +opencores/spi/rtl/verilog/spi_top.v \ +opencores/spi/rtl/verilog/timescale.v \ +sdr_lib/acc.v \ +sdr_lib/add2.v \ +sdr_lib/add2_and_round.v \ +sdr_lib/add2_and_round_reg.v \ +sdr_lib/add2_reg.v \ +sdr_lib/cic_dec_shifter.v \ +sdr_lib/cic_decim.v \ +sdr_lib/cic_int_shifter.v \ +sdr_lib/cic_interp.v \ +sdr_lib/cic_strober.v \ +sdr_lib/clip.v \ +sdr_lib/clip_reg.v \ +sdr_lib/cordic.v \ +sdr_lib/cordic_z24.v \ +sdr_lib/cordic_stage.v \ +sdr_lib/dsp_core_rx.v \ +sdr_lib/dsp_core_tx.v \ +sdr_lib/hb_dec.v \ +sdr_lib/hb_interp.v \ +sdr_lib/round.v \ +sdr_lib/round_reg.v \ +sdr_lib/rx_control.v \ +sdr_lib/rx_dcoffset.v \ +sdr_lib/sign_extend.v \ +sdr_lib/small_hb_dec.v \ +sdr_lib/small_hb_int.v \ +sdr_lib/tx_control.v \ +serdes/serdes.v \ +serdes/serdes_fc_rx.v \ +serdes/serdes_fc_tx.v \ +serdes/serdes_rx.v \ +serdes/serdes_tx.v \ +timing/time_receiver.v \ +timing/time_sender.v \ +timing/time_sync.v \ +timing/timer.v \ +top/u1_core/u1_core.v \ +top/u1plus/u1plus.ucf \ +top/u1plus/timing.ucf \ +top/u1plus/u1plus.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +clean: + rm -rf $(BUILD_DIR) + + diff --git a/usrp2/top/u1plus/timing.ucf b/usrp2/top/u1plus/timing.ucf new file mode 100644 index 000000000..ca5ebf8e3 --- /dev/null +++ b/usrp2/top/u1plus/timing.ucf @@ -0,0 +1,2 @@ +NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; +TIMESPEC "TS_CLK_FPGA_P" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; diff --git a/usrp2/top/u1plus/u1plus.ucf b/usrp2/top/u1plus/u1plus.ucf new file mode 100644 index 000000000..8a22d0966 --- /dev/null +++ b/usrp2/top/u1plus/u1plus.ucf @@ -0,0 +1,203 @@ +## Main Clock +NET "CLK_FPGA_P" LOC = "R7" ; +NET "CLK_FPGA_N" LOC = "T7" ; + +## UART +NET "FPGA_TXD" LOC = "H16" ; +NET "FPGA_RXD" LOC = "H12" ; + +## I2C +NET "SDA_FPGA" LOC = "T13" ; +NET "SCL_FPGA" LOC = "R13" ; + +## CGEN +NET "cgen_st_ld" LOC = "M13" ; +NET "cgen_st_refmon" LOC = "J14" ; +NET "cgen_st_status" LOC = "P6" ; +NET "cgen_ref_sel" LOC = "T2" ; +NET "cgen_sync_b" LOC = "H15" ; + +## FPGA Config +NET "fpga_cfg_din" LOC = "T14" ; +NET "fpga_cfg_cclk" LOC = "R14" ; +NET "fpga_cfg_init_b" LOC = "T12" ; + +## MISC +NET "mystery_bus<2>" LOC = "T11" ; +NET "mystery_bus<1>" LOC = "C4" ; +NET "mystery_bus<0>" LOC = "E7" ; +NET "reset_n" LOC = "D5" ; +NET "PPS_IN" LOC = "M14" ; +NET "reset_codec" LOC = "B14" ; + +## GPIF +NET "GPIF_D<15>" LOC = "P7" ; +NET "GPIF_D<14>" LOC = "N8" ; +NET "GPIF_D<13>" LOC = "T5" ; +NET "GPIF_D<12>" LOC = "T6" ; +NET "GPIF_D<11>" LOC = "N6" ; +NET "GPIF_D<10>" LOC = "P5" ; +NET "GPIF_D<9>" LOC = "R3" ; +NET "GPIF_D<8>" LOC = "T3" ; +NET "GPIF_D<7>" LOC = "N12" ; +NET "GPIF_D<6>" LOC = "P13" ; +NET "GPIF_D<5>" LOC = "P11" ; +NET "GPIF_D<4>" LOC = "R9" ; +NET "GPIF_D<3>" LOC = "T9" ; +NET "GPIF_D<2>" LOC = "N9" ; +NET "GPIF_D<1>" LOC = "P9" ; +NET "GPIF_D<0>" LOC = "P8" ; + +NET "GPIF_CTL<3>" LOC = "N5" ; +NET "GPIF_CTL<2>" LOC = "M11" ; +NET "GPIF_CTL<1>" LOC = "M9" ; +NET "GPIF_CTL<0>" LOC = "M7" ; + +NET "GPIF_RDY<3>" LOC = "N11" ; +NET "GPIF_RDY<2>" LOC = "T10" ; +NET "GPIF_RDY<1>" LOC = "T4" ; +NET "GPIF_RDY<0>" LOC = "R5" ; + +NET "FX2_PA7_FLAGD" LOC = "P12" ; +NET "FX2_PA6_PKTEND" LOC = "R11" ; +NET "FX2_PA2_SLOE" LOC = "P10" ; + +NET "IFCLK" LOC = "T8" ; + +## LEDs +NET "debug_led<2>" LOC = "R2" ; +NET "debug_led<1>" LOC = "N4" ; +NET "debug_led<0>" LOC = "P4" ; + +## Debug bus +NET "debug_clk<0>" LOC = "K15" ; +NET "debug_clk<1>" LOC = "K14" ; +NET "debug<0>" LOC = "K16" ; +NET "debug<1>" LOC = "J16" ; +NET "debug<2>" LOC = "C16" ; +NET "debug<3>" LOC = "C15" ; +NET "debug<4>" LOC = "E13" ; +NET "debug<5>" LOC = "D14" ; +NET "debug<6>" LOC = "D16" ; +NET "debug<7>" LOC = "D15" ; +NET "debug<8>" LOC = "E14" ; +NET "debug<9>" LOC = "F13" ; +NET "debug<10>" LOC = "G13" ; +NET "debug<11>" LOC = "F14" ; +NET "debug<12>" LOC = "E16" ; +NET "debug<13>" LOC = "F15" ; +NET "debug<14>" LOC = "H13" ; +NET "debug<15>" LOC = "G14" ; +NET "debug<16>" LOC = "G16" ; +NET "debug<17>" LOC = "F16" ; +NET "debug<18>" LOC = "J12" ; +NET "debug<19>" LOC = "J13" ; +NET "debug<20>" LOC = "L14" ; +NET "debug<21>" LOC = "L16" ; +NET "debug<22>" LOC = "M15" ; +NET "debug<23>" LOC = "M16" ; +NET "debug<24>" LOC = "L13" ; +NET "debug<25>" LOC = "K13" ; +NET "debug<26>" LOC = "P16" ; +NET "debug<27>" LOC = "N16" ; +NET "debug<28>" LOC = "R15" ; +NET "debug<29>" LOC = "P15" ; +NET "debug<30>" LOC = "N13" ; +NET "debug<31>" LOC = "N14" ; + +## ADC +NET "adc<11>" LOC = "B15" ; +NET "adc<10>" LOC = "A8" ; +NET "adc<9>" LOC = "B8" ; +NET "adc<8>" LOC = "C8" ; +NET "adc<7>" LOC = "D8" ; +NET "adc<6>" LOC = "C9" ; +NET "adc<5>" LOC = "A9" ; +NET "adc<4>" LOC = "C10" ; +NET "adc<3>" LOC = "D9" ; +NET "adc<2>" LOC = "A3" ; +NET "adc<1>" LOC = "B3" ; +NET "adc<0>" LOC = "A4" ; +NET "RXSYNC" LOC = "D10" ; + +## DAC +NET "TXBLANK" LOC = "K1" ; +NET "TXSYNC" LOC = "J2" ; +NET "dac<0>" LOC = "J1" ; +NET "dac<1>" LOC = "H3" ; +NET "dac<2>" LOC = "J3" ; +NET "dac<3>" LOC = "G2" ; +NET "dac<4>" LOC = "H1" ; +NET "dac<5>" LOC = "N3" ; +NET "dac<6>" LOC = "M4" ; +NET "dac<7>" LOC = "R1" ; +NET "dac<8>" LOC = "P2" ; +NET "dac<9>" LOC = "P1" ; +NET "dac<10>" LOC = "M1" ; +NET "dac<11>" LOC = "N1" ; +NET "dac<12>" LOC = "M3" ; +NET "dac<13>" LOC = "L4" ; + +## TX DB +NET "io_tx<0>" LOC = "K4" ; +NET "io_tx<1>" LOC = "L3" ; +NET "io_tx<2>" LOC = "L2" ; +NET "io_tx<3>" LOC = "F1" ; +NET "io_tx<4>" LOC = "F3" ; +NET "io_tx<5>" LOC = "G3" ; +NET "io_tx<6>" LOC = "E3" ; +NET "io_tx<7>" LOC = "E2" ; +NET "io_tx<8>" LOC = "E4" ; +NET "io_tx<9>" LOC = "F4" ; +NET "io_tx<10>" LOC = "D1" ; +NET "io_tx<11>" LOC = "E1" ; +NET "io_tx<12>" LOC = "D4" ; +NET "io_tx<13>" LOC = "D3" ; +NET "io_tx<14>" LOC = "C2" ; +NET "io_tx<15>" LOC = "C1" ; + +## RX DB +NET "io_rx<0>" LOC = "D7" ; +NET "io_rx<1>" LOC = "C6" ; +NET "io_rx<2>" LOC = "A6" ; +NET "io_rx<3>" LOC = "B6" ; +NET "io_rx<4>" LOC = "E9" ; +NET "io_rx<5>" LOC = "A7" ; +NET "io_rx<6>" LOC = "C7" ; +NET "io_rx<7>" LOC = "B10" ; +NET "io_rx<8>" LOC = "A10" ; +NET "io_rx<9>" LOC = "C11" ; +NET "io_rx<10>" LOC = "A11" ; +NET "io_rx<11>" LOC = "D11" ; +NET "io_rx<12>" LOC = "B12" ; +NET "io_rx<13>" LOC = "A12" ; +NET "io_rx<14>" LOC = "A14" ; +NET "io_rx<15>" LOC = "A13" ; + +## SPI +NET "SEN_AUX" LOC = "C12" ; +NET "SCLK_AUX" LOC = "D12" ; +NET "MISO_AUX" LOC = "J5" ; +NET "SCLK_CODEC" LOC = "K3" ; +NET "SEN_CODEC" LOC = "D13" ; +NET "MOSI_CODEC" LOC = "C13" ; +NET "MISO_CODEC" LOC = "G4" ; + +NET "MISO_RX_DB" LOC = "E6" ; +NET "SEN_RX_DB" LOC = "B4" ; +NET "MOSI_RX_DB" LOC = "A5" ; +NET "SCLK_RX_DB" LOC = "C5" ; + +NET "MISO_TX_DB" LOC = "J4" ; +NET "SEN_TX_DB" LOC = "N2" ; +NET "MOSI_TX_DB" LOC = "L1" ; +NET "SCLK_TX_DB" LOC = "G1" ; + +## Dedicated pins +#NET "TMS" LOC = "B2" ; +#NET "TDO" LOC = "B16" ; +#NET "TDI" LOC = "B1" ; +#NET "TCK" LOC = "A15" ; + +##NET "fpga_cfg_prog_b" LOC = "A2" ; +##NET "fpga_cfg_done" LOC = "T15" ; diff --git a/usrp2/top/u1plus/u1plus.v b/usrp2/top/u1plus/u1plus.v new file mode 100644 index 000000000..cb5fbdd36 --- /dev/null +++ b/usrp2/top/u1plus/u1plus.v @@ -0,0 +1,141 @@ + +module u1plus + (input CLK_FPGA_P, input CLK_FPGA_N, // Main Clock + output FPGA_TXD, input FPGA_RXD, // UART + inout SDA_FPGA, inout SCL_FPGA, // I2C + + // CGEN + input cgen_st_ld, + input cgen_st_refmon, + input cgen_st_status, + input cgen_ref_sel, + input cgen_sync_b, + + // FPGA Config + input fpga_cfg_din, + input fpga_cfg_cclk, + input fpga_cfg_init_b, + + // MISC + input [2:0] mystery_bus, + input reset_n, + input PPS_IN, + output reset_codec, + + // GPIF + inout [15:0] GPIF_D, + input [3:0] GPIF_CTL, + output [3:0] GPIF_RDY, + input FX2_PA7_FLAGD, + input FX2_PA6_PKTEND, + input FX2_PA2_SLOE, + input IFCLK, + + output [2:0] debug_led, + + // Debug bus + output [1:0] debug_clk, + output [31:0] debug, + + input [11:0] adc, + input RXSYNC, + + output TXBLANK, + output TXSYNC, + output [13:0] dac, + + // TX DB + inout [15:0] io_tx, + inout [15:0] io_rx, + + // SPI + output SEN_AUX, output SCLK_AUX, input MISO_AUX, + output SEN_CODEC, output SCLK_CODEC, output MOSI_CODEC, input MISO_CODEC, + output SEN_RX_DB, output SCLK_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, + output SEN_TX_DB, output SCLK_TX_DB, output MOSI_TX_DB, input MISO_TX_DB + ); + + wire clk_fpga, sys_clk, wb_clk, dcm_out, clk_div, dcm_locked; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + DCM DCM_INST (.CLKFB(sys_clk), + .CLKIN(clk_fpga), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(), + .CLK180(), + .CLK270(), + .LOCKED(dcm_locked), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 15.625; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG sysclk_BUFG (.I(dcm_out), .O(sys_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + wire mosi, miso, sclk; + assign SCLK_AUX = ~SEN_AUX ? sclk : 2'b00; + assign {SCLK_CODEC,MOSI_CODEC} = ~SEN_CODEC ? {sclk,mosi} : 2'b00; + assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'b00; + assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'b00; + assign miso = (~SEN_CODEC & MISO_CODEC) | (~SEN_AUX & MISO_AUX) | + (~SEN_RX_DB & MISO_RX_DB) |(~SEN_TX_DB & MISO_TX_DB); + + u1_core u1_core + (.sys_clk(sys_clk), .sys_rst(sys_rst), + .wb_clk(wb_clk), .wb_rst(wb_rst), + .uart_tx_o(FPGA_TXD), .uart_rx_i(FPGA_RXD), .uart_baud_o(), + + .leds(debug_led), .debug(debug), .debug_clk(debug_clk), + + .scl_pad_i(scl_pad_i), .scl_pad_o(scl_pad_o), .scl_pad_oen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i), .sda_pad_o(sda_pad_o), .sda_pad_oen_o(sda_pad_oen_o), + + .pps(PPS_IN), + .reset_codec(reset_codec), + + // GPIF + .gpif_clk(IFCLK), .gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_rdy(GPIF_RDY), + .gpif_misc({FX2_PA7_FLAGD, FX2_PA6_PKTEND, FX2_PA2_SLOE}), + + .adc(adc), .rxsync(RXSYNC), + + .txblank(TXBLANK), .txsync(TXSYNC), .dac(dac), + + .io_tx(io_tx), .io_rx(io_rx), + + // SPI + .sclk(sclk), .mosi(mosi), .miso(miso), .sen({SEN_AUX, SEN_CODEC, SEN_RX_DB, SEN_TX_DB}), + .sim_mode(0) + ); + +endmodule // u1plus + + -- cgit v1.2.3 From 020df898dfddcb33c851b469f25dbfa75c91a045 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 2 Jun 2010 15:40:06 -0700 Subject: compiles now --- usrp2/top/safe_u1plus/Makefile | 131 +------------ usrp2/top/safe_u1plus/safe_u1plus.ucf | 170 ++++++++++++++++ usrp2/top/safe_u1plus/safe_u1plus.v | 359 ++-------------------------------- usrp2/top/safe_u1plus/u1plus.ucf | 168 ---------------- 4 files changed, 185 insertions(+), 643 deletions(-) create mode 100644 usrp2/top/safe_u1plus/safe_u1plus.ucf delete mode 100644 usrp2/top/safe_u1plus/u1plus.ucf diff --git a/usrp2/top/safe_u1plus/Makefile b/usrp2/top/safe_u1plus/Makefile index 2f000df0f..33a2a51c7 100644 --- a/usrp2/top/safe_u1plus/Makefile +++ b/usrp2/top/safe_u1plus/Makefile @@ -37,8 +37,8 @@ export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise # Project Properties ################################################## export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3s1400a \ +family "Spartan3A" \ +device XC3S1400A \ package ft256 \ speed -4 \ top_level_module_type "HDL" \ @@ -53,136 +53,13 @@ simulator "ISE Simulator (VHDL/Verilog)" \ ################################################## export SOURCE_ROOT := ../../../ export SOURCES := \ -control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ -control_lib/bin2gray.v \ -control_lib/dcache.v \ -control_lib/decoder_3_8.v \ -control_lib/dpram32.v \ -control_lib/gray2bin.v \ -control_lib/gray_send.v \ -control_lib/icache.v \ -control_lib/mux4.v \ -control_lib/mux8.v \ -control_lib/nsgpio.v \ -control_lib/ram_2port.v \ -control_lib/ram_harv_cache.v \ -control_lib/ram_loader.v \ -control_lib/setting_reg.v \ -control_lib/settings_bus.v \ -control_lib/srl.v \ -control_lib/system_control.v \ -control_lib/wb_1master.v \ -control_lib/wb_readback_mux.v \ -control_lib/simple_uart.v \ -control_lib/simple_uart_tx.v \ -control_lib/simple_uart_rx.v \ -control_lib/oneshot_2clk.v \ -control_lib/sd_spi.v \ -control_lib/sd_spi_wb.v \ -control_lib/wb_bridge_16_32.v \ -control_lib/reset_sync.v \ -simple_gemac/simple_gemac_wrapper.v \ -simple_gemac/simple_gemac.v \ -simple_gemac/simple_gemac_wb.v \ -simple_gemac/simple_gemac_tx.v \ -simple_gemac/simple_gemac_rx.v \ -simple_gemac/crc.v \ -simple_gemac/delay_line.v \ -simple_gemac/flow_ctrl_tx.v \ -simple_gemac/flow_ctrl_rx.v \ -simple_gemac/address_filter.v \ -simple_gemac/ll8_to_txmac.v \ -simple_gemac/rxmac_to_ll8.v \ -simple_gemac/miim/eth_miim.v \ -simple_gemac/miim/eth_clockgen.v \ -simple_gemac/miim/eth_outputcontrol.v \ -simple_gemac/miim/eth_shiftreg.v \ -control_lib/newfifo/buffer_int.v \ -control_lib/newfifo/buffer_pool.v \ -control_lib/newfifo/fifo_2clock.v \ -control_lib/newfifo/fifo_2clock_cascade.v \ -control_lib/newfifo/ll8_shortfifo.v \ -control_lib/newfifo/ll8_to_fifo36.v \ -control_lib/newfifo/fifo_short.v \ -control_lib/newfifo/fifo_long.v \ -control_lib/newfifo/fifo_cascade.v \ -control_lib/newfifo/fifo36_to_ll8.v \ -control_lib/longfifo.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ -coregen/fifo_xlnx_2Kx36_2clk.v \ -coregen/fifo_xlnx_2Kx36_2clk.xco \ -coregen/fifo_xlnx_512x36_2clk.v \ -coregen/fifo_xlnx_512x36_2clk.xco \ -coregen/fifo_xlnx_64x36_2clk.v \ -coregen/fifo_xlnx_64x36_2clk.xco \ -extram/wb_zbt16_b.v \ -opencores/8b10b/decode_8b10b.v \ -opencores/8b10b/encode_8b10b.v \ -opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -opencores/aemb/rtl/verilog/aeMB_core_BE.v \ -opencores/aemb/rtl/verilog/aeMB_ctrl.v \ -opencores/aemb/rtl/verilog/aeMB_edk32.v \ -opencores/aemb/rtl/verilog/aeMB_ibuf.v \ -opencores/aemb/rtl/verilog/aeMB_regf.v \ -opencores/aemb/rtl/verilog/aeMB_xecu.v \ -opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_defines.v \ -opencores/i2c/rtl/verilog/i2c_master_top.v \ -opencores/i2c/rtl/verilog/timescale.v \ -opencores/simple_pic/rtl/simple_pic.v \ -opencores/spi/rtl/verilog/spi_clgen.v \ -opencores/spi/rtl/verilog/spi_defines.v \ -opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ -sdr_lib/acc.v \ -sdr_lib/add2.v \ -sdr_lib/add2_and_round.v \ -sdr_lib/add2_and_round_reg.v \ -sdr_lib/add2_reg.v \ -sdr_lib/cic_dec_shifter.v \ -sdr_lib/cic_decim.v \ -sdr_lib/cic_int_shifter.v \ -sdr_lib/cic_interp.v \ -sdr_lib/cic_strober.v \ -sdr_lib/clip.v \ -sdr_lib/clip_reg.v \ -sdr_lib/cordic.v \ -sdr_lib/cordic_z24.v \ -sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_rx.v \ -sdr_lib/dsp_core_tx.v \ -sdr_lib/hb_dec.v \ -sdr_lib/hb_interp.v \ -sdr_lib/round.v \ -sdr_lib/round_reg.v \ -sdr_lib/rx_control.v \ -sdr_lib/rx_dcoffset.v \ -sdr_lib/sign_extend.v \ -sdr_lib/small_hb_dec.v \ -sdr_lib/small_hb_int.v \ -sdr_lib/tx_control.v \ -serdes/serdes.v \ -serdes/serdes_fc_rx.v \ -serdes/serdes_fc_tx.v \ -serdes/serdes_rx.v \ -serdes/serdes_tx.v \ -timing/time_receiver.v \ -timing/time_sender.v \ -timing/time_sync.v \ -timing/timer.v \ -top/u2_core/u2_core.v \ -top/safe_u2plus/u1plus.ucf \ -top/safe_u2plus/safe_u1plus.v +top/safe_u1plus/safe_u1plus.ucf \ +top/safe_u1plus/safe_u1plus.v ################################################## # Process Properties ################################################## export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ "Pack I/O Registers into IOBs" Yes \ "Optimization Effort" High \ "Optimize Instantiated Primitives" TRUE \ diff --git a/usrp2/top/safe_u1plus/safe_u1plus.ucf b/usrp2/top/safe_u1plus/safe_u1plus.ucf new file mode 100644 index 000000000..1a078a9cc --- /dev/null +++ b/usrp2/top/safe_u1plus/safe_u1plus.ucf @@ -0,0 +1,170 @@ +NET "debug_led<2>" LOC = "R2" ; +NET "debug_led<1>" LOC = "N4" ; +NET "debug_led<0>" LOC = "P4" ; +NET "reset_n" LOC = "D5" ; +NET "CLK_FPGA_P" LOC = "R7" ; +NET "CLK_FPGA_N" LOC = "T7" ; + + +#NET "TMS" LOC = "B2" ; +#NET "TDO" LOC = "B16" ; +#NET "TDI" LOC = "B1" ; +#NET "TCK" LOC = "A15" ; +#NET "GPIF_D07" LOC = "N12" ; +#NET "GPIF_D06" LOC = "P13" ; +#NET "GPIF_D05" LOC = "P11" ; +#NET "GPIF_RDY3" LOC = "N11" ; +#NET "GPIF_RDY2" LOC = "T10" ; +#NET "GPIF_RDY1" LOC = "T4" ; +#NET "GPIF_RDY0" LOC = "R5" ; +#NET "cgen_st_status" LOC = "P6" ; +#NET "GPIF_CTL3" LOC = "N5" ; +#NET "GPIF_CTL2" LOC = "M11" ; +#NET "GPIF_CTL1" LOC = "M9" ; +#NET "GPIF_CTL0" LOC = "M7" ; +#NET "fpga_cfg_prog_b" LOC = "A2" ; +#NET "fpga_cfg_done" LOC = "T15" ; +#NET "fpga_cfg_din" LOC = "T14" ; +#NET "fpga_cfg_cclk" LOC = "R14" ; +#NET "SDA_FPGA" LOC = "T13" ; +#NET "SCL_FPGA" LOC = "R13" ; +#NET "fpga_cfg_init_b" LOC = "T12" ; +#NET "FX2_PA7_FLAGD" LOC = "P12" ; +#NET "mystery_bus_2" LOC = "T11" ; +#NET "FX2_PA6_PKTEND" LOC = "R11" ; +#NET "FX2_PA2_SLOE" LOC = "P10" ; +#NET "GPIF_D15" LOC = "P7" ; +#NET "GPIF_D14" LOC = "N8" ; +#NET "GPIF_D13" LOC = "T5" ; +#NET "GPIF_D12" LOC = "T6" ; +#NET "GPIF_D11" LOC = "N6" ; +#NET "GPIF_D10" LOC = "P5" ; +#NET "GPIF_D09" LOC = "R3" ; +#NET "GPIF_D08" LOC = "T3" ; +#NET "cgen_ref_sel" LOC = "T2" ; +#NET "GPIF_D04" LOC = "R9" ; +#NET "GPIF_D03" LOC = "T9" ; +#NET "GPIF_D02" LOC = "N9" ; +#NET "GPIF_D01" LOC = "P9" ; +#NET "GPIF_D00" LOC = "P8" ; +#NET "IFCLK" LOC = "T8" ; +#NET "cgen_sync_b" LOC = "H15" ; +#NET "FPGA_TXD" LOC = "H16" ; +#NET "debug_00" LOC = "K16" ; +#NET "debug_01" LOC = "J16" ; +#NET "debug_clk0" LOC = "K15" ; +#NET "debug_clk1" LOC = "K14" ; +#NET "debug_02" LOC = "C16" ; +#NET "debug_03" LOC = "C15" ; +#NET "debug_04" LOC = "E13" ; +#NET "debug_05" LOC = "D14" ; +#NET "debug_06" LOC = "D16" ; +#NET "debug_07" LOC = "D15" ; +#NET "debug_08" LOC = "E14" ; +#NET "debug_09" LOC = "F13" ; +#NET "debug_10" LOC = "G13" ; +#NET "debug_11" LOC = "F14" ; +#NET "debug_12" LOC = "E16" ; +#NET "debug_13" LOC = "F15" ; +#NET "debug_14" LOC = "H13" ; +#NET "debug_15" LOC = "G14" ; +#NET "debug_16" LOC = "G16" ; +#NET "debug_17" LOC = "F16" ; +#NET "debug_18" LOC = "J12" ; +#NET "debug_19" LOC = "J13" ; +#NET "debug_20" LOC = "L14" ; +#NET "debug_21" LOC = "L16" ; +#NET "debug_22" LOC = "M15" ; +#NET "debug_23" LOC = "M16" ; +#NET "debug_24" LOC = "L13" ; +#NET "debug_25" LOC = "K13" ; +#NET "debug_26" LOC = "P16" ; +#NET "debug_27" LOC = "N16" ; +#NET "debug_28" LOC = "R15" ; +#NET "debug_29" LOC = "P15" ; +#NET "debug_30" LOC = "N13" ; +#NET "debug_31" LOC = "N14" ; +#NET "PPS_IN" LOC = "M14" ; +#NET "cgen_st_ld" LOC = "M13" ; +#NET "cgen_st_refmon" LOC = "J14" ; +#NET "FPGA_RXD" LOC = "H12" ; +#NET "DA10" LOC = "A8" ; +#NET "DA09" LOC = "B8" ; +#NET "DA08" LOC = "C8" ; +#NET "DA07" LOC = "D8" ; +#NET "DA06" LOC = "C9" ; +#NET "DA05" LOC = "A9" ; +#NET "DA04" LOC = "C10" ; +#NET "DA03" LOC = "D9" ; +#NET "SCLK_CODEC" LOC = "K3" ; +#NET "TXBLANK" LOC = "K1" ; +#NET "TXSYNC" LOC = "J2" ; +#NET "TX00" LOC = "J1" ; +#NET "TX01" LOC = "H3" ; +#NET "TX02" LOC = "J3" ; +#NET "TX03" LOC = "G2" ; +#NET "TX04" LOC = "H1" ; +#NET "TX05" LOC = "N3" ; +#NET "TX06" LOC = "M4" ; +#NET "TX07" LOC = "R1" ; +#NET "TX08" LOC = "P2" ; +#NET "TX09" LOC = "P1" ; +#NET "TX10" LOC = "M1" ; +#NET "TX11" LOC = "N1" ; +#NET "TX12" LOC = "M3" ; +#NET "TX13" LOC = "L4" ; +#NET "io_tx_00" LOC = "K4" ; +#NET "io_tx_01" LOC = "L3" ; +#NET "io_tx_02" LOC = "L2" ; +#NET "io_tx_03" LOC = "F1" ; +#NET "io_tx_04" LOC = "F3" ; +#NET "io_tx_05" LOC = "G3" ; +#NET "io_tx_06" LOC = "E3" ; +#NET "io_tx_07" LOC = "E2" ; +#NET "io_tx_08" LOC = "E4" ; +#NET "io_tx_09" LOC = "F4" ; +#NET "io_tx_10" LOC = "D1" ; +#NET "io_tx_11" LOC = "E1" ; +#NET "io_tx_12" LOC = "D4" ; +#NET "io_tx_13" LOC = "D3" ; +#NET "io_tx_14" LOC = "C2" ; +#NET "io_tx_15" LOC = "C1" ; +#NET "MISO_AUX" LOC = "J5" ; +#NET "MISO_CODEC" LOC = "G4" ; +#NET "MISO_TX_DB" LOC = "J4" ; +#NET "SEN_TX_DB" LOC = "N2" ; +#NET "MOSI_TX_DB" LOC = "L1" ; +#NET "SCLK_TX_DB" LOC = "G1" ; +#NET "DA02" LOC = "A3" ; +#NET "DA01" LOC = "B3" ; +#NET "DA00" LOC = "A4" ; +#NET "SEN_RX_DB" LOC = "B4" ; +#NET "MOSI_RX_DB" LOC = "A5" ; +#NET "SCLK_RX_DB" LOC = "C5" ; +#NET "io_rx_00" LOC = "D7" ; +#NET "io_rx_01" LOC = "C6" ; +#NET "io_rx_02" LOC = "A6" ; +#NET "io_rx_03" LOC = "B6" ; +#NET "io_rx_04" LOC = "E9" ; +#NET "io_rx_05" LOC = "A7" ; +#NET "io_rx_06" LOC = "C7" ; +#NET "io_rx_07" LOC = "B10" ; +#NET "io_rx_08" LOC = "A10" ; +#NET "io_rx_09" LOC = "C11" ; +#NET "io_rx_10" LOC = "A11" ; +#NET "io_rx_11" LOC = "D11" ; +#NET "io_rx_12" LOC = "B12" ; +#NET "io_rx_13" LOC = "A12" ; +#NET "io_rx_14" LOC = "A14" ; +#NET "io_rx_15" LOC = "A13" ; +#NET "SEN_AUX" LOC = "C12" ; +#NET "SCLK_AUX" LOC = "D12" ; +#NET "reset_codec" LOC = "B14" ; +#NET "SEN_CODEC" LOC = "D13" ; +#NET "MOSI_CODEC" LOC = "C13" ; +#NET "MISO_RX_DB" LOC = "E6" ; +#NET "mystery_bus_1" LOC = "C4" ; +#NET "mystery_bus_0" LOC = "E7" ; +#NET "RXSYNC" LOC = "D10" ; +#NET "DA11" LOC = "B15" ; + diff --git a/usrp2/top/safe_u1plus/safe_u1plus.v b/usrp2/top/safe_u1plus/safe_u1plus.v index 38b276000..108364833 100644 --- a/usrp2/top/safe_u1plus/safe_u1plus.v +++ b/usrp2/top/safe_u1plus/safe_u1plus.v @@ -1,362 +1,25 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -module safe_u2plus - ( - input CLK_FPGA_P, input CLK_FPGA_N, // Diff - - // ADC - //input ADC_clkout_p, //input ADC_clkout_n, - //input ADCA_12_p, //input ADCA_12_n, - //input ADCA_10_p, //input ADCA_10_n, - //input ADCA_8_p, //input ADCA_8_n, - //input ADCA_6_p, //input ADCA_6_n, - //input ADCA_4_p, //input ADCA_4_n, - //input ADCA_2_p, //input ADCA_2_n, - //input ADCA_0_p, //input ADCA_0_n, - //input ADCB_12_p, //input ADCB_12_n, - //input ADCB_10_p, //input ADCB_10_n, - //input ADCB_8_p, //input ADCB_8_n, - //input ADCB_6_p, //input ADCB_6_n, - //input ADCB_4_p, //input ADCB_4_n, - //input ADCB_2_p, //input ADCB_2_n, - //input ADCB_0_p, //input ADCB_0_n, - - // DAC - //output [15:0] DACA, - //output [15:0] DACB, - //input DAC_LOCK, // unused for now - - // DB IO Pins - //inout [15:0] io_tx, - //inout [15:0] io_rx, - - // Misc, debug - output [5:1] leds, // LED4 is shared w/INIT_B - //input FPGA_RESET, - //output [1:0] debug_clk, - //output [31:0] debug, - //output [3:1] TXD, //input [3:1] RXD, // UARTs - ////input [3:0] dipsw, // Forgot DIP Switches... - - // Clock Gen Control - //output [1:0] clk_en, - //output [1:0] clk_sel, - //input CLK_FUNC, // FIXME is an //input to control the 9510 - //input CLK_STATUS, - - //inout SCL, //inout SDA, // I2C - - // PPS - //input PPS_IN, //input PPS2_IN, - - // SPI - //output SEN_CLK, //output SCLK_CLK, //output MOSI_CLK, //input MISO_CLK, - //output SEN_DAC, //output SCLK_DAC, //output MOSI_DAC, //input MISO_DAC, - //output SEN_ADC, //output SCLK_ADC, //output MOSI_ADC, - //output SEN_TX_DB, //output SCLK_TX_DB, //output MOSI_TX_DB, //input MISO_TX_DB, - //output SEN_TX_DAC, //output SCLK_TX_DAC, //output MOSI_TX_DAC, - //output SEN_TX_ADC, //output SCLK_TX_ADC, //output MOSI_TX_ADC, //input MISO_TX_ADC, - //output SEN_RX_DB, //output SCLK_RX_DB, //output MOSI_RX_DB, //input MISO_RX_DB, - //output SEN_RX_DAC, //output SCLK_RX_DAC, //output MOSI_RX_DAC, - //output SEN_RX_ADC, //output SCLK_RX_ADC, //output MOSI_RX_ADC, //input MISO_RX_ADC, - - // GigE PHY - //input CLK_TO_MAC, - - //output reg [7:0] GMII_TXD, - //output reg GMII_TX_EN, - //output reg GMII_TX_ER, - //output GMII_GTX_CLK, - //input GMII_TX_CLK, // 100mbps clk - - //input GMII_RX_CLK, - //input [7:0] GMII_RXD, - //input GMII_RX_DV, - //input GMII_RX_ER, - //input GMII_COL, - //input GMII_CRS, - - //input PHY_INTn, // open drain - //inout MDIO, - //output MDC, - //output PHY_RESETn, - output ETH_LED - - //input POR, - - // Expansion - //input exp_time_in_p, //input exp_time_in_n, // Diff - //output exp_time_out_p, //output exp_time_out_n, // Diff - //input exp_user_in_p, //input exp_user_in_n, // Diff - //output exp_user_out_p, //output exp_user_out_n, // Diff - - // SERDES - //output ser_enable, - //output ser_prbsen, - //output ser_loopen, - //output ser_rx_en, - - //output ser_tx_clk, - //output reg [15:0] ser_t, - //output reg ser_tklsb, - //output reg ser_tkmsb, - - //input ser_rx_clk, - //input [15:0] ser_r, - //input ser_rklsb, - //input ser_rkmsb, - - // SRAM - //inout [35:0] RAM_D, - //output [20:0] RAM_A, - //output [3:0] RAM_BWn, - //output RAM_ZZ, - //output RAM_LDn, - //output RAM_OEn, - //output RAM_WEn, - //output RAM_CENn, - //output RAM_CLK, - - // SPI Flash - //output flash_cs, - //output flash_clk, - //output flash_mosi, - //input flash_miso +module safe_u1plus + (input CLK_FPGA_P, input CLK_FPGA_N, + input reset_n, + output [2:0] debug_led // LED4 is shared w/INIT_B ); - + // FPGA-specific pins connections wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; - + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; - + reg [31:0] ctr; - + always @(posedge clk_fpga) ctr <= ctr + 1; - - assign {leds,ETH_LED} = ~ctr[29:24]; - - -/* - wire exp_time_in; - IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); - defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; - wire exp_time_out; - OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); - defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; - - wire dcm_rst = 0; - - wire [13:0] adc_a, adc_b; - - capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds - (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), - .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p}, - {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), - .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n}, - {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), - .out({adc_a,adc_b})); - - // Handle Clocks - DCM DCM_INST (.CLKFB(dsp_clk), - .CLKIN(clk_fpga), - .DSSEN(0), - .PSCLK(0), - .PSEN(0), - .PSINCDEC(0), - .RST(dcm_rst), - .CLKDV(clk_div), - .CLKFX(), - .CLKFX180(), - .CLK0(dcm_out), - .CLK2X(), - .CLK2X180(), - .CLK90(), - .CLK180(), - .CLK270(), - .LOCKED(LOCKED_OUT), - .PSDONE(), - .STATUS()); - defparam DCM_INST.CLK_FEEDBACK = "1X"; - defparam DCM_INST.CLKDV_DIVIDE = 2.0; - defparam DCM_INST.CLKFX_DIVIDE = 1; - defparam DCM_INST.CLKFX_MULTIPLY = 4; - defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; - defparam DCM_INST.CLKIN_PERIOD = 10.000; - defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; - defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; - defparam DCM_INST.FACTORY_JF = 16'h8080; - defparam DCM_INST.PHASE_SHIFT = 0; - defparam DCM_INST.STARTUP_WAIT = "FALSE"; - - BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); - BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); - - // I2C -- Don't use external transistors for open drain, the FPGA implements this - IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); - IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); - - // LEDs are active low outputs - wire [4:0] leds_int; - assign leds = ~leds_int; // drive low to turn on leds - - // SPI - wire miso, mosi, sclk; - - assign {SCLK_CLK,MOSI_CLK} = ~SEN_CLK ? {sclk,mosi} : 2'B0; - assign {SCLK_DAC,MOSI_DAC} = ~SEN_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_ADC,MOSI_ADC} = ~SEN_ADC ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_DAC,MOSI_TX_DAC} = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_ADC,MOSI_TX_ADC} = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_DAC,MOSI_RX_DAC} = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_ADC,MOSI_RX_ADC} = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0; - - assign miso = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) | - (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) | - (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC); - - wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; - wire [7:0] GMII_TXD_unreg; - wire GMII_GTX_CLK_int; - - always @(posedge GMII_GTX_CLK_int) - begin - GMII_TX_EN <= GMII_TX_EN_unreg; - GMII_TX_ER <= GMII_TX_ER_unreg; - GMII_TXD <= GMII_TXD_unreg; - end - - OFDDRRSE OFDDRRSE_gmii_inst - (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) - .C0(GMII_GTX_CLK_int), // 0 degree clock input - .C1(~GMII_GTX_CLK_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - - wire ser_tklsb_unreg, ser_tkmsb_unreg; - wire [15:0] ser_t_unreg; - wire ser_tx_clk_int; - - always @(posedge ser_tx_clk_int) - begin - ser_tklsb <= ser_tklsb_unreg; - ser_tkmsb <= ser_tkmsb_unreg; - ser_t <= ser_t_unreg; - end - - assign ser_tx_clk = clk_fpga; - - reg [15:0] ser_r_int; - reg ser_rklsb_int, ser_rkmsb_int; + assign debug_led[1:0] = ~ctr[26:25]; - always @(posedge ser_rx_clk) - begin - ser_r_int <= ser_r; - ser_rklsb_int <= ser_rklsb; - ser_rkmsb_int <= ser_rkmsb; - end + assign debug_led[2] = ~reset_n; - u2_core u2_core(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), - .leds (leds_int), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_time_in), - .exp_pps_out (exp_time_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD_unreg[7:0]), - .GMII_TX_EN (GMII_TX_EN_unreg), - .GMII_TX_ER (GMII_TX_ER_unreg), - .GMII_GTX_CLK (GMII_GTX_CLK_int), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk_int), - .ser_t (ser_t_unreg[15:0]), - .ser_tklsb (ser_tklsb_unreg), - .ser_tkmsb (ser_tkmsb_unreg), - .ser_rx_clk (ser_rx_clk), - .ser_r (ser_r_int[15:0]), - .ser_rklsb (ser_rklsb_int), - .ser_rkmsb (ser_rkmsb_int), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .adc_a (adc_a[13:0]), - .adc_ovf_a (adc_ovf_a), - .adc_on_a (adc_on_a), - .adc_oe_a (adc_oe_a), - .adc_b (adc_b[13:0]), - .adc_ovf_b (adc_ovf_b), - .adc_on_b (adc_on_b), - .adc_oe_b (adc_oe_b), - .dac_a (DACA[15:0]), - .dac_b (DACB[15:0]), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk_int), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D (RAM_D), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - .RAM_CLK (RAM_CLK), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (uart_tx_o), - .uart_rx_i (uart_rx_i), - .uart_baud_o (), - .sim_mode (1'b0), - .clock_divider (2) - ); -*/ -endmodule // safe_u2plus +endmodule // safe_u1plus diff --git a/usrp2/top/safe_u1plus/u1plus.ucf b/usrp2/top/safe_u1plus/u1plus.ucf deleted file mode 100644 index c3b20b76f..000000000 --- a/usrp2/top/safe_u1plus/u1plus.ucf +++ /dev/null @@ -1,168 +0,0 @@ -NET "TMS" LOC = "B2" ; -NET "TDO" LOC = "B16" ; -NET "TDI" LOC = "B1" ; -NET "TCK" LOC = "A15" ; -NET "GPIF_D07" LOC = "N12" ; -NET "GPIF_D06" LOC = "P13" ; -NET "GPIF_D05" LOC = "P11" ; -NET "GPIF_RDY3" LOC = "N11" ; -NET "GPIF_RDY2" LOC = "T10" ; -NET "GPIF_RDY1" LOC = "T4" ; -NET "GPIF_RDY0" LOC = "R5" ; -NET "cgen_st_status" LOC = "P6" ; -NET "GPIF_CTL3" LOC = "N5" ; -NET "GPIF_CTL2" LOC = "M11" ; -NET "GPIF_CTL1" LOC = "M9" ; -NET "GPIF_CTL0" LOC = "M7" ; -NET "fpga_cfg_prog_b" LOC = "A2" ; -NET "fpga_cfg_done" LOC = "T15" ; -NET "reset_n" LOC = "D5" ; -NET "fpga_cfg_din" LOC = "T14" ; -NET "fpga_cfg_cclk" LOC = "R14" ; -NET "SDA_FPGA" LOC = "T13" ; -NET "SCL_FPGA" LOC = "R13" ; -NET "fpga_cfg_init_b" LOC = "T12" ; -NET "FX2_PA7_FLAGD" LOC = "P12" ; -NET "mystery_bus_2" LOC = "T11" ; -NET "FX2_PA6_PKTEND" LOC = "R11" ; -NET "FX2_PA2_SLOE" LOC = "P10" ; -NET "GPIF_D15" LOC = "P7" ; -NET "GPIF_D14" LOC = "N8" ; -NET "GPIF_D13" LOC = "T5" ; -NET "GPIF_D12" LOC = "T6" ; -NET "GPIF_D11" LOC = "N6" ; -NET "GPIF_D10" LOC = "P5" ; -NET "GPIF_D09" LOC = "R3" ; -NET "GPIF_D08" LOC = "T3" ; -NET "debug_led2" LOC = "R2" ; -NET "cgen_ref_sel" LOC = "T2" ; -NET "debug_led1" LOC = "N4" ; -NET "debug_led0" LOC = "P4" ; -NET "GPIF_D04" LOC = "R9" ; -NET "GPIF_D03" LOC = "T9" ; -NET "GPIF_D02" LOC = "N9" ; -NET "GPIF_D01" LOC = "P9" ; -NET "GPIF_D00" LOC = "P8" ; -NET "IFCLK" LOC = "T8" ; -NET "CLK_FPGA_P" LOC = "R7" ; -NET "CLK_FPGA_N" LOC = "T7" ; -NET "cgen_sync_b" LOC = "H15" ; -NET "FPGA_TXD" LOC = "H16" ; -NET "debug_00" LOC = "K16" ; -NET "debug_01" LOC = "J16" ; -NET "debug_clk0" LOC = "K15" ; -NET "debug_clk1" LOC = "K14" ; -NET "debug_02" LOC = "C16" ; -NET "debug_03" LOC = "C15" ; -NET "debug_04" LOC = "E13" ; -NET "debug_05" LOC = "D14" ; -NET "debug_06" LOC = "D16" ; -NET "debug_07" LOC = "D15" ; -NET "debug_08" LOC = "E14" ; -NET "debug_09" LOC = "F13" ; -NET "debug_10" LOC = "G13" ; -NET "debug_11" LOC = "F14" ; -NET "debug_12" LOC = "E16" ; -NET "debug_13" LOC = "F15" ; -NET "debug_14" LOC = "H13" ; -NET "debug_15" LOC = "G14" ; -NET "debug_16" LOC = "G16" ; -NET "debug_17" LOC = "F16" ; -NET "debug_18" LOC = "J12" ; -NET "debug_19" LOC = "J13" ; -NET "debug_20" LOC = "L14" ; -NET "debug_21" LOC = "L16" ; -NET "debug_22" LOC = "M15" ; -NET "debug_23" LOC = "M16" ; -NET "debug_24" LOC = "L13" ; -NET "debug_25" LOC = "K13" ; -NET "debug_26" LOC = "P16" ; -NET "debug_27" LOC = "N16" ; -NET "debug_28" LOC = "R15" ; -NET "debug_29" LOC = "P15" ; -NET "debug_30" LOC = "N13" ; -NET "debug_31" LOC = "N14" ; -NET "PPS_IN" LOC = "M14" ; -NET "cgen_st_ld" LOC = "M13" ; -NET "cgen_st_refmon" LOC = "J14" ; -NET "FPGA_RXD" LOC = "H12" ; -NET "DA10" LOC = "A8" ; -NET "DA09" LOC = "B8" ; -NET "DA08" LOC = "C8" ; -NET "DA07" LOC = "D8" ; -NET "DA06" LOC = "C9" ; -NET "DA05" LOC = "A9" ; -NET "DA04" LOC = "C10" ; -NET "DA03" LOC = "D9" ; -NET "SCLK_CODEC" LOC = "K3" ; -NET "TXBLANK" LOC = "K1" ; -NET "TXSYNC" LOC = "J2" ; -NET "TX00" LOC = "J1" ; -NET "TX01" LOC = "H3" ; -NET "TX02" LOC = "J3" ; -NET "TX03" LOC = "G2" ; -NET "TX04" LOC = "H1" ; -NET "TX05" LOC = "N3" ; -NET "TX06" LOC = "M4" ; -NET "TX07" LOC = "R1" ; -NET "TX08" LOC = "P2" ; -NET "TX09" LOC = "P1" ; -NET "TX10" LOC = "M1" ; -NET "TX11" LOC = "N1" ; -NET "TX12" LOC = "M3" ; -NET "TX13" LOC = "L4" ; -NET "io_tx_00" LOC = "K4" ; -NET "io_tx_01" LOC = "L3" ; -NET "io_tx_02" LOC = "L2" ; -NET "io_tx_03" LOC = "F1" ; -NET "io_tx_04" LOC = "F3" ; -NET "io_tx_05" LOC = "G3" ; -NET "io_tx_06" LOC = "E3" ; -NET "io_tx_07" LOC = "E2" ; -NET "io_tx_08" LOC = "E4" ; -NET "io_tx_09" LOC = "F4" ; -NET "io_tx_10" LOC = "D1" ; -NET "io_tx_11" LOC = "E1" ; -NET "io_tx_12" LOC = "D4" ; -NET "io_tx_13" LOC = "D3" ; -NET "io_tx_14" LOC = "C2" ; -NET "io_tx_15" LOC = "C1" ; -NET "MISO_AUX" LOC = "J5" ; -NET "MISO_CODEC" LOC = "G4" ; -NET "MISO_TX_DB" LOC = "J4" ; -NET "SEN_TX_DB" LOC = "N2" ; -NET "MOSI_TX_DB" LOC = "L1" ; -NET "SCLK_TX_DB" LOC = "G1" ; -NET "DA02" LOC = "A3" ; -NET "DA01" LOC = "B3" ; -NET "DA00" LOC = "A4" ; -NET "SEN_RX_DB" LOC = "B4" ; -NET "MOSI_RX_DB" LOC = "A5" ; -NET "SCLK_RX_DB" LOC = "C5" ; -NET "io_rx_00" LOC = "D7" ; -NET "io_rx_01" LOC = "C6" ; -NET "io_rx_02" LOC = "A6" ; -NET "io_rx_03" LOC = "B6" ; -NET "io_rx_04" LOC = "E9" ; -NET "io_rx_05" LOC = "A7" ; -NET "io_rx_06" LOC = "C7" ; -NET "io_rx_07" LOC = "B10" ; -NET "io_rx_08" LOC = "A10" ; -NET "io_rx_09" LOC = "C11" ; -NET "io_rx_10" LOC = "A11" ; -NET "io_rx_11" LOC = "D11" ; -NET "io_rx_12" LOC = "B12" ; -NET "io_rx_13" LOC = "A12" ; -NET "io_rx_14" LOC = "A14" ; -NET "io_rx_15" LOC = "A13" ; -NET "SEN_AUX" LOC = "C12" ; -NET "SCLK_AUX" LOC = "D12" ; -NET "reset_codec" LOC = "B14" ; -NET "SEN_CODEC" LOC = "D13" ; -NET "MOSI_CODEC" LOC = "C13" ; -NET "MISO_RX_DB" LOC = "E6" ; -NET "mystery_bus_1" LOC = "C4" ; -NET "mystery_bus_0" LOC = "E7" ; -NET "RXSYNC" LOC = "D10" ; -NET "DA11" LOC = "B15" ; - -- cgit v1.2.3 From 7e7e329a4a6ab48d6bea348176b5bcf5cbac5b9d Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 4 Jun 2010 15:28:13 -0700 Subject: Use the 4th LED which is shared on the cfg_init_b pin --- usrp2/top/safe_u1plus/safe_u1plus.ucf | 11 ++++++----- usrp2/top/safe_u1plus/safe_u1plus.v | 5 ++++- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/usrp2/top/safe_u1plus/safe_u1plus.ucf b/usrp2/top/safe_u1plus/safe_u1plus.ucf index 1a078a9cc..a0c743525 100644 --- a/usrp2/top/safe_u1plus/safe_u1plus.ucf +++ b/usrp2/top/safe_u1plus/safe_u1plus.ucf @@ -5,6 +5,12 @@ NET "reset_n" LOC = "D5" ; NET "CLK_FPGA_P" LOC = "R7" ; NET "CLK_FPGA_N" LOC = "T7" ; +#NET "fpga_cfg_prog_b" LOC = "A2" ; +#NET "fpga_cfg_done" LOC = "T15" ; +#NET "fpga_cfg_din" LOC = "T14" ; +#NET "fpga_cfg_cclk" LOC = "R14" ; +NET "fpga_cfg_init_b" LOC = "T12" ; + #NET "TMS" LOC = "B2" ; #NET "TDO" LOC = "B16" ; @@ -22,13 +28,8 @@ NET "CLK_FPGA_N" LOC = "T7" ; #NET "GPIF_CTL2" LOC = "M11" ; #NET "GPIF_CTL1" LOC = "M9" ; #NET "GPIF_CTL0" LOC = "M7" ; -#NET "fpga_cfg_prog_b" LOC = "A2" ; -#NET "fpga_cfg_done" LOC = "T15" ; -#NET "fpga_cfg_din" LOC = "T14" ; -#NET "fpga_cfg_cclk" LOC = "R14" ; #NET "SDA_FPGA" LOC = "T13" ; #NET "SCL_FPGA" LOC = "R13" ; -#NET "fpga_cfg_init_b" LOC = "T12" ; #NET "FX2_PA7_FLAGD" LOC = "P12" ; #NET "mystery_bus_2" LOC = "T11" ; #NET "FX2_PA6_PKTEND" LOC = "R11" ; diff --git a/usrp2/top/safe_u1plus/safe_u1plus.v b/usrp2/top/safe_u1plus/safe_u1plus.v index 108364833..e55c7f0be 100644 --- a/usrp2/top/safe_u1plus/safe_u1plus.v +++ b/usrp2/top/safe_u1plus/safe_u1plus.v @@ -4,8 +4,11 @@ module safe_u1plus (input CLK_FPGA_P, input CLK_FPGA_N, input reset_n, - output [2:0] debug_led // LED4 is shared w/INIT_B + output [2:0] debug_led, // LED4 is shared w/INIT_B + output fpga_cfg_init_b ); + + assign fpga_cfg_init_b = 1; // FPGA-specific pins connections wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; -- cgit v1.2.3 From cf69f2b3c7f65f2f1f9f390d34cda89ec6c39663 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 8 Jun 2010 14:09:01 -0700 Subject: copied over from u1e, most pins hooked up. --- usrp2/top/u1_core/.gitignore | 44 ---- usrp2/top/u1_core/u1_core.v | 455 ----------------------------------------- usrp2/top/u1plus/Makefile | 30 ++- usrp2/top/u1plus/u1plus.ucf | 18 +- usrp2/top/u1plus/u1plus.v | 254 ++++++++++++----------- usrp2/top/u1plus/u1plus_core.v | 424 ++++++++++++++++++++++++++++++++++++++ 6 files changed, 588 insertions(+), 637 deletions(-) delete mode 100644 usrp2/top/u1_core/.gitignore delete mode 100755 usrp2/top/u1_core/u1_core.v create mode 100644 usrp2/top/u1plus/u1plus_core.v diff --git a/usrp2/top/u1_core/.gitignore b/usrp2/top/u1_core/.gitignore deleted file mode 100644 index 9728395c1..000000000 --- a/usrp2/top/u1_core/.gitignore +++ /dev/null @@ -1,44 +0,0 @@ -*~ -/xst -/_ngo -/_xmsgs -/*.stx -/*.tspec -/*.xml -/*.gyd -/*.ngr -/*.tim -/*.err -/*.lso -/*.bld -/*.cmd_log -/*.ise_ISE_Backup -/*.mfd -/*.vm6 -/*.syr -/*.xst -/*.csv -/*.html -/*.jed -/*.pad -/*.ng* -/*.pnx -/*.rpt -/*.prj -/*_html -/*_log -/*.lfp -/*.bit -/*.bin -/*.vcd -/*.unroutes -/*.drc -/*_map.* -/*_guide.* -/*.twr -/*.twx -/a.out -/*.xpi -/*_pad.txt -/*.bgn -/*.par diff --git a/usrp2/top/u1_core/u1_core.v b/usrp2/top/u1_core/u1_core.v deleted file mode 100755 index 24a57936e..000000000 --- a/usrp2/top/u1_core/u1_core.v +++ /dev/null @@ -1,455 +0,0 @@ -// //////////////////////////////////////////////////////////////////////////////// -// Module Name: u2_core -// //////////////////////////////////////////////////////////////////////////////// - -module u1_core - #(parameter RAM_SIZE=16384) - (input sys_clk, input sys_rst, - input wb_clk, input wb_rst, - - output uart_tx_o, input uart_rx_i, output uart_baud_o, - output [2:0] leds, output [31:0] debug, output [1:0] debug_clk, - - input scl_pad_i, output scl_pad_o, output scl_pad_oen_o, - input sda_pad_i, output sda_pad_o, output sda_pad_oen_o, - - input pps, - output reset_codec, - - input gpif_clk, inout [15:0] gpif_d, input [3:0] gpif_ctl, output [3:0] gpif_rdy, - input [2:0] gpif_misc, - - input [11:0] adc, input rxsync, - output [13:0] dac, output txsync, output txblank, - - // Generic SPI - output sclk, - output mosi, - input miso, - output [3:0] sen, - - // GPIO to DBoards - inout [15:0] io_tx, - inout [15:0] io_rx, - - input sim_mode - ); - - wire [7:0] set_addr; - wire [31:0] set_data; - wire set_stb; - - wire ram_loader_done, ram_loader_rst; - - wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; - wire bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int; - - wire [31:0] debug_gpio_0, debug_gpio_1; - wire [31:0] atr_lines; - - wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp; - - wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; - wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; - wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; - - wire serdes_link_up; - wire epoch; - wire [31:0] irq; - - // /////////////////////////////////////////////////////////////////////////////////////////////// - // Wishbone Single Master INTERCON - localparam dw = 32; // Data bus width - localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space - localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. - - wire [dw-1:0] m0_dat_o, m0_dat_i; - wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, - s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, - s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, - sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o; - wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr; - wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel; - wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack; - wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb; - wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc; - wire m0_err, m0_rty; - wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we; - - wb_1master #(.decode_w(6), - .s0_addr(6'b0000_00),.s0_mask(6'b100000), - .s1_addr(6'b1000_00),.s1_mask(6'b110000), - .s2_addr(6'b1100_00),.s2_mask(6'b111111), - .s3_addr(6'b1100_01),.s3_mask(6'b111111), - .s4_addr(6'b1100_10),.s4_mask(6'b111111), - .s5_addr(6'b1100_11),.s5_mask(6'b111111), - .s6_addr(6'b1101_00),.s6_mask(6'b111111), - .s7_addr(6'b1101_01),.s7_mask(6'b111111), - .s8_addr(6'b1101_10),.s8_mask(6'b111111), - .s9_addr(6'b1101_11),.s9_mask(6'b111111), - .sa_addr(6'b1110_00),.sa_mask(6'b111111), - .sb_addr(6'b1110_01),.sb_mask(6'b111111), - .sc_addr(6'b1110_10),.sc_mask(6'b111111), - .sd_addr(6'b1110_11),.sd_mask(6'b111111), - .se_addr(6'b1111_00),.se_mask(6'b111111), - .sf_addr(6'b1111_01),.sf_mask(6'b111111), - .dw(dw),.aw(aw),.sw(sw)) wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), - .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), - .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), - .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), - .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), - .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), - .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), - .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), - .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), - .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), - .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), - .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), - .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), - .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), - .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), - .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), - .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), - .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), - .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), - .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), - .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), - .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), - .sf_dat_i(0),.sf_ack_i(0),.sf_err_i(0),.sf_rty_i(0) ); - - // /////////////////////////////////////////////////////////////////// - // RAM Loader - - wire [31:0] ram_loader_dat, iwb_dat; - wire [15:0] ram_loader_adr, iwb_adr; - wire [3:0] ram_loader_sel; - wire ram_loader_stb, ram_loader_we, ram_loader_ack; - wire iwb_ack, iwb_stb; - ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) - ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), - // CPLD Interface - .cfg_clk_i(cpld_clk), - .cfg_data_i(cpld_din), - .start_o(cpld_start_int), - .mode_o(cpld_mode_int), - .done_o(cpld_done_int), - .detached_i(cpld_detached), - // Wishbone Interface - .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), - .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), - .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), - .ram_loader_done_o(ram_loader_done)); - - // ///////////////////////////////////////////////////////////////////////// - // Processor - aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) - aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), - // Instruction Wishbone bus to I-RAM - .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), - .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), - // Data Wishbone bus to system bus fabric - .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), - .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), - // Interrupts and exceptions - .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - assign bus_error = m0_err | m0_rty; - - // ///////////////////////////////////////////////////////////////////////// - // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone - // I-port connects directly to processor and ram loader - - wire flush_icache; - ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) - sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - - .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), - .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), - .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), - .ram_loader_done_i(ram_loader_done), - - .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), - .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), - - .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), - .flush_icache(flush_icache)); - - setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(flush_icache)); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool, slave #1 - wire rd0_ready_i, rd0_ready_o; - wire rd1_ready_i, rd1_ready_o; - wire rd2_ready_i, rd2_ready_o; - wire rd3_ready_i, rd3_ready_o; - wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; - wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; - - wire wr0_ready_i, wr0_ready_o; - wire wr1_ready_i, wr1_ready_o; - wire wr2_ready_i, wr2_ready_o; - wire wr3_ready_i, wr3_ready_o; - wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; - wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - buffer_pool #(.BUF_SIZE(9), .SET_ADDR(64)) buffer_pool - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), - .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .status(status),.sys_int_o(buffer_int), - - .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), - .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), - - // Write Interfaces - .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o), - .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o), - .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o), - .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o), - // Read Interfaces - .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o), - .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o), - .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o), - .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o) - ); - - wire [31:0] status_enc; - priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc)); - - // ///////////////////////////////////////////////////////////////////////// - // SPI -- Slave #2 - spi_top shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), - .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), - .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), - .ss_pad_o(sen), - .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); - - // ///////////////////////////////////////////////////////////////////////// - // I2C -- Slave #3 - i2c_master_top #(.ARST_LVL(1)) - i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_dat_i[31:8] = 24'd0; - - // ///////////////////////////////////////////////////////////////////////// - // GPIOs -- Slave #4 - nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), - .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), - .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( {io_tx,io_rx} ) ); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool Status -- Slave #5 - - reg [31:0] cycle_count; - always @(posedge wb_clk) - if(wb_rst) - cycle_count <= 0; - else - cycle_count <= cycle_count + 1; - - wb_readback_mux buff_pool_status - (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), - .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - - .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), - .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), - .word08(status),.word09({sim_mode,31'b0}),.word10(32'b0), - .word11(32'b0),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count) - ); - - // ///////////////////////////////////////////////////////////////////////// - // Settings Bus -- Slave #7 - settings_bus settings_bus - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), - .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), - .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data)); - - assign s7_dat_i = 32'd0; - - // Output control lines - setting_reg #(.my_addr(0)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), - .in(set_data),.out(clock_outs),.changed()); - - // ///////////////////////////////////////////////////////////////////////// - // LEDS - // register 8 determines whether leds are controlled by SW or not - // 1 = controlled by HW, 0 = by SW - // In Rev3 there are only 6 leds, and the highest one is on the ETH connector - - wire [7:0] led_hw = 0; - - setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_sw),.changed()); - setting_reg #(.my_addr(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_src),.changed()); - - assign leds = (led_src & led_hw) | (~led_src & led_sw); - - // ///////////////////////////////////////////////////////////////////////// - // Interrupt Controller, Slave #8 - - assign irq= {{8'b0}, - {8'b0}, - {6'b0, uart_tx_int, uart_rx_int}, - {pps_int,overrun,underrun,1'b0,i2c_int,spi_int,timer_int,buffer_int}}; - - pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]), - .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), - .irq(irq) ); - - // ///////////////////////////////////////////////////////////////////////// - // Master Timer, Slave #9 - - wire [31:0] master_time; - timer timer - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), - .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), - .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); - - // ///////////////////////////////////////////////////////////////////////// - // UART, Slave #10 - - simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries - (.clk_i(wb_clk),.rst_i(wb_rst), - .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), - .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), - .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), - .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); - - // ///////////////////////////////////////////////////////////////////////// - // ATR Controller, Slave #11 - - wire run_rx, run_tx; - reg run_rx_d1; - always @(posedge dsp_clk) - run_rx_d1 <= run_rx; - - atr_controller atr_controller - (.clk_i(wb_clk),.rst_i(wb_rst), - .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), - .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), - .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); - - // ////////////////////////////////////////////////////////////////////////// - // Time Sync, Slave #12 - - reg pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1; - always @(negedge dsp_clk) pps_negedge <= pps; - always @(posedge dsp_clk) pps_posedge <= pps; - always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge; - always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge; - - wire pps_o; - time_sync time_sync - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(sc_cyc),.stb_i(sc_stb),.adr_i(sc_adr[4:2]), - .we_i(sc_we),.dat_i(sc_dat_o),.dat_o(sc_dat_i),.ack_o(sc_ack), - .sys_clk_i(dsp_clk),.master_time_o(master_time), - .pps_posedge(pps_posedge),.pps_negedge(pps_negedge), - .exp_pps_in(),.exp_pps_out(), - .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) ); - - // ///////////////////////////////////////////////////////////////////////// - // DSP - wire [31:0] sample_rx, sample_tx; - wire strobe_rx, strobe_tx; - - rx_control #(.FIFOSIZE(10)) rx_control - (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .master_time(master_time),.overrun(overrun), - .wr_dat_o(wr1_dat), .wr_flags_o(wr1_flags), .wr_ready_o(wr1_ready_i), .wr_ready_i(wr1_ready_o), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty), - .debug_rx(debug_rx) ); - - dsp_core_rx dsp_core_rx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), - .debug(debug_rx_dsp) ); - - tx_control #(.FIFOSIZE(10)) tx_control - (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .master_time(master_time),.underrun(underrun), - .rd_dat_i(rd1_dat), .rd_flags_i(rd1_flags), .rd_ready_i(rd1_ready_o), .rd_ready_o(rd1_ready_i), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty), - .debug(debug_txc) ); - - dsp_core_tx dsp_core_tx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .dac_a(dac_a),.dac_b(dac_b), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_tx_dsp) ); - - assign dsp_rst = wb_rst; - - // ///////////////////////////////////////////////////////////////////////////////////////// - // CODEC Interface - - assign txblank = 0; - - always @(posedge dsp_clk) - if(tx_strobe) - begin - dac <= dac_a; - txsync <= 0; - end - else - begin - dac <= dac_b; - txsync <= 1; - end - - always @(posedge dsp_clk) - if(rxsync) - begin - adc_a_hold <= adc; - rx_strobe <= 0; - end - else - begin - adc_a <= adc_a_hold; - adc_b <= adc; - rx_strobe <= 1; - end - - // ///////////////////////////////////////////////////////////////////////////////////////// - // Debug Pins - - assign debug_clk[0] = 0; - assign debug_clk[1] = 0; - assign debug = 0; - - -endmodule // u1_core diff --git a/usrp2/top/u1plus/Makefile b/usrp2/top/u1plus/Makefile index 8a7c7856d..684b7bcd7 100644 --- a/usrp2/top/u1plus/Makefile +++ b/usrp2/top/u1plus/Makefile @@ -54,7 +54,7 @@ simulator "ISE Simulator (VHDL/Verilog)" \ export SOURCE_ROOT := ../../../ export SOURCES := \ control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ +control_lib/atr_controller16.v \ control_lib/bin2gray.v \ control_lib/dcache.v \ control_lib/decoder_3_8.v \ @@ -64,12 +64,13 @@ control_lib/gray_send.v \ control_lib/icache.v \ control_lib/mux4.v \ control_lib/mux8.v \ -control_lib/nsgpio.v \ +control_lib/nsgpio16LE.v \ control_lib/ram_2port.v \ +control_lib/ram_2port_mixed_width.v \ control_lib/ram_harv_cache.v \ control_lib/ram_loader.v \ control_lib/setting_reg.v \ -control_lib/settings_bus.v \ +control_lib/settings_bus_16LE.v \ control_lib/srl.v \ control_lib/system_control.v \ control_lib/wb_1master.v \ @@ -92,6 +93,13 @@ control_lib/newfifo/fifo_short.v \ control_lib/newfifo/fifo_long.v \ control_lib/newfifo/fifo_cascade.v \ control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/newfifo/fifo36_to_fifo19.v \ +control_lib/newfifo/fifo19_to_fifo36.v \ +control_lib/newfifo/packet_generator.v \ +control_lib/newfifo/packet_verifier.v \ +control_lib/newfifo/packet_generator32.v \ +control_lib/newfifo/packet_verifier32.v \ +control_lib/newfifo/fifo_pacer.v \ control_lib/longfifo.v \ control_lib/shortfifo.v \ control_lib/medfifo.v \ @@ -122,8 +130,7 @@ opencores/simple_pic/rtl/simple_pic.v \ opencores/spi/rtl/verilog/spi_clgen.v \ opencores/spi/rtl/verilog/spi_defines.v \ opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ +opencores/spi/rtl/verilog/spi_top16.v \ sdr_lib/acc.v \ sdr_lib/add2.v \ sdr_lib/add2_and_round.v \ @@ -139,7 +146,7 @@ sdr_lib/clip_reg.v \ sdr_lib/cordic.v \ sdr_lib/cordic_z24.v \ sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_rx.v \ +sdr_lib/dsp_core_rx_udp.v \ sdr_lib/dsp_core_tx.v \ sdr_lib/hb_dec.v \ sdr_lib/hb_interp.v \ @@ -160,7 +167,13 @@ timing/time_receiver.v \ timing/time_sender.v \ timing/time_sync.v \ timing/timer.v \ -top/u1_core/u1_core.v \ +timing/time_64bit.v \ +vrt/vita_rx_control.v \ +vrt/vita_rx_framer.v \ +vrt/vita_tx_control.v \ +vrt/vita_tx_deframer.v \ +timing/time_compare.v \ +top/u1plus/u1plus_core.v \ top/u1plus/u1plus.ucf \ top/u1plus/timing.ucf \ top/u1plus/u1plus.v @@ -204,7 +217,8 @@ export GEN_PROG_FILE_PROPERTIES := \ "Create Binary Configuration File" TRUE \ "Done (Output Events)" 5 \ "Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" export SIM_MODEL_PROPERTIES := "" diff --git a/usrp2/top/u1plus/u1plus.ucf b/usrp2/top/u1plus/u1plus.ucf index 8a22d0966..cd89878e3 100644 --- a/usrp2/top/u1plus/u1plus.ucf +++ b/usrp2/top/u1plus/u1plus.ucf @@ -18,14 +18,14 @@ NET "cgen_ref_sel" LOC = "T2" ; NET "cgen_sync_b" LOC = "H15" ; ## FPGA Config -NET "fpga_cfg_din" LOC = "T14" ; -NET "fpga_cfg_cclk" LOC = "R14" ; -NET "fpga_cfg_init_b" LOC = "T12" ; +#NET "fpga_cfg_din" LOC = "T14" ; +#NET "fpga_cfg_cclk" LOC = "R14" ; +#NET "fpga_cfg_init_b" LOC = "T12" ; ## MISC -NET "mystery_bus<2>" LOC = "T11" ; -NET "mystery_bus<1>" LOC = "C4" ; -NET "mystery_bus<0>" LOC = "E7" ; +#NET "mystery_bus<2>" LOC = "T11" ; +#NET "mystery_bus<1>" LOC = "C4" ; +#NET "mystery_bus<0>" LOC = "E7" ; NET "reset_n" LOC = "D5" ; NET "PPS_IN" LOC = "M14" ; NET "reset_codec" LOC = "B14" ; @@ -175,9 +175,9 @@ NET "io_rx<14>" LOC = "A14" ; NET "io_rx<15>" LOC = "A13" ; ## SPI -NET "SEN_AUX" LOC = "C12" ; -NET "SCLK_AUX" LOC = "D12" ; -NET "MISO_AUX" LOC = "J5" ; +#NET "SEN_AUX" LOC = "C12" ; +#NET "SCLK_AUX" LOC = "D12" ; +#NET "MISO_AUX" LOC = "J5" ; NET "SCLK_CODEC" LOC = "K3" ; NET "SEN_CODEC" LOC = "D13" ; NET "MOSI_CODEC" LOC = "C13" ; diff --git a/usrp2/top/u1plus/u1plus.v b/usrp2/top/u1plus/u1plus.v index cb5fbdd36..6ed478420 100644 --- a/usrp2/top/u1plus/u1plus.v +++ b/usrp2/top/u1plus/u1plus.v @@ -1,141 +1,153 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// module u1plus - (input CLK_FPGA_P, input CLK_FPGA_N, // Main Clock - output FPGA_TXD, input FPGA_RXD, // UART - inout SDA_FPGA, inout SCL_FPGA, // I2C + (input CLK_FPGA_P, input CLK_FPGA_N, // Diff + output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + output FPGA_TXD, input FPGA_RXD, - // CGEN - input cgen_st_ld, - input cgen_st_refmon, - input cgen_st_status, - input cgen_ref_sel, - input cgen_sync_b, - - // FPGA Config - input fpga_cfg_din, - input fpga_cfg_cclk, - input fpga_cfg_init_b, - - // MISC - input [2:0] mystery_bus, - input reset_n, - input PPS_IN, - output reset_codec, - // GPIF - inout [15:0] GPIF_D, - input [3:0] GPIF_CTL, - output [3:0] GPIF_RDY, - input FX2_PA7_FLAGD, - input FX2_PA6_PKTEND, - input FX2_PA2_SLOE, + inout [15:0] GPIF_D, input [3:0] GPIF_CTL, output [3:0] GPIF_RDY, + input FX2_PA7_FLAGD, input FX2_PA6_PKTEND, input FX2_PA2_SLOE, input IFCLK, - output [2:0] debug_led, + inout SDA_FPGA, inout SCL_FPGA, // I2C - // Debug bus - output [1:0] debug_clk, - output [31:0] debug, - - input [11:0] adc, - input RXSYNC, - - output TXBLANK, - output TXSYNC, - output [13:0] dac, + output SCLK_TX_DB, output SEN_TX_DB, output MOSI_TX_DB, input MISO_TX_DB, // DB TX SPI + output SCLK_RX_DB, output SEN_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, // DB TX SPI + output SCLK_CODEC, output SEN_CODEC, output MOSI_CODEC, input MISO_CODEC, // AD9862 main SPI - // TX DB - inout [15:0] io_tx, - inout [15:0] io_rx, + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, + + inout [15:0] io_tx, inout [15:0] io_rx, - // SPI - output SEN_AUX, output SCLK_AUX, input MISO_AUX, - output SEN_CODEC, output SCLK_CODEC, output MOSI_CODEC, input MISO_CODEC, - output SEN_RX_DB, output SCLK_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, - output SEN_TX_DB, output SCLK_TX_DB, output MOSI_TX_DB, input MISO_TX_DB + output [13:0] dac, output TXSYNC, output TXBLANK, + input [11:0] adc, input RXSYNC, + + input PPS_IN ); - wire clk_fpga, sys_clk, wb_clk, dcm_out, clk_div, dcm_locked; + // ///////////////////////////////////////////////////////////////////////// + // Clocking + wire clk_fpga, clk_fpga_in, reset; + + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) + clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + + BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga)); - IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + reset_sync reset_sync(.clk(clk_fpga), .reset_in(~reset_n), .reset_out(reset)); - DCM DCM_INST (.CLKFB(sys_clk), - .CLKIN(clk_fpga), - .DSSEN(0), - .PSCLK(0), - .PSEN(0), - .PSINCDEC(0), - .RST(dcm_rst), - .CLKDV(clk_div), - .CLKFX(), - .CLKFX180(), - .CLK0(dcm_out), - .CLK2X(), - .CLK2X180(), - .CLK90(), - .CLK180(), - .CLK270(), - .LOCKED(dcm_locked), - .PSDONE(), - .STATUS()); - defparam DCM_INST.CLK_FEEDBACK = "1X"; - defparam DCM_INST.CLKDV_DIVIDE = 2.0; - defparam DCM_INST.CLKFX_DIVIDE = 1; - defparam DCM_INST.CLKFX_MULTIPLY = 4; - defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; - defparam DCM_INST.CLKIN_PERIOD = 15.625; - defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; - defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; - defparam DCM_INST.FACTORY_JF = 16'h8080; - defparam DCM_INST.PHASE_SHIFT = 0; - defparam DCM_INST.STARTUP_WAIT = "FALSE"; + // ///////////////////////////////////////////////////////////////////////// + // SPI + wire mosi, sclk, miso; + assign { SCLK_TX_DB, MOSI_TX_DB } = ~SEN_TX_DB ? {sclk,mosi} : 2'b0; + assign { SCLK_RX_DB, MOSI_RX_DB } = ~SEN_RX_DB ? {sclk,mosi} : 2'b0; + assign { SCLK_CODEC, MOSI_CODEC } = ~SEN_CODEC ? {sclk,mosi} : 2'b0; + assign miso = (~SEN_TX_DB & MISO_TX_DB) | (~SEN_RX_DB & MISO_RX_DB) | + (~SEN_CODEC & MISO_CODEC); + + // ///////////////////////////////////////////////////////////////////////// + // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL + + assign TXBLANK = 0; + wire [13:0] tx_i, tx_q; - BUFG sysclk_BUFG (.I(dcm_out), .O(sys_clk)); - BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + genvar i; + generate + for(i=0;i<14;i=i+1) + begin : gen_dacout + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_inst (.Q(dac[i]), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(tx_i[i]), // 1-bit data input (associated with C0) + .D1(tx_q[i]), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + end // block: gen_dacout + endgenerate + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(1'b0), // 1-bit data input (associated with C0) + .D1(1'b1), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input - IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); - IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + // ///////////////////////////////////////////////////////////////////////// + // RX ADC -- handles deinterleaving - wire mosi, miso, sclk; - assign SCLK_AUX = ~SEN_AUX ? sclk : 2'b00; - assign {SCLK_CODEC,MOSI_CODEC} = ~SEN_CODEC ? {sclk,mosi} : 2'b00; - assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'b00; - assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'b00; - assign miso = (~SEN_CODEC & MISO_CODEC) | (~SEN_AUX & MISO_AUX) | - (~SEN_RX_DB & MISO_RX_DB) |(~SEN_TX_DB & MISO_TX_DB); + reg [11:0] rx_i, rx_q; + wire [11:0] rx_a, rx_b; - u1_core u1_core - (.sys_clk(sys_clk), .sys_rst(sys_rst), - .wb_clk(wb_clk), .wb_rst(wb_rst), - .uart_tx_o(FPGA_TXD), .uart_rx_i(FPGA_RXD), .uart_baud_o(), - - .leds(debug_led), .debug(debug), .debug_clk(debug_clk), - - .scl_pad_i(scl_pad_i), .scl_pad_o(scl_pad_o), .scl_pad_oen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i), .sda_pad_o(sda_pad_o), .sda_pad_oen_o(sda_pad_oen_o), - - .pps(PPS_IN), - .reset_codec(reset_codec), - - // GPIF - .gpif_clk(IFCLK), .gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_rdy(GPIF_RDY), - .gpif_misc({FX2_PA7_FLAGD, FX2_PA6_PKTEND, FX2_PA2_SLOE}), - - .adc(adc), .rxsync(RXSYNC), - - .txblank(TXBLANK), .txsync(TXSYNC), .dac(dac), - - .io_tx(io_tx), .io_rx(io_rx), - - // SPI - .sclk(sclk), .mosi(mosi), .miso(miso), .sen({SEN_AUX, SEN_CODEC, SEN_RX_DB, SEN_TX_DB}), - .sim_mode(0) - ); + genvar j; + generate + for(j=0;j<12;j=j+1) + begin : gen_adcin + IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1 + .INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + IDDR2_inst (.Q0(rx_a[j]), // 1-bit output captured with C0 clock + .Q1(rx_b[j]), // 1-bit output captured with C1 clock + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D(adc[j]), // 1-bit DDR data input + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + end // block: gen_adcin + endgenerate + + IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1 + .INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + IDDR2_sync (.Q0(rxsync_0), // 1-bit output captured with C0 clock + .Q1(rxsync_1), // 1-bit output captured with C1 clock + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D(RXSYNC), // 1-bit DDR data input + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input -endmodule // u1plus + always @(posedge clk_fpga) + if(rxsync_0) + begin + rx_i <= rx_a; + rx_q <= rx_b; + end + else + begin + rx_i <= rx_b; + rx_q <= rx_a; + end + + // ///////////////////////////////////////////////////////////////////////// + // Main U1E Core + u1plus_core u1p_c(.clk_fpga(clk_fpga), .rst_fpga(reset), + .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), + .gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_rdy(GPIF_RDY), + .gpif_misc({FX2_PA7_FLAGD,FX_PA6_PKTEND,FX2_PA2_SLOE}), + .gpif_clk(IFCLK), + .db_sda(db_sda), .db_scl(db_scl), + .sclk(sclk), .sen({SEN_CODEC,SEN_TX_DB,SEN_RX_DB}), .mosi(mosi), .miso(miso), + .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), + .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel), + .io_tx(io_tx), .io_rx(io_rx), + .tx_i(tx_i), .tx_q(tx_q), + .rx_i(rx_i), .rx_q(rx_q), + .pps_in(PPS_IN) ); +endmodule // u1plus diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v new file mode 100644 index 000000000..bcfb0a5fe --- /dev/null +++ b/usrp2/top/u1plus/u1plus_core.v @@ -0,0 +1,424 @@ + + +//`define LOOPBACK 1 +//`define TIMED 1 +`define DSP 1 + +module u1plus_core + (input clk_fpga, input rst_fpga, + output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + output debug_txd, input debug_rxd, + + // GPIF + inout [15:0] gpif_d, input [3:0] gpif_ctl, output [3:0] gpif_rdy, + input [2:0] gpif_misc, input gpif_clk, + + inout db_sda, inout db_scl, + output sclk, output [7:0] sen, output mosi, input miso, + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, + inout [15:0] io_tx, inout [15:0] io_rx, + output [13:0] tx_i, output [13:0] tx_q, + input [11:0] rx_i, input [11:0] rx_q, + input pps_in + ); + + localparam TXFIFOSIZE = 11; + localparam RXFIFOSIZE = 11; + + localparam SR_RX_DSP = 0; // 5 regs + localparam SR_RX_CTRL = 8; // 9 regs + localparam SR_TX_DSP = 17; // 5 regs + localparam SR_TX_CTRL = 24; // 2 regs + localparam SR_TIME64 = 28; // 4 regs + + wire wb_clk = clk_fpga; + wire wb_rst = rst_fpga; + + wire pps_int; + wire [63:0] vita_time; + reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; + + wire [7:0] set_addr; + wire [31:0] set_data; + wire set_stb; + + // ///////////////////////////////////////////////////////////////////////////////////// + // GPMC Slave to Wishbone Master + localparam dw = 16; + localparam aw = 11; + localparam sw = 2; + + wire [dw-1:0] m0_dat_mosi, m0_dat_miso; + wire [aw-1:0] m0_adr; + wire [sw-1:0] m0_sel; + wire m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty; + + wire [31:0] debug_gpmc; + + wire [35:0] tx_data, rx_data; + wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy; + reg [15:0] tx_frame_len; + wire [15:0] rx_frame_len; + wire [7:0] rate; + + wire bus_error; + + gpif #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE)) + gpif (.arst(wb_rst), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), + .EM_NOE(EM_NOE), + + .rx_have_data(rx_have_data), .tx_have_space(tx_have_space), + .bus_error(bus_error), .bus_reset(0), + + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), + .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), + .wb_ack_i(m0_ack), + + .fifo_clk(wb_clk), .fifo_rst(wb_rst), + .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), + .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), + + .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), + .debug(debug_gpmc)); + + wire rx_sof = rx_data[32]; + wire rx_eof = rx_data[33]; + wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int; + +`ifdef LOOPBACK + fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), + .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); +`endif // LOOPBACK + +`ifdef TIMED + + // TX side + wire tx_enable; + + fifo_pacer tx_pacer + (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(tx_enable), + .src1_rdy_i(tx_src_rdy), .dst1_rdy_o(tx_dst_rdy), + .src2_rdy_o(tx_src_rdy_int), .dst2_rdy_i(tx_dst_rdy_int), + .underrun(tx_underrun), .overrun()); + + packet_verifier32 pktver32 + (.clk(wb_clk), .reset(wb_rst), .clear(clear), + .data_i(tx_data), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + + // RX side + wire rx_enable; + + packet_generator32 pktgen32 + (.clk(wb_clk), .reset(wb_rst), .clear(clear), + .data_o(rx_data), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int)); + + fifo_pacer rx_pacer + (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(rx_enable), + .src1_rdy_i(rx_src_rdy_int), .dst1_rdy_o(rx_dst_rdy_int), + .src2_rdy_o(rx_src_rdy), .dst2_rdy_i(rx_dst_rdy), + .underrun(), .overrun(rx_overrun)); + +`endif // `ifdef TIMED + +`ifdef DSP + wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug; + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX + wire [31:0] sample_rx, sample_tx; + wire strobe_rx, strobe_tx; + wire rx1_dst_rdy, rx1_src_rdy; + wire [99:0] rx1_data; + wire run_rx; + + + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx + (.clk(wb_clk),.rst(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a({rx_i,2'b0}),.adc_ovf_a(0),.adc_b({rx_q,2'b0}),.adc_ovf_b(0), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time), .overrun(overrun), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy), + .debug_rx(vrc_debug)); + + vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy), + .data_o(rx_data), .dst_rdy_i(rx_dst_rdy), .src_rdy_o(rx_src_rdy), + .fifo_occupied(), .fifo_full(), .fifo_empty(), + .debug_rx(vrf_debug) ); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [99:0] tx1_data; + wire tx1_src_rdy, tx1_dst_rdy; + wire [15:0] tx_i_int, tx_q_int; + wire [31:0] debug_vtc, debug_vtd, debug_vt; + wire run_tx; + + vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), + .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), + .debug(debug_vtd) ); + + vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time),.underrun(underrun), + .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .debug(debug_vtc) ); + + dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx + (.clk(wb_clk),.rst(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .dac_a(tx_i_int),.dac_b(tx_q_int), + .debug(debug_tx_dsp) ); + + assign tx_i = tx_i_int[15:2]; + assign tx_q = tx_q_int[15:2]; + +`else // !`ifdef DSP + // Dummy DSP signal generator for test purposes + wire [23:0] tx_i_int, tx_q_int; + wire [23:0] freq = {reg_test,8'd0}; + reg [23:0] phase; + + always @(posedge wb_clk) + phase <= phase + freq; + + cordic_z24 #(.bitwidth(24)) tx_cordic + (.clock(wb_clk), .reset(wb_rst), .enable(1), + .xi(24'd2500000), .yi(24'd0), .zi(phase), .xo(tx_i_int), .yo(tx_q_int), .zo()); + + assign tx_i = tx_i_int[23:10]; + assign tx_q = tx_q_int[23:10]; +`endif // !`ifdef DSP + + // ///////////////////////////////////////////////////////////////////////////////////// + // Wishbone Intercon, single master + wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, + s4_dat_mosi, s5_dat_mosi, s4_dat_miso, s5_dat_miso, s6_dat_mosi, s7_dat_mosi, s6_dat_miso, s7_dat_miso, + s8_dat_mosi, s9_dat_mosi, s8_dat_miso, s9_dat_miso, sa_dat_mosi, sb_dat_mosi, sa_dat_miso, sb_dat_miso, + sc_dat_mosi, sd_dat_mosi, sc_dat_miso, sd_dat_miso, se_dat_mosi, sf_dat_mosi, se_dat_miso, sf_dat_miso; + wire [aw-1:0] s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr; + wire [aw-1:0] s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; + wire [sw-1:0] s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel; + wire [sw-1:0] s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; + wire s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack; + wire s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; + wire s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb; + wire s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; + wire s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc; + wire s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; + wire s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we; + wire s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we, sf_we; + + wb_1master #(.dw(dw), .aw(aw), .sw(sw), .decode_w(4), + .s0_addr(4'h0), .s0_mask(4'hF), .s1_addr(4'h1), .s1_mask(4'hF), + .s2_addr(4'h2), .s2_mask(4'hF), .s3_addr(4'h3), .s3_mask(4'hF), + .s4_addr(4'h4), .s4_mask(4'hF), .s5_addr(4'h5), .s5_mask(4'hF), + .s6_addr(4'h6), .s6_mask(4'hF), .s7_addr(4'h7), .s7_mask(4'hF), + .s8_addr(4'h8), .s8_mask(4'hF), .s9_addr(4'h9), .s9_mask(4'hF), + .sa_addr(4'ha), .sa_mask(4'hF), .sb_addr(4'hb), .sb_mask(4'hF), + .sc_addr(4'hc), .sc_mask(4'hF), .sd_addr(4'hd), .sd_mask(4'hF), + .se_addr(4'he), .se_mask(4'hF), .sf_addr(4'hf), .sf_mask(4'hF)) + wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_miso),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_mosi), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_mosi),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_miso),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_mosi),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_miso),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_mosi),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_miso),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_mosi),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_miso),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_mosi),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_miso),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_mosi),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_miso),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_mosi),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_miso),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_mosi),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_miso),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_mosi),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_miso),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_mosi),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_miso),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_mosi),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_miso),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_mosi),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_miso),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_mosi),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_miso),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_mosi),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_miso),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_mosi),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_miso),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), + .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); + + assign s7_ack = 0; + assign s8_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; + assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 0, Misc LEDs, Switches, controls + + localparam REG_LEDS = 7'd0; // out + localparam REG_SWITCHES = 7'd2; // in + localparam REG_CGEN_CTRL = 7'd4; // out + localparam REG_CGEN_ST = 7'd6; // in + localparam REG_TEST = 7'd8; // out + localparam REG_RX_FRAMELEN = 7'd10; // out + localparam REG_TX_FRAMELEN = 7'd12; // in + localparam REG_XFER_RATE = 7'd14; // in + + always @(posedge wb_clk) + if(wb_rst) + begin + reg_leds <= 0; + reg_cgen_ctrl <= 2'b11; + reg_test <= 0; + tx_frame_len <= 0; + xfer_rate <= 0; + end + else + if(s0_cyc & s0_stb & s0_we) + case(s0_adr[6:0]) + REG_LEDS : + reg_leds <= s0_dat_mosi; + REG_CGEN_CTRL : + reg_cgen_ctrl <= s0_dat_mosi; + REG_TEST : + reg_test <= s0_dat_mosi; + REG_TX_FRAMELEN : + tx_frame_len <= s0_dat_mosi; + REG_XFER_RATE : + xfer_rate <= s0_dat_mosi; + endcase // case (s0_adr[6:0]) + + assign tx_enable = xfer_rate[15]; + assign rx_enable = xfer_rate[14]; + assign rate = xfer_rate[7:0]; + + assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board + assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; + //assign { rx_overrun, tx_underrun } = 0; // reg_test; + + assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : + //(s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : + (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : + (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : + (s0_adr[6:0] == REG_TEST) ? reg_test : + (s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len : + 16'hBEEF; + + assign s0_ack = s0_stb & s0_cyc; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 1, UART + // depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack), + .adr_i(s1_adr[3:1]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso), + .rx_int_o(),.tx_int_o(), + .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o()); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 2, SPI + + spi_top16 shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_mosi), + .wb_dat_o(s2_dat_miso),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(), + .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // Slave 3, I2C + + wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o; + i2c_master_top #(.ARST_LVL(1)) i2c + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_miso[15:8] = 8'd0; + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + + wire [31:0] atr_lines; + wire [31:0] debug_gpio_0, debug_gpio_1; + + nsgpio16LE + nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio( {io_tx,io_rx} ) ); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #5 + + // only have 32 regs, 32 bits each with current setup... + settings_bus_16LE #(.AWIDTH(11),.RWIDTH(11-4-2)) settings_bus_16LE + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s5_adr),.wb_dat_i(s5_dat_mosi), + .wb_stb_i(s5_stb),.wb_we_i(s5_we),.wb_ack_o(s5_ack), + .strobe(set_stb),.addr(set_addr),.data(set_data) ); + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller -- Slave #6 + + atr_controller16 atr_controller16 + (.clk_i(wb_clk), .rst_i(wb_rst), + .adr_i(s6_adr), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), + .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), + .run_rx(0), .run_tx(0), .ctrl_lines(atr_lines)); + + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing + + time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit + (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Debug circuitry + + assign debug_clk = { 1'b0, clk_fpga }; + assign debug = 0; + assign debug_gpio_0 = 0; + assign debug_gpio_1 = 0; + +endmodule // u1plus_core -- cgit v1.2.3 From e25f67d54ad40479415a5208b8f9a4739a79df30 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 14 Jun 2010 14:29:11 -0700 Subject: skeleton --- usrp2/gpif/gpif.v | 122 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 usrp2/gpif/gpif.v diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v new file mode 100644 index 000000000..2da6daa66 --- /dev/null +++ b/usrp2/gpif/gpif.v @@ -0,0 +1,122 @@ +////////////////////////////////////////////////////////////////////////////////// + +module gpif + #(parameter TXFIFOSIZE = 11, parameter RXFIFOSIZE = 11) + (// GPIF signals + input gpif_clk, + inout [15:0] gpif_d, input [3:0] gpif_ctl, output [3:0] gpif_rdy, + input [2:0] gpif_misc, + + // Wishbone signals + input wb_clk, input wb_rst, + output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + + // FIFO interface + input fifo_clk, input fifo_rst, + output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, + input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, + + input [15:0] tx_frame_len, output [15:0] rx_frame_len, + + output [31:0] debug + ); + + wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); + wire [15:0] EM_D_fifo; + wire [15:0] EM_D_wb; + + wire bus_error_tx, bus_error_rx; + + always @(posedge fifo_clk) + if(fifo_rst) + bus_error <= 0; + else + bus_error <= bus_error_tx | bus_error_rx; + + // CS4 is RAM_2PORT for DATA PATH (high-speed data) + // Writes go into one RAM, reads come from the other + // CS6 is for CONTROL PATH (wishbone) + + // //////////////////////////////////////////// + // TX Data Path + + wire [17:0] tx18_data, tx18b_data; + wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; + wire [15:0] tx_fifo_space; + wire [35:0] tx36_data; + wire tx36_src_rdy, tx36_dst_rdy; + + gpmc_to_fifo_async gpmc_to_fifo_async + (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), + .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), + .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), + .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space), + .bus_error(bus_error_tx) ); + + fifo_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), + .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied()); + + fifo19_to_fifo36 #(.LE(1)) f19_to_f36 // Little endian because ARM is LE + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), + .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); + + fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy), + .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i)); + + // //////////////////////////////////////////// + // RX Data Path + + wire [17:0] rx18_data, rx18b_data; + wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; + wire [15:0] rx_fifo_space; + wire [35:0] rx36_data; + wire rx36_src_rdy, rx36_dst_rdy; + wire dummy; + + fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), + .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); + + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), + .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); + + fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .datain(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space), + .dataout(rx18b_data), .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied()); + + fifo_to_gpmc_async fifo_to_gpmc_async + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy), + .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), + .frame_len(rx_frame_len) ); + + fifo_watcher fifo_watcher + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .src_rdy1(rx18_src_rdy), .dst_rdy1(rx18_dst_rdy), .sof1(rx18_data[16]), .eof1(rx18_data[17]), + .src_rdy2(rx18b_src_rdy), .dst_rdy2(rx18b_dst_rdy), .sof2(rx18b_data[16]), .eof2(rx18b_data[17]), + .have_packet(rx_have_data), .length(rx_frame_len), .bus_error(bus_error_rx) ); + + // //////////////////////////////////////////// + // Control path on CS6 + + gpmc_wb gpmc_wb + (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), + .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), + .wb_ack_i(wb_ack_i) ); + + assign debug = 0; + +endmodule // gpmc_async -- cgit v1.2.3 From 014ea68739c616836bcdfce292c8ab89da26afad Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 14 Jun 2010 16:14:30 -0700 Subject: gpif skeletons --- usrp2/gpif/Makefile.srcs | 12 ++++ usrp2/gpif/gpif.v | 16 +++++ usrp2/gpif/gpif_rd.v | 5 ++ usrp2/gpif/gpif_wr.v | 47 +++++++++++++ usrp2/top/u1plus/Makefile | 151 +++++++---------------------------------- usrp2/top/u1plus/u1plus.v | 5 +- usrp2/top/u1plus/u1plus_core.v | 9 +-- 7 files changed, 111 insertions(+), 134 deletions(-) create mode 100644 usrp2/gpif/Makefile.srcs create mode 100644 usrp2/gpif/gpif_rd.v create mode 100644 usrp2/gpif/gpif_wr.v diff --git a/usrp2/gpif/Makefile.srcs b/usrp2/gpif/Makefile.srcs new file mode 100644 index 000000000..9bcbb29f3 --- /dev/null +++ b/usrp2/gpif/Makefile.srcs @@ -0,0 +1,12 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# SERDES Sources +################################################## +GPIF_SRCS = $(abspath $(addprefix $(BASE_DIR)/../gpif/, \ +gpif.v \ +gpif_wr.v \ +gpif_rd.v \ +)) diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index 2da6daa66..9609a5000 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -22,6 +22,21 @@ module gpif output [31:0] debug ); + wire WR = gpif_ctl[0]; + wire RD = gpif_ctl[1]; + wire OE = gpif_ctl[2]; + + gpif_wr gpif_wr + (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), + .gpif_data(), .WR(WR), .have_space(gpif_rdy[0]), + .sys_clk(sys_clk), .sys_rst(sys_rst), + .data_o(data_o), .src_rdy_o(), .dst_rdy_i(), + .debug() ); + + +endmodule // gpif + +/* wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); wire [15:0] EM_D_fifo; wire [15:0] EM_D_wb; @@ -120,3 +135,4 @@ module gpif assign debug = 0; endmodule // gpmc_async +*/ diff --git a/usrp2/gpif/gpif_rd.v b/usrp2/gpif/gpif_rd.v new file mode 100644 index 000000000..f716d4a5d --- /dev/null +++ b/usrp2/gpif/gpif_rd.v @@ -0,0 +1,5 @@ + +module gpif_rd + (); + +endmodule // gpif_rd diff --git a/usrp2/gpif/gpif_wr.v b/usrp2/gpif/gpif_wr.v new file mode 100644 index 000000000..c5cdc7597 --- /dev/null +++ b/usrp2/gpif/gpif_wr.v @@ -0,0 +1,47 @@ + +module gpif_wr + (input gpif_clk, input gpif_rst, + input [15:0] gpif_data, input WR, + output reg have_space, + + input sys_clk, input sys_rst, + output [19:0] data_o, output src_rdy_o, input dst_rdy_i, + output [31:0] debug ); + + reg wr_reg; + reg [15:0] gpif_data_reg; + + always @(posedge gpif_clk) + begin + wr_reg <= WR; + gpif_data_reg <= gpif_data; + end + + reg [9:0] write_count; + + always @(posedge gpif_clk) + if(gpif_rst) + write_count <= 0; + else if(wr_reg) + write_count <= write_count + 1; + else + write_count <= 0; + + reg sop; + wire occ = 0; + wire eop = (write_count == 255); + + always @(posedge gpif_clk) + sop <= WR & ~wr_reg; + + wire [15:0] fifo_space; + always @(posedge gpif_clk) + have_space <= fifo_space > 256; + + fifo_2clock_cascade #(.WIDTH(19), .SIZE(9)) wr_fifo + (.wclk(gpif_clk), .datain({occ,eop,sop,gpif_data_reg}), + .src_rdy_i(wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space), + .rclk(sys_clk), .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(), + .arst(sys_rst)); + +endmodule // gpif_wr diff --git a/usrp2/top/u1plus/Makefile b/usrp2/top/u1plus/Makefile index 684b7bcd7..74d747acf 100644 --- a/usrp2/top/u1plus/Makefile +++ b/usrp2/top/u1plus/Makefile @@ -33,6 +33,20 @@ BUILD_DIR := build/ export TOP_MODULE := u1plus export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extram/Makefile.srcs +include ../../gpif/Makefile.srcs + ################################################## # Project Properties ################################################## @@ -51,132 +65,17 @@ simulator "ISE Simulator (VHDL/Verilog)" \ ################################################## # Sources ################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -control_lib/CRC16_D16.v \ -control_lib/atr_controller16.v \ -control_lib/bin2gray.v \ -control_lib/dcache.v \ -control_lib/decoder_3_8.v \ -control_lib/dpram32.v \ -control_lib/gray2bin.v \ -control_lib/gray_send.v \ -control_lib/icache.v \ -control_lib/mux4.v \ -control_lib/mux8.v \ -control_lib/nsgpio16LE.v \ -control_lib/ram_2port.v \ -control_lib/ram_2port_mixed_width.v \ -control_lib/ram_harv_cache.v \ -control_lib/ram_loader.v \ -control_lib/setting_reg.v \ -control_lib/settings_bus_16LE.v \ -control_lib/srl.v \ -control_lib/system_control.v \ -control_lib/wb_1master.v \ -control_lib/wb_readback_mux.v \ -control_lib/simple_uart.v \ -control_lib/simple_uart_tx.v \ -control_lib/simple_uart_rx.v \ -control_lib/oneshot_2clk.v \ -control_lib/sd_spi.v \ -control_lib/sd_spi_wb.v \ -control_lib/wb_bridge_16_32.v \ -control_lib/reset_sync.v \ -control_lib/newfifo/buffer_int.v \ -control_lib/newfifo/buffer_pool.v \ -control_lib/newfifo/fifo_2clock.v \ -control_lib/newfifo/fifo_2clock_cascade.v \ -control_lib/newfifo/ll8_shortfifo.v \ -control_lib/newfifo/ll8_to_fifo36.v \ -control_lib/newfifo/fifo_short.v \ -control_lib/newfifo/fifo_long.v \ -control_lib/newfifo/fifo_cascade.v \ -control_lib/newfifo/fifo36_to_ll8.v \ -control_lib/newfifo/fifo36_to_fifo19.v \ -control_lib/newfifo/fifo19_to_fifo36.v \ -control_lib/newfifo/packet_generator.v \ -control_lib/newfifo/packet_verifier.v \ -control_lib/newfifo/packet_generator32.v \ -control_lib/newfifo/packet_verifier32.v \ -control_lib/newfifo/fifo_pacer.v \ -control_lib/longfifo.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ -control_lib/priority_enc.v \ -control_lib/pic.v \ -coregen/fifo_xlnx_2Kx36_2clk.v \ -coregen/fifo_xlnx_2Kx36_2clk.xco \ -coregen/fifo_xlnx_512x36_2clk.v \ -coregen/fifo_xlnx_512x36_2clk.xco \ -coregen/fifo_xlnx_64x36_2clk.v \ -coregen/fifo_xlnx_64x36_2clk.xco \ -extram/wb_zbt16_b.v \ -opencores/8b10b/decode_8b10b.v \ -opencores/8b10b/encode_8b10b.v \ -opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -opencores/aemb/rtl/verilog/aeMB_core_BE.v \ -opencores/aemb/rtl/verilog/aeMB_ctrl.v \ -opencores/aemb/rtl/verilog/aeMB_edk32.v \ -opencores/aemb/rtl/verilog/aeMB_ibuf.v \ -opencores/aemb/rtl/verilog/aeMB_regf.v \ -opencores/aemb/rtl/verilog/aeMB_xecu.v \ -opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_defines.v \ -opencores/i2c/rtl/verilog/i2c_master_top.v \ -opencores/i2c/rtl/verilog/timescale.v \ -opencores/simple_pic/rtl/simple_pic.v \ -opencores/spi/rtl/verilog/spi_clgen.v \ -opencores/spi/rtl/verilog/spi_defines.v \ -opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top16.v \ -sdr_lib/acc.v \ -sdr_lib/add2.v \ -sdr_lib/add2_and_round.v \ -sdr_lib/add2_and_round_reg.v \ -sdr_lib/add2_reg.v \ -sdr_lib/cic_dec_shifter.v \ -sdr_lib/cic_decim.v \ -sdr_lib/cic_int_shifter.v \ -sdr_lib/cic_interp.v \ -sdr_lib/cic_strober.v \ -sdr_lib/clip.v \ -sdr_lib/clip_reg.v \ -sdr_lib/cordic.v \ -sdr_lib/cordic_z24.v \ -sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_rx_udp.v \ -sdr_lib/dsp_core_tx.v \ -sdr_lib/hb_dec.v \ -sdr_lib/hb_interp.v \ -sdr_lib/round.v \ -sdr_lib/round_reg.v \ -sdr_lib/rx_control.v \ -sdr_lib/rx_dcoffset.v \ -sdr_lib/sign_extend.v \ -sdr_lib/small_hb_dec.v \ -sdr_lib/small_hb_int.v \ -sdr_lib/tx_control.v \ -serdes/serdes.v \ -serdes/serdes_fc_rx.v \ -serdes/serdes_fc_tx.v \ -serdes/serdes_rx.v \ -serdes/serdes_tx.v \ -timing/time_receiver.v \ -timing/time_sender.v \ -timing/time_sync.v \ -timing/timer.v \ -timing/time_64bit.v \ -vrt/vita_rx_control.v \ -vrt/vita_rx_framer.v \ -vrt/vita_tx_control.v \ -vrt/vita_tx_deframer.v \ -timing/time_compare.v \ -top/u1plus/u1plus_core.v \ -top/u1plus/u1plus.ucf \ -top/u1plus/timing.ucf \ -top/u1plus/u1plus.v +TOP_SRCS = \ +u1plus.v \ +u1plus_core.v \ +u1plus.ucf \ +timing.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ +$(GPIF_SRCS) ################################################## # Process Properties diff --git a/usrp2/top/u1plus/u1plus.v b/usrp2/top/u1plus/u1plus.v index 6ed478420..370d3e4ea 100644 --- a/usrp2/top/u1plus/u1plus.v +++ b/usrp2/top/u1plus/u1plus.v @@ -24,9 +24,12 @@ module u1plus output [13:0] dac, output TXSYNC, output TXBLANK, input [11:0] adc, input RXSYNC, - input PPS_IN + input PPS_IN, + input reset_n, output reset_codec ); + assign reset_codec = 1; // Believed to be active low + // ///////////////////////////////////////////////////////////////////////// // Clocking wire clk_fpga, clk_fpga_in, reset; diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index bcfb0a5fe..c2718de20 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -65,13 +65,8 @@ module u1plus_core wire bus_error; gpif #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE)) - gpif (.arst(wb_rst), - .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), - .EM_NOE(EM_NOE), - - .rx_have_data(rx_have_data), .tx_have_space(tx_have_space), - .bus_error(bus_error), .bus_reset(0), + gpif (.gpif_clk(gpif_clk), .gpif_d(gpif_d), .gpif_ctl(gpif_ctl), + .gpif_rdy(gpif_rdy), .gpif_misc(gpif_misc), .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), -- cgit v1.2.3 From 2d67e1453a47a54cf2c9ae651fc7c03d0292ab68 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 1 Jul 2010 00:45:20 -0700 Subject: progress on gpif interface --- usrp2/gpif/gpif.v | 151 +++++++++++++++++------------------------ usrp2/gpif/gpif_rd.v | 40 ++++++++++- usrp2/gpif/gpif_wr.v | 28 +++++--- usrp2/top/u1plus/u1plus_core.v | 10 +-- 4 files changed, 119 insertions(+), 110 deletions(-) diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index 9609a5000..bd813126f 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -17,122 +17,93 @@ module gpif output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, - input [15:0] tx_frame_len, output [15:0] rx_frame_len, - output [31:0] debug ); wire WR = gpif_ctl[0]; wire RD = gpif_ctl[1]; wire OE = gpif_ctl[2]; - - gpif_wr gpif_wr - (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), - .gpif_data(), .WR(WR), .have_space(gpif_rdy[0]), - .sys_clk(sys_clk), .sys_rst(sys_rst), - .data_o(data_o), .src_rdy_o(), .dst_rdy_i(), - .debug() ); - - -endmodule // gpif -/* - wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); - wire [15:0] EM_D_fifo; - wire [15:0] EM_D_wb; + wire [15:0] gpif_dat_out; + assign gpif_dat = OE ? gpif_dat_out : 16'bz; - wire bus_error_tx, bus_error_rx; + // //////////////////////////////////////////////////////////////////// + // TX Side - always @(posedge fifo_clk) - if(fifo_rst) - bus_error <= 0; - else - bus_error <= bus_error_tx | bus_error_rx; + wire [18:0] tx19_data; + wire tx19_src_rdy, tx19_dst_rdy; + wire [35:0] tx36_data, tx36b_data, tx36c_data; + wire tx36_src_rdy, tx36_dst_rdy, tx36b_src_rdy, tx36b_dst_rdy, tx36c_src_rdy, tx36c_dst_rdy; + wire [35:0] ctrl_data; + wire ctrl_src_rdy, ctrl_dst_rdy; - // CS4 is RAM_2PORT for DATA PATH (high-speed data) - // Writes go into one RAM, reads come from the other - // CS6 is for CONTROL PATH (wishbone) - - // //////////////////////////////////////////// - // TX Data Path + gpif_wr gpif_wr + (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), + .gpif_data(gpif_d), .gpif_wr(WR), .have_space(gpif_rdy[0]), + .sys_clk(fifo_clk), .sys_rst(fifo_rst), + .data_o(tx19_data), .src_rdy_o(tx19_src_rdy), .dst_rdy_i(tx_19_dst_rdy), + .debug() ); - wire [17:0] tx18_data, tx18b_data; - wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; - wire [15:0] tx_fifo_space; - wire [35:0] tx36_data; - wire tx36_src_rdy, tx36_dst_rdy; - - gpmc_to_fifo_async gpmc_to_fifo_async - (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), - .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), - .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), - .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space), - .bus_error(bus_error_tx) ); + fifo19_to_fifo36 #(.LE(1)) f19_to_f36 + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .f19_datain(tx19_data), .f19_src_rdy_i(tx19_src_rdy), .f19_dst_rdy_o(tx19_dst_rdy), + .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); - fifo_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo + fifo_short #(.WIDTH(36)) tx_sfifo (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), - .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied()); + .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy), + .dataout(tx36b_data), .src_rdy_o(tx36b_src_rdy), .dst_rdy_i(tx36b_dst_rdy)); - fifo19_to_fifo36 #(.LE(1)) f19_to_f36 // Little endian because ARM is LE + fifo36_demux #(.match_data(32'h1000_0000), .match_mask(32'hF000_0000)) tx_demux (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), - .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); + .data_i(tx36b_data), .src_rdy_i(tx36b_src_rdy), .dst_rdy_o(tx36b_dst_rdy), + .data0_o(ctrl_data), .src0_rdy_o(ctrl_src_rdy), .dst0_rdy_i(ctrl_dst_rdy), + .data1_o(tx36c_data), .src1_rdy_o(tx36c_src_rdy), .dst1_rdy_i(tx36c_dst_rdy)); fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 - (.clk(wb_clk), .reset(wb_rst), .clear(0), - .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy), + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .datain(tx36c_data), .src_rdy_i(tx36c_src_rdy), .dst_rdy_o(tx36c_dst_rdy), .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i)); - // //////////////////////////////////////////// - // RX Data Path - - wire [17:0] rx18_data, rx18b_data; - wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; - wire [15:0] rx_fifo_space; - wire [35:0] rx36_data; - wire rx36_src_rdy, rx36_dst_rdy; - wire dummy; + // //////////////////////////////////////////////////////////////////// + // RX Side + + wire [35:0] rx36_data, rx36b_data, rx36c_data; + wire rx36_src_rdy, rx36_dst_rdy, rx36b_src_rdy, rx36b_dst_rdy, rx36c_src_rdy, rx36c_dst_rdy; + wire [18:0] rx19_data; + wire rx19_src_rdy, rx19_dst_rdy; + wire [35:0] resp_data; + wire resp_src_rdy, resp_dst_rdy; fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 - (.clk(wb_clk), .reset(wb_rst), .clear(0), + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), - .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); + .dataout(rx36c_data), .src_rdy_o(rx36c_src_rdy), .dst_rdy_i(rx36c_dst_rdy)); - fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE + fifo36_mux #(.prio(1)) rx_mux (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), - .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); - - fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo + .data0_i(resp_data), .src0_rdy_i(resp_src_rdy), .dst0_rdy_o(resp_dst_rdy), + .data1_i(rx36c_data), .src1_rdy_i(rx36c_src_rdy), .dst1_rdy_o(rx36c_dst_rdy), + .data_o(rx36b_data), .src_rdy_o(rx36b_src_rdy), .dst_rdy_i(rx36b_dst_rdy)); + + fifo_short #(.WIDTH(36)) rx_sfifo (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .datain(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space), - .dataout(rx18b_data), .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied()); - - fifo_to_gpmc_async fifo_to_gpmc_async + .datain(rx36b_data), .src_rdy_i(rx36b_src_rdy), .dst_rdy_o(rx36b_dst_rdy), + .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); + + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // FIXME Endianness? (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy), - .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), - .frame_len(rx_frame_len) ); + .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), + .f19_dataout(rx19_data), .f19_src_rdy_o(rx19_src_rdy), .f19_dst_rdy_i(rx19_dst_rdy) ); - fifo_watcher fifo_watcher - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .src_rdy1(rx18_src_rdy), .dst_rdy1(rx18_dst_rdy), .sof1(rx18_data[16]), .eof1(rx18_data[17]), - .src_rdy2(rx18b_src_rdy), .dst_rdy2(rx18b_dst_rdy), .sof2(rx18b_data[16]), .eof2(rx18b_data[17]), - .have_packet(rx_have_data), .length(rx_frame_len), .bus_error(bus_error_rx) ); + gpif_rd gpif_rd + (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), + .gpif_data(gpif_dat_out), .gpif_rd(RD), .have_pkt_rdy(have_pkt_rdy), + .sys_clk(fifo_clk), .sys_rst(fifo_rst), + .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy)); + + // //////////////////////////////////////////////////////////////////// + // FIFO to Wishbone interface - // //////////////////////////////////////////// - // Control path on CS6 - - gpmc_wb gpmc_wb - (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), - .wb_clk(wb_clk), .wb_rst(wb_rst), - .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), - .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), - .wb_ack_i(wb_ack_i) ); - - assign debug = 0; -endmodule // gpmc_async -*/ +endmodule // gpif diff --git a/usrp2/gpif/gpif_rd.v b/usrp2/gpif/gpif_rd.v index f716d4a5d..a3167da16 100644 --- a/usrp2/gpif/gpif_rd.v +++ b/usrp2/gpif/gpif_rd.v @@ -1,5 +1,43 @@ module gpif_rd - (); + (input gpif_clk, input gpif_rst, + output [15:0] gpif_data, input gpif_rd, output reg have_pkt_rdy, + + input sys_clk, input sys_rst, + input [18:0] data_i, input src_rdy_i, output dst_rdy_o + ); + + wire [15:0] rxfifolevel; + wire [15:0] data_o; + wire rx_full; + + // USB Read Side of FIFO + always @(negedge gpif_clk) + have_pkt_rdy <= (rxfifolevel >= 256); // FIXME make this more robust + + // 257 Bug Fix + reg [8:0] read_count; + always @(negedge gpif_clk) + if(gpif_rst) + read_count <= 0; + else if(gpif_rd) + read_count <= read_count + 1; + else + read_count <= 0; + + wire [17:0] data_int; + wire src_rdy_int, dst_rdy_int; + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) rd_fifo_2clk + (.wclk(sys_clk), .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(), + .rclk(~gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(), + .arst(sys_rst)); + + fifo_cascade #(.WIDTH(19), .SIZE(9)) rd_fifo + (.clk(~gpif_clk), .reset(gpif_rst), .clear(0), + .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), + .dataout(data_o), .src_rdy_o(), .dst_rdy_i(gpif_rd & ~read_count[8]), .occupied(rxfifolevel)); + + assign gpif_data = data_o[15:0]; endmodule // gpif_rd diff --git a/usrp2/gpif/gpif_wr.v b/usrp2/gpif/gpif_wr.v index c5cdc7597..6a73d1721 100644 --- a/usrp2/gpif/gpif_wr.v +++ b/usrp2/gpif/gpif_wr.v @@ -1,11 +1,11 @@ module gpif_wr (input gpif_clk, input gpif_rst, - input [15:0] gpif_data, input WR, + input [15:0] gpif_data, input gpif_wr, output reg have_space, input sys_clk, input sys_rst, - output [19:0] data_o, output src_rdy_o, input dst_rdy_i, + output [18:0] data_o, output src_rdy_o, input dst_rdy_i, output [31:0] debug ); reg wr_reg; @@ -13,7 +13,7 @@ module gpif_wr always @(posedge gpif_clk) begin - wr_reg <= WR; + wr_reg <= gpif_wr; gpif_data_reg <= gpif_data; end @@ -28,20 +28,28 @@ module gpif_wr write_count <= 0; reg sop; - wire occ = 0; wire eop = (write_count == 255); always @(posedge gpif_clk) - sop <= WR & ~wr_reg; + sop <= gpif_wr & ~wr_reg; wire [15:0] fifo_space; always @(posedge gpif_clk) have_space <= fifo_space > 256; - - fifo_2clock_cascade #(.WIDTH(19), .SIZE(9)) wr_fifo - (.wclk(gpif_clk), .datain({occ,eop,sop,gpif_data_reg}), - .src_rdy_i(wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space), - .rclk(sys_clk), .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(), + + wire [17:0] data_int; + wire src_rdy_int, dst_rdy_int; + + fifo_cascade #(.WIDTH(18), .SIZE(9)) wr_fifo + (.clk(gpif_clk), .reset(gpif_rst), .clear(0), + .datain({eop,sop,gpif_data_reg}), .src_rdy_i(wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space), + .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied()); + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) wr_fifo_2clk + (.wclk(gpif_clk), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), + .rclk(sys_clk), .dataout(data_o[17:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(), .arst(sys_rst)); + + assign data_o[18] = 0; endmodule // gpif_wr diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index c2718de20..3cdc74835 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -44,7 +44,7 @@ module u1plus_core wire set_stb; // ///////////////////////////////////////////////////////////////////////////////////// - // GPMC Slave to Wishbone Master + // GPIF Slave to Wishbone Master localparam dw = 16; localparam aw = 11; localparam sw = 2; @@ -58,8 +58,6 @@ module u1plus_core wire [35:0] tx_data, rx_data; wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy; - reg [15:0] tx_frame_len; - wire [15:0] rx_frame_len; wire [7:0] rate; wire bus_error; @@ -77,7 +75,6 @@ module u1plus_core .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), - .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), .debug(debug_gpmc)); wire rx_sof = rx_data[32]; @@ -295,7 +292,6 @@ module u1plus_core reg_leds <= 0; reg_cgen_ctrl <= 2'b11; reg_test <= 0; - tx_frame_len <= 0; xfer_rate <= 0; end else @@ -307,8 +303,6 @@ module u1plus_core reg_cgen_ctrl <= s0_dat_mosi; REG_TEST : reg_test <= s0_dat_mosi; - REG_TX_FRAMELEN : - tx_frame_len <= s0_dat_mosi; REG_XFER_RATE : xfer_rate <= s0_dat_mosi; endcase // case (s0_adr[6:0]) @@ -319,14 +313,12 @@ module u1plus_core assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; - //assign { rx_overrun, tx_underrun } = 0; // reg_test; assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : //(s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : (s0_adr[6:0] == REG_TEST) ? reg_test : - (s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len : 16'hBEEF; assign s0_ack = s0_stb & s0_cyc; -- cgit v1.2.3 From 900f8cd5528bd92e1b00c1cdd2a923234bed8466 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 1 Jul 2010 23:40:27 -0700 Subject: added a loopback control port, will do full wishbone interface later --- usrp2/control_lib/fifo_to_wb.v | 34 ++++++++++++++++++++++++++++++++++ usrp2/gpif/gpif.v | 9 ++++++++- usrp2/top/u1plus/u1plus_core.v | 14 ++++++++------ 3 files changed, 50 insertions(+), 7 deletions(-) create mode 100644 usrp2/control_lib/fifo_to_wb.v diff --git a/usrp2/control_lib/fifo_to_wb.v b/usrp2/control_lib/fifo_to_wb.v new file mode 100644 index 000000000..fdc76f89e --- /dev/null +++ b/usrp2/control_lib/fifo_to_wb.v @@ -0,0 +1,34 @@ + +module fifo_to_wb + (input clk, input reset, input clear, + input [35:0] data_i, input src_rdy_i, output dst_rdy_o, + output [35:0] data_o, output src_rdy_o, input dst_rdy_i, + output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + output [31:0] debug0, output [31:0] debug1); + + wire [35:0] ctrl_data, resp_data; + wire ctrl_src_rdy, ctrl_dst_rdy, resp_src_rdy, resp_dst_rdy; + + fifo_short #(.WIDTH(36)) ctrl_sfifo + (.clk(clk), .reset(reset), .clear(clear), + .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), + .dataout(ctrl_data), .src_rdy_o(ctrl_src_rdy), .dst_rdy_i(ctrl_dst_rdy)); + + fifo_short #(.WIDTH(36)) resp_sfifo + (.clk(clk), .reset(reset), .clear(clear), + .datain(resp_data), .src_rdy_i(resp_src_rdy), .dst_rdy_o(resp_dst_rdy), + .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); + + // Loopback control packets + + assign resp_data = ctrl_data; + assign resp_src_rdy = ctrl_src_rdy; + assign ctrl_dst_rdy = resp_dst_rdy; + + assign debug0 = ctrl_data[31:0]; + assign debug1 = { ctrl_src_rdy, ctrl_dst_rdy, resp_src_rdy, resp_dst_rdy, ctrl_data[35:31] }; + +endmodule // fifo_to_wb + + diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index bd813126f..9697a7f8b 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -17,7 +17,7 @@ module gpif output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, - output [31:0] debug + output [31:0] debug0, output [31:0] debug1 ); wire WR = gpif_ctl[0]; @@ -105,5 +105,12 @@ module gpif // //////////////////////////////////////////////////////////////////// // FIFO to Wishbone interface + fifo_to_wb fifo_to_wb + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .data_i(ctrl_data), .src_rdy_i(ctrl_src_rdy), .dst_rdy_o(ctrl_dst_rdy), + .data_o(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy), + .wb_adr_o(), .wb_dat_mosi(), .wb_dat_miso(), + .wb_sel_o(), .wb_cyc_o(), .wb_stb_o(), .wb_we_o(), .wb_ack_i(), + .debug0(), .debug1()); endmodule // gpif diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index 3cdc74835..97064a561 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -54,7 +54,7 @@ module u1plus_core wire [sw-1:0] m0_sel; wire m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty; - wire [31:0] debug_gpmc; + wire [31:0] debug_gpmc, debug0, debug1; wire [35:0] tx_data, rx_data; wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy; @@ -75,7 +75,7 @@ module u1plus_core .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), - .debug(debug_gpmc)); + .debug0(debug0), .debug1(debug1)); wire rx_sof = rx_data[32]; wire rx_eof = rx_data[33]; @@ -366,14 +366,14 @@ module u1plus_core wire [31:0] atr_lines; wire [31:0] debug_gpio_0, debug_gpio_1; - +/* nsgpio16LE nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst), .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), .gpio( {io_tx,io_rx} ) ); - +*/ // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #5 @@ -403,9 +403,11 @@ module u1plus_core // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry - assign debug_clk = { 1'b0, clk_fpga }; - assign debug = 0; + assign debug_clk = { gpif_clk, clk_fpga }; + assign debug = debug0; assign debug_gpio_0 = 0; assign debug_gpio_1 = 0; + + assign {io_tx,io_rx} = debug1; endmodule // u1plus_core -- cgit v1.2.3 From 038ea25032068ea228442dbe86c01f25f51a0d75 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 6 Jul 2010 14:28:18 -0700 Subject: hook up flow control pins --- usrp2/gpif/gpif.v | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index 9697a7f8b..789e22e98 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -23,9 +23,17 @@ module gpif wire WR = gpif_ctl[0]; wire RD = gpif_ctl[1]; wire OE = gpif_ctl[2]; - + wire have_space, have_pkt_rdy; wire [15:0] gpif_dat_out; assign gpif_dat = OE ? gpif_dat_out : 16'bz; + + assign gpif_rdy[0] = have_space; + assign gpif_rdy[1] = have_pkt_rdy; + + wire [15:0] gpif_d_copy = gpif_d; + + assign debug0 = {11'd0, WR, RD, OE, have_space, have_pkt_rdy, gpif_d_copy}; + assign debug1 = 32'd0; // //////////////////////////////////////////////////////////////////// // TX Side @@ -39,7 +47,7 @@ module gpif gpif_wr gpif_wr (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), - .gpif_data(gpif_d), .gpif_wr(WR), .have_space(gpif_rdy[0]), + .gpif_data(gpif_d), .gpif_wr(WR), .have_space(have_space), .sys_clk(fifo_clk), .sys_rst(fifo_rst), .data_o(tx19_data), .src_rdy_o(tx19_src_rdy), .dst_rdy_i(tx_19_dst_rdy), .debug() ); -- cgit v1.2.3 From e55e1540c6601fd467d04f9deebcbdc6fd8bffcc Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 20 Sep 2010 16:25:22 -0700 Subject: use vita_tx_chain top level block --- usrp2/top/u1plus/u1plus_core.v | 36 ++++++++++++++---------------------- 1 file changed, 14 insertions(+), 22 deletions(-) diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index 97064a561..b52515610 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -157,34 +157,26 @@ module u1plus_core // /////////////////////////////////////////////////////////////////////////////////// // DSP TX - wire [99:0] tx1_data; - wire tx1_src_rdy, tx1_dst_rdy; wire [15:0] tx_i_int, tx_q_int; - wire [31:0] debug_vtc, debug_vtd, debug_vt; + wire [31:0] debug_vt; wire run_tx; - - vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer - (.clk(wb_clk), .reset(wb_rst), .clear(0), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), - .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), - .debug(debug_vtd) ); - vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control - (.clk(wb_clk), .reset(wb_rst), .clear(0), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time),.underrun(underrun), - .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .debug(debug_vtc) ); + wire [31:0] tx_err_data; + wire tx_err_src_rdy, tx_err_dst_rdy; + assign tx_err_dst_rdy = 1'b1; - dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx - (.clk(wb_clk),.rst(wb_rst), + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(0), .PROT_ENG_FLAGS(0)) + vita_tx_chain + (.clk(wb_clk), .reset(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), .dac_a(tx_i_int),.dac_b(tx_q_int), - .debug(debug_tx_dsp) ); - + .underrun(underrun), .run(run_tx), + .debug(debug_vt)); + assign tx_i = tx_i_int[15:2]; assign tx_q = tx_q_int[15:2]; -- cgit v1.2.3 From 8e6bbbbcd295af744c47304ed305d1676bea1375 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 21 Sep 2010 14:17:59 -0700 Subject: redone gpif interface to match nick's new spec --- usrp2/gpif/gpif.v | 78 ++++++++++++++++++++---------------------- usrp2/gpif/gpif_rd.v | 69 +++++++++++++++++++++++++++++-------- usrp2/gpif/gpif_wr.v | 36 +++++++++++++++---- usrp2/top/u1plus/u1plus_core.v | 4 +-- 4 files changed, 125 insertions(+), 62 deletions(-) diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index 789e22e98..bcb33eb4d 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -23,16 +23,18 @@ module gpif wire WR = gpif_ctl[0]; wire RD = gpif_ctl[1]; wire OE = gpif_ctl[2]; - wire have_space, have_pkt_rdy; + wire EP = gpif_ctl[3]; + + wire CF, CE, DF, DE; + + assign gpif_rdy = { CF, CE, DF, DE }; + wire [15:0] gpif_dat_out; assign gpif_dat = OE ? gpif_dat_out : 16'bz; - assign gpif_rdy[0] = have_space; - assign gpif_rdy[1] = have_pkt_rdy; - wire [15:0] gpif_d_copy = gpif_d; - assign debug0 = {11'd0, WR, RD, OE, have_space, have_pkt_rdy, gpif_d_copy}; + assign debug0 = { 5'd0, gpif_misc[2:0], gpif_ctl[3:0], gpif_rdy[3:0], gpif_d_copy[15:0] }; assign debug1 = 32'd0; // //////////////////////////////////////////////////////////////////// @@ -40,16 +42,20 @@ module gpif wire [18:0] tx19_data; wire tx19_src_rdy, tx19_dst_rdy; - wire [35:0] tx36_data, tx36b_data, tx36c_data; - wire tx36_src_rdy, tx36_dst_rdy, tx36b_src_rdy, tx36b_dst_rdy, tx36c_src_rdy, tx36c_dst_rdy; - wire [35:0] ctrl_data; + wire [35:0] tx36_data; + wire tx36_src_rdy, tx36_dst_rdy; + + wire [18:0] ctrl; wire ctrl_src_rdy, ctrl_dst_rdy; gpif_wr gpif_wr (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), - .gpif_data(gpif_d), .gpif_wr(WR), .have_space(have_space), + .gpif_data(gpif_d), .gpif_wr(WR), .gpif_ep(EP), + .gpif_full_d(DF), .gpif_full_c(CF), + .sys_clk(fifo_clk), .sys_rst(fifo_rst), - .data_o(tx19_data), .src_rdy_o(tx19_src_rdy), .dst_rdy_i(tx_19_dst_rdy), + .data_o(tx19_data), .src_rdy_o(tx19_src_rdy), .dst_rdy_i(tx19_dst_rdy), + .ctrl_o(ctrl), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy), .debug() ); fifo19_to_fifo36 #(.LE(1)) f19_to_f36 @@ -57,48 +63,26 @@ module gpif .f19_datain(tx19_data), .f19_src_rdy_i(tx19_src_rdy), .f19_dst_rdy_o(tx19_dst_rdy), .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); - fifo_short #(.WIDTH(36)) tx_sfifo - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy), - .dataout(tx36b_data), .src_rdy_o(tx36b_src_rdy), .dst_rdy_i(tx36b_dst_rdy)); - - fifo36_demux #(.match_data(32'h1000_0000), .match_mask(32'hF000_0000)) tx_demux - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .data_i(tx36b_data), .src_rdy_i(tx36b_src_rdy), .dst_rdy_o(tx36b_dst_rdy), - .data0_o(ctrl_data), .src0_rdy_o(ctrl_src_rdy), .dst0_rdy_i(ctrl_dst_rdy), - .data1_o(tx36c_data), .src1_rdy_o(tx36c_src_rdy), .dst1_rdy_i(tx36c_dst_rdy)); - fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .datain(tx36c_data), .src_rdy_i(tx36c_src_rdy), .dst_rdy_o(tx36c_dst_rdy), + .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy), .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i)); // //////////////////////////////////////////////////////////////////// // RX Side - wire [35:0] rx36_data, rx36b_data, rx36c_data; - wire rx36_src_rdy, rx36_dst_rdy, rx36b_src_rdy, rx36b_dst_rdy, rx36c_src_rdy, rx36c_dst_rdy; + wire [35:0] rx36_data; + wire rx36_src_rdy, rx36_dst_rdy; wire [18:0] rx19_data; wire rx19_src_rdy, rx19_dst_rdy; - wire [35:0] resp_data; + wire [18:0] resp_data; wire resp_src_rdy, resp_dst_rdy; fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), - .dataout(rx36c_data), .src_rdy_o(rx36c_src_rdy), .dst_rdy_i(rx36c_dst_rdy)); - - fifo36_mux #(.prio(1)) rx_mux - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .data0_i(resp_data), .src0_rdy_i(resp_src_rdy), .dst0_rdy_o(resp_dst_rdy), - .data1_i(rx36c_data), .src1_rdy_i(rx36c_src_rdy), .dst1_rdy_o(rx36c_dst_rdy), - .data_o(rx36b_data), .src_rdy_o(rx36b_src_rdy), .dst_rdy_i(rx36b_dst_rdy)); - - fifo_short #(.WIDTH(36)) rx_sfifo - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .datain(rx36b_data), .src_rdy_i(rx36b_src_rdy), .dst_rdy_o(rx36b_dst_rdy), .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); - + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // FIXME Endianness? (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), @@ -106,13 +90,17 @@ module gpif gpif_rd gpif_rd (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), - .gpif_data(gpif_dat_out), .gpif_rd(RD), .have_pkt_rdy(have_pkt_rdy), + .gpif_data(gpif_dat_out), .gpif_rd(RD), .gpif_ep(EP), + .gpif_empty_d(DE), .gpif_empty_c(CE), + .sys_clk(fifo_clk), .sys_rst(fifo_rst), - .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy)); + .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy), + .resp_i(resp), .resp_src_rdy_i(resp_src_rdy), .resp_dst_rdy_o(resp_dst_rdy), + .debug() ); // //////////////////////////////////////////////////////////////////// // FIFO to Wishbone interface - +/* fifo_to_wb fifo_to_wb (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .data_i(ctrl_data), .src_rdy_i(ctrl_src_rdy), .dst_rdy_o(ctrl_dst_rdy), @@ -120,5 +108,15 @@ module gpif .wb_adr_o(), .wb_dat_mosi(), .wb_dat_miso(), .wb_sel_o(), .wb_cyc_o(), .wb_stb_o(), .wb_we_o(), .wb_ack_i(), .debug0(), .debug1()); + */ + + // Loopback for testing + assign resp = ctrl; + assign resp_src_rdy = ctrl_src_rdy; + assign ctrl_dst_rdy = resp_src_rdy; + + //assign rx_data_i = tx_data_o; + //assign rx_src_rdy_i = tx_src_rdy_o; + //assign tx_dst_rdy_i = rx_dst_rdy_o; endmodule // gpif diff --git a/usrp2/gpif/gpif_rd.v b/usrp2/gpif/gpif_rd.v index a3167da16..7581592cb 100644 --- a/usrp2/gpif/gpif_rd.v +++ b/usrp2/gpif/gpif_rd.v @@ -1,21 +1,19 @@ module gpif_rd (input gpif_clk, input gpif_rst, - output [15:0] gpif_data, input gpif_rd, output reg have_pkt_rdy, - + output [15:0] gpif_data, input gpif_rd, input gpif_ep, + output reg gpif_empty_d, output reg gpif_empty_c, + input sys_clk, input sys_rst, - input [18:0] data_i, input src_rdy_i, output dst_rdy_o + input [18:0] data_i, input src_rdy_i, output dst_rdy_o, + input [18:0] resp_i, input resp_src_rdy_i, output resp_dst_rdy_o, + output [31:0] debug ); - wire [15:0] rxfifolevel; - wire [15:0] data_o; + wire [17:0] data_o; wire rx_full; - // USB Read Side of FIFO - always @(negedge gpif_clk) - have_pkt_rdy <= (rxfifolevel >= 256); // FIXME make this more robust - - // 257 Bug Fix + // 33/257 Bug Fix reg [8:0] read_count; always @(negedge gpif_clk) if(gpif_rst) @@ -25,19 +23,62 @@ module gpif_rd else read_count <= 0; + // Data Path wire [17:0] data_int; wire src_rdy_int, dst_rdy_int; - fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) rd_fifo_2clk (.wclk(sys_clk), .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(), .rclk(~gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(), .arst(sys_rst)); - fifo_cascade #(.WIDTH(19), .SIZE(9)) rd_fifo + // FIXME -- handle short packets + wire send_data_line = gpif_rd & ~gpif_ep & ~read_count[8]; + + fifo_cascade #(.WIDTH(18), .SIZE(9)) rd_fifo (.clk(~gpif_clk), .reset(gpif_rst), .clear(0), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), - .dataout(data_o), .src_rdy_o(), .dst_rdy_i(gpif_rd & ~read_count[8]), .occupied(rxfifolevel)); + .dataout(data_o), .src_rdy_o(), .dst_rdy_i(send_data_line), .occupied()); - assign gpif_data = data_o[15:0]; + reg [7:0] packet_count; + always @(negedge gpif_clk) + if(gpif_rst) + packet_count <= 0; + else + if(src_rdy_int & dst_rdy_int & data_int[17]) // eop + if(~(send_data_line & data_o[16])) + packet_count <= packet_count + 1; + else + ; + else + if(send_data_line & data_o[16]) + packet_count <= packet_count - 1; + + always @(negedge gpif_clk) + if(gpif_rst) + gpif_empty_d <= 1; + else + gpif_empty_d <= ~|packet_count; + + // Response Path + wire [15:0] resp_fifolevel; + wire send_resp_line = gpif_rd & gpif_ep & ~read_count[4]; + wire [17:0] resp_o; + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) resp_fifo_2clk + (.wclk(sys_clk), .datain(resp_i), .src_rdy_i(resp_src_rdy_i), .dst_rdy_o(resp_dst_rdy_o), .space(), + .rclk(~gpif_clk), .dataout(resp_o), + .src_rdy_o(), .dst_rdy_i(send_resp_line), .occupied(resp_fifolevel), + .arst(sys_rst)); + + // FIXME -- handle short packets + + always @(negedge gpif_clk) + if(gpif_rst) + gpif_empty_c <= 1; + else + gpif_empty_c <= resp_fifolevel < 16; + + // Output Mux + assign gpif_data = gpif_ep ? resp_o[15:0] : data_o[15:0]; endmodule // gpif_rd diff --git a/usrp2/gpif/gpif_wr.v b/usrp2/gpif/gpif_wr.v index 6a73d1721..4c6ee9efc 100644 --- a/usrp2/gpif/gpif_wr.v +++ b/usrp2/gpif/gpif_wr.v @@ -1,18 +1,20 @@ module gpif_wr (input gpif_clk, input gpif_rst, - input [15:0] gpif_data, input gpif_wr, - output reg have_space, + input [15:0] gpif_data, input gpif_wr, input gpif_ep, + output reg gpif_full_d, output reg gpif_full_c, input sys_clk, input sys_rst, output [18:0] data_o, output src_rdy_o, input dst_rdy_i, + output [18:0] ctrl_o, output ctrl_src_rdy_o, input ctrl_dst_rdy_i, output [31:0] debug ); - reg wr_reg; + reg wr_reg, ep_reg; reg [15:0] gpif_data_reg; always @(posedge gpif_clk) begin + ep_reg <= gpif_ep; wr_reg <= gpif_wr; gpif_data_reg <= gpif_data; end @@ -29,20 +31,25 @@ module gpif_wr reg sop; wire eop = (write_count == 255); + wire eop_ctrl = (write_count == 15); always @(posedge gpif_clk) sop <= gpif_wr & ~wr_reg; + // Data Path wire [15:0] fifo_space; always @(posedge gpif_clk) - have_space <= fifo_space > 256; + if(gpif_rst) + gpif_full_d <= 1; + else + gpif_full_d <= fifo_space < 256; wire [17:0] data_int; wire src_rdy_int, dst_rdy_int; - + fifo_cascade #(.WIDTH(18), .SIZE(9)) wr_fifo (.clk(gpif_clk), .reset(gpif_rst), .clear(0), - .datain({eop,sop,gpif_data_reg}), .src_rdy_i(wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space), + .datain({eop,sop,gpif_data_reg}), .src_rdy_i(~ep_reg & wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied()); fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) wr_fifo_2clk @@ -51,5 +58,22 @@ module gpif_wr .arst(sys_rst)); assign data_o[18] = 0; + + // Control Path + wire [15:0] ctrl_fifo_space; + always @(posedge gpif_clk) + if(gpif_rst) + gpif_full_c <= 1; + else + gpif_full_c <= ctrl_fifo_space < 16; + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) ctrl_fifo_2clk + (.wclk(gpif_clk), .datain({eop_ctrl,sop,gpif_data_reg}), + .src_rdy_i(ep_reg & wr_reg & ~write_count[4]), .dst_rdy_o(), .space(ctrl_fifo_space), + .rclk(sys_clk), .dataout(ctrl_o[17:0]), + .src_rdy_o(ctrl_src_rdy_o), .dst_rdy_i(ctrl_dst_rdy_i), .occupied(), + .arst(sys_rst)); + + assign ctrl_o[18] = 0; endmodule // gpif_wr diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index b52515610..9dca0031b 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -1,8 +1,8 @@ -//`define LOOPBACK 1 +`define LOOPBACK 1 //`define TIMED 1 -`define DSP 1 +//`define DSP 1 module u1plus_core (input clk_fpga, input rst_fpga, -- cgit v1.2.3 From af9c419ec95c665b9f7921957115c870aea0ce46 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 21 Sep 2010 23:15:53 -0700 Subject: first steps to a command packet handler for u1+ --- usrp2/gpif/Makefile.srcs | 1 + usrp2/gpif/ctrl_resp.v | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 usrp2/gpif/ctrl_resp.v diff --git a/usrp2/gpif/Makefile.srcs b/usrp2/gpif/Makefile.srcs index 9bcbb29f3..1055baaa8 100644 --- a/usrp2/gpif/Makefile.srcs +++ b/usrp2/gpif/Makefile.srcs @@ -9,4 +9,5 @@ GPIF_SRCS = $(abspath $(addprefix $(BASE_DIR)/../gpif/, \ gpif.v \ gpif_wr.v \ gpif_rd.v \ +ctrl_resp.v \ )) diff --git a/usrp2/gpif/ctrl_resp.v b/usrp2/gpif/ctrl_resp.v new file mode 100644 index 000000000..1877478e6 --- /dev/null +++ b/usrp2/gpif/ctrl_resp.v @@ -0,0 +1,16 @@ + + +module ctrl_resp + (input clk, input reset, + input [17:0] ctrl_i, input ctrl_src_rdy_i, output ctrl_dst_rdy_o, + output [17:0] resp_i, output resp_src_rdy_o, input resp_dst_rdy_i, + + output [15:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + + input [3:0] trigger_i + ); + + + +endmodule // ctrl_resp -- cgit v1.2.3 From 955572c4ad4866202256fed4c7200ac14106e079 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 22 Sep 2010 19:05:10 -0700 Subject: constrain the gpif clock --- usrp2/top/u1plus/timing.ucf | 3 +++ 1 file changed, 3 insertions(+) diff --git a/usrp2/top/u1plus/timing.ucf b/usrp2/top/u1plus/timing.ucf index ca5ebf8e3..b2a455f6d 100644 --- a/usrp2/top/u1plus/timing.ucf +++ b/usrp2/top/u1plus/timing.ucf @@ -1,2 +1,5 @@ NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; TIMESPEC "TS_CLK_FPGA_P" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; + +NET "IFCLK" TNM_NET = "IFCLK"; +TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20833 ps HIGH 50 %; -- cgit v1.2.3 From 92a608b2fc874df1a7af16202d626dcc5676fd72 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 22 Sep 2010 19:06:02 -0700 Subject: send reset to the gpif --- usrp2/top/u1plus/u1plus_core.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index 9dca0031b..2674c3251 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -61,10 +61,11 @@ module u1plus_core wire [7:0] rate; wire bus_error; + wire gpif_rst = 0; gpif #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE)) - gpif (.gpif_clk(gpif_clk), .gpif_d(gpif_d), .gpif_ctl(gpif_ctl), - .gpif_rdy(gpif_rdy), .gpif_misc(gpif_misc), + gpif (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_d(gpif_d), + .gpif_ctl(gpif_ctl), .gpif_rdy(gpif_rdy), .gpif_misc(gpif_misc), .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), -- cgit v1.2.3 From 294b8a282cc556cdf89650e1e78fd71eed6b844f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 22 Sep 2010 19:26:12 -0700 Subject: fix ctrl/resp path to pass all 16 bits of data instead of the bottom bit typos fixed, everything is connected now, should just have off-by-1 error lots of debug pins added --- usrp2/gpif/gpif.v | 58 ++++++++++++++++++++++++++++++---------------------- usrp2/gpif/gpif_rd.v | 19 +++++++++-------- usrp2/gpif/gpif_wr.v | 8 +++----- 3 files changed, 47 insertions(+), 38 deletions(-) diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index bcb33eb4d..af698c24a 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -3,7 +3,7 @@ module gpif #(parameter TXFIFOSIZE = 11, parameter RXFIFOSIZE = 11) (// GPIF signals - input gpif_clk, + input gpif_clk, input gpif_rst, inout [15:0] gpif_d, input [3:0] gpif_ctl, output [3:0] gpif_rdy, input [2:0] gpif_misc, @@ -29,23 +29,22 @@ module gpif assign gpif_rdy = { CF, CE, DF, DE }; - wire [15:0] gpif_dat_out; - assign gpif_dat = OE ? gpif_dat_out : 16'bz; + wire [15:0] gpif_d_out; + assign gpif_d = OE ? gpif_d_out : 16'bz; wire [15:0] gpif_d_copy = gpif_d; - - assign debug0 = { 5'd0, gpif_misc[2:0], gpif_ctl[3:0], gpif_rdy[3:0], gpif_d_copy[15:0] }; - assign debug1 = 32'd0; + + wire [31:0] debug_rd, debug_wr; // //////////////////////////////////////////////////////////////////// // TX Side - wire [18:0] tx19_data; - wire tx19_src_rdy, tx19_dst_rdy; + wire [17:0] tx18_data; + wire tx18_src_rdy, tx18_dst_rdy; wire [35:0] tx36_data; wire tx36_src_rdy, tx36_dst_rdy; - wire [18:0] ctrl; + wire [17:0] ctrl_data; wire ctrl_src_rdy, ctrl_dst_rdy; gpif_wr gpif_wr @@ -54,13 +53,13 @@ module gpif .gpif_full_d(DF), .gpif_full_c(CF), .sys_clk(fifo_clk), .sys_rst(fifo_rst), - .data_o(tx19_data), .src_rdy_o(tx19_src_rdy), .dst_rdy_i(tx19_dst_rdy), - .ctrl_o(ctrl), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy), - .debug() ); + .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), + .ctrl_o(ctrl_data), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy), + .debug(debug_wr) ); - fifo19_to_fifo36 #(.LE(1)) f19_to_f36 + fifo19_to_fifo36 #(.LE(1)) f18_to_f36 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .f19_datain(tx19_data), .f19_src_rdy_i(tx19_src_rdy), .f19_dst_rdy_o(tx19_dst_rdy), + .f19_datain({1'b0,tx18_data}), .f19_src_rdy_i(tx18_src_rdy), .f19_dst_rdy_o(tx18_dst_rdy), .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 @@ -73,9 +72,9 @@ module gpif wire [35:0] rx36_data; wire rx36_src_rdy, rx36_dst_rdy; - wire [18:0] rx19_data; - wire rx19_src_rdy, rx19_dst_rdy; - wire [18:0] resp_data; + wire [17:0] rx18_data; + wire rx18_src_rdy, rx18_dst_rdy; + wire [17:0] resp_data; wire resp_src_rdy, resp_dst_rdy; fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 @@ -83,20 +82,20 @@ module gpif .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); - fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // FIXME Endianness? + fifo36_to_fifo19 #(.LE(1)) f36_to_f18 // FIXME Endianness? (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), - .f19_dataout(rx19_data), .f19_src_rdy_o(rx19_src_rdy), .f19_dst_rdy_i(rx19_dst_rdy) ); + .f19_dataout(rx18_data), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); gpif_rd gpif_rd (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), - .gpif_data(gpif_dat_out), .gpif_rd(RD), .gpif_ep(EP), + .gpif_data(gpif_d_out), .gpif_rd(RD), .gpif_ep(EP), .gpif_empty_d(DE), .gpif_empty_c(CE), .sys_clk(fifo_clk), .sys_rst(fifo_rst), - .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy), - .resp_i(resp), .resp_src_rdy_i(resp_src_rdy), .resp_dst_rdy_o(resp_dst_rdy), - .debug() ); + .data_i(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), + .resp_i(resp_data), .resp_src_rdy_i(resp_src_rdy), .resp_dst_rdy_o(resp_dst_rdy), + .debug(debug_rd) ); // //////////////////////////////////////////////////////////////////// // FIFO to Wishbone interface @@ -110,13 +109,22 @@ module gpif .debug0(), .debug1()); */ + // //////////////////////////////////////////// + // DEBUG + // Loopback for testing - assign resp = ctrl; + assign resp_data = ctrl_data; assign resp_src_rdy = ctrl_src_rdy; - assign ctrl_dst_rdy = resp_src_rdy; + assign ctrl_dst_rdy = resp_dst_rdy; //assign rx_data_i = tx_data_o; //assign rx_src_rdy_i = tx_src_rdy_o; //assign tx_dst_rdy_i = rx_dst_rdy_o; + assign debug0 = { 5'd0, gpif_misc[2:0], gpif_ctl[3:0], gpif_rdy[3:0], gpif_d_copy[15:0] }; + assign debug1 = { { debug_rd[15:8] }, + { debug_rd[7:0] }, + { rx_src_rdy_i, rx_dst_rdy_o, rx36_src_rdy, rx36_dst_rdy, rx18_src_rdy, rx18_dst_rdy, resp_src_rdy, resp_dst_rdy}, + { tx_src_rdy_o, tx_dst_rdy_i, tx18_src_rdy, tx18_dst_rdy, tx36_src_rdy, tx36_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy} }; + endmodule // gpif diff --git a/usrp2/gpif/gpif_rd.v b/usrp2/gpif/gpif_rd.v index 7581592cb..c6e503fce 100644 --- a/usrp2/gpif/gpif_rd.v +++ b/usrp2/gpif/gpif_rd.v @@ -5,13 +5,13 @@ module gpif_rd output reg gpif_empty_d, output reg gpif_empty_c, input sys_clk, input sys_rst, - input [18:0] data_i, input src_rdy_i, output dst_rdy_o, - input [18:0] resp_i, input resp_src_rdy_i, output resp_dst_rdy_o, + input [17:0] data_i, input src_rdy_i, output dst_rdy_o, + input [17:0] resp_i, input resp_src_rdy_i, output resp_dst_rdy_o, output [31:0] debug ); - wire [17:0] data_o; - wire rx_full; + wire [17:0] data_o, resp_o; + wire final_rdy_data, final_rdy_resp; // 33/257 Bug Fix reg [8:0] read_count; @@ -37,7 +37,7 @@ module gpif_rd fifo_cascade #(.WIDTH(18), .SIZE(9)) rd_fifo (.clk(~gpif_clk), .reset(gpif_rst), .clear(0), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), - .dataout(data_o), .src_rdy_o(), .dst_rdy_i(send_data_line), .occupied()); + .dataout(data_o), .src_rdy_o(final_rdy_data), .dst_rdy_i(send_data_line), .occupied()); reg [7:0] packet_count; always @(negedge gpif_clk) @@ -62,12 +62,11 @@ module gpif_rd // Response Path wire [15:0] resp_fifolevel; wire send_resp_line = gpif_rd & gpif_ep & ~read_count[4]; - wire [17:0] resp_o; - + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) resp_fifo_2clk (.wclk(sys_clk), .datain(resp_i), .src_rdy_i(resp_src_rdy_i), .dst_rdy_o(resp_dst_rdy_o), .space(), .rclk(~gpif_clk), .dataout(resp_o), - .src_rdy_o(), .dst_rdy_i(send_resp_line), .occupied(resp_fifolevel), + .src_rdy_o(final_rdy_resp), .dst_rdy_i(send_resp_line), .occupied(resp_fifolevel), .arst(sys_rst)); // FIXME -- handle short packets @@ -80,5 +79,9 @@ module gpif_rd // Output Mux assign gpif_data = gpif_ep ? resp_o[15:0] : data_o[15:0]; + + assign debug = { { 16'd0 }, + { data_int[17:16], data_o[17:16], packet_count[3:0] }, + { 2'b0,final_rdy_data, final_rdy_resp, send_data_line, send_resp_line, src_rdy_int, dst_rdy_int} }; endmodule // gpif_rd diff --git a/usrp2/gpif/gpif_wr.v b/usrp2/gpif/gpif_wr.v index 4c6ee9efc..813e27290 100644 --- a/usrp2/gpif/gpif_wr.v +++ b/usrp2/gpif/gpif_wr.v @@ -5,8 +5,8 @@ module gpif_wr output reg gpif_full_d, output reg gpif_full_c, input sys_clk, input sys_rst, - output [18:0] data_o, output src_rdy_o, input dst_rdy_i, - output [18:0] ctrl_o, output ctrl_src_rdy_o, input ctrl_dst_rdy_i, + output [17:0] data_o, output src_rdy_o, input dst_rdy_i, + output [17:0] ctrl_o, output ctrl_src_rdy_o, input ctrl_dst_rdy_i, output [31:0] debug ); reg wr_reg, ep_reg; @@ -57,8 +57,6 @@ module gpif_wr .rclk(sys_clk), .dataout(data_o[17:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(), .arst(sys_rst)); - assign data_o[18] = 0; - // Control Path wire [15:0] ctrl_fifo_space; always @(posedge gpif_clk) @@ -74,6 +72,6 @@ module gpif_wr .src_rdy_o(ctrl_src_rdy_o), .dst_rdy_i(ctrl_dst_rdy_i), .occupied(), .arst(sys_rst)); - assign ctrl_o[18] = 0; + assign debug = { 16'd0, ep_reg, wr_reg, eop, sop, (~ep_reg & wr_reg & ~write_count[8]), src_rdy_int, dst_rdy_int, write_count[8:0]}; endmodule // gpif_wr -- cgit v1.2.3 From 6f19b5f935117dbce949c21c7719d6c125fd3d15 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 13 Oct 2010 22:13:06 -0700 Subject: not used --- usrp2/gpif/ctrl_resp.v | 16 ---------------- 1 file changed, 16 deletions(-) delete mode 100644 usrp2/gpif/ctrl_resp.v diff --git a/usrp2/gpif/ctrl_resp.v b/usrp2/gpif/ctrl_resp.v deleted file mode 100644 index 1877478e6..000000000 --- a/usrp2/gpif/ctrl_resp.v +++ /dev/null @@ -1,16 +0,0 @@ - - -module ctrl_resp - (input clk, input reset, - input [17:0] ctrl_i, input ctrl_src_rdy_i, output ctrl_dst_rdy_o, - output [17:0] resp_i, output resp_src_rdy_o, input resp_dst_rdy_i, - - output [15:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, - output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, - - input [3:0] trigger_i - ); - - - -endmodule // ctrl_resp -- cgit v1.2.3 From d3f97446e7cd6a12050101310d5c0b09197d1788 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 14 Oct 2010 10:39:46 -0700 Subject: fifo to wb should be functionally complete, needs testing --- usrp2/control_lib/fifo_to_wb.v | 162 +++++++++++++++++++++++++++++++++++------ usrp2/gpif/Makefile.srcs | 1 - usrp2/gpif/gpif.v | 21 +++--- 3 files changed, 150 insertions(+), 34 deletions(-) diff --git a/usrp2/control_lib/fifo_to_wb.v b/usrp2/control_lib/fifo_to_wb.v index fdc76f89e..21d3945da 100644 --- a/usrp2/control_lib/fifo_to_wb.v +++ b/usrp2/control_lib/fifo_to_wb.v @@ -1,34 +1,154 @@ module fifo_to_wb - (input clk, input reset, input clear, - input [35:0] data_i, input src_rdy_i, output dst_rdy_o, - output [35:0] data_o, output src_rdy_o, input dst_rdy_i, - output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, - output wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, - output [31:0] debug0, output [31:0] debug1); - - wire [35:0] ctrl_data, resp_data; - wire ctrl_src_rdy, ctrl_dst_rdy, resp_src_rdy, resp_dst_rdy; + #(parameter PKT_LEN = 16) + (input clk, input reset, input clear, + input [17:0] data_i, input src_rdy_i, output dst_rdy_o, + output [17:0] data_o, output src_rdy_o, input dst_rdy_i, + output reg [15:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + input [7:0] triggers, + output [31:0] debug0, output [31:0] debug1); + + wire [17:0] ctrl_data; + reg [17:0] resp_data; + wire ctrl_src_rdy, ctrl_dst_rdy, resp_src_rdy, resp_dst_rdy; - fifo_short #(.WIDTH(36)) ctrl_sfifo + fifo_short #(.WIDTH(18)) ctrl_sfifo (.clk(clk), .reset(reset), .clear(clear), .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .dataout(ctrl_data), .src_rdy_o(ctrl_src_rdy), .dst_rdy_i(ctrl_dst_rdy)); - - fifo_short #(.WIDTH(36)) resp_sfifo + + fifo_short #(.WIDTH(18)) resp_sfifo (.clk(clk), .reset(reset), .clear(clear), .datain(resp_data), .src_rdy_i(resp_src_rdy), .dst_rdy_o(resp_dst_rdy), .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); - // Loopback control packets + // Need a programmable state machine here. The program is the fifo contents. + // All words are 16 bits wide + // Word 0 Command { Read, Write, Triggers[5:0], Seqno [7:0] } + // Word 1 Length + // Word 2 Address LSW + // Word 3 Address MSW (should all be 0) - assign resp_data = ctrl_data; - assign resp_src_rdy = ctrl_src_rdy; - assign ctrl_dst_rdy = resp_dst_rdy; - - assign debug0 = ctrl_data[31:0]; - assign debug1 = { ctrl_src_rdy, ctrl_dst_rdy, resp_src_rdy, resp_dst_rdy, ctrl_data[35:31] }; - -endmodule // fifo_to_wb + localparam RESP_IDLE = 0; + localparam RESP_LEN = 1; + localparam RESP_ADDR_LSW = 2; + localparam RESP_ADDR_MSW = 3; + localparam RESP_WRITE = 4; + localparam RESP_DUMP = 5; + localparam RESP_WAIT_READ = 6; + localparam RESP_RCMD = 7; + localparam RESP_RLEN = 8; + localparam RESP_READ = 9; + + reg [3:0] resp_state; + reg rd, wr; + reg [15:0] base_addr; + reg [15:0] length; + reg [15:0] count; + reg [7:0] seqnum; + reg [5:0] which_trig; + + always @(posedge clk) + if(reset | clear) + resp_state <= RESP_IDLE; + else + case(resp_state) + RESP_IDLE : + if(ctrl_src_rdy) + begin + { rd, wr, which_trig[5:0], seqnum[7:0] } <= ctrl_data[15:0]; + if(ctrl_data[16]) // WAIT for start of packet, clean out otherwise + resp_state <= RESP_LEN; + end + RESP_LEN : + if(ctrl_src_rdy) + begin + length <= ctrl_data[15:0]; + count <= ctrl_data[15:0]; + resp_state <= RESP_ADDR_LSW; + end + RESP_ADDR_LSW : + if(ctrl_src_rdy) + begin + base_addr <= ctrl_data[15:0]; + wb_adr_o <= ctrl_data[15:0]; + resp_state <= RESP_ADDR_MSW; + end + RESP_ADDR_MSW : + if(ctrl_src_rdy) + if(wr) + resp_state <= RESP_WRITE; + else + resp_state <= RESP_DUMP; + RESP_WRITE : + if(ctrl_src_rdy & wb_ack_i) + if(count==1) + if(ctrl_data[17]) //eof + resp_state <= RESP_IDLE; + else // clean out padding + resp_state <= RESP_DUMP; + else + begin + wb_adr_o <= wb_adr_o + 2; + count <= count - 1; + end + RESP_DUMP : + if(ctrl_src_rdy & ctrl_data[17]) + if(rd) + resp_state <= RESP_WAIT_READ; + else + resp_state <= RESP_IDLE; + RESP_WAIT_READ : + begin + wb_adr_o <= base_addr; + count <= length; + if( &(triggers | ~which_trig) ) + resp_state <= RESP_RCMD; + end + RESP_RCMD : + if(resp_dst_rdy) + resp_state <= RESP_RLEN; + RESP_RLEN : + if(resp_dst_rdy) + resp_state <= RESP_READ; + RESP_READ : + if(resp_dst_rdy & wb_ack_i) + if(count==1) + resp_state <= RESP_IDLE; + else + begin + wb_adr_o <= wb_adr_o + 2; + count <= count - 1; + end + endcase // case (resp_state) + always @* + case(resp_state) + RESP_RCMD : resp_data <= { 2'b01, 8'hAA, seqnum }; + RESP_RLEN : resp_data <= { 2'b00, length }; + default : resp_data <= { (count==1), 1'b0, wb_dat_miso }; + endcase // case (resp_state) + + assign ctrl_dst_rdy = (resp_state == RESP_IDLE) | + (resp_state == RESP_LEN) | + (resp_state == RESP_ADDR_LSW) | + (resp_state == RESP_ADDR_MSW) | + ((resp_state == RESP_WRITE) & wb_ack_i) | + (resp_state == RESP_DUMP); + + assign resp_src_rdy = (resp_state == RESP_RCMD) | + (resp_state == RESP_RLEN) | + ((resp_state == RESP_READ) & wb_ack_i); + + assign wb_dat_mosi = ctrl_data[15:0]; + assign wb_we_o = (resp_state == RESP_WRITE); + assign wb_cyc_o = wb_stb_o; + assign wb_sel_o = 2'b11; + assign wb_stb_o = (ctrl_src_rdy & (resp_state == RESP_WRITE)) | (resp_dst_rdy & (resp_state == RESP_READ)); + + assign debug0 = { 14'd0, ctrl_data[17:0] }; + assign debug1 = { ctrl_src_rdy, ctrl_dst_rdy, resp_src_rdy, resp_dst_rdy, 2'b00, ctrl_data[17:16] }; + +endmodule // fifo_to_wb diff --git a/usrp2/gpif/Makefile.srcs b/usrp2/gpif/Makefile.srcs index 1055baaa8..9bcbb29f3 100644 --- a/usrp2/gpif/Makefile.srcs +++ b/usrp2/gpif/Makefile.srcs @@ -9,5 +9,4 @@ GPIF_SRCS = $(abspath $(addprefix $(BASE_DIR)/../gpif/, \ gpif.v \ gpif_wr.v \ gpif_rd.v \ -ctrl_resp.v \ )) diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index af698c24a..e88ffce20 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -9,8 +9,9 @@ module gpif // Wishbone signals input wb_clk, input wb_rst, - output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output [15:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + input [7:0] triggers, // FIFO interface input fifo_clk, input fifo_rst, @@ -99,27 +100,23 @@ module gpif // //////////////////////////////////////////////////////////////////// // FIFO to Wishbone interface -/* + fifo_to_wb fifo_to_wb (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .data_i(ctrl_data), .src_rdy_i(ctrl_src_rdy), .dst_rdy_o(ctrl_dst_rdy), .data_o(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy), - .wb_adr_o(), .wb_dat_mosi(), .wb_dat_miso(), - .wb_sel_o(), .wb_cyc_o(), .wb_stb_o(), .wb_we_o(), .wb_ack_i(), + .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), .wb_sel_o(wb_sel_o), + .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), .wb_ack_i(wb_ack_i), + .triggers(triggers), .debug0(), .debug1()); - */ // //////////////////////////////////////////// // DEBUG // Loopback for testing - assign resp_data = ctrl_data; - assign resp_src_rdy = ctrl_src_rdy; - assign ctrl_dst_rdy = resp_dst_rdy; - - //assign rx_data_i = tx_data_o; - //assign rx_src_rdy_i = tx_src_rdy_o; - //assign tx_dst_rdy_i = rx_dst_rdy_o; + //assign resp_data = ctrl_data; + //assign resp_src_rdy = ctrl_src_rdy; + //assign ctrl_dst_rdy = resp_dst_rdy; assign debug0 = { 5'd0, gpif_misc[2:0], gpif_ctl[3:0], gpif_rdy[3:0], gpif_d_copy[15:0] }; assign debug1 = { { debug_rd[15:8] }, -- cgit v1.2.3 From cde50d7a6b1bc8d1b650fac2124ce120b2ece690 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 14 Oct 2010 10:42:38 -0700 Subject: put gpio back in --- usrp2/top/u1plus/u1plus_core.v | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index 2674c3251..b408b04b6 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -70,7 +70,7 @@ module u1plus_core .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), - .wb_ack_i(m0_ack), + .wb_ack_i(m0_ack), .triggers(8'd0), .fifo_clk(wb_clk), .fifo_rst(wb_rst), .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), @@ -359,14 +359,14 @@ module u1plus_core wire [31:0] atr_lines; wire [31:0] debug_gpio_0, debug_gpio_1; -/* + nsgpio16LE nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst), .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), .gpio( {io_tx,io_rx} ) ); -*/ + // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #5 @@ -401,6 +401,5 @@ module u1plus_core assign debug_gpio_0 = 0; assign debug_gpio_1 = 0; - assign {io_tx,io_rx} = debug1; endmodule // u1plus_core -- cgit v1.2.3 From 24f8740efc3326c8777857d1265931e8903fa8fc Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 14 Oct 2010 10:45:40 -0700 Subject: old and unused --- usrp2/control_lib/fifo_tb.v | 151 -------------------------------------------- 1 file changed, 151 deletions(-) delete mode 100644 usrp2/control_lib/fifo_tb.v diff --git a/usrp2/control_lib/fifo_tb.v b/usrp2/control_lib/fifo_tb.v deleted file mode 100644 index 616fe4ee7..000000000 --- a/usrp2/control_lib/fifo_tb.v +++ /dev/null @@ -1,151 +0,0 @@ -module fifo_tb(); - - reg clk, rst; - wire short_full, short_empty, long_full, long_empty; - wire casc2_full, casc2_empty; - reg read, write; - - wire [7:0] short_do, long_do; - wire [7:0] casc2_do; - reg [7:0] di; - - reg clear = 0; - - shortfifo #(.WIDTH(8)) shortfifo - (.clk(clk),.rst(rst),.datain(di),.dataout(short_do),.clear(clear), - .read(read),.write(write),.full(short_full),.empty(short_empty)); - - longfifo #(.WIDTH(8), .SIZE(4)) longfifo - (.clk(clk),.rst(rst),.datain(di),.dataout(long_do),.clear(clear), - .read(read),.write(write),.full(long_full),.empty(long_empty)); - - cascadefifo2 #(.WIDTH(8), .SIZE(4)) cascadefifo2 - (.clk(clk),.rst(rst),.datain(di),.dataout(casc2_do),.clear(clear), - .read(read),.write(write),.full(casc2_full),.empty(casc2_empty)); - - initial rst = 1; - initial #1000 rst = 0; - initial clk = 0; - always #50 clk = ~clk; - - initial di = 8'hAE; - initial read = 0; - initial write = 0; - - always @(posedge clk) - if(write) - di <= di + 1; - - always @(posedge clk) - begin - if(short_full != long_full) - $display("Error: FULL mismatch"); - if(short_empty != long_empty) - $display("Note: EMPTY mismatch, usually not a problem (longfifo has 2 cycle latency)"); - if(read & (short_do != long_do)) - $display("Error: DATA mismatch"); - end - - initial $dumpfile("fifo_tb.vcd"); - initial $dumpvars(0,fifo_tb); - - initial - begin - @(negedge rst); - @(posedge clk); - repeat (10) - @(posedge clk); - write <= 1; - @(posedge clk); - write <= 0; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - read <= 1; - @(posedge clk); - read <= 0; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - - repeat(10) - begin - write <= 1; - @(posedge clk); - write <= 0; - @(posedge clk); - @(posedge clk); - @(posedge clk); - read <= 1; - @(posedge clk); - read <= 0; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - end // repeat (10) - - write <= 1; - repeat (4) - @(posedge clk); - write <= 0; - @(posedge clk); - read <= 1; - repeat (4) - @(posedge clk); - read <= 0; - @(posedge clk); - - - write <= 1; - repeat (4) - @(posedge clk); - write <= 0; - @(posedge clk); - repeat (4) - begin - read <= 1; - @(posedge clk); - read <= 0; - @(posedge clk); - end - - write <= 1; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - read <= 1; - repeat (5) - @(posedge clk); - write <= 0; - @(posedge clk); - @(posedge clk); - read <= 0; - @(posedge clk); - - write <= 1; - repeat (16) - @(posedge clk); - write <= 0; - @(posedge clk); - - read <= 1; - repeat (16) - @(posedge clk); - read <= 0; - @(posedge clk); - - repeat (10) - @(posedge clk); - $finish; - end -endmodule // longfifo_tb -- cgit v1.2.3 From 3a244ca4b5a8d330958882936e8f74fbcf81f0e5 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 14 Oct 2010 11:39:18 -0700 Subject: successful test --- usrp2/control_lib/fifo_to_wb_tb.v | 104 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 usrp2/control_lib/fifo_to_wb_tb.v diff --git a/usrp2/control_lib/fifo_to_wb_tb.v b/usrp2/control_lib/fifo_to_wb_tb.v new file mode 100644 index 000000000..971d3db1a --- /dev/null +++ b/usrp2/control_lib/fifo_to_wb_tb.v @@ -0,0 +1,104 @@ +module fifo_to_wb_tb(); + + reg clk = 0; + reg rst = 1; + reg clear = 0; + initial #1000 rst = 0; + always #50 clk = ~clk; + + reg trigger = 0; + initial #10000 trigger = 1; + + wire wb_cyc, wb_stb, wb_we, wb_ack; + wire [15:0] wb_adr; + wire [15:0] wb_dat_miso, wb_dat_mosi; + + reg cmd_src_rdy; + wire cmd_dst_rdy, resp_src_rdy, resp_dst_rdy; + reg [17:0] cmd; + wire [17:0] resp; + + fifo_to_wb fifo_to_wb + (.clk(clk), .reset(rst), .clear(clear), + .data_i(cmd), .src_rdy_i(cmd_src_rdy), .dst_rdy_o(cmd_dst_rdy), + .data_o(resp), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy), + + .wb_adr_o(wb_adr), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), + .wb_sel_o(), .wb_cyc_o(wb_cyc), .wb_stb_o(wb_stb), + .wb_we_o(wb_we), .wb_ack_i(wb_ack), + .triggers()); + + assign wb_dat_miso = {wb_adr[7:0],8'hBF}; + + // Set up monitors + always @(posedge clk) + if(wb_cyc & wb_stb & wb_ack) + if(wb_we) + $display("WB-WRITE ADDR:%h DATA:%h",wb_adr, wb_dat_mosi); + else + $display("WB-READ ADDR:%h DATA:%h",wb_adr, wb_dat_miso); + + always @(posedge clk) + if(cmd_src_rdy & cmd_dst_rdy) + $display("CMD-WRITE SOF:%b EOF:%b DATA:%h",cmd[16],cmd[17],cmd[15:0]); + + always @(posedge clk) + if(resp_src_rdy & resp_dst_rdy) + $display("RESP-READ SOF:%b EOF:%b DATA:%h",resp[16],resp[17],resp[15:0]); + + assign wb_ack = wb_stb; + assign resp_dst_rdy = 1; + + task InsertRW; + input [15:0] data_start; + input [5:0] triggers; + input [7:0] seqno; + input [15:0] len; + input [15:0] addr; + reg [15:0] data_val; + + begin + data_val <= data_start; + @(posedge clk); + cmd <= {2'b01,2'b11,triggers,seqno}; + cmd_src_rdy <= 1; + @(posedge clk); + cmd <= {2'b00,len}; + @(posedge clk); + cmd <= {2'b00,addr}; + @(posedge clk); + cmd <= {2'b00,16'd0}; + @(posedge clk); + repeat (len) + begin + cmd <= {2'b00,data_val}; + data_val <= data_val + 1; + @(posedge clk); + end + repeat (16-len-1) + begin + cmd <= {2'b00,16'hBEEF}; + @(posedge clk); + end + cmd <= {2'b10, 16'hDEAD}; + @(posedge clk); + cmd_src_rdy <= 0; + end + endtask // InsertRead + + initial $dumpfile("fifo_to_wb_tb.vcd"); + initial $dumpvars(0,fifo_to_wb_tb); + + initial + begin + @(negedge rst); + //#10000; + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + InsertRW(16'hF00D, 6'd0, 8'hB5, 16'd7, 16'h1234); + end + + initial #20000 $finish; +endmodule // fifo_to_wb_tb -- cgit v1.2.3 From 9ff35c8e1e6b04e191c83ce21e10772969ea4b64 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 15 Oct 2010 15:47:51 -0700 Subject: give response packets the same format as tx packets --- usrp2/control_lib/fifo_to_wb.v | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/usrp2/control_lib/fifo_to_wb.v b/usrp2/control_lib/fifo_to_wb.v index 21d3945da..5be865a83 100644 --- a/usrp2/control_lib/fifo_to_wb.v +++ b/usrp2/control_lib/fifo_to_wb.v @@ -39,7 +39,9 @@ module fifo_to_wb localparam RESP_WAIT_READ = 6; localparam RESP_RCMD = 7; localparam RESP_RLEN = 8; - localparam RESP_READ = 9; + localparam RESP_RADDR_LSW = 9; + localparam RESP_RADDR_MSW = 10; + localparam RESP_READ = 11; reg [3:0] resp_state; reg rd, wr; @@ -110,6 +112,12 @@ module fifo_to_wb if(resp_dst_rdy) resp_state <= RESP_RLEN; RESP_RLEN : + if(resp_dst_rdy) + resp_state <= RESP_RADDR_LSW; + RESP_RADDR_LSW : + if(resp_dst_rdy) + resp_state <= RESP_RADDR_MSW; + RESP_RADDR_MSW : if(resp_dst_rdy) resp_state <= RESP_READ; RESP_READ : @@ -127,6 +135,8 @@ module fifo_to_wb case(resp_state) RESP_RCMD : resp_data <= { 2'b01, 8'hAA, seqnum }; RESP_RLEN : resp_data <= { 2'b00, length }; + RESP_RADDR_LSW : resp_data <= { 2'b00, base_addr }; + RESP_RADDR_MSW : resp_data <= { 2'b00, 16'd0 }; default : resp_data <= { (count==1), 1'b0, wb_dat_miso }; endcase // case (resp_state) @@ -139,6 +149,8 @@ module fifo_to_wb assign resp_src_rdy = (resp_state == RESP_RCMD) | (resp_state == RESP_RLEN) | + (resp_state == RESP_RADDR_LSW) | + (resp_state == RESP_RADDR_MSW) | ((resp_state == RESP_READ) & wb_ack_i); assign wb_dat_mosi = ctrl_data[15:0]; -- cgit v1.2.3 From 8f78482c36bdef3d0c25f294df699ea8c00bba03 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 15 Oct 2010 15:52:26 -0700 Subject: fixed length command packets --- usrp2/control_lib/fifo_to_wb_tb.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/control_lib/fifo_to_wb_tb.v b/usrp2/control_lib/fifo_to_wb_tb.v index 971d3db1a..e02e60b7c 100644 --- a/usrp2/control_lib/fifo_to_wb_tb.v +++ b/usrp2/control_lib/fifo_to_wb_tb.v @@ -75,7 +75,7 @@ module fifo_to_wb_tb(); data_val <= data_val + 1; @(posedge clk); end - repeat (16-len-1) + repeat (12-len-1) begin cmd <= {2'b00,16'hBEEF}; @(posedge clk); -- cgit v1.2.3 From 0ce67c4b8512f66978402271e2487223ec012c7b Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 15 Oct 2010 18:50:05 -0700 Subject: pad out packets to a minimum length --- usrp2/control_lib/fifo_to_wb_tb.v | 11 ++++++- usrp2/fifo/fifo19_pad.v | 66 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 usrp2/fifo/fifo19_pad.v diff --git a/usrp2/control_lib/fifo_to_wb_tb.v b/usrp2/control_lib/fifo_to_wb_tb.v index e02e60b7c..f1538e8d9 100644 --- a/usrp2/control_lib/fifo_to_wb_tb.v +++ b/usrp2/control_lib/fifo_to_wb_tb.v @@ -17,11 +17,14 @@ module fifo_to_wb_tb(); wire cmd_dst_rdy, resp_src_rdy, resp_dst_rdy; reg [17:0] cmd; wire [17:0] resp; + + wire [17:0] resp_int; + wire resp_src_rdy_int, resp_dst_rdy_int; fifo_to_wb fifo_to_wb (.clk(clk), .reset(rst), .clear(clear), .data_i(cmd), .src_rdy_i(cmd_src_rdy), .dst_rdy_o(cmd_dst_rdy), - .data_o(resp), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy), + .data_o(resp_int), .src_rdy_o(resp_src_rdy_int), .dst_rdy_i(resp_dst_rdy_int), .wb_adr_o(wb_adr), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), .wb_sel_o(), .wb_cyc_o(wb_cyc), .wb_stb_o(wb_stb), @@ -29,6 +32,12 @@ module fifo_to_wb_tb(); .triggers()); assign wb_dat_miso = {wb_adr[7:0],8'hBF}; + + fifo19_pad #(.LENGTH(16)) fifo19_pad + (.clk(clk), .reset(rst), .clear(clear), + .data_i(resp_int), .src_rdy_i(resp_src_rdy_int), .dst_rdy_o(resp_dst_rdy_int), + .data_o(resp), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy)); + // Set up monitors always @(posedge clk) diff --git a/usrp2/fifo/fifo19_pad.v b/usrp2/fifo/fifo19_pad.v new file mode 100644 index 000000000..1a40c1631 --- /dev/null +++ b/usrp2/fifo/fifo19_pad.v @@ -0,0 +1,66 @@ + +// Pads a packet out to the minimum length +// Packets already longer than min length are unchanged + + +module fifo19_pad + #(parameter LENGTH=16, + parameter PAD_VALUE=0) + (input clk, input reset, input clear, + input [18:0] data_i, + input src_rdy_i, + output dst_rdy_o, + output [18:0] data_o, + output src_rdy_o, + input dst_rdy_i); + + reg [15:0] count; + reg [1:0] pad_state; + localparam PAD_IDLE = 0; + localparam PAD_TOOSHORT = 1; + localparam PAD_LONGENOUGH = 2; + localparam PAD_PADDING = 3; + + always @(posedge clk) + if(reset | clear) + pad_state <= PAD_IDLE; + else + case(pad_state) + PAD_IDLE : + begin + count <= 1; + pad_state <= PAD_TOOSHORT; + end + PAD_TOOSHORT : + if(src_rdy_i & dst_rdy_i) + begin + count <= count + 1; + if(data_i[17]) + pad_state <= PAD_PADDING; + else if(count == (LENGTH-1)) + pad_state <= PAD_LONGENOUGH; + end + PAD_PADDING : + if(dst_rdy_i) + begin + count <= count + 1; + if(count == LENGTH) + pad_state <= PAD_IDLE; + end + PAD_LONGENOUGH : + if(src_rdy_i & dst_rdy_i & data_i[17]) + pad_state <= PAD_IDLE; + endcase // case (pad_state) + + wire passthru = (pad_state == PAD_TOOSHORT) | (pad_state == PAD_LONGENOUGH); + + assign dst_rdy_o = passthru ? dst_rdy_i : 1'b0; + assign src_rdy_o = passthru ? src_rdy_i : (pad_state == PAD_PADDING); + + assign data_o[15:0] = (pad_state == PAD_PADDING) ? PAD_VALUE : data_i[15:0]; + assign data_o[16] = (count == 1); + assign data_o[17] = (pad_state == PAD_LONGENOUGH) ? data_i[17] : (count == LENGTH); + assign data_o[18] = (pad_state == PAD_LONGENOUGH) ? data_i[18] : 1'b0; + + +endmodule // fifo19_pad -- cgit v1.2.3 From a9f3336efeec5936ddfaf7f37344700cf79b3243 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 25 Oct 2010 17:00:18 -0700 Subject: add padding into gpif response path --- usrp2/control_lib/fifo_to_wb_tb.v | 8 +++++++- usrp2/fifo/Makefile.srcs | 1 + usrp2/gpif/gpif.v | 11 ++++++++--- 3 files changed, 16 insertions(+), 4 deletions(-) diff --git a/usrp2/control_lib/fifo_to_wb_tb.v b/usrp2/control_lib/fifo_to_wb_tb.v index f1538e8d9..96ef4647c 100644 --- a/usrp2/control_lib/fifo_to_wb_tb.v +++ b/usrp2/control_lib/fifo_to_wb_tb.v @@ -107,7 +107,13 @@ module fifo_to_wb_tb(); @(posedge clk); @(posedge clk); InsertRW(16'hF00D, 6'd0, 8'hB5, 16'd7, 16'h1234); + #20000; + InsertRW(16'h9876, 6'd0, 8'h43, 16'd8, 16'hBEEF); + #20000; + InsertRW(16'h1000, 6'd0, 8'h96, 16'd4, 16'hF00D); + #20000; + InsertRW(16'h3000, 6'd0, 8'h12, 16'd10,16'hDEAD); + #20000 $finish; end - initial #20000 $finish; endmodule // fifo_to_wb_tb diff --git a/usrp2/fifo/Makefile.srcs b/usrp2/fifo/Makefile.srcs index 31b1f505a..7e6a231ae 100644 --- a/usrp2/fifo/Makefile.srcs +++ b/usrp2/fifo/Makefile.srcs @@ -34,4 +34,5 @@ packet_generator32.v \ packet_generator.v \ packet_verifier32.v \ packet_verifier.v \ +fifo19_pad.v \ )) diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index e88ffce20..1edcbf6ad 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -75,8 +75,8 @@ module gpif wire rx36_src_rdy, rx36_dst_rdy; wire [17:0] rx18_data; wire rx18_src_rdy, rx18_dst_rdy; - wire [17:0] resp_data; - wire resp_src_rdy, resp_dst_rdy; + wire [17:0] resp_data, resp_int; + wire resp_src_rdy, resp_dst_rdy, resp_src_rdy_int, resp_dst_rdy_int; fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), @@ -104,12 +104,17 @@ module gpif fifo_to_wb fifo_to_wb (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .data_i(ctrl_data), .src_rdy_i(ctrl_src_rdy), .dst_rdy_o(ctrl_dst_rdy), - .data_o(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy), + .data_o(resp_int), .src_rdy_o(resp_src_rdy_int), .dst_rdy_i(resp_dst_rdy_int), .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), .wb_ack_i(wb_ack_i), .triggers(triggers), .debug0(), .debug1()); + fifo19_pad #(.LENGTH(16)) fifo19_pad + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear), + .data_i(resp_int), .src_rdy_i(resp_src_rdy_int), .dst_rdy_o(resp_dst_rdy_int), + .data_o(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy)); + // //////////////////////////////////////////// // DEBUG -- cgit v1.2.3 From 65ee9c7ad33de945461e30f7423f25a5afa3299c Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Mon, 1 Nov 2010 17:29:57 -0700 Subject: Fixed I2C pin names. --- usrp2/top/u1plus/u1plus.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u1plus/u1plus.v b/usrp2/top/u1plus/u1plus.v index 370d3e4ea..9d52353db 100644 --- a/usrp2/top/u1plus/u1plus.v +++ b/usrp2/top/u1plus/u1plus.v @@ -144,7 +144,7 @@ module u1plus .gpif_misc({FX2_PA7_FLAGD,FX_PA6_PKTEND,FX2_PA2_SLOE}), .gpif_clk(IFCLK), - .db_sda(db_sda), .db_scl(db_scl), + .db_sda(SDA_FPGA), .db_scl(SCL_FPGA), .sclk(sclk), .sen({SEN_CODEC,SEN_TX_DB,SEN_RX_DB}), .mosi(mosi), .miso(miso), .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel), -- cgit v1.2.3 From e7e51ee81e6f4ee5e556c3d7fc2845ab261c7af3 Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Thu, 4 Nov 2010 12:09:04 -0700 Subject: I2C slave address decoding for 16-bit dw instead of 32-bit --- usrp2/top/u1plus/u1plus_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index b408b04b6..03318563f 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -342,7 +342,7 @@ module u1plus_core wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o; i2c_master_top #(.ARST_LVL(1)) i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]), + .wb_adr_i(s3_adr[3:1]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]), .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), .wb_ack_o(s3_ack),.wb_inta_o(), .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), -- cgit v1.2.3 From 9515a3a820cf181be9a980e89c517f1b5083eadf Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Mon, 8 Nov 2010 17:19:50 -0800 Subject: select bus is 2 bits wide --- usrp2/control_lib/fifo_to_wb.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/control_lib/fifo_to_wb.v b/usrp2/control_lib/fifo_to_wb.v index 5be865a83..fc0f29f2d 100644 --- a/usrp2/control_lib/fifo_to_wb.v +++ b/usrp2/control_lib/fifo_to_wb.v @@ -5,7 +5,7 @@ module fifo_to_wb input [17:0] data_i, input src_rdy_i, output dst_rdy_o, output [17:0] data_o, output src_rdy_o, input dst_rdy_i, output reg [15:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, - output wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, input [7:0] triggers, output [31:0] debug0, output [31:0] debug1); -- cgit v1.2.3 From 5772aa4be365615b4313e94a86141dd3e2a6abe7 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 2 Feb 2011 17:56:46 -0800 Subject: modernize the make files, it now compiles. not tested. --- usrp2/control_lib/Makefile.srcs | 1 + usrp2/top/u1plus/Makefile | 65 ++++++----------------------------------- 2 files changed, 10 insertions(+), 56 deletions(-) diff --git a/usrp2/control_lib/Makefile.srcs b/usrp2/control_lib/Makefile.srcs index 751b40828..a1c11c026 100644 --- a/usrp2/control_lib/Makefile.srcs +++ b/usrp2/control_lib/Makefile.srcs @@ -50,4 +50,5 @@ bootram.v \ nsgpio16LE.v \ settings_bus_16LE.v \ atr_controller16.v \ +fifo_to_wb.v \ )) diff --git a/usrp2/top/u1plus/Makefile b/usrp2/top/u1plus/Makefile index 74d747acf..8453352f0 100644 --- a/usrp2/top/u1plus/Makefile +++ b/usrp2/top/u1plus/Makefile @@ -1,30 +1,6 @@ # # Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -################################################## -# xtclsh Shell and tcl Script Path -################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl +# ################################################## # Project Setup @@ -80,8 +56,8 @@ $(GPIF_SRCS) ################################################## # Process Properties ################################################## -export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ "Pack I/O Registers into IOBs" Yes \ "Optimization Effort" High \ "Optimize Instantiated Primitives" TRUE \ @@ -90,10 +66,10 @@ export SYNTHESIZE_PROPERTIES := \ "Use Synchronous Reset" Auto \ "Use Synchronous Set" Auto -export TRANSLATE_PROPERTIES := \ +TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" -export MAP_PROPERTIES := \ +MAP_PROPERTIES = \ "Allow Logic Optimization Across Hierarchy" TRUE \ "Map to Input Functions" 4 \ "Optimization Strategy (Cover Mode)" Speed \ @@ -104,14 +80,14 @@ export MAP_PROPERTIES := \ "Combinatorial Logic Optimization" TRUE \ "Register Duplication" TRUE -export PLACE_ROUTE_PROPERTIES := \ +PLACE_ROUTE_PROPERTIES = \ "Place & Route Effort Level (Overall)" High -export STATIC_TIMING_PROPERTIES := \ +STATIC_TIMING_PROPERTIES = \ "Number of Paths in Error/Verbose Report" 10 \ "Report Type" "Error Report" -export GEN_PROG_FILE_PROPERTIES := \ +GEN_PROG_FILE_PROPERTIES = \ "Configuration Rate" 6 \ "Create Binary Configuration File" TRUE \ "Done (Output Events)" 5 \ @@ -119,27 +95,4 @@ export GEN_PROG_FILE_PROPERTIES := \ "Enable Outputs (Output Events)" 6 \ "Unused IOB Pins" "Pull Up" -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -clean: - rm -rf $(BUILD_DIR) - - +SIM_MODEL_PROPERTIES = "" -- cgit v1.2.3 From 9136be2281be8ab6dd673b0f1dbfe9e9733438cf Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 16 Mar 2011 13:49:22 -0700 Subject: u1p: catch up with all the recent u1e changes --- usrp2/top/u1plus/u1plus_core.v | 198 +++++++++++++++++++---------------------- 1 file changed, 91 insertions(+), 107 deletions(-) diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index 03318563f..8a5f5f2f9 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -1,9 +1,5 @@ -`define LOOPBACK 1 -//`define TIMED 1 -//`define DSP 1 - module u1plus_core (input clk_fpga, input rst_fpga, output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, @@ -26,18 +22,27 @@ module u1plus_core localparam TXFIFOSIZE = 11; localparam RXFIFOSIZE = 11; - localparam SR_RX_DSP = 0; // 5 regs - localparam SR_RX_CTRL = 8; // 9 regs - localparam SR_TX_DSP = 17; // 5 regs - localparam SR_TX_CTRL = 24; // 2 regs - localparam SR_TIME64 = 28; // 4 regs - - wire wb_clk = clk_fpga; - wire wb_rst = rst_fpga; + // 64 total regs in address space + localparam SR_RX_CTRL = 0; // 9 regs (+0 to +8) + localparam SR_RX_DSP = 16; // 7 regs (+0 to +6) + localparam SR_TX_CTRL = 24; // 6 regs (+0 to +5) + localparam SR_TX_DSP = 32; // 5 regs (+0 to +4) + localparam SR_TIME64 = 40; // 6 regs (+0 to +5) + localparam SR_CLEAR_RX_FIFO = 48; // 1 reg + localparam SR_CLEAR_TX_FIFO = 49; // 1 reg + localparam SR_GLOBAL_RESET = 50; // 1 reg + localparam SR_REG_TEST32 = 52; // 1 reg + + wire [7:0] COMPAT_NUM = 8'd3; + wire wb_clk = clk_fpga; + wire wb_rst, global_reset; + wire pps_int; - wire [63:0] vita_time; + wire [63:0] vita_time, vita_time_pps; reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; + wire [7:0] test_rate; + wire [3:0] test_ctrl; wire [7:0] set_addr; wire [31:0] set_data; @@ -54,15 +59,26 @@ module u1plus_core wire [sw-1:0] m0_sel; wire m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty; - wire [31:0] debug_gpmc, debug0, debug1; + wire [31:0] debug_gpmc; - wire [35:0] tx_data, rx_data; - wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy; - wire [7:0] rate; + wire [35:0] tx_data, rx_data, tx_err_data; + wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, + tx_err_src_rdy, tx_err_dst_rdy; + reg [15:0] tx_frame_len; + wire [15:0] rx_frame_len; wire bus_error; wire gpif_rst = 0; + wire clear_tx, clear_rx; + setting_reg #(.my_addr(SR_CLEAR_RX_FIFO), .width(1)) sr_clear_rx + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_rx)); + + setting_reg #(.my_addr(SR_CLEAR_TX_FIFO), .width(1)) sr_clear_tx + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_tx)); + gpif #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE)) gpif (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_d(gpif_d), .gpif_ctl(gpif_ctl), .gpif_rdy(gpif_rdy), .gpif_misc(gpif_misc), @@ -72,7 +88,7 @@ module u1plus_core .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), .wb_ack_i(m0_ack), .triggers(8'd0), - .fifo_clk(wb_clk), .fifo_rst(wb_rst), + .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx), .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), @@ -82,45 +98,6 @@ module u1plus_core wire rx_eof = rx_data[33]; wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int; -`ifdef LOOPBACK - fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo - (.clk(wb_clk), .reset(wb_rst), .clear(0), - .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), - .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); -`endif // LOOPBACK - -`ifdef TIMED - - // TX side - wire tx_enable; - - fifo_pacer tx_pacer - (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(tx_enable), - .src1_rdy_i(tx_src_rdy), .dst1_rdy_o(tx_dst_rdy), - .src2_rdy_o(tx_src_rdy_int), .dst2_rdy_i(tx_dst_rdy_int), - .underrun(tx_underrun), .overrun()); - - packet_verifier32 pktver32 - (.clk(wb_clk), .reset(wb_rst), .clear(clear), - .data_i(tx_data), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int), - .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); - - // RX side - wire rx_enable; - - packet_generator32 pktgen32 - (.clk(wb_clk), .reset(wb_rst), .clear(clear), - .data_o(rx_data), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int)); - - fifo_pacer rx_pacer - (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(rx_enable), - .src1_rdy_i(rx_src_rdy_int), .dst1_rdy_o(rx_dst_rdy_int), - .src2_rdy_o(rx_src_rdy), .dst2_rdy_i(rx_dst_rdy), - .underrun(), .overrun(rx_overrun)); - -`endif // `ifdef TIMED - -`ifdef DSP wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug; // ///////////////////////////////////////////////////////////////////////// @@ -130,8 +107,9 @@ module u1plus_core wire rx1_dst_rdy, rx1_src_rdy; wire [99:0] rx1_data; wire run_rx; - - + wire [35:0] vita_rx_data; + wire vita_rx_src_rdy, vita_rx_dst_rdy; + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx (.clk(wb_clk),.rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), @@ -140,34 +118,36 @@ module u1plus_core .debug(debug_rx_dsp) ); vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control - (.clk(wb_clk), .reset(wb_rst), .clear(0), + (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time), .overrun(overrun), + .vita_time(vita_time), .overrun(rx_overrun_dsp), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy), .debug_rx(vrc_debug)); vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer - (.clk(wb_clk), .reset(wb_rst), .clear(0), + (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy), - .data_o(rx_data), .dst_rdy_i(rx_dst_rdy), .src_rdy_o(rx_src_rdy), - .fifo_occupied(), .fifo_full(), .fifo_empty(), + .data_o(vita_rx_data), .dst_rdy_i(vita_rx_dst_rdy), .src_rdy_o(vita_rx_src_rdy), .debug_rx(vrf_debug) ); - + + fifo36_mux #(.prio(0)) mux_err_stream + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .data0_i(vita_rx_data), .src0_rdy_i(vita_rx_src_rdy), .dst0_rdy_o(vita_rx_dst_rdy), + .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), + .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + // /////////////////////////////////////////////////////////////////////////////////// // DSP TX wire [15:0] tx_i_int, tx_q_int; - wire [31:0] debug_vt; wire run_tx; - - wire [31:0] tx_err_data; - wire tx_err_src_rdy, tx_err_dst_rdy; - assign tx_err_dst_rdy = 1'b1; vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), - .REPORT_ERROR(0), .PROT_ENG_FLAGS(0)) + .REPORT_ERROR(0), .DO_FLOW_CONTROL(0), + .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0), + .DSP_NUMBER(0)) vita_tx_chain (.clk(wb_clk), .reset(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), @@ -175,29 +155,12 @@ module u1plus_core .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), .dac_a(tx_i_int),.dac_b(tx_q_int), - .underrun(underrun), .run(run_tx), + .underrun(tx_underrun_dsp), .run(run_tx), .debug(debug_vt)); assign tx_i = tx_i_int[15:2]; assign tx_q = tx_q_int[15:2]; -`else // !`ifdef DSP - // Dummy DSP signal generator for test purposes - wire [23:0] tx_i_int, tx_q_int; - wire [23:0] freq = {reg_test,8'd0}; - reg [23:0] phase; - - always @(posedge wb_clk) - phase <= phase + freq; - - cordic_z24 #(.bitwidth(24)) tx_cordic - (.clock(wb_clk), .reset(wb_rst), .enable(1), - .xi(24'd2500000), .yi(24'd0), .zi(phase), .xo(tx_i_int), .yo(tx_q_int), .zo()); - - assign tx_i = tx_i_int[23:10]; - assign tx_q = tx_q_int[23:10]; -`endif // !`ifdef DSP - // ///////////////////////////////////////////////////////////////////////////////////// // Wishbone Intercon, single master wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, @@ -222,7 +185,7 @@ module u1plus_core .s2_addr(4'h2), .s2_mask(4'hF), .s3_addr(4'h3), .s3_mask(4'hF), .s4_addr(4'h4), .s4_mask(4'hF), .s5_addr(4'h5), .s5_mask(4'hF), .s6_addr(4'h6), .s6_mask(4'hF), .s7_addr(4'h7), .s7_mask(4'hF), - .s8_addr(4'h8), .s8_mask(4'hF), .s9_addr(4'h9), .s9_mask(4'hF), + .s8_addr(4'h8), .s8_mask(4'hE), .s9_addr(4'hf), .s9_mask(4'hF), // slave 8 is double wide .sa_addr(4'ha), .sa_mask(4'hF), .sb_addr(4'hb), .sb_mask(4'hF), .sc_addr(4'hc), .sc_mask(4'hF), .sd_addr(4'hd), .sd_mask(4'hF), .se_addr(4'he), .se_mask(4'hF), .sf_addr(4'hf), .sf_mask(4'hF)) @@ -263,21 +226,20 @@ module u1plus_core .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); - assign s7_ack = 0; - assign s8_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; + assign s5_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; // ///////////////////////////////////////////////////////////////////////////////////// // Slave 0, Misc LEDs, Switches, controls localparam REG_LEDS = 7'd0; // out - localparam REG_SWITCHES = 7'd2; // in localparam REG_CGEN_CTRL = 7'd4; // out localparam REG_CGEN_ST = 7'd6; // in localparam REG_TEST = 7'd8; // out - localparam REG_RX_FRAMELEN = 7'd10; // out - localparam REG_TX_FRAMELEN = 7'd12; // in - localparam REG_XFER_RATE = 7'd14; // in + localparam REG_RX_FRAMELEN = 7'd10; // in + localparam REG_TX_FRAMELEN = 7'd12; // out + localparam REG_XFER_RATE = 7'd14; // out + localparam REG_COMPAT = 7'd16; // in always @(posedge wb_clk) if(wb_rst) @@ -300,18 +262,18 @@ module u1plus_core xfer_rate <= s0_dat_mosi; endcase // case (s0_adr[6:0]) - assign tx_enable = xfer_rate[15]; - assign rx_enable = xfer_rate[14]; - assign rate = xfer_rate[7:0]; + assign test_ctrl = xfer_rate[11:8]; + assign test_rate = xfer_rate[7:0]; assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : - //(s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : (s0_adr[6:0] == REG_TEST) ? reg_test : + (s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len : + (s0_adr[6:0] == REG_COMPAT) ? { 8'd0, COMPAT_NUM } : 16'hBEEF; assign s0_ack = s0_stb & s0_cyc; @@ -368,12 +330,12 @@ module u1plus_core .gpio( {io_tx,io_rx} ) ); // ///////////////////////////////////////////////////////////////////////// - // Settings Bus -- Slave #5 + // Settings Bus -- Slave #8 + 9 - // only have 32 regs, 32 bits each with current setup... - settings_bus_16LE #(.AWIDTH(11),.RWIDTH(11-4-2)) settings_bus_16LE - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s5_adr),.wb_dat_i(s5_dat_mosi), - .wb_stb_i(s5_stb),.wb_we_i(s5_we),.wb_ack_o(s5_ack), + // only have 64 regs, 32 bits each with current setup... + settings_bus_16LE #(.AWIDTH(11),.RWIDTH(6)) settings_bus_16LE + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr),.wb_dat_i(s8_dat_mosi), + .wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack), .strobe(set_stb),.addr(set_addr),.data(set_data) ); // ///////////////////////////////////////////////////////////////////////// @@ -383,15 +345,37 @@ module u1plus_core (.clk_i(wb_clk), .rst_i(wb_rst), .adr_i(s6_adr), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), - .run_rx(0), .run_tx(0), .ctrl_lines(atr_lines)); + .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines)); + + // ///////////////////////////////////////////////////////////////////////// + // Readback mux 32 -- Slave #7 + + wire [31:0] reg_test32; + + setting_reg #(.my_addr(SR_REG_TEST32)) sr_reg_test32 + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(reg_test32),.changed()); + + wb_readback_mux_16LE readback_mux_32 + (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s7_stb), + .wb_adr_i(s7_adr), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack), + .word00(vita_time[63:32]), .word01(vita_time[31:0]), + .word02(vita_time_pps[63:32]), .word03(vita_time_pps[31:0]), + .word04(reg_test32), .word05(32'b0), + .word06(32'b0), .word07(32'b0), + .word08(32'b0), .word09(32'b0), + .word10(32'b0), .word11(32'b0), + .word12(32'b0), .word13(32'b0), + .word14(32'b0), .word15(32'b0) + ); // ///////////////////////////////////////////////////////////////////////// // VITA Timing time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int)); // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry -- cgit v1.2.3 From a24962fce5d31b8e824aab2afefa5372a98a3ac1 Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Wed, 16 Mar 2011 13:52:09 -0700 Subject: u1p: remove extram from Makefile --- usrp2/top/u1plus/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/usrp2/top/u1plus/Makefile b/usrp2/top/u1plus/Makefile index 8453352f0..ca6ec9320 100644 --- a/usrp2/top/u1plus/Makefile +++ b/usrp2/top/u1plus/Makefile @@ -20,7 +20,6 @@ include ../../opencores/Makefile.srcs include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs -include ../../extram/Makefile.srcs include ../../gpif/Makefile.srcs ################################################## -- cgit v1.2.3 From 40856137fb23b7e979d5b9040779b3606987cc49 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 16 Mar 2011 14:06:05 -0700 Subject: u1p: add clear ports to gpif, not hooked up yet --- usrp2/gpif/gpif.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index 1edcbf6ad..d53487535 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -14,7 +14,7 @@ module gpif input [7:0] triggers, // FIFO interface - input fifo_clk, input fifo_rst, + input fifo_clk, input fifo_rst, input clear_tx, input clear_rx, output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, -- cgit v1.2.3 From 61ace1e0656cd61896e7f457e1d303c2857632c1 Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Wed, 16 Mar 2011 15:06:42 -0700 Subject: u1p: added debug0, debug1 for GPIF debugging --- usrp2/top/u1plus/u1plus_core.v | 3 +++ 1 file changed, 3 insertions(+) diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index 8a5f5f2f9..6a479cc83 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -47,6 +47,9 @@ module u1plus_core wire [7:0] set_addr; wire [31:0] set_data; wire set_stb; + + wire [31:0] debug0; + wire [31:0] debug1; // ///////////////////////////////////////////////////////////////////////////////////// // GPIF Slave to Wishbone Master -- cgit v1.2.3 From 39f96a4751e1917a31e940d358399f14d08288fd Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 16 Mar 2011 16:45:27 -0700 Subject: u1p: fix bus widths and other warnings --- usrp2/control_lib/fifo_to_wb.v | 22 +++++++++++----------- usrp2/gpif/gpif.v | 30 +++++++++++++++--------------- usrp2/gpif/gpif_rd.v | 14 +++++++------- usrp2/gpif/gpif_wr.v | 20 ++++++++++---------- usrp2/top/u1plus/u1plus_core.v | 19 ++++++++++--------- 5 files changed, 53 insertions(+), 52 deletions(-) diff --git a/usrp2/control_lib/fifo_to_wb.v b/usrp2/control_lib/fifo_to_wb.v index fc0f29f2d..b2a2fd18b 100644 --- a/usrp2/control_lib/fifo_to_wb.v +++ b/usrp2/control_lib/fifo_to_wb.v @@ -2,23 +2,23 @@ module fifo_to_wb #(parameter PKT_LEN = 16) (input clk, input reset, input clear, - input [17:0] data_i, input src_rdy_i, output dst_rdy_o, - output [17:0] data_o, output src_rdy_o, input dst_rdy_i, + input [18:0] data_i, input src_rdy_i, output dst_rdy_o, + output [18:0] data_o, output src_rdy_o, input dst_rdy_i, output reg [15:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, input [7:0] triggers, output [31:0] debug0, output [31:0] debug1); - wire [17:0] ctrl_data; - reg [17:0] resp_data; + wire [18:0] ctrl_data; + reg [18:0] resp_data; wire ctrl_src_rdy, ctrl_dst_rdy, resp_src_rdy, resp_dst_rdy; - fifo_short #(.WIDTH(18)) ctrl_sfifo + fifo_short #(.WIDTH(19)) ctrl_sfifo (.clk(clk), .reset(reset), .clear(clear), .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .dataout(ctrl_data), .src_rdy_o(ctrl_src_rdy), .dst_rdy_i(ctrl_dst_rdy)); - fifo_short #(.WIDTH(18)) resp_sfifo + fifo_short #(.WIDTH(19)) resp_sfifo (.clk(clk), .reset(reset), .clear(clear), .datain(resp_data), .src_rdy_i(resp_src_rdy), .dst_rdy_o(resp_dst_rdy), .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); @@ -133,11 +133,11 @@ module fifo_to_wb always @* case(resp_state) - RESP_RCMD : resp_data <= { 2'b01, 8'hAA, seqnum }; - RESP_RLEN : resp_data <= { 2'b00, length }; - RESP_RADDR_LSW : resp_data <= { 2'b00, base_addr }; - RESP_RADDR_MSW : resp_data <= { 2'b00, 16'd0 }; - default : resp_data <= { (count==1), 1'b0, wb_dat_miso }; + RESP_RCMD : resp_data <= { 3'b001, 8'hAA, seqnum }; + RESP_RLEN : resp_data <= { 3'b000, length }; + RESP_RADDR_LSW : resp_data <= { 3'b000, base_addr }; + RESP_RADDR_MSW : resp_data <= { 3'b000, 16'd0 }; + default : resp_data <= { 1'b0, (count==1), 1'b0, wb_dat_miso }; endcase // case (resp_state) assign ctrl_dst_rdy = (resp_state == RESP_IDLE) | diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index d53487535..14ed2690f 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -40,12 +40,12 @@ module gpif // //////////////////////////////////////////////////////////////////// // TX Side - wire [17:0] tx18_data; - wire tx18_src_rdy, tx18_dst_rdy; + wire [18:0] tx19_data; + wire tx19_src_rdy, tx19_dst_rdy; wire [35:0] tx36_data; wire tx36_src_rdy, tx36_dst_rdy; - wire [17:0] ctrl_data; + wire [18:0] ctrl_data; wire ctrl_src_rdy, ctrl_dst_rdy; gpif_wr gpif_wr @@ -54,13 +54,13 @@ module gpif .gpif_full_d(DF), .gpif_full_c(CF), .sys_clk(fifo_clk), .sys_rst(fifo_rst), - .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), + .data_o(tx19_data), .src_rdy_o(tx19_src_rdy), .dst_rdy_i(tx19_dst_rdy), .ctrl_o(ctrl_data), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy), .debug(debug_wr) ); - fifo19_to_fifo36 #(.LE(1)) f18_to_f36 + fifo19_to_fifo36 #(.LE(1)) f19_to_f36 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .f19_datain({1'b0,tx18_data}), .f19_src_rdy_i(tx18_src_rdy), .f19_dst_rdy_o(tx18_dst_rdy), + .f19_datain(tx19_data), .f19_src_rdy_i(tx19_src_rdy), .f19_dst_rdy_o(tx19_dst_rdy), .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 @@ -73,9 +73,9 @@ module gpif wire [35:0] rx36_data; wire rx36_src_rdy, rx36_dst_rdy; - wire [17:0] rx18_data; - wire rx18_src_rdy, rx18_dst_rdy; - wire [17:0] resp_data, resp_int; + wire [18:0] rx19_data; + wire rx19_src_rdy, rx19_dst_rdy; + wire [18:0] resp_data, resp_int; wire resp_src_rdy, resp_dst_rdy, resp_src_rdy_int, resp_dst_rdy_int; fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 @@ -83,10 +83,10 @@ module gpif .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); - fifo36_to_fifo19 #(.LE(1)) f36_to_f18 // FIXME Endianness? + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // FIXME Endianness? (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), - .f19_dataout(rx18_data), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); + .f19_dataout(rx19_data), .f19_src_rdy_o(rx19_src_rdy), .f19_dst_rdy_i(rx19_dst_rdy) ); gpif_rd gpif_rd (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), @@ -94,7 +94,7 @@ module gpif .gpif_empty_d(DE), .gpif_empty_c(CE), .sys_clk(fifo_clk), .sys_rst(fifo_rst), - .data_i(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), + .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy), .resp_i(resp_data), .resp_src_rdy_i(resp_src_rdy), .resp_dst_rdy_o(resp_dst_rdy), .debug(debug_rd) ); @@ -111,7 +111,7 @@ module gpif .debug0(), .debug1()); fifo19_pad #(.LENGTH(16)) fifo19_pad - (.clk(fifo_clk), .reset(fifo_rst), .clear(clear), + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .data_i(resp_int), .src_rdy_i(resp_src_rdy_int), .dst_rdy_o(resp_dst_rdy_int), .data_o(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy)); @@ -126,7 +126,7 @@ module gpif assign debug0 = { 5'd0, gpif_misc[2:0], gpif_ctl[3:0], gpif_rdy[3:0], gpif_d_copy[15:0] }; assign debug1 = { { debug_rd[15:8] }, { debug_rd[7:0] }, - { rx_src_rdy_i, rx_dst_rdy_o, rx36_src_rdy, rx36_dst_rdy, rx18_src_rdy, rx18_dst_rdy, resp_src_rdy, resp_dst_rdy}, - { tx_src_rdy_o, tx_dst_rdy_i, tx18_src_rdy, tx18_dst_rdy, tx36_src_rdy, tx36_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy} }; + { rx_src_rdy_i, rx_dst_rdy_o, rx36_src_rdy, rx36_dst_rdy, rx19_src_rdy, rx19_dst_rdy, resp_src_rdy, resp_dst_rdy}, + { tx_src_rdy_o, tx_dst_rdy_i, tx19_src_rdy, tx19_dst_rdy, tx36_src_rdy, tx36_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy} }; endmodule // gpif diff --git a/usrp2/gpif/gpif_rd.v b/usrp2/gpif/gpif_rd.v index c6e503fce..76db72d8a 100644 --- a/usrp2/gpif/gpif_rd.v +++ b/usrp2/gpif/gpif_rd.v @@ -5,12 +5,12 @@ module gpif_rd output reg gpif_empty_d, output reg gpif_empty_c, input sys_clk, input sys_rst, - input [17:0] data_i, input src_rdy_i, output dst_rdy_o, - input [17:0] resp_i, input resp_src_rdy_i, output resp_dst_rdy_o, + input [18:0] data_i, input src_rdy_i, output dst_rdy_o, + input [18:0] resp_i, input resp_src_rdy_i, output resp_dst_rdy_o, output [31:0] debug ); - wire [17:0] data_o, resp_o; + wire [18:0] data_o, resp_o; wire final_rdy_data, final_rdy_resp; // 33/257 Bug Fix @@ -24,9 +24,9 @@ module gpif_rd read_count <= 0; // Data Path - wire [17:0] data_int; + wire [18:0] data_int; wire src_rdy_int, dst_rdy_int; - fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) rd_fifo_2clk + fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) rd_fifo_2clk (.wclk(sys_clk), .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(), .rclk(~gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(), .arst(sys_rst)); @@ -34,7 +34,7 @@ module gpif_rd // FIXME -- handle short packets wire send_data_line = gpif_rd & ~gpif_ep & ~read_count[8]; - fifo_cascade #(.WIDTH(18), .SIZE(9)) rd_fifo + fifo_cascade #(.WIDTH(19), .SIZE(9)) rd_fifo (.clk(~gpif_clk), .reset(gpif_rst), .clear(0), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), .dataout(data_o), .src_rdy_o(final_rdy_data), .dst_rdy_i(send_data_line), .occupied()); @@ -63,7 +63,7 @@ module gpif_rd wire [15:0] resp_fifolevel; wire send_resp_line = gpif_rd & gpif_ep & ~read_count[4]; - fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) resp_fifo_2clk + fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) resp_fifo_2clk (.wclk(sys_clk), .datain(resp_i), .src_rdy_i(resp_src_rdy_i), .dst_rdy_o(resp_dst_rdy_o), .space(), .rclk(~gpif_clk), .dataout(resp_o), .src_rdy_o(final_rdy_resp), .dst_rdy_i(send_resp_line), .occupied(resp_fifolevel), diff --git a/usrp2/gpif/gpif_wr.v b/usrp2/gpif/gpif_wr.v index 813e27290..e9b3c72ea 100644 --- a/usrp2/gpif/gpif_wr.v +++ b/usrp2/gpif/gpif_wr.v @@ -5,8 +5,8 @@ module gpif_wr output reg gpif_full_d, output reg gpif_full_c, input sys_clk, input sys_rst, - output [17:0] data_o, output src_rdy_o, input dst_rdy_i, - output [17:0] ctrl_o, output ctrl_src_rdy_o, input ctrl_dst_rdy_i, + output [18:0] data_o, output src_rdy_o, input dst_rdy_i, + output [18:0] ctrl_o, output ctrl_src_rdy_o, input ctrl_dst_rdy_i, output [31:0] debug ); reg wr_reg, ep_reg; @@ -44,17 +44,17 @@ module gpif_wr else gpif_full_d <= fifo_space < 256; - wire [17:0] data_int; + wire [18:0] data_int; wire src_rdy_int, dst_rdy_int; - fifo_cascade #(.WIDTH(18), .SIZE(9)) wr_fifo + fifo_cascade #(.WIDTH(19), .SIZE(9)) wr_fifo (.clk(gpif_clk), .reset(gpif_rst), .clear(0), - .datain({eop,sop,gpif_data_reg}), .src_rdy_i(~ep_reg & wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space), + .datain({1'b0,eop,sop,gpif_data_reg}), .src_rdy_i(~ep_reg & wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied()); - fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) wr_fifo_2clk + fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) wr_fifo_2clk (.wclk(gpif_clk), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), - .rclk(sys_clk), .dataout(data_o[17:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(), + .rclk(sys_clk), .dataout(data_o[18:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(), .arst(sys_rst)); // Control Path @@ -65,10 +65,10 @@ module gpif_wr else gpif_full_c <= ctrl_fifo_space < 16; - fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) ctrl_fifo_2clk - (.wclk(gpif_clk), .datain({eop_ctrl,sop,gpif_data_reg}), + fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) ctrl_fifo_2clk + (.wclk(gpif_clk), .datain({1'b0,eop_ctrl,sop,gpif_data_reg}), .src_rdy_i(ep_reg & wr_reg & ~write_count[4]), .dst_rdy_o(), .space(ctrl_fifo_space), - .rclk(sys_clk), .dataout(ctrl_o[17:0]), + .rclk(sys_clk), .dataout(ctrl_o[18:0]), .src_rdy_o(ctrl_src_rdy_o), .dst_rdy_i(ctrl_dst_rdy_i), .occupied(), .arst(sys_rst)); diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index 6a479cc83..0fbc2f593 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -10,7 +10,7 @@ module u1plus_core input [2:0] gpif_misc, input gpif_clk, inout db_sda, inout db_scl, - output sclk, output [7:0] sen, output mosi, input miso, + output sclk, output [15:0] sen, output mosi, input miso, input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, inout [15:0] io_tx, inout [15:0] io_rx, @@ -54,7 +54,7 @@ module u1plus_core // ///////////////////////////////////////////////////////////////////////////////////// // GPIF Slave to Wishbone Master localparam dw = 16; - localparam aw = 11; + localparam aw = 16; localparam sw = 2; wire [dw-1:0] m0_dat_mosi, m0_dat_miso; @@ -108,7 +108,7 @@ module u1plus_core wire [31:0] sample_rx, sample_tx; wire strobe_rx, strobe_tx; wire rx1_dst_rdy, rx1_src_rdy; - wire [99:0] rx1_data; + wire [100:0] rx1_data; wire run_rx; wire [35:0] vita_rx_data; wire vita_rx_src_rdy, vita_rx_dst_rdy; @@ -123,7 +123,7 @@ module u1plus_core vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time), .overrun(rx_overrun_dsp), + .vita_time(vita_time), .overrun(), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy), .debug_rx(vrc_debug)); @@ -158,8 +158,8 @@ module u1plus_core .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), .dac_a(tx_i_int),.dac_b(tx_q_int), - .underrun(tx_underrun_dsp), .run(run_tx), - .debug(debug_vt)); + .underrun(), .run(run_tx), + .debug()); assign tx_i = tx_i_int[15:2]; assign tx_q = tx_q_int[15:2]; @@ -337,7 +337,7 @@ module u1plus_core // only have 64 regs, 32 bits each with current setup... settings_bus_16LE #(.AWIDTH(11),.RWIDTH(6)) settings_bus_16LE - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr),.wb_dat_i(s8_dat_mosi), + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr[10:0]),.wb_dat_i(s8_dat_mosi), .wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack), .strobe(set_stb),.addr(set_addr),.data(set_data) ); @@ -346,7 +346,7 @@ module u1plus_core atr_controller16 atr_controller16 (.clk_i(wb_clk), .rst_i(wb_rst), - .adr_i(s6_adr), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), + .adr_i(s6_adr[5:0]), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines)); @@ -378,7 +378,8 @@ module u1plus_core time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int)); + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), + .exp_time_in(0)); // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry -- cgit v1.2.3 From f04a393d48266f5d3e4f35aaddf12ab3214ae8b4 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 16 Mar 2011 16:48:16 -0700 Subject: u1p: use icarus verilog to find warnings --- usrp2/models/FIFO_GENERATOR_V6_1.v | 4575 ++++++++++++++++++++++++++++++++++++ usrp2/top/u1plus/core_compile | 2 + 2 files changed, 4577 insertions(+) create mode 100644 usrp2/models/FIFO_GENERATOR_V6_1.v create mode 100755 usrp2/top/u1plus/core_compile diff --git a/usrp2/models/FIFO_GENERATOR_V6_1.v b/usrp2/models/FIFO_GENERATOR_V6_1.v new file mode 100644 index 000000000..65bbac447 --- /dev/null +++ b/usrp2/models/FIFO_GENERATOR_V6_1.v @@ -0,0 +1,4575 @@ +/* + ******************************************************************************* + * + * FIFO Generator - Verilog Behavioral Model + * + ******************************************************************************* + * + * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. + * + * This file contains confidential and proprietary information + * of Xilinx, Inc. and is protected under U.S. and + * international copyright and other intellectual property + * laws. + * + * DISCLAIMER + * This disclaimer is not a license and does not grant any + * rights to the materials distributed herewith. Except as + * otherwise provided in a valid license issued to you by + * Xilinx, and to the maximum extent permitted by applicable + * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + * (2) Xilinx shall not be liable (whether in contract or tort, + * including negligence, or under any other theory of + * liability) for any loss or damage of any kind or nature + * related to, arising under or in connection with these + * materials, including for any direct, or any indirect, + * special, incidental, or consequential loss or damage + * (including loss of data, profits, goodwill, or any type of + * loss or damage suffered as a result of any action brought + * by a third party) even if such damage or loss was + * reasonably foreseeable or Xilinx had been advised of the + * possibility of the same. + * + * CRITICAL APPLICATIONS + * Xilinx products are not designed or intended to be fail- + * safe, or for use in any application requiring fail-safe + * performance, such as life-support or safety devices or + * systems, Class III medical devices, nuclear facilities, + * applications related to the deployment of airbags, or any + * other applications that could lead to death, personal + * injury, or severe property or environmental damage + * (individually and collectively, "Critical + * Applications"). Customer assumes the sole risk and + * liability of any use of Xilinx products in Critical + * Applications, subject only to applicable laws and + * regulations governing limitations on product liability. + * + * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + * PART OF THIS FILE AT ALL TIMES. + * + ******************************************************************************* + ******************************************************************************* + * + * Filename: FIFO_GENERATOR_V6_1.v + * + * Author : Xilinx + * + ******************************************************************************* + * Structure: + * + * fifo_generator_v6_1.vhd + * | + * +-fifo_generator_v6_1_bhv_ver_as + * | + * +-fifo_generator_v6_1_bhv_ver_ss + * | + * +-fifo_generator_v6_1_bhv_ver_preload0 + * + ******************************************************************************* + * Description: + * + * The Verilog behavioral model for the FIFO Generator. + * + * The behavioral model has three parts: + * - The behavioral model for independent clocks FIFOs (_as) + * - The behavioral model for common clock FIFOs (_ss) + * - The "preload logic" block which implements First-word Fall-through + * + ******************************************************************************* + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps +`ifndef TCQ + `define TCQ 100 +`endif + + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module FIFO_GENERATOR_V6_1 + #( + parameter C_COMMON_CLOCK = 0, + parameter C_COUNT_TYPE = 0, + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DEFAULT_VALUE = "", + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_ENABLE_RLOCS = 0, + parameter C_FAMILY = "virtex6", //Not allowed in Verilog model + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_BACKUP = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_INT_CLK = 0, + parameter C_HAS_MEMINIT_FILE = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RD_RST = 0, + parameter C_HAS_RST = 0, + parameter C_HAS_SRST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_HAS_WR_RST = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_INIT_WR_PNTR_VAL = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_MIF_FILE_NAME = "", + parameter C_OPTIMIZATION_MODE = 0, + parameter C_OVERFLOW_LOW = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PRIM_FIFO_TYPE = "", + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_FREQ = 1, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_ECC = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_USE_FIFO16_FLAGS = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_FREQ = 1, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_WR_RESPONSE_LATENCY = 1, + parameter C_MSGON_VAL = 1, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0 + ) + + ( + input BACKUP, + input BACKUP_MARKER, + input CLK, + input RST, + input SRST, + input WR_CLK, + input WR_RST, + input RD_CLK, + input RD_RST, + input [C_DIN_WIDTH-1:0] DIN, + input WR_EN, + input RD_EN, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, + input INT_CLK, + input INJECTDBITERR, + input INJECTSBITERR, + + output [C_DOUT_WIDTH-1:0] DOUT, + output FULL, + output ALMOST_FULL, + output WR_ACK, + output OVERFLOW, + output EMPTY, + output ALMOST_EMPTY, + output VALID, + output UNDERFLOW, + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT, + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, + output PROG_FULL, + output PROG_EMPTY, + output SBITERR, + output DBITERR + ); + +/* + ****************************************************************************** + * Definition of Parameters + ****************************************************************************** + * C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0) + * C_COUNT_TYPE : *not used + * C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus + * C_DEFAULT_VALUE : *not used + * C_DIN_WIDTH : Width of DIN bus + * C_DOUT_RST_VAL : Reset value of DOUT + * C_DOUT_WIDTH : Width of DOUT bus + * C_ENABLE_RLOCS : *not used + * C_FAMILY : not used in bhv model + * C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1) + * C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag + * C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag + * C_HAS_BACKUP : *not used + * C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus + * C_HAS_INT_CLK : not used in bhv model + * C_HAS_MEMINIT_FILE : *not used + * C_HAS_OVERFLOW : 1=Core has OVERFLOW flag + * C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus + * C_HAS_RD_RST : *not used + * C_HAS_RST : 1=Core has Async Rst + * C_HAS_SRST : 1=Core has Sync Rst + * C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag + * C_HAS_VALID : 1=Core has VALID flag + * C_HAS_WR_ACK : 1=Core has WR_ACK flag + * C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus + * C_HAS_WR_RST : *not used + * C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram + * 1=Common-Clock ShiftRam + * 2=Indep. Clocks Bram/Dram + * 3=Virtex-4 Built-in + * 4=Virtex-5 Built-in + * C_INIT_WR_PNTR_VAL : *not used + * C_MEMORY_TYPE : 1=Block RAM + * 2=Distributed RAM + * 3=Shift RAM + * 4=Built-in FIFO + * C_MIF_FILE_NAME : *not used + * C_OPTIMIZATION_MODE : *not used + * C_OVERFLOW_LOW : 1=OVERFLOW active low + * C_PRELOAD_LATENCY : Latency of read: 0, 1, 2 + * C_PRELOAD_REGS : 1=Use output registers + * C_PRIM_FIFO_TYPE : not used in bhv model + * C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold + * C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold + * C_PROG_EMPTY_TYPE : 0=No programmable empty + * 1=Single prog empty thresh constant + * 2=Multiple prog empty thresh constants + * 3=Single prog empty thresh input + * 4=Multiple prog empty thresh inputs + * C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold + * C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold + * C_PROG_FULL_TYPE : 0=No prog full + * 1=Single prog full thresh constant + * 2=Multiple prog full thresh constants + * 3=Single prog full thresh input + * 4=Multiple prog full thresh inputs + * C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus + * C_RD_DEPTH : Depth of read interface (2^N) + * C_RD_FREQ : not used in bhv model + * C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH) + * C_UNDERFLOW_LOW : 1=UNDERFLOW active low + * C_USE_DOUT_RST : 1=Resets DOUT on RST + * C_USE_ECC : Used for error injection purpose + * C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register + * C_USE_FIFO16_FLAGS : not used in bhv model + * C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count + * C_VALID_LOW : 1=VALID active low + * C_WR_ACK_LOW : 1=WR_ACK active low + * C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus + * C_WR_DEPTH : Depth of write interface (2^N) + * C_WR_FREQ : not used in bhv model + * C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH) + * C_WR_RESPONSE_LATENCY : *not used + * C_MSGON_VAL : *not used by bhv model + * C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST + * 1 = Use RST + * C_ERROR_INJECTION_TYPE : 0 = No error injection + * 1 = Single bit error injection only + * 2 = Double bit error injection only + * 3 = Single and double bit error injection + ****************************************************************************** + * Definition of Ports + ****************************************************************************** + * BACKUP : Not used + * BACKUP_MARKER: Not used + * CLK : Clock + * DIN : Input data bus + * PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag + * PROG_FULL_THRESH : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag + * RD_CLK : Read Domain Clock + * RD_EN : Read enable + * RD_RST : Read Reset + * RST : Asynchronous Reset + * SRST : Synchronous Reset + * WR_CLK : Write Domain Clock + * WR_EN : Write enable + * WR_RST : Write Reset + * INT_CLK : Internal Clock + * INJECTSBITERR: Inject Signle bit error + * INJECTDBITERR: Inject Double bit error + * ALMOST_EMPTY : One word remaining in FIFO + * ALMOST_FULL : One empty space remaining in FIFO + * DATA_COUNT : Number of data words in fifo( synchronous to CLK) + * DOUT : Output data bus + * EMPTY : Empty flag + * FULL : Full flag + * OVERFLOW : Last write rejected + * PROG_EMPTY : Programmable Empty Flag + * PROG_FULL : Programmable Full Flag + * RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK) + * UNDERFLOW : Last read rejected + * VALID : Last read acknowledged, DOUT bus VALID + * WR_ACK : Last write acknowledged + * WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK) + * SBITERR : Single Bit ECC Error Detected + * DBITERR : Double Bit ECC Error Detected + ****************************************************************************** + */ + + + /***************************************************************************** + * Derived parameters + ****************************************************************************/ + //There are 2 Verilog behavioral models + // 0 = Common-Clock FIFO/ShiftRam FIFO + // 1 = Independent Clocks FIFO + parameter C_VERILOG_IMPL = (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0; + + //Internal reset signals + reg rd_rst_asreg = 0; + reg rd_rst_asreg_d1 = 0; + reg rd_rst_asreg_d2 = 0; + reg rd_rst_reg = 0; + wire rd_rst_comb; + reg rd_rst_d1 = 0; + reg wr_rst_asreg = 0; + reg wr_rst_asreg_d1 = 0; + reg wr_rst_asreg_d2 = 0; + reg wr_rst_reg = 0; + wire wr_rst_comb; + wire wr_rst_i; + wire rd_rst_i; + wire rst_i; + + //Internal reset signals + reg rst_asreg = 0; + reg rst_asreg_d1 = 0; + reg rst_asreg_d2 = 0; + reg rst_reg = 0; + wire rst_comb; + wire rst_full_gen_i; + wire rst_full_ff_i; + + wire RD_CLK_P0_IN; + wire RST_P0_IN; + wire RD_EN_FIFO_IN; + wire RD_EN_P0_IN; + + wire ALMOST_EMPTY_FIFO_OUT; + wire ALMOST_FULL_FIFO_OUT; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; + wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; + wire EMPTY_FIFO_OUT; + wire FULL_FIFO_OUT; + wire OVERFLOW_FIFO_OUT; + wire PROG_EMPTY_FIFO_OUT; + wire PROG_FULL_FIFO_OUT; + wire VALID_FIFO_OUT; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; + wire UNDERFLOW_FIFO_OUT; + wire WR_ACK_FIFO_OUT; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; + + + //*************************************************************************** + // Internal Signals + // The core uses either the internal_ wires or the preload0_ wires depending + // on whether the core uses Preload0 or not. + // When using preload0, the internal signals connect the internal core to + // the preload logic, and the external core's interfaces are tied to the + // preload0 signals from the preload logic. + //*************************************************************************** + wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; + wire VALID_P0_OUT; + wire EMPTY_P0_OUT; + wire ALMOSTEMPTY_P0_OUT; + reg EMPTY_P0_OUT_Q; + reg ALMOSTEMPTY_P0_OUT_Q; + wire UNDERFLOW_P0_OUT; + wire RDEN_P0_OUT; + wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; + wire EMPTY_P0_IN; + reg [31:0] DATA_COUNT_FWFT; + reg SS_FWFT_WR ; + reg SS_FWFT_RD ; + + wire sbiterr_fifo_out; + wire dbiterr_fifo_out; + + // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR. + assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ? + INJECTSBITERR : 0; + assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ? + INJECTDBITERR : 0; + + +// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL +// parameter (1=Independent Clocks, 0=Common Clock) + + localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL; +generate +case (C_VERILOG_IMPL) +0 : begin : block1 + //Common Clock Behavioral Model + fifo_generator_v6_1_bhv_ver_ss + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, +// C_FULL_FLAGS_RST_VAL, + FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_SRST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_USE_ECC, + C_ENABLE_RST_SYNC, + C_ERROR_INJECTION_TYPE + ) + gen_ss + ( + .CLK (CLK), + .RST (rst_i), + .SRST (SRST), + .RST_FULL_GEN (rst_full_gen_i), + .RST_FULL_FF (rst_full_ff_i), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .DATA_COUNT (DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end +1 : begin : block1 + //Independent Clocks Behavioral Model + fifo_generator_v6_1_bhv_ver_as + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_USE_ECC, + C_ENABLE_RST_SYNC, + C_ERROR_INJECTION_TYPE + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (rst_i), + .RST_FULL_GEN (rst_full_gen_i), + .RST_FULL_FF (rst_full_ff_i), + .WR_RST (wr_rst_i), + .RD_RST (rd_rst_i), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .RD_EN_USER (RD_EN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .USER_EMPTY_FB (EMPTY_P0_OUT), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end + +default : begin : block1 + //Independent Clocks Behavioral Model + fifo_generator_v6_1_bhv_ver_as + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_USE_ECC, + C_ENABLE_RST_SYNC, + C_ERROR_INJECTION_TYPE + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (rst_i), + .RST_FULL_GEN (rst_full_gen_i), + .RST_FULL_FF (rst_full_ff_i), + .WR_RST (wr_rst_i), + .RD_RST (rd_rst_i), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .RD_EN_USER (RD_EN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .USER_EMPTY_FB (EMPTY_P0_OUT), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end + +endcase +endgenerate + + + //************************************************************************** + // Connect Internal Signals + // (Signals labeled internal_*) + // In the normal case, these signals tie directly to the FIFO's inputs and + // outputs. + // In the case of Preload Latency 0 or 1, there are intermediate + // signals between the internal FIFO and the preload logic. + //************************************************************************** + + + //*********************************************** + // If First-Word Fall-Through, instantiate + // the preload0 (FWFT) module + //*********************************************** + generate + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin : block2 + + + fifo_generator_v6_1_bhv_ver_preload0 + #( + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_HAS_RST, + C_ENABLE_RST_SYNC, + C_HAS_SRST, + C_USE_DOUT_RST, + C_USE_ECC, + C_VALID_LOW, + C_UNDERFLOW_LOW, + C_MEMORY_TYPE + ) + fgpl0 + ( + .RD_CLK (RD_CLK_P0_IN), + .RD_RST (RST_P0_IN), + .SRST (SRST), + .RD_EN (RD_EN_P0_IN), + .FIFOEMPTY (EMPTY_P0_IN), + .FIFODATA (DATA_P0_IN), + .FIFOSBITERR (sbiterr_fifo_out), + .FIFODBITERR (dbiterr_fifo_out), + .USERDATA (DATA_P0_OUT), + .USERVALID (VALID_P0_OUT), + .USEREMPTY (EMPTY_P0_OUT), + .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), + .USERUNDERFLOW (UNDERFLOW_P0_OUT), + .RAMVALID (RAMVALID_P0_OUT), + .FIFORDEN (RDEN_P0_OUT), + .USERSBITERR (SBITERR), + .USERDBITERR (DBITERR) + ); + + + //*********************************************** + // Connect inputs to preload (FWFT) module + //*********************************************** + //Connect the RD_CLK of the Preload (FWFT) module to CLK if we + // have a common-clock FIFO, or RD_CLK if we have an + // independent clock FIFO + assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); + assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0; + assign RD_EN_P0_IN = RD_EN; + assign EMPTY_P0_IN = EMPTY_FIFO_OUT; + assign DATA_P0_IN = DOUT_FIFO_OUT; + + //*********************************************** + // Connect outputs from preload (FWFT) module + //*********************************************** + assign DOUT = DATA_P0_OUT; + assign VALID = VALID_P0_OUT ; + assign EMPTY = EMPTY_P0_OUT; + assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; + assign UNDERFLOW = UNDERFLOW_P0_OUT ; + + assign RD_EN_FIFO_IN = RDEN_P0_OUT; + + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT: + (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : + DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1]; + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + always @ (posedge RD_CLK or posedge RST_P0_IN) begin + if (RST_P0_IN) begin + EMPTY_P0_OUT_Q <= #`TCQ 1; + ALMOSTEMPTY_P0_OUT_Q <= #`TCQ 1; + end else begin + EMPTY_P0_OUT_Q <= #`TCQ EMPTY_P0_OUT; + ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT; + end + end //always + + + //*********************************************** + // logic for common-clock data count when FWFT is selected + //*********************************************** + initial begin + SS_FWFT_RD = 1'b0; + DATA_COUNT_FWFT = 0 ; + SS_FWFT_WR = 1'b0 ; + end //initial + + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter. SS_FWFT_WR and SS_FWFT_RD + // are the up/down enables for the counter. + //*********************************************** + always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT) begin + if (C_VALID_LOW == 1) begin + SS_FWFT_RD = RD_EN && ~VALID_P0_OUT ; + end else begin + SS_FWFT_RD = RD_EN && VALID_P0_OUT ; + end + SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ; + end + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter for FWFT. This always block + // calculates the counter. + //*********************************************** + always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin + if (RST_P0_IN) begin + DATA_COUNT_FWFT <= #`TCQ 0; + end else begin + if (SRST && (C_HAS_SRST == 1) ) begin + DATA_COUNT_FWFT <= #`TCQ 0; + end else begin + case ( {SS_FWFT_WR, SS_FWFT_RD}) + 2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; + 2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ; + 2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ; + 2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; + endcase + end //if SRST + end //IF RST + end //always + + + end else begin : block2 //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + //*********************************************** + // If NOT First-Word Fall-Through, wire the outputs + // of the internal _ss or _as FIFO directly to the + // output, and do not instantiate the preload0 + // module. + //*********************************************** + + assign RD_CLK_P0_IN = 0; + assign RST_P0_IN = 0; + assign RD_EN_P0_IN = 0; + + assign RD_EN_FIFO_IN = RD_EN; + + assign DOUT = DOUT_FIFO_OUT; + assign DATA_P0_IN = 0; + assign VALID = VALID_FIFO_OUT; + assign EMPTY = EMPTY_FIFO_OUT; + assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; + assign EMPTY_P0_IN = 0; + assign UNDERFLOW = UNDERFLOW_FIFO_OUT; + assign DATA_COUNT = DATA_COUNT_FIFO_OUT; + assign SBITERR = sbiterr_fifo_out; + assign DBITERR = dbiterr_fifo_out; + + end //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + endgenerate + + + //*********************************************** + // Connect user flags to internal signals + //*********************************************** + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ) begin : block3 + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT); + end //block3 + endgenerate + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) ) begin : block30 + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT); + end //block30 + endgenerate + + //If we are not using extra logic for the FWFT data count, + //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the + //internal FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31 + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + endgenerate + + //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal + //FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==1) begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + else begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + endgenerate + + + //Connect other flags to the internal FIFO instance + assign FULL = FULL_FIFO_OUT; + assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; + assign WR_ACK = WR_ACK_FIFO_OUT; + assign OVERFLOW = OVERFLOW_FIFO_OUT; + assign PROG_FULL = PROG_FULL_FIFO_OUT; + assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; + + + // if an asynchronous FIFO has been selected, display a message that the FIFO + // will not be cycle-accurate in simulation + initial begin + if (C_IMPLEMENTATION_TYPE == 2) begin + $display("WARNING: Behavioral models for independent clock FIFO configurations are not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information."); + end else if (C_MEMORY_TYPE == 4) begin + $display("FAILURE : Behavioral models for Virtex-4, Virtex-5 and Virtex-6 built-in FIFO configurations is currently not supported. Please select the structural simulation model option in CORE Generator. You can enable this in CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information."); + $finish; + end + end //initial + + /************************************************************************** + * Internal reset logic + **************************************************************************/ + assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0; + assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0; + assign rst_i = C_HAS_RST ? rst_reg : 0; + + wire rst_2_sync; + wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK; + generate + if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync + always @* begin + wr_rst_reg <= WR_RST; + rd_rst_reg <= RD_RST; + rst_reg <= 1'b0; + end + assign rst_2_sync = WR_RST; + end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : gic_rst + assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg; + assign rd_rst_comb = !rd_rst_asreg_d2 && rd_rst_asreg; + assign rst_2_sync = RST; + + always @(posedge WR_CLK or posedge RST) begin + if (RST == 1'b1) begin + wr_rst_asreg <= #`TCQ 1'b1; + end else begin + if (wr_rst_asreg_d1 == 1'b1) begin + wr_rst_asreg <= #`TCQ 1'b0; + end else begin + wr_rst_asreg <= #`TCQ wr_rst_asreg; + end + end + end + + always @(posedge WR_CLK) begin + wr_rst_asreg_d1 <= #`TCQ wr_rst_asreg; + wr_rst_asreg_d2 <= #`TCQ wr_rst_asreg_d1; + end + + always @(posedge WR_CLK or posedge wr_rst_comb) begin + if (wr_rst_comb == 1'b1) begin + wr_rst_reg <= #`TCQ 1'b1; + end else begin + wr_rst_reg <= #`TCQ 1'b0; + end + end + + always @(posedge RD_CLK or posedge RST) begin + if (RST == 1'b1) begin + rd_rst_asreg <= #`TCQ 1'b1; + end else begin + if (rd_rst_asreg_d1 == 1'b1) begin + rd_rst_asreg <= #`TCQ 1'b0; + end else begin + rd_rst_asreg <= #`TCQ rd_rst_asreg; + end + end + end + + always @(posedge RD_CLK) begin + rd_rst_asreg_d1 <= #`TCQ rd_rst_asreg; + rd_rst_asreg_d2 <= #`TCQ rd_rst_asreg_d1; + end + + always @(posedge RD_CLK or posedge rd_rst_comb) begin + if (rd_rst_comb == 1'b1) begin + rd_rst_reg <= #`TCQ 1'b1; + end else begin + rd_rst_reg <= #`TCQ 1'b0; + end + end + end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : gcc_rst + assign rst_comb = !rst_asreg_d2 && rst_asreg; + assign rst_2_sync = RST; + + always @(posedge CLK or posedge RST) begin + if (RST == 1'b1) begin + rst_asreg <= #`TCQ 1'b1; + end else begin + if (rst_asreg_d1 == 1'b1) begin + rst_asreg <= #`TCQ 1'b0; + end else begin + rst_asreg <= #`TCQ rst_asreg; + end + end + end + + always @(posedge CLK) begin + rst_asreg_d1 <= #`TCQ rst_asreg; + rst_asreg_d2 <= #`TCQ rst_asreg_d1; + end + + always @(posedge CLK or posedge rst_comb) begin + if (rst_comb == 1'b1) begin + rst_reg <= #`TCQ 1'b1; + end else begin + rst_reg <= #`TCQ 1'b0; + end + end + end + endgenerate + + reg rst_d1 = 1'b0; + reg rst_d2 = 1'b0; + reg rst_d3 = 1'b0; + reg rst_d4 = 1'b0; + generate + if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1 + // RST_FULL_GEN replaces the reset falling edge detection used to de-assert + // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1. + + // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL & + // PROG_FULL + + always @ (posedge rst_2_sync or posedge clk_2_sync) begin + if (rst_2_sync) begin + rst_d1 <= 1'b1; + rst_d2 <= 1'b1; + rst_d3 <= 1'b1; + rst_d4 <= 1'b0; + end else begin + if (SRST) begin + rst_d1 <= #`TCQ 1'b1; + rst_d2 <= #`TCQ 1'b1; + rst_d3 <= #`TCQ 1'b1; + rst_d4 <= #`TCQ 1'b0; + end else begin + rst_d1 <= #`TCQ 1'b0; + rst_d2 <= #`TCQ rst_d1; + rst_d3 <= #`TCQ rst_d2; + rst_d4 <= #`TCQ rst_d3; + end + end + end + assign rst_full_ff_i = (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ; + assign rst_full_gen_i = rst_d4; + + end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full + assign rst_full_gen_i = 1'b0; + assign rst_full_ff_i = (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i; + end + endgenerate + +endmodule //FIFO_GENERATOR_V6_1 + + + +/******************************************************************************* + * Declaration of Independent-Clocks FIFO Module + ******************************************************************************/ +module fifo_generator_v6_1_bhv_ver_as + + /*************************************************************************** + * Declare user parameters and their defaults + ***************************************************************************/ + #( + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_OVERFLOW_LOW = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_USE_ECC = 0, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0 + ) + + /*************************************************************************** + * Declare Input and Output Ports + ***************************************************************************/ + ( + input [C_DIN_WIDTH-1:0] DIN, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, + input RD_CLK, + input RD_EN, + input RD_EN_USER, + input RST, + input RST_FULL_GEN, + input RST_FULL_FF, + input WR_RST, + input RD_RST, + input WR_CLK, + input WR_EN, + input INJECTDBITERR, + input INJECTSBITERR, + input USER_EMPTY_FB, + output reg ALMOST_EMPTY = 1'b1, + output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL, + output [C_DOUT_WIDTH-1:0] DOUT, + output reg EMPTY = 1'b1, + output reg FULL = C_FULL_FLAGS_RST_VAL, + output OVERFLOW, + output PROG_EMPTY, + output PROG_FULL, + output VALID, + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, + output UNDERFLOW, + output WR_ACK, + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, + output SBITERR, + output DBITERR + ); + + reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0; + reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0; + reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0; + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + parameter C_DEPTH_RATIO_WR = + (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; + parameter C_DEPTH_RATIO_RD = + (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; + parameter C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; + parameter C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; + + // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC + // -----------------|------------------|-----------------|--------------- + // 1 | 8 | C_RD_PNTR_WIDTH | 2 + // 1 | 4 | C_RD_PNTR_WIDTH | 2 + // 1 | 2 | C_RD_PNTR_WIDTH | 2 + // 1 | 1 | C_WR_PNTR_WIDTH | 2 + // 2 | 1 | C_WR_PNTR_WIDTH | 4 + // 4 | 1 | C_WR_PNTR_WIDTH | 8 + // 8 | 1 | C_WR_PNTR_WIDTH | 16 + + localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; + wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + + parameter [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; + + parameter [31:0] log2_reads_per_write = log2_val(reads_per_write); + + parameter [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; + + parameter [31:0] log2_writes_per_read = log2_val(writes_per_read); + + + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + // Local parameters used to determine whether to inject ECC error or not + localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; + localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; + localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; + // Array that holds the error injection type (single/double bit error) on + // a specific write operation, which is returned on read to corrupt the + // output data. + reg [1:0] ecc_err[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK + // domain. + //num_wr_bits is calculated by considering the total words in the FIFO, + // and the state of the read pointer (which may not have yet crossed clock + // domains.) + //num_rd_bits is calculated by considering the total words in the FIFO, + // and the state of the write pointer (which may not have yet crossed clock + // domains.) + reg [31:0] num_wr_bits; + reg [31:0] num_rd_bits; + reg [31:0] next_num_wr_bits; + reg [31:0] next_num_rd_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0; + wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0; + wire wr_rst_i = WR_RST; + reg wr_rst_d1 =0; + + //The read pointer - tracks read operations + // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0; + wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0; + wire rd_rst_i = RD_RST; + wire ram_rd_en; + reg ram_rd_en_d1 = 1'b0; + + + // Delayed ram_rd_en is needed only for STD Embedded register option + generate + if (C_PRELOAD_LATENCY == 2) begin : grd_d + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + ram_rd_en_d1 <= #`TCQ 1'b0; + else + ram_rd_en_d1 <= #`TCQ ram_rd_en; + end + end + endgenerate + + // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation + generate + if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth + assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; + assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0; + end else begin : rdl // Read depth lesser than or equal to write depth + assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end + endgenerate + + // Generate Empty and Almost Empty + // ram_rd_en used to determine EMPTY should depend on the EMPTY. + assign ram_rd_en = RD_EN & !EMPTY; + assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1)))); + assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2)))); + + // Register Empty and Almost Empty + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin + EMPTY <= #`TCQ 1'b1; + ALMOST_EMPTY <= #`TCQ 1'b1; + rd_data_count_int <= #`TCQ {C_RD_PNTR_WIDTH-1{1'b0}}; + end else begin + rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0}; + + if (empty_int) + EMPTY <= #`TCQ 1'b1; + else + EMPTY <= #`TCQ 1'b0; + + if (!EMPTY) begin + if (almost_empty_int) + ALMOST_EMPTY <= #`TCQ 1'b1; + else + ALMOST_EMPTY <= #`TCQ 1'b0; + end + end // rd_rst_i + end // always + + // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation + generate + if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth + assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; + assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0; + end else begin : wdl // Write depth lesser than or equal to read depth + assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + end + endgenerate + + // Generate FULL and ALMOST_FULL + // ram_wr_en used to determine FULL should depend on the FULL. + assign ram_wr_en = WR_EN & !FULL; + assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2)))); + assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3)))); + + // Register FULL and ALMOST_FULL Empty + always @ (posedge WR_CLK or posedge RST_FULL_FF) + begin + if (RST_FULL_FF) begin + FULL <= #`TCQ C_FULL_FLAGS_RST_VAL; + ALMOST_FULL <= #`TCQ C_FULL_FLAGS_RST_VAL; + wr_data_count_int <= #`TCQ {C_WR_DATA_COUNT_WIDTH-1{1'b0}}; + end else begin + wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0}; + if (full_int) begin + FULL <= #`TCQ 1'b1; + end else begin + FULL <= #`TCQ 1'b0; + end + + if (RST_FULL_GEN) begin + ALMOST_FULL <= #`TCQ 1'b0; + end else if (!FULL) begin + if (almost_full_int) + ALMOST_FULL <= #`TCQ 1'b1; + else + ALMOST_FULL <= #`TCQ 1'b0; + end + end // wr_rst_i + end // always + + // Determine which stage in FWFT registers are valid + reg stage1_valid = 0; + reg stage2_valid = 0; + generate + if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + stage1_valid <= #`TCQ 0; + stage2_valid <= #`TCQ 0; + end else begin + + if (!stage1_valid && !stage2_valid) begin + if (!EMPTY) + stage1_valid <= #`TCQ 1'b1; + else + stage1_valid <= #`TCQ 1'b0; + end else if (stage1_valid && !stage2_valid) begin + if (EMPTY) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end + end else if (!stage1_valid && stage2_valid) begin + if (EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b0; + end else if (!EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b0; + end else if (!EMPTY && !RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end + end else if (stage1_valid && stage2_valid) begin + if (EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end + end else begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b0; + end + end // rd_rst_i + end // always + end + endgenerate + + //Pointers passed into opposite clock domain + reg [31:0] wr_ptr_rdclk; + reg [31:0] wr_ptr_rdclk_next; + reg [31:0] rd_ptr_wrclk; + reg [31:0] rd_ptr_wrclk_next; + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_EMPTY. + wire [31:0] num_read_words_pe = + num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR); + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_FULL. + wire [31:0] num_write_words_pf = + num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD); + + /************************** + * Read Data Count + *************************/ + + reg [31:0] num_read_words_dc; + reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; + + always @(num_rd_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //If using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain, + // and add two read words for FWFT stages + //This value is only a temporary value and not used in the code. + num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; + + end else begin + + //If not using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain. + //This value is only a temporary value and not used in the code. + num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + /************************** + * Write Data Count + *************************/ + + reg [31:0] num_write_words_dc; + reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; + + always @(num_wr_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //Calculate the Data Count value for the number of write words, + // when using First-Word Fall-Through with extra logic for Data + // Counts. This takes into consideration the number of words that + // are expected to be stored in the FWFT register stages (it always + // assumes they are filled). + //This value is scaled to the Write Domain. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //EXTRA_WORDS_DC is the number of words added to write_words + // due to FWFT. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; + + //Trim the write words for use with WR_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; + + end else begin + + //Calculate the Data Count value for the number of write words, when NOT + // using First-Word Fall-Through with extra logic for Data Counts. This + // calculates only the number of words in the internal FIFO. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //This value is scaled to the Write Domain. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; + + //Trim the read words for use with RD_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + + /*************************************************************************** + * Internal registers and wires + **************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire valid_i; + wire valid_out; + wire underflow_i; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [1:0] err_type = 0; + reg [1:0] err_type_d1 = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; + reg ideal_wr_ack = 0; + reg ideal_valid = 0; + reg ideal_overflow = 0; + reg ideal_underflow = 0; + reg ideal_prog_full = 0; + reg ideal_prog_empty = 1; + reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0; + reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0; + + //Assorted reg values for delayed versions of signals + reg valid_d1 = 0; + + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; + + //temporary registers for WR_RESPONSE_LATENCY feature + + integer tmp_wr_listsize; + integer tmp_rd_listsize; + + //Signal for registered version of prog full and empty + + //Threshold values for Programmable Flags + integer prog_empty_actual_thresh_assert; + integer prog_empty_actual_thresh_negate; + integer prog_full_actual_thresh_assert; + integer prog_full_actual_thresh_negate; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + begin + memory[wr_ptr] <= DIN; + wr_pntr <= #`TCQ wr_pntr + 1; + // Store the type of error injection (double/single) on write + case (C_ERROR_INJECTION_TYPE) + 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; + 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; + 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; + default: ecc_err[wr_ptr] <= 0; + endcase + // (Works opposite to core: wr_ptr is a DOWN counter) + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + integer i; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [C_DIN_WIDTH-1:0] memory_read; + reg [31:0] tmp_rd_ptr; + reg [31:0] rd_ptr_high; + reg [31:0] rd_ptr_low; + reg [1:0] tmp_ecc_err; + begin + rd_pntr <= #`TCQ rd_pntr + 1; + // output is wider than input + if (reads_per_write == 0) begin + tmp_dout = 0; + tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); + for (i = writes_per_read - 1; i >= 0; i = i - 1) begin + tmp_dout = tmp_dout << C_DIN_WIDTH; + tmp_dout = tmp_dout | memory[tmp_rd_ptr]; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (tmp_rd_ptr == 0) begin + tmp_rd_ptr = C_WR_DEPTH - 1; + end else begin + tmp_rd_ptr = tmp_rd_ptr - 1; + end + end + + // output is symmetric + end else if (reads_per_write == 1) begin + tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0]; + // Retreive the error injection type. Based on the error injection type + // corrupt the output data. + tmp_ecc_err = ecc_err[rd_ptr]; + if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin + if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error + if (C_DOUT_WIDTH == 1) + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + else if (C_DOUT_WIDTH == 2) + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; + else + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; + end else begin + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + end + err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; + end else begin + err_type <= 0; + end + + // input is wider than output + end else begin + rd_ptr_high = rd_ptr >> log2_reads_per_write; + rd_ptr_low = rd_ptr & (reads_per_write - 1); + memory_read = memory[rd_ptr_high]; + tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); + end + ideal_dout <= tmp_dout; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /*********************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_wr_bits = 0; + num_rd_bits = 0; + next_num_wr_bits = 0; + next_num_rd_bits = 0; + rd_ptr = C_RD_DEPTH - 1; + wr_ptr = C_WR_DEPTH - 1; + wr_pntr = 0; + rd_pntr = 0; + rd_ptr_wrclk = rd_ptr; + wr_ptr_rdclk = wr_ptr; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + err_type = 0; + ideal_dout_d1 = dout_reset_val; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + ideal_wr_count = 0; + ideal_rd_count = 0; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_CLK; + wire RD_EN; + wire RST; + wire WR_CLK; + wire WR_EN; + */ + + //*************************************************************************** + // Dout may change behavior based on latency + //*************************************************************************** + assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; + + //*************************************************************************** + // Assign SBITERR and DBITERR based on latency + //*************************************************************************** + assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && + (C_PRELOAD_LATENCY == 2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[0]: err_type[0]; + assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && + (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[1]: err_type[1]; + + + //*************************************************************************** + // Overflow may be active-low + //*************************************************************************** + generate + if (C_HAS_OVERFLOW==1) begin : blockOF1 + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + end + endgenerate + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //*************************************************************************** + // Valid may change behavior based on latency or active-low + //*************************************************************************** + generate + if (C_HAS_VALID==1) begin : blockVL1 + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + valid_d1: valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + end + endgenerate + + + //*************************************************************************** + // Underflow may change behavior based on latency or active-low + //*************************************************************************** + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF1 + assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + end + endgenerate + + //*************************************************************************** + // Write acknowledge may be active low + //*************************************************************************** + generate + if (C_HAS_WR_ACK==1) begin : blockWK1 + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + end + endgenerate + + + //*************************************************************************** + // Generate RD_DATA_COUNT if Use Extra Logic option is selected + //*************************************************************************** + generate + if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext + + reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0; + reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0; + wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp; + wire [C_PNTR_WIDTH:0] diff_wr_rd; + reg [C_PNTR_WIDTH:0] wr_data_count_i = 0; + always @* begin + if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin + adjusted_wr_pntr = wr_pntr; + adjusted_rd_pntr = 0; + adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; + end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin + adjusted_rd_pntr = rd_pntr_wr; + adjusted_wr_pntr = 0; + adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr; + end else begin + adjusted_wr_pntr = wr_pntr; + adjusted_rd_pntr = rd_pntr_wr; + end + end // always @* + + assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr; + assign diff_wr_rd = {1'b0,diff_wr_rd_tmp}; + + always @ (posedge wr_rst_i or posedge WR_CLK) + begin + if (wr_rst_i) + wr_data_count_i <= #`TCQ 0; + else + wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC; + end // always @ (posedge WR_CLK or posedge WR_CLK) + + always @* begin + if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH) + wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0]; + else + wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + end // always @* + end // wdc_fwft_ext + endgenerate + + //*************************************************************************** + // Generate RD_DATA_COUNT if Use Extra Logic option is selected + //*************************************************************************** + reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0; + + generate + if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext + reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0; + wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp; + wire [C_RD_PNTR_WIDTH:0] diff_rd_wr; + always @* begin + if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin + adjusted_wr_pntr_rd = 0; + adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; + end else begin + adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end + end // always @* + + assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr; + assign diff_rd_wr = {1'b0,diff_rd_wr_tmp}; + + always @ (posedge rd_rst_i or posedge RD_CLK) + begin + if (rd_rst_i) begin + rdc_fwft_ext_as <= #`TCQ 0; + end else begin + if (!stage2_valid) + rdc_fwft_ext_as <= #`TCQ 0; + else if (!stage1_valid && stage2_valid) + rdc_fwft_ext_as <= #`TCQ 1; + else + rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2; + end + end // always @ (posedge WR_CLK or posedge WR_CLK) + end // rdc_fwft_ext + endgenerate + + //*************************************************************************** + // Assign the read data count value only if it is selected, + // otherwise output zeros. + //*************************************************************************** + generate + if (C_HAS_RD_DATA_COUNT == 1) begin : grdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ? + rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] : + rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH]; + end + endgenerate + + generate + if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH-1{1'b0}}; + end + endgenerate + + //*************************************************************************** + // Assign the write data count value only if it is selected, + // otherwise output zeros + //*************************************************************************** + generate + if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ? + wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] : + wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH]; + end + endgenerate + + generate + if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH-1{1'b0}}; + end + endgenerate + + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + generate + if (C_HAS_VALID==1) begin : blockVL2 + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + valid_d1 <= #`TCQ valid_i; + end + end + end + endgenerate + + //Capture delayed version of dout + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type_d1 <= #`TCQ 0; + end else if (ram_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1 <= #`TCQ err_type; + end + end + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + generate + if (C_HAS_OVERFLOW==1) begin : blockOF2 + always @(posedge WR_CLK) begin + ideal_overflow <= #`TCQ WR_EN & FULL; + end + end + endgenerate + + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF2 + always @(posedge RD_CLK) begin + ideal_underflow <= #`TCQ EMPTY & RD_EN; + end + end + endgenerate + + /************************************************************************** + * Write Domain Logic + **************************************************************************/ + reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0; + always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w + + /****** Reset fifo (case 1)***************************************/ + if (wr_rst_i == 1'b1) begin + num_wr_bits <= #`TCQ 0; + next_num_wr_bits = #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1; + ideal_wr_ack <= #`TCQ 0; + ideal_wr_count <= #`TCQ 0; + tmp_wr_listsize = #`TCQ 0; + rd_ptr_wrclk_next <= #`TCQ 0; + wr_pntr <= #`TCQ 0; + wr_pntr_rd1 <= #`TCQ 0; + rd_pntr_wr2 <= #`TCQ 0; + rd_pntr_wr3 <= #`TCQ 0; + rd_pntr_wr4 <= #`TCQ 0; + rd_pntr_wr <= #`TCQ 0; + + + end else begin //wr_rst_i==0 + + wr_pntr_rd1 <= #`TCQ wr_pntr; + + // Synchronize the rd_pntr in read domain + rd_pntr_wr2 <= #`TCQ rd_pntr_wr1; + rd_pntr_wr3 <= #`TCQ rd_pntr_wr2; + rd_pntr_wr4 <= #`TCQ rd_pntr_wr2; + rd_pntr_wr <= #`TCQ rd_pntr_wr4; + + + + //Determine the current number of words in the FIFO + tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : + num_wr_bits/C_DIN_WIDTH; + rd_ptr_wrclk_next = rd_ptr; + if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH + - rd_ptr_wrclk_next); + end else begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); + end + + //If this is a write, handle the write by adding the value + // to the linked list, and updating all outputs appropriately + if (WR_EN == 1'b1) begin + if (FULL == 1'b1) begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD + >= C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is one from full, but reporting full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= #`TCQ 0; + //With DEPTH-1 words in the FIFO, it is almost_full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + + //If the FIFO is completely empty, but it is + // reporting FULL for some reason (like reset) + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <= + C_FIFO_WR_DEPTH-2) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= #`TCQ 0; + //FIFO is really not close to full, so change flag status. + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end //(tmp_wr_listsize == 0) + + end else begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= + C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is one from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //This write is CAUSING the FIFO to go full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is 2 from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Still 2 from full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is not close to being full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD < + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Not even close to full. + + ideal_wr_count <= num_write_words_sized_i; + + end + + end + + end else begin //(WR_EN == 1'b1) + + //If user did not attempt a write, then do not + // give ack or err + ideal_wr_ack <= #`TCQ 0; + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end + num_wr_bits <= #`TCQ next_num_wr_bits; + rd_ptr_wrclk <= #`TCQ rd_ptr; + + end //wr_rst_i==0 + end // write always + + + /*************************************************************************** + * Programmable FULL flags + ***************************************************************************/ + + always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf + + if (RST_FULL_FF == 1'b1) begin + diff_pntr <= 0; + ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + end else begin + if (ram_wr_en) + diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1); + else if (!ram_wr_en) + diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr); + + if (RST_FULL_GEN) + ideal_prog_full <= #`TCQ 0; + //Single Programmable Full Constant Threshold + else if (C_PROG_FULL_TYPE == 1) begin + if (FULL == 0) begin + if (diff_pntr >= C_PROG_FULL_THRESH_ASSERT_VAL) + ideal_prog_full <= #`TCQ 1; + else + ideal_prog_full <= #`TCQ 0; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Two Programmable Full Constant Thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if (FULL == 0) begin + if (diff_pntr >= C_PROG_FULL_THRESH_ASSERT_VAL) + ideal_prog_full <= #`TCQ 1; + else if (diff_pntr < C_PROG_FULL_THRESH_NEGATE_VAL) + ideal_prog_full <= #`TCQ 0; + else + ideal_prog_full <= #`TCQ ideal_prog_full; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Single Programmable Full Threshold Input + end else if (C_PROG_FULL_TYPE == 3) begin + if (FULL == 0) begin + if (diff_pntr >= PROG_FULL_THRESH) + ideal_prog_full <= #`TCQ 1; + else + ideal_prog_full <= #`TCQ 0; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Two Programmable Full Threshold Inputs + end else if (C_PROG_FULL_TYPE == 4) begin + if (FULL == 0) begin + if (diff_pntr >= PROG_FULL_THRESH_ASSERT) + ideal_prog_full <= #`TCQ 1; + else if (diff_pntr < PROG_FULL_THRESH_NEGATE) + ideal_prog_full <= #`TCQ 0; + else + ideal_prog_full <= #`TCQ ideal_prog_full; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + end // C_PROG_FULL_TYPE + + end //wr_rst_i==0 + end // + + + /************************************************************************** + * Read Domain Logic + **************************************************************************/ + + + /********************************************************* + * Programmable EMPTY flags + *********************************************************/ + //Determine the Assert and Negate thresholds for Programmable Empty + + reg [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val = 0; + reg [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val = 0; + reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0; + always @* begin + + if (C_PROG_EMPTY_TYPE == 3) begin + + // If empty input threshold is selected, then subtract 2 for FWFT to + // compensate the FWFT stage, otherwise assign the input value. + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) // FWFT + pe_thr_assert_val <= PROG_EMPTY_THRESH - 2'h2; + else + pe_thr_assert_val <= PROG_EMPTY_THRESH; + + end else if (C_PROG_EMPTY_TYPE == 4) begin + + // If empty input threshold is selected, then subtract 2 for FWFT to + // compensate the FWFT stage, otherwise assign the input value. + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT + pe_thr_assert_val <= PROG_EMPTY_THRESH_ASSERT - 2'h2; + pe_thr_negate_val <= PROG_EMPTY_THRESH_NEGATE - 2'h2; + end else begin + pe_thr_assert_val <= PROG_EMPTY_THRESH_ASSERT; + pe_thr_negate_val <= PROG_EMPTY_THRESH_NEGATE; + end + end else begin + + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT + pe_thr_assert_val <= C_PROG_EMPTY_THRESH_ASSERT_VAL - 2; + pe_thr_negate_val <= C_PROG_EMPTY_THRESH_NEGATE_VAL - 2; + end else begin + pe_thr_assert_val <= C_PROG_EMPTY_THRESH_ASSERT_VAL; + pe_thr_negate_val <= C_PROG_EMPTY_THRESH_NEGATE_VAL; + end + end + end // always @* + + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe + + if (rd_rst_i) begin + diff_pntr_rd <= #`TCQ 0; + ideal_prog_empty <= #`TCQ 1'b1; + end else begin + if (ram_rd_en) + diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1; + else if (!ram_rd_en) + diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr); + else + diff_pntr_rd <= #`TCQ diff_pntr_rd; + + if (C_PROG_EMPTY_TYPE == 1) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else + ideal_prog_empty <= #`TCQ 0; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 2) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else if (diff_pntr_rd > pe_thr_negate_val) + ideal_prog_empty <= #`TCQ 0; + else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 3) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else + ideal_prog_empty <= #`TCQ 0; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 4) begin + if (EMPTY == 0) begin + if (diff_pntr_rd >= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else if (diff_pntr_rd > pe_thr_negate_val) + ideal_prog_empty <= #`TCQ 0; + else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end //C_PROG_EMPTY_TYPE + end + end + + // block memory has a synchronous reset + always @(posedge RD_CLK) begin : gen_fifo_blkmemdout + // make it consistent with the core. + if (rd_rst_i) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0 && C_MEMORY_TYPE < 2) + err_type <= #`TCQ 0; + + // BRAM resets synchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin + ideal_dout <= #`TCQ dout_reset_val; + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end + end //always + + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r + + /****** Reset fifo (case 1)***************************************/ + if (rd_rst_i) begin + num_rd_bits <= #`TCQ 0; + next_num_rd_bits = #`TCQ 0; + rd_ptr <= #`TCQ C_RD_DEPTH -1; + rd_pntr <= #`TCQ 0; + rd_pntr_wr1 <= #`TCQ 0; + wr_pntr_rd2 <= #`TCQ 0; + wr_pntr_rd3 <= #`TCQ 0; + wr_pntr_rd <= #`TCQ 0; + wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1; + + // DRAM resets asynchronously + if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1) + ideal_dout <= #`TCQ dout_reset_val; + + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type <= #`TCQ 0; + ideal_valid <= #`TCQ 1'b0; + ideal_rd_count <= #`TCQ 0; + + end else begin //rd_rst_i==0 + + rd_pntr_wr1 <= #`TCQ rd_pntr; + + // Synchronize the wr_pntr in read domain + wr_pntr_rd2 <= #`TCQ wr_pntr_rd1; + wr_pntr_rd3 <= #`TCQ wr_pntr_rd2; + wr_pntr_rd <= #`TCQ wr_pntr_rd3; + + + + //Determine the current number of words in the FIFO + tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : + num_rd_bits/C_DOUT_WIDTH; + wr_ptr_rdclk_next = wr_ptr; + + if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH + - wr_ptr_rdclk_next); + end else begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); + end + + /*****************************************************************/ + // Read Operation - Read Latency 1 + /*****************************************************************/ + if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin + ideal_valid <= #`TCQ 1'b0; + + if (ram_rd_en == 1'b1) begin + + if (EMPTY == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + end // if (tmp_rd_listsize <= 0) + + //If the FIFO is one from empty, but it is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + //If the FIFO is two from empty, and is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Fifo has two words, so is neither empty or almost empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + end // else: if(ideal_empty == 1'b1) + + else //if (ideal_empty == 1'b0) + begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) + + //If the FIFO is not close to being empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + //If the FIFO is two from empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Fifo is not yet empty. It is going almost_empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is one from empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Note that FIFO is GOING empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + + //If the FIFO is completely empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end //(RD_EN == 1'b1) + + else //if (RD_EN == 1'b0) + begin + //If user did not attempt a read, do not give an ack or err + ideal_valid <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + + /*****************************************************************/ + // Read Operation - Read Latency 0 + /*****************************************************************/ + end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + ideal_valid <= #`TCQ 1'b0; + if (ram_rd_en == 1'b1) begin + + if (EMPTY == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is one from empty, but it is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is two from empty, and is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Fifo has two words, so is neither empty or almost empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + end else begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is not close to being empty + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is two from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Fifo is not yet empty. It is going almost_empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is one from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Note that FIFO is GOING empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is completely empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end else begin//(RD_EN == 1'b0) + + + //If user did not attempt a read, do not give an ack or err + ideal_valid <= #`TCQ 1'b0; + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + num_rd_bits <= #`TCQ next_num_rd_bits; + wr_ptr_rdclk <= #`TCQ wr_ptr; + end //rd_rst_i==0 + end //always + +endmodule // fifo_generator_v6_1_bhv_ver_as + + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module fifo_generator_v6_1_bhv_ver_ss + + /************************************************************************** + * Declare user parameters and their defaults + *************************************************************************/ + #( + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RST = 0, + parameter C_HAS_SRST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_OVERFLOW_LOW = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_USE_ECC = 0, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0 + ) + + /************************************************************************** + * Declare Input and Output Ports + *************************************************************************/ + ( + //Inputs + input CLK, + input [C_DIN_WIDTH-1:0] DIN, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, + input RD_EN, + input RST, + input RST_FULL_GEN, + input RST_FULL_FF, + input SRST, + input WR_EN, + input INJECTDBITERR, + input INJECTSBITERR, + + //Outputs + output ALMOST_EMPTY, + output ALMOST_FULL, + output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT, + output [C_DOUT_WIDTH-1:0] DOUT, + output EMPTY, + output FULL, + output OVERFLOW, + output PROG_EMPTY, + output PROG_FULL, + output VALID, + output UNDERFLOW, + output WR_ACK, + output SBITERR, + output DBITERR + ); + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not + //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. + // Therefore, during SRST, all the FULL flags reset to 0. + parameter C_HAS_FAST_FIFO = 0; + parameter C_FIFO_WR_DEPTH = C_WR_DEPTH; + parameter C_FIFO_RD_DEPTH = C_RD_DEPTH; + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + // Local parameters used to determine whether to inject ECC error or not + localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; + localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; + localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; + // Array that holds the error injection type (single/double bit error) on + // a specific write operation, which is returned on read to corrupt the + // output data. + reg [1:0] ecc_err[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_bits. + //num_bits is calculated by from the total words in the FIFO. + reg [31:0] num_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + + //The write pointer - tracks read operations + // (Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + + /************************** + * Data Count + *************************/ + //Amount of data stored in the FIFO scaled to read words + wire [31:0] num_read_words = num_bits/C_DOUT_WIDTH; + //num_read_words delayed 1 clock cycle + reg [31:0] num_read_words_q; + + //Amount of data stored in the FIFO scaled to write words + wire [31:0] num_write_words = num_bits/C_DIN_WIDTH; + //num_write_words delayed 1 clock cycle + reg [31:0] num_write_words_q; + + + /************************************************************************** + * Internal Registers and wires + *************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire underflow_i; + wire valid_i; + wire valid_out; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [1:0] err_type = 0; + reg [1:0] err_type_d1 = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire fwft_enabled; + reg ideal_wr_ack = 0; + reg ideal_valid = 0; + reg ideal_overflow = 0; + reg ideal_underflow = 0; + reg ideal_full = 0; + reg ideal_empty = 1; + reg ideal_almost_full = 0; + reg ideal_almost_empty = 1; + reg ideal_prog_full = 0; + reg ideal_prog_empty = 1; + + //Assorted reg values for delayed versions of signals + reg valid_d1 = 0; + reg prog_full_d = 0; + reg prog_empty_d = 1; + + wire rst_i; + wire srst_i; + + //Delayed version of RST + reg rst_q; + reg rst_qq; + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + reg [1:0] corrupted_data; + begin + memory[wr_ptr] <= DIN; + // Store the type of error injection (double/single) on write + case (C_ERROR_INJECTION_TYPE) + 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; + 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; + 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; + default: ecc_err[wr_ptr] <= 0; + endcase + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [1:0] tmp_ecc_err; + begin + tmp_dout = memory[rd_ptr][C_DOUT_WIDTH-1:0]; + // Retreive the error injection type. Based on the error injection type + // corrupt the output data. + tmp_ecc_err = ecc_err[rd_ptr]; + if (ENABLE_ERR_INJECTION) begin + if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error + if (C_DOUT_WIDTH == 1) + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + else if (C_DOUT_WIDTH == 2) + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; + else + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; + end else begin + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + end + err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; + end else begin + err_type <= 0; + end + ideal_dout <= tmp_dout; + + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /**************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /**************************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***************************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_bits = 0; + num_read_words_q = 0; + num_write_words_q = 0; + rd_ptr = C_RD_DEPTH -1; + wr_ptr = C_WR_DEPTH -1; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + err_type = 0; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + ideal_full = 1'b0; + ideal_empty = 1'b1; + ideal_almost_full = 1'b0; + ideal_almost_empty = 1'b1; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + prog_full_d = 1'b0; + prog_empty_d = 1'b1; + rst_q = 1'b0; + rst_qq = 1'b0; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire CLK; + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_EN; + wire RST; + wire WR_EN; + */ + + //Outputs + generate + if (C_HAS_ALMOST_EMPTY==1) begin : blockAE10 + assign ALMOST_EMPTY = ideal_almost_empty; + end + endgenerate + + generate + if (C_HAS_ALMOST_FULL==1) begin : blockAF10 + assign ALMOST_FULL = ideal_almost_full; + end + endgenerate + + //Dout may change behavior based on latency + assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)? + 1: 0; + assign ideal_dout_out= ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT = ideal_dout_out; + + // Assign SBITERR and DBITERR based on latency + assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && + ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[0]: err_type[0]; + assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && + ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[1]: err_type[1]; + + assign EMPTY = ideal_empty; + assign FULL = ideal_full; + + //Overflow may be active-low + generate + if (C_HAS_OVERFLOW==1) begin : blockOF10 + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + end + endgenerate + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //Valid may change behavior based on latency or active-low + generate + if (C_HAS_VALID==1) begin : blockVL10 + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + valid_d1: valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + end + endgenerate + + //Trim data count differently depending on set widths + generate + if ((C_HAS_DATA_COUNT == 1) && + (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH)) begin : blockDC1 + always @(num_read_words) + DATA_COUNT = num_read_words[C_RD_PNTR_WIDTH:0]; + end else if (C_HAS_DATA_COUNT == 1) begin : blockDC2 + always @(num_read_words) + DATA_COUNT = num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; + end //if + endgenerate + + //Underflow may change behavior based on latency or active-low + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF10 + assign underflow_i = ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + end + endgenerate + + + //Write acknowledge may be active low + generate + if (C_HAS_WR_ACK==1) begin : blockWK10 + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + end + endgenerate + + + /***************************************************************************** + * Internal reset logic + ****************************************************************************/ + assign srst_i = C_HAS_SRST ? SRST : 0; + assign rst_i = C_HAS_RST ? RST : 0; + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + generate + if (C_HAS_VALID==1) begin : blockVL20 + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + if (srst_i) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + valid_d1 <= #`TCQ valid_i; + end + end + end // always @ (posedge CLK or posedge rst_i) + end + endgenerate + + + // block memory has a synchronous reset + always @(posedge CLK) begin : gen_fifo_blkmemdout_emb + // make it consistent with the core. + if (rst_i || srst_i) begin + // BRAM resets synchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end + end //always + + reg ram_rd_en_d1 = 1'b0; + //Capture delayed version of dout + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type_d1 <= #`TCQ 0; + + // DRAM and SRAM reset asynchronously + if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) + ideal_dout_d1 <= #`TCQ dout_reset_val; + + ram_rd_en_d1 <= #`TCQ 1'b0; + end else begin + ram_rd_en_d1 <= #`TCQ RD_EN & !EMPTY; + if (srst_i) begin + ram_rd_en_d1 <= #`TCQ 1'b0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type_d1 <= #`TCQ 0; + // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above + if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end else if (ram_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1 <= #`TCQ err_type; + end + end + end + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + generate + if (C_HAS_OVERFLOW==1) begin : blockOF20 + always @(posedge CLK) begin + ideal_overflow <= #`TCQ WR_EN & ideal_full; + end + end + endgenerate + + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF20 + always @(posedge CLK) begin + ideal_underflow <= #`TCQ ideal_empty & RD_EN; + end + end + endgenerate + + /************************************************************************* + * Write and Read Logic + ************************************************************************/ + always @(posedge CLK or posedge rst_i) + begin : gen_wr_ack_resp + + //Register reset + rst_q <= #`TCQ rst_i; + rst_qq <= #`TCQ rst_q; + + end // block: gen_wr_ack_resp + + // block memory has a synchronous reset + always @(posedge CLK) begin : gen_fifo_blkmemdout + //Changed the latency of during async reset to '1' instead of '2' to + // make it consistent with the core. + if (rst_i || rst_q || srst_i) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0 && C_MEMORY_TYPE == 1) + err_type <= #`TCQ 0; + /******Initialize Read Domain Signals*********************************/ + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin + ideal_dout <= #`TCQ dout_reset_val; + end + end + end //always + + // FULL_FLAG_RESET value given for SRST as well. + reg srst_i_d1 = 0; + reg srst_i_d2 = 0; + always @(posedge CLK or posedge RST_FULL_FF) begin : gen_fifo + + /****** Reset fifo - Asynchronous Reset**********************************/ + //Changed the latency of during async reset to '1' instead of '2' to + // make it consistent with the core. + if (RST_FULL_FF) begin //v3.2 + /******Initialize Generic FIFO constructs*****************************/ + num_bits <= #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr <= #`TCQ C_RD_DEPTH - 1; + num_read_words_q <= #`TCQ 0; + num_write_words_q <= #`TCQ 0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0 && C_MEMORY_TYPE != 1) + err_type <= #`TCQ 0; + + + /******Initialize Write Domain Signals********************************/ + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + + /******Initialize Read Domain Signals*********************************/ + // DRAM and SRAM reset asynchronously + if (C_USE_DOUT_RST == 1 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3)) begin + ideal_dout <= #`TCQ dout_reset_val; + end + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + end else begin + // Register SRST twice to be consistant with RST behavior + srst_i_d1 <= #`TCQ srst_i; + srst_i_d2 <= #`TCQ srst_i_d1; + if (srst_i) begin + // SRST is available only for Sync BRAM, DRAM and SRAM. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) begin + /******Initialize Generic FIFO constructs***********************/ + num_bits <= #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr <= #`TCQ C_RD_DEPTH - 1; + num_read_words_q <= #`TCQ 0; + num_write_words_q <= #`TCQ 0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type <= #`TCQ 0; + + /******Initialize Write Domain Signals**************************/ + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + + /******Initialize Read Domain Signals***************************/ + //Reset DOUT of Sync DRAM/Shift RAM. Sync BRAM DOUT was reset in the + // above always block. + if (C_USE_DOUT_RST == 1 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3)) begin + ideal_dout <= #`TCQ dout_reset_val; + end + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + end + + end else if ((srst_i_d1 || srst_i_d2) && (C_FULL_FLAGS_RST_VAL == 1)) begin //Hold full flag reset value set during RST/SRST + ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + end else begin //normal operating conditions + /********************************************************************/ + // Synchronous FIFO Condition #1 : Writing and not reading + /********************************************************************/ + ideal_valid <= #`TCQ 1'b0; + if (WR_EN & ~RD_EN) begin + + /*********************************/ + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + ideal_wr_ack <= #`TCQ 0; + + //still full + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + + /*********************************/ + //If the FIFO is reporting FULL + // (Startup condition) + /*********************************/ + end else if ((num_write_words < C_FIFO_WR_DEPTH) && (ideal_full == 1'b1)) begin + ideal_wr_ack <= #`TCQ 0; + + //still full + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //FIFO EMPTY in this state can not be determined + //ideal_empty <= 1'b0; + //ideal_almost_empty <= 1'b0; + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + //good write + ideal_wr_ack <= #`TCQ 1; + + //FIFO is one from FULL and going FULL + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is 2 from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-2) begin + //good write + ideal_wr_ack <= #`TCQ 1; + + //2 from full, and writing, so set almost_full + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //Add input data + write_fifo; + + //no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //good write + ideal_wr_ack <= #`TCQ 1; + + //Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Leaving ALMOST_EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + // good write + ideal_wr_ack <= #`TCQ 1; + + //Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Leaving EMPTY (still ALMOST_EMPTY) + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + // good write + ideal_wr_ack <= #`TCQ 1; + + //Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + end // average case + + + /******************************************************************/ + // Synchronous FIFO Condition #2 : Reading and not writing + /******************************************************************/ + end else if (~WR_EN & RD_EN) begin + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + if ((num_read_words == 0) || (ideal_empty == 1'b1)) begin + //no write attemped + ideal_wr_ack <= #`TCQ 0; + + //FIFO is not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read will fail + ideal_valid <= #`TCQ 1'b0; + + //FIFO is still empty + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //No read + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //This read will make FIFO go empty + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is 2 from EMPTY + /*********************************/ + end else if (num_read_words == 2) begin + + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //FIFO is going ALMOST_EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is leaving ALMOST FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is FULL + /*********************************/ + end else if (num_write_words >= C_FIFO_WR_DEPTH) + begin + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is leaving FULL, but is still ALMOST_FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + //no write attemped + ideal_wr_ack <= #`TCQ 0; + + //Not near empty + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + end // average read + + + /******************************************************************/ + // Synchronous FIFO Condition #3 : Reading and writing + /******************************************************************/ + end else if (WR_EN & RD_EN) begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + ideal_wr_ack <= #`TCQ 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is reporting FULL, but it is empty + // (This is a special case, when coming out of RST + /*********************************/ + end else if ((num_write_words == 0) && (ideal_full == 1'b1)) begin + + ideal_wr_ack <= #`TCQ 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read unsuccessful + ideal_valid <= #`TCQ 1'b0; + + //Report empty condition + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //Do not read from empty FIFO + // Read from the FIFO + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + //FIFO will remain ALMOST_FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + // Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //FIFO will stay ALMOST_EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + // Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read will fail + ideal_valid <= #`TCQ 1'b0; + + //FIFO will leave EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + // No read + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + // Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + // Not near EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + end // average case + + /******************************************************************/ + // Synchronous FIFO Condition #4 : Not reading or writing + /******************************************************************/ + end else begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + //No change to memory + + end // almost empty + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + else if (num_read_words == 0) + begin + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //No change to memory + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //No change to memory + + end // average case + + end // neither reading or writing + + num_read_words_q <= #`TCQ num_read_words; + num_write_words_q <= #`TCQ num_write_words; + + end //normal operating conditions + end + + end // block: gen_fifo + + + always @(posedge CLK or posedge RST_FULL_FF) begin : gen_fifo_p + + /****** Reset fifo - Async Reset****************************************/ + //The latency of de-assertion of the flags is reduced by 1 to be + // consistent with the core. + if (RST_FULL_FF) begin + ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_prog_empty <= #`TCQ 1'b1; + prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; + prog_empty_d <= #`TCQ 1'b1; + + end else begin + if (srst_i) begin + //SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) begin + ideal_prog_empty <= #`TCQ 1'b1; + prog_empty_d <= #`TCQ 1'b1; + ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; + end + end else if ((srst_i_d1 || srst_i_d2) && (C_FULL_FLAGS_RST_VAL == 1)) begin + ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; + end else begin + + /*************************************************************** + * Programmable FULL flags + ****************************************************************/ + //calculation for standard fifo and latency =2 + if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin + //Single constant threshold + if (C_PROG_FULL_TYPE == 1) begin + if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL) + && RD_EN && !WR_EN) || (RST_FULL_GEN)) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual constant thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL) + && RD_EN && !WR_EN) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_FULL_TYPE == 3) begin + if ((num_write_words == PROG_FULL_THRESH-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH) + && !WR_EN && RD_EN) begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if ((num_write_words == PROG_FULL_THRESH_ASSERT-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH_NEGATE) + && !WR_EN && RD_EN)begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH_ASSERT) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH_NEGATE) begin + prog_full_d <= #`TCQ 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + + //calculation for FWFT fifo + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + if (C_PROG_FULL_TYPE == 1) begin + if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL - 2) + && RD_EN && !WR_EN) || (RST_FULL_GEN)) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual constant thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL - 2) + && RD_EN && !WR_EN) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_FULL_TYPE == 3) begin + if ((num_write_words == PROG_FULL_THRESH-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH - 2) + && !WR_EN && RD_EN) begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH - 2) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH - 2) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if ((num_write_words == PROG_FULL_THRESH_ASSERT-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH_NEGATE - 2) + && !WR_EN && RD_EN)begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH_ASSERT - 2) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH_NEGATE - 2) begin + prog_full_d <= #`TCQ 1'b0; + end + end + end // (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + /***************************************************************** + * Programmable EMPTY flags + ****************************************************************/ + //calculation for standard fifo and latency = 2 + if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin + //Single constant threshold + if (C_PROG_EMPTY_TYPE == 1) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL) + && WR_EN && !RD_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + //Dual constant thresholds + end else if (C_PROG_EMPTY_TYPE == 2) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_EMPTY_TYPE == 3) begin + if ((num_read_words == PROG_EMPTY_THRESH+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end else if (num_read_words <= PROG_EMPTY_THRESH) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH)begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if (num_read_words <= PROG_EMPTY_THRESH_ASSERT) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE)begin + prog_empty_d <= #`TCQ 1'b0; + end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + //calculation for FWFT fifo + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + //Single constant threshold + if (C_PROG_EMPTY_TYPE == 1) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL - 2) + && WR_EN && !RD_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + //Dual constant thresholds + end else if (C_PROG_EMPTY_TYPE == 2) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_EMPTY_TYPE == 3) begin + if ((num_read_words == PROG_EMPTY_THRESH+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end else if (num_read_words <= PROG_EMPTY_THRESH - 2) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH - 2)begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if (num_read_words <= PROG_EMPTY_THRESH_ASSERT - 2) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE - 2)begin + prog_empty_d <= #`TCQ 1'b0; + end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + ideal_prog_empty <= prog_empty_d; + if (RST_FULL_GEN) begin + ideal_prog_full <= #`TCQ 1'b0; + prog_full_d <= #`TCQ 1'b0; + end else begin + ideal_prog_full <= #`TCQ prog_full_d; + end + + end //if (srst_i) begin + end //if (rst_i) begin + end //always @(posedge CLK or posedge rst_i) begin : gen_fifo_p +endmodule // fifo_generator_v6_1_bhv_ver_ss + + + +/************************************************************************** + * First-Word Fall-Through module (preload 0) + **************************************************************************/ +module fifo_generator_v6_1_bhv_ver_preload0 + ( + RD_CLK, + RD_RST, + SRST, + RD_EN, + FIFOEMPTY, + FIFODATA, + FIFOSBITERR, + FIFODBITERR, + USERDATA, + USERVALID, + USERUNDERFLOW, + USEREMPTY, + USERALMOSTEMPTY, + RAMVALID, + FIFORDEN, + USERSBITERR, + USERDBITERR + ); + + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_HAS_RST = 0; + parameter C_ENABLE_RST_SYNC = 0; + parameter C_HAS_SRST = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_ECC = 0; + parameter C_USERVALID_LOW = 0; + parameter C_USERUNDERFLOW_LOW = 0; + parameter C_MEMORY_TYPE = 0; + + //Inputs + input RD_CLK; + input RD_RST; + input SRST; + input RD_EN; + input FIFOEMPTY; + input [C_DOUT_WIDTH-1:0] FIFODATA; + input FIFOSBITERR; + input FIFODBITERR; + + //Outputs + output [C_DOUT_WIDTH-1:0] USERDATA; + output USERVALID; + output USERUNDERFLOW; + output USEREMPTY; + output USERALMOSTEMPTY; + output RAMVALID; + output FIFORDEN; + output USERSBITERR; + output USERDBITERR; + + //Inputs + wire RD_CLK; + wire RD_RST; + wire RD_EN; + wire FIFOEMPTY; + wire [C_DOUT_WIDTH-1:0] FIFODATA; + wire FIFOSBITERR; + wire FIFODBITERR; + + //Outputs + reg [C_DOUT_WIDTH-1:0] USERDATA; + wire USERVALID; + wire USERUNDERFLOW; + wire USEREMPTY; + wire USERALMOSTEMPTY; + wire RAMVALID; + wire FIFORDEN; + reg USERSBITERR; + reg USERDBITERR; + + //Internal signals + wire preloadstage1; + wire preloadstage2; + reg ram_valid_i; + reg read_data_valid_i; + wire ram_regout_en; + wire ram_rd_en; + reg empty_i = 1'b1; + reg empty_q = 1'b1; + reg rd_en_q = 1'b0; + reg almost_empty_i = 1'b1; + reg almost_empty_q = 1'b1; + wire rd_rst_i; + wire srst_i; + + +/************************************************************************* +* FUNCTIONS +*************************************************************************/ + + /************************************************************************* + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + //************************************************************************* + // Set power-on states for regs + //************************************************************************* + initial begin + ram_valid_i = 1'b0; + read_data_valid_i = 1'b0; + USERDATA = hexstr_conv(C_DOUT_RST_VAL); + USERSBITERR = 1'b0; + USERDBITERR = 1'b0; + end //initial + + //*************************************************************************** + // connect up optional reset + //*************************************************************************** + assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0; + assign srst_i = C_HAS_SRST ? SRST : 0; + + + //*************************************************************************** + // preloadstage2 indicates that stage2 needs to be updated. This is true + // whenever read_data_valid is false, and RAM_valid is true. + //*************************************************************************** + assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN); + + //*************************************************************************** + // preloadstage1 indicates that stage1 needs to be updated. This is true + // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is + // false (indicating that Stage1 needs updating), or preloadstage2 is active + // (indicating that Stage2 is going to update, so Stage1, therefore, must + // also be updated to keep it valid. + //*************************************************************************** + assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); + + //*************************************************************************** + // Calculate RAM_REGOUT_EN + // The output registers are controlled by the ram_regout_en signal. + // These registers should be updated either when the output in Stage2 is + // invalid (preloadstage2), OR when the user is reading, in which case the + // Stage2 value will go invalid unless it is replenished. + //*************************************************************************** + assign ram_regout_en = preloadstage2; + + //*************************************************************************** + // Calculate RAM_RD_EN + // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to + // update the value in Stage1. + // One case when this happens is when preloadstage1=true, which indicates + // that the data in Stage1 or Stage2 is invalid, and needs to automatically + // be updated. + // The other case is when the user is reading from the FIFO, which + // guarantees that Stage1 or Stage2 will be invalid on the next clock + // cycle, unless it is replinished by data from the memory. So, as long + // as the RAM has data in it, a read of the RAM should occur. + //*************************************************************************** + assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; + + //*************************************************************************** + // Calculate RAMVALID_P0_OUT + // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. + // + // If the RAM is being read from on this clock cycle (ram_rd_en=1), then + // RAMVALID_P0_OUT is certainly going to be true. + // If the RAM is not being read from, but the output registers are being + // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, + // therefore causing RAMVALID_P0_OUT to be false. + // Otherwise, RAMVALID_P0_OUT will remain unchanged. + //*************************************************************************** + // PROCESS regout_valid + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + ram_valid_i <= #`TCQ 1'b0; + end else begin + if (srst_i) begin + // synchronous reset (active high) + ram_valid_i <= #`TCQ 1'b0; + end else begin + if (ram_rd_en == 1'b1) begin + ram_valid_i <= #`TCQ 1'b1; + end else begin + if (ram_regout_en == 1'b1) + ram_valid_i <= #`TCQ 1'b0; + else + ram_valid_i <= #`TCQ ram_valid_i; + end + end //srst_i + end //rd_rst_i + end //always + + //*************************************************************************** + // Calculate READ_DATA_VALID + // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. + // Stage2 has valid data whenever Stage1 had valid data and + // ram_regout_en_i=1, such that the data in Stage1 is propogated + // into Stage2. + //*************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + read_data_valid_i <= #`TCQ 1'b0; + else if (srst_i) + read_data_valid_i <= #`TCQ 1'b0; + else + read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN); + end //always + + + //************************************************************************** + // Calculate EMPTY + // Defined as the inverse of READ_DATA_VALID + // + // Description: + // + // If read_data_valid_i indicates that the output is not valid, + // and there is no valid data on the output of the ram to preload it + // with, then we will report empty. + // + // If there is no valid data on the output of the ram and we are + // reading, then the FIFO will go empty. + // + //************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + if (srst_i) begin + // synchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + // rising clock edge + empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); + end + end + end //always + + // Register RD_EN from user to calculate USERUNDERFLOW. + // Register empty_i to calculate USERUNDERFLOW. + always @ (posedge RD_CLK) begin + rd_en_q <= #`TCQ RD_EN; + empty_q <= #`TCQ empty_i; + end //always + + + //*************************************************************************** + // Calculate user_almost_empty + // user_almost_empty is defined such that, unless more words are written + // to the FIFO, the next read will cause the FIFO to go EMPTY. + // + // In most cases, whenever the output registers are updated (due to a user + // read or a preload condition), then user_almost_empty will update to + // whatever RAM_EMPTY is. + // + // The exception is when the output is valid, the user is not reading, and + // Stage1 is not empty. In this condition, Stage1 will be preloaded from the + // memory, so we need to make sure user_almost_empty deasserts properly under + // this condition. + //*************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin // asynchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin // rising clock edge + if (srst_i) begin // synchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin + if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin + almost_empty_i <= #`TCQ FIFOEMPTY; + end + almost_empty_q <= #`TCQ empty_i; + end + end + end //always + + + assign USEREMPTY = empty_i; + assign USERALMOSTEMPTY = almost_empty_i; + assign FIFORDEN = ram_rd_en; + assign RAMVALID = ram_valid_i; + assign USERVALID = C_USERVALID_LOW ? ~read_data_valid_i : read_data_valid_i; + assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; + + // BRAM resets synchronously + always @ (posedge RD_CLK) + begin + if (rd_rst_i || srst_i) begin + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end //always + + + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin //asynchronous reset (active high) + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + end + // DRAM resets asynchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) //asynchronous reset (active high) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end else begin // rising clock edge + if (srst_i) begin + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + end + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end else begin + if (ram_regout_en) begin + USERDATA <= #`TCQ FIFODATA; + USERSBITERR <= #`TCQ FIFOSBITERR; + USERDBITERR <= #`TCQ FIFODBITERR; + end + end + end + end //always + +endmodule + diff --git a/usrp2/top/u1plus/core_compile b/usrp2/top/u1plus/core_compile new file mode 100755 index 000000000..0d95f704d --- /dev/null +++ b/usrp2/top/u1plus/core_compile @@ -0,0 +1,2 @@ +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ u1plus_core.v 2>&1 + -- cgit v1.2.3 From fd2f7f333a643f070a9f9c19228ea83c15c875fb Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 16 Mar 2011 21:23:47 -0700 Subject: u1p: revert change to address bus width --- usrp2/top/u1plus/u1plus_core.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index 0fbc2f593..8e83c01ff 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -54,7 +54,7 @@ module u1plus_core // ///////////////////////////////////////////////////////////////////////////////////// // GPIF Slave to Wishbone Master localparam dw = 16; - localparam aw = 16; + localparam aw = 11; localparam sw = 2; wire [dw-1:0] m0_dat_mosi, m0_dat_miso; @@ -361,7 +361,7 @@ module u1plus_core wb_readback_mux_16LE readback_mux_32 (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s7_stb), - .wb_adr_i(s7_adr), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack), + .wb_adr_i({5'b0,s7_adr}), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack), .word00(vita_time[63:32]), .word01(vita_time[31:0]), .word02(vita_time_pps[63:32]), .word03(vita_time_pps[31:0]), -- cgit v1.2.3 From 262c6e9225889a1ff4afd045ad0c6d929d06478c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 17 Mar 2011 12:23:20 -0700 Subject: u1p: added loopback and timed capability just like u1e --- usrp2/gpif/gpif.v | 110 ++++++++++++++++++++++++++++++++++------- usrp2/top/u1plus/core_compile | 3 +- usrp2/top/u1plus/u1plus_core.v | 26 +++++++--- 3 files changed, 111 insertions(+), 28 deletions(-) diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index 14ed2690f..e72490b17 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -17,7 +17,9 @@ module gpif input fifo_clk, input fifo_rst, input clear_tx, input clear_rx, output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, - + + output tx_underrun, output rx_overrun, + input [7:0] test_rate, input [3:0] test_ctrl, output [31:0] debug0, output [31:0] debug1 ); @@ -38,12 +40,12 @@ module gpif wire [31:0] debug_rd, debug_wr; // //////////////////////////////////////////////////////////////////// - // TX Side - + // TX Data Path + wire [18:0] tx19_data; wire tx19_src_rdy, tx19_dst_rdy; - wire [35:0] tx36_data; - wire tx36_src_rdy, tx36_dst_rdy; + wire [35:0] tx36_data, tx_data; + wire tx36_src_rdy, tx36_dst_rdy, tx_src_rdy, tx_dst_rdy; wire [18:0] ctrl_data; wire ctrl_src_rdy, ctrl_dst_rdy; @@ -64,27 +66,27 @@ module gpif .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy), - .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i)); + .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy)); - // //////////////////////////////////////////////////////////////////// - // RX Side + // //////////////////////////////////////////// + // RX Data Path - wire [35:0] rx36_data; - wire rx36_src_rdy, rx36_dst_rdy; + wire [35:0] rx36_data, rx_data; + wire rx36_src_rdy, rx36_dst_rdy, rx_src_rdy, rx_dst_rdy; wire [18:0] rx19_data; wire rx19_src_rdy, rx19_dst_rdy; wire [18:0] resp_data, resp_int; wire resp_src_rdy, resp_dst_rdy, resp_src_rdy_int, resp_dst_rdy_int; fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .datain(rx_data), .src_rdy_i(rx_src_rdy), .dst_rdy_o(rx_dst_rdy), .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // FIXME Endianness? - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), .f19_dataout(rx19_data), .f19_src_rdy_o(rx19_src_rdy), .f19_dst_rdy_i(rx19_dst_rdy) ); @@ -115,14 +117,84 @@ module gpif .data_i(resp_int), .src_rdy_i(resp_src_rdy_int), .dst_rdy_o(resp_dst_rdy_int), .data_o(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy)); + // //////////////////////////////////////////////////////////////////// + // Debug support, timed and loopback + // RX side muxes test data into the same stream + wire [35:0] timedrx_data, loopbackrx_data, testrx_data; + wire [35:0] timedtx_data, loopbacktx_data, testtx_data; + wire timedrx_src_rdy, timedrx_dst_rdy, loopbackrx_src_rdy, loopbackrx_dst_rdy, + testrx_src_rdy, testrx_dst_rdy; + wire timedtx_src_rdy, timedtx_dst_rdy, loopbacktx_src_rdy, loopbacktx_dst_rdy, + testtx_src_rdy, testtx_dst_rdy; + wire timedrx_src_rdy_int, timedrx_dst_rdy_int, timedtx_src_rdy_int, timedtx_dst_rdy_int; + + wire [31:0] total, crc_err, seq_err, len_err; + wire sel_testtx = test_ctrl[0]; + wire sel_loopbacktx = test_ctrl[1]; + wire pkt_src_enable = test_ctrl[2]; + wire pkt_sink_enable = test_ctrl[3]; + + fifo36_mux rx_test_mux_lvl_1 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .data0_i(timedrx_data), .src0_rdy_i(timedrx_src_rdy), .dst0_rdy_o(timedrx_dst_rdy), + .data1_i(loopbackrx_data), .src1_rdy_i(loopbackrx_src_rdy), .dst1_rdy_o(loopbackrx_dst_rdy), + .data_o(testrx_data), .src_rdy_o(testrx_src_rdy), .dst_rdy_i(testrx_dst_rdy)); + + fifo36_mux rx_test_mux_lvl_2 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .data0_i(testrx_data), .src0_rdy_i(testrx_src_rdy), .dst0_rdy_o(testrx_dst_rdy), + .data1_i(rx_data_i), .src1_rdy_i(rx_src_rdy_i), .dst1_rdy_o(rx_dst_rdy_o), + .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + + fifo_short #(.WIDTH(36)) loopback_fifo + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx | clear_rx), + .datain(loopbacktx_data), .src_rdy_i(loopbacktx_src_rdy), .dst_rdy_o(loopbacktx_dst_rdy), + .dataout(loopbackrx_data), .src_rdy_o(loopbackrx_src_rdy), .dst_rdy_i(loopbackrx_dst_rdy)); + + // Crossbar used as a demux for switching TX stream to main DSP or to test logic + crossbar36 tx_crossbar_lvl_1 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .cross(sel_testtx), + .data0_i(tx_data), .src0_rdy_i(tx_src_rdy), .dst0_rdy_o(tx_dst_rdy), + .data1_i(tx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(), // No 2nd input + .data0_o(tx_data_o), .src0_rdy_o(tx_src_rdy_o), .dst0_rdy_i(tx_dst_rdy_i), + .data1_o(testtx_data), .src1_rdy_o(testtx_src_rdy), .dst1_rdy_i(testtx_dst_rdy) ); + + crossbar36 tx_crossbar_lvl_2 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .cross(sel_loopbacktx), + .data0_i(testtx_data), .src0_rdy_i(testtx_src_rdy), .dst0_rdy_o(testtx_dst_rdy), + .data1_i(testtx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(), // No 2nd input + .data0_o(timedtx_data), .src0_rdy_o(timedtx_src_rdy), .dst0_rdy_i(timedtx_dst_rdy), + .data1_o(loopbacktx_data), .src1_rdy_o(loopbacktx_src_rdy), .dst1_rdy_i(loopbacktx_dst_rdy) ); + + // Fixed rate TX traffic consumer + fifo_pacer tx_pacer + (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_sink_enable), + .src1_rdy_i(timedtx_src_rdy), .dst1_rdy_o(timedtx_dst_rdy), + .src2_rdy_o(timedtx_src_rdy_int), .dst2_rdy_i(timedtx_dst_rdy_int), + .underrun(tx_underrun), .overrun()); + + packet_verifier32 pktver32 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .data_i(timedtx_data), .src_rdy_i(timedtx_src_rdy_int), .dst_rdy_o(timedtx_dst_rdy_int), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + + // Fixed rate RX traffic generator + packet_generator32 pktgen32 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .header({len_err,seq_err,crc_err,total}), + .data_o(timedrx_data), .src_rdy_o(timedrx_src_rdy_int), .dst_rdy_i(timedrx_dst_rdy_int)); + + fifo_pacer rx_pacer + (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_src_enable), + .src1_rdy_i(timedrx_src_rdy_int), .dst1_rdy_o(timedrx_dst_rdy_int), + .src2_rdy_o(timedrx_src_rdy), .dst2_rdy_i(timedrx_dst_rdy), + .underrun(), .overrun(rx_overrun)); + // //////////////////////////////////////////// // DEBUG - // Loopback for testing - //assign resp_data = ctrl_data; - //assign resp_src_rdy = ctrl_src_rdy; - //assign ctrl_dst_rdy = resp_dst_rdy; - assign debug0 = { 5'd0, gpif_misc[2:0], gpif_ctl[3:0], gpif_rdy[3:0], gpif_d_copy[15:0] }; assign debug1 = { { debug_rd[15:8] }, { debug_rd[7:0] }, diff --git a/usrp2/top/u1plus/core_compile b/usrp2/top/u1plus/core_compile index 0d95f704d..b2ccc8b49 100755 --- a/usrp2/top/u1plus/core_compile +++ b/usrp2/top/u1plus/core_compile @@ -1,2 +1 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ u1plus_core.v 2>&1 - +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index 8e83c01ff..75845e8f4 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -13,6 +13,7 @@ module u1plus_core output sclk, output [15:0] sen, output mosi, input miso, input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, + output tx_underrun, output rx_overrun, inout [15:0] io_tx, inout [15:0] io_rx, output [13:0] tx_i, output [13:0] tx_q, input [11:0] rx_i, input [11:0] rx_q, @@ -51,6 +52,17 @@ module u1plus_core wire [31:0] debug0; wire [31:0] debug1; + wire [31:0] debug_vt; + wire rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc; + assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp; + assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp; + + setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(global_reset)); + + reset_sync reset_sync(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(wb_rst)); + // ///////////////////////////////////////////////////////////////////////////////////// // GPIF Slave to Wishbone Master localparam dw = 16; @@ -67,8 +79,6 @@ module u1plus_core wire [35:0] tx_data, rx_data, tx_err_data; wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, tx_err_src_rdy, tx_err_dst_rdy; - reg [15:0] tx_frame_len; - wire [15:0] rx_frame_len; wire bus_error; wire gpif_rst = 0; @@ -94,7 +104,10 @@ module u1plus_core .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx), .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), - + + .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc), + + .test_rate(test_rate), .test_ctrl(test_ctrl), .debug0(debug0), .debug1(debug1)); wire rx_sof = rx_data[32]; @@ -123,7 +136,7 @@ module u1plus_core vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time), .overrun(), + .vita_time(vita_time), .overrun(rx_overrun_dsp), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy), .debug_rx(vrc_debug)); @@ -158,8 +171,8 @@ module u1plus_core .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), .dac_a(tx_i_int),.dac_b(tx_q_int), - .underrun(), .run(run_tx), - .debug()); + .underrun(tx_underrun_dsp), .run(run_tx), + .debug(debug_vt)); assign tx_i = tx_i_int[15:2]; assign tx_q = tx_q_int[15:2]; @@ -275,7 +288,6 @@ module u1plus_core (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : (s0_adr[6:0] == REG_TEST) ? reg_test : - (s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len : (s0_adr[6:0] == REG_COMPAT) ? { 8'd0, COMPAT_NUM } : 16'hBEEF; -- cgit v1.2.3 From f5ef91168704f2203b006f515c6c889bb696af2f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 18 Mar 2011 14:17:46 -0700 Subject: u1p: pass tx status/error packets back through GPIF over the response channel (short packets) --- usrp2/fifo/Makefile.srcs | 1 + usrp2/fifo/fifo19_mux.v | 77 ++++++++++++++++++++++++++++++++++++++++++ usrp2/fifo/fifo36_mux.v | 3 +- usrp2/gpif/gpif.v | 26 +++++++++++--- usrp2/top/u1plus/u1plus_core.v | 17 +++------- 5 files changed, 106 insertions(+), 18 deletions(-) create mode 100644 usrp2/fifo/fifo19_mux.v diff --git a/usrp2/fifo/Makefile.srcs b/usrp2/fifo/Makefile.srcs index 7e6a231ae..02c567049 100644 --- a/usrp2/fifo/Makefile.srcs +++ b/usrp2/fifo/Makefile.srcs @@ -23,6 +23,7 @@ fifo19_to_ll8.v \ ll8_to_fifo19.v \ fifo36_to_fifo19.v \ fifo19_to_fifo36.v \ +fifo19_mux.v \ fifo36_mux.v \ fifo36_demux.v \ packet_router.v \ diff --git a/usrp2/fifo/fifo19_mux.v b/usrp2/fifo/fifo19_mux.v new file mode 100644 index 000000000..ebf961678 --- /dev/null +++ b/usrp2/fifo/fifo19_mux.v @@ -0,0 +1,77 @@ + +// Mux packets from multiple FIFO interfaces onto a single one. +// Can alternate or give priority to one port (port 0) +// In prio mode, port 1 will never get access if port 0 is always busy + +module fifo19_mux + #(parameter prio = 0) + (input clk, input reset, input clear, + input [18:0] data0_i, input src0_rdy_i, output dst0_rdy_o, + input [18:0] data1_i, input src1_rdy_i, output dst1_rdy_o, + output [18:0] data_o, output src_rdy_o, input dst_rdy_i); + + wire [18:0] data0_int, data1_int; + wire src0_rdy_int, dst0_rdy_int, src1_rdy_int, dst1_rdy_int; + + fifo_short #(.WIDTH(19)) mux_fifo_in0 + (.clk(clk), .reset(reset), .clear(clear), + .datain(data0_i), .src_rdy_i(src0_rdy_i), .dst_rdy_o(dst0_rdy_o), + .dataout(data0_int), .src_rdy_o(src0_rdy_int), .dst_rdy_i(dst0_rdy_int)); + + fifo_short #(.WIDTH(19)) mux_fifo_in1 + (.clk(clk), .reset(reset), .clear(clear), + .datain(data1_i), .src_rdy_i(src1_rdy_i), .dst_rdy_o(dst1_rdy_o), + .dataout(data1_int), .src_rdy_o(src1_rdy_int), .dst_rdy_i(dst1_rdy_int)); + + localparam MUX_IDLE0 = 0; + localparam MUX_DATA0 = 1; + localparam MUX_IDLE1 = 2; + localparam MUX_DATA1 = 3; + + reg [1:0] state; + + wire eof0 = data0_int[17]; + wire eof1 = data1_int[17]; + + wire [18:0] data_int; + wire src_rdy_int, dst_rdy_int; + + always @(posedge clk) + if(reset | clear) + state <= MUX_IDLE0; + else + case(state) + MUX_IDLE0 : + if(src0_rdy_int) + state <= MUX_DATA0; + else if(src1_rdy_int) + state <= MUX_DATA1; + + MUX_DATA0 : + if(src0_rdy_int & dst_rdy_int & eof0) + state <= prio ? MUX_IDLE0 : MUX_IDLE1; + + MUX_IDLE1 : + if(src1_rdy_int) + state <= MUX_DATA1; + else if(src0_rdy_int) + state <= MUX_DATA0; + + MUX_DATA1 : + if(src1_rdy_int & dst_rdy_int & eof1) + state <= MUX_IDLE0; + + default : + state <= MUX_IDLE0; + endcase // case (state) + + assign dst0_rdy_int = (state==MUX_DATA0) ? dst_rdy_int : 0; + assign dst1_rdy_int = (state==MUX_DATA1) ? dst_rdy_int : 0; + assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_int : (state==MUX_DATA1) ? src1_rdy_int : 0; + assign data_int = (state==MUX_DATA0) ? data0_int : data1_int; + + fifo_short #(.WIDTH(19)) mux_fifo + (.clk(clk), .reset(reset), .clear(clear), + .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), + .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); +endmodule // fifo19_mux diff --git a/usrp2/fifo/fifo36_mux.v b/usrp2/fifo/fifo36_mux.v index 7f0f803ff..2b454abaf 100644 --- a/usrp2/fifo/fifo36_mux.v +++ b/usrp2/fifo/fifo36_mux.v @@ -74,4 +74,5 @@ module fifo36_mux (.clk(clk), .reset(reset), .clear(clear), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); -endmodule // fifo36_demux + +endmodule // fifo36_mux diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index e72490b17..8cac8b466 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -17,7 +17,8 @@ module gpif input fifo_clk, input fifo_rst, input clear_tx, input clear_rx, output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, - + input [35:0] tx_err_data_i, input tx_err_src_rdy_i, output tx_err_dst_rdy_o, + output tx_underrun, output rx_overrun, input [7:0] test_rate, input [3:0] test_ctrl, output [31:0] debug0, output [31:0] debug1 @@ -77,8 +78,9 @@ module gpif wire rx36_src_rdy, rx36_dst_rdy, rx_src_rdy, rx_dst_rdy; wire [18:0] rx19_data; wire rx19_src_rdy, rx19_dst_rdy; - wire [18:0] resp_data, resp_int; - wire resp_src_rdy, resp_dst_rdy, resp_src_rdy_int, resp_dst_rdy_int; + wire [18:0] resp_data, resp_int1, resp_int2; + wire resp_src_rdy, resp_dst_rdy; + wire resp_src_rdy_int1, resp_dst_rdy_int1, resp_src_rdy_int2, resp_dst_rdy_int2; fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), @@ -106,15 +108,29 @@ module gpif fifo_to_wb fifo_to_wb (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .data_i(ctrl_data), .src_rdy_i(ctrl_src_rdy), .dst_rdy_o(ctrl_dst_rdy), - .data_o(resp_int), .src_rdy_o(resp_src_rdy_int), .dst_rdy_i(resp_dst_rdy_int), + .data_o(resp_int1), .src_rdy_o(resp_src_rdy_int1), .dst_rdy_i(resp_dst_rdy_int1), .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), .wb_ack_i(wb_ack_i), .triggers(triggers), .debug0(), .debug1()); + wire [18:0] tx_err19_data; + wire tx_err19_src_rdy, tx_err19_dst_rdy; + + fifo36_to_fifo19 #(.LE(1)) f36_to_f19_txerr + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .f36_datain(tx_err_data_i), .f36_src_rdy_i(tx_err_src_rdy_i), .f36_dst_rdy_o(tx_err_dst_rdy_o), + .f19_dataout(tx_err19_data), .f19_src_rdy_o(tx_err19_src_rdy), .f19_dst_rdy_i(tx_err19_dst_rdy) ); + + fifo19_mux #(.prio(0)) mux_err_stream + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .data0_i(resp_int1), .src0_rdy_i(resp_src_rdy_int1), .dst0_rdy_o(resp_dst_rdy_int1), + .data1_i(tx_err19_data), .src1_rdy_i(tx_err19_src_rdy), .dst1_rdy_o(tx_err19_dst_rdy), + .data_o(resp_int2), .src_rdy_o(resp_src_rdy_int2), .dst_rdy_i(resp_dst_rdy_int2)); + fifo19_pad #(.LENGTH(16)) fifo19_pad (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .data_i(resp_int), .src_rdy_i(resp_src_rdy_int), .dst_rdy_o(resp_dst_rdy_int), + .data_i(resp_int2), .src_rdy_i(resp_src_rdy_int2), .dst_rdy_o(resp_dst_rdy_int2), .data_o(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy)); // //////////////////////////////////////////////////////////////////// diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index 75845e8f4..5b10b3260 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -104,7 +104,8 @@ module u1plus_core .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx), .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), - + .tx_err_data_i(tx_err_data), .tx_err_src_rdy_i(tx_err_src_rdy), .tx_err_dst_rdy_o(tx_err_dst_rdy), + .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc), .test_rate(test_rate), .test_ctrl(test_ctrl), @@ -123,8 +124,6 @@ module u1plus_core wire rx1_dst_rdy, rx1_src_rdy; wire [100:0] rx1_data; wire run_rx; - wire [35:0] vita_rx_data; - wire vita_rx_src_rdy, vita_rx_dst_rdy; dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx (.clk(wb_clk),.rst(wb_rst), @@ -145,15 +144,9 @@ module u1plus_core (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy), - .data_o(vita_rx_data), .dst_rdy_i(vita_rx_dst_rdy), .src_rdy_o(vita_rx_src_rdy), + .data_o(rx_data), .dst_rdy_i(rx_dst_rdy), .src_rdy_o(rx_src_rdy), .debug_rx(vrf_debug) ); - fifo36_mux #(.prio(0)) mux_err_stream - (.clk(wb_clk), .reset(wb_rst), .clear(0), - .data0_i(vita_rx_data), .src0_rdy_i(vita_rx_src_rdy), .dst0_rdy_o(vita_rx_dst_rdy), - .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), - .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); - // /////////////////////////////////////////////////////////////////////////////////// // DSP TX @@ -161,8 +154,8 @@ module u1plus_core wire run_tx; vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), - .REPORT_ERROR(0), .DO_FLOW_CONTROL(0), - .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0), + .REPORT_ERROR(1), .DO_FLOW_CONTROL(0), + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(0), .DSP_NUMBER(0)) vita_tx_chain (.clk(wb_clk), .reset(wb_rst), -- cgit v1.2.3 From ac3e42d1053772f324245dfff23eadcc7c6135cd Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 18 Mar 2011 14:56:01 -0700 Subject: u1p: gpif-to-fx2 path should now handle arbitrary sized packets, up to 2KB --- usrp2/gpif/gpif_rd.v | 51 +++++++++++++++++++++++++++++---------------------- 1 file changed, 29 insertions(+), 22 deletions(-) diff --git a/usrp2/gpif/gpif_rd.v b/usrp2/gpif/gpif_rd.v index 76db72d8a..e79b275b3 100644 --- a/usrp2/gpif/gpif_rd.v +++ b/usrp2/gpif/gpif_rd.v @@ -10,7 +10,7 @@ module gpif_rd output [31:0] debug ); - wire [18:0] data_o, resp_o; + wire [17:0] data_o, resp_o; // drop occ bit from input data wire final_rdy_data, final_rdy_resp; // 33/257 Bug Fix @@ -24,35 +24,42 @@ module gpif_rd read_count <= 0; // Data Path - wire [18:0] data_int; + wire [17:0] data_int; wire src_rdy_int, dst_rdy_int; - fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) rd_fifo_2clk - (.wclk(sys_clk), .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(), + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) rd_fifo_2clk + (.wclk(sys_clk), .datain(data_i[17:0]), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(), .rclk(~gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(), .arst(sys_rst)); - // FIXME -- handle short packets - wire send_data_line = gpif_rd & ~gpif_ep & ~read_count[8]; + reg [7:0] packet_count; + reg do_padding; + wire consume_data_line = gpif_rd & ~gpif_ep & ~read_count[8] & ~do_padding; + wire produce_eop = src_rdy_int & dst_rdy_int & data_int[17]; + wire consume_sop = consume_data_line & final_rdy_data & data_o[16]; + wire consume_eop = consume_data_line & final_rdy_data & data_o[17]; - fifo_cascade #(.WIDTH(19), .SIZE(9)) rd_fifo + fifo_cascade #(.WIDTH(18), .SIZE(10)) rd_fifo (.clk(~gpif_clk), .reset(gpif_rst), .clear(0), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), - .dataout(data_o), .src_rdy_o(final_rdy_data), .dst_rdy_i(send_data_line), .occupied()); + .dataout(data_o), .src_rdy_o(final_rdy_data), .dst_rdy_i(consume_data_line), .occupied()); - reg [7:0] packet_count; always @(negedge gpif_clk) if(gpif_rst) packet_count <= 0; else - if(src_rdy_int & dst_rdy_int & data_int[17]) // eop - if(~(send_data_line & data_o[16])) - packet_count <= packet_count + 1; - else - ; - else - if(send_data_line & data_o[16]) - packet_count <= packet_count - 1; + if(produce_eop & ~consume_sop) + packet_count <= packet_count + 1; + else if(consume_sop & ~produce_eop) + packet_count <= packet_count - 1; + always @(negedge gpif_clk) + if(gpif_rst) + do_padding <= 0; + else if(~gpif_rd) + do_padding <= 0; + else if(consume_eop) + do_padding <= 1; + always @(negedge gpif_clk) if(gpif_rst) gpif_empty_d <= 1; @@ -61,12 +68,12 @@ module gpif_rd // Response Path wire [15:0] resp_fifolevel; - wire send_resp_line = gpif_rd & gpif_ep & ~read_count[4]; + wire consume_resp_line = gpif_rd & gpif_ep & ~read_count[4]; - fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) resp_fifo_2clk - (.wclk(sys_clk), .datain(resp_i), .src_rdy_i(resp_src_rdy_i), .dst_rdy_o(resp_dst_rdy_o), .space(), + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) resp_fifo_2clk + (.wclk(sys_clk), .datain(resp_i[17:0]), .src_rdy_i(resp_src_rdy_i), .dst_rdy_o(resp_dst_rdy_o), .space(), .rclk(~gpif_clk), .dataout(resp_o), - .src_rdy_o(final_rdy_resp), .dst_rdy_i(send_resp_line), .occupied(resp_fifolevel), + .src_rdy_o(final_rdy_resp), .dst_rdy_i(consume_resp_line), .occupied(resp_fifolevel), .arst(sys_rst)); // FIXME -- handle short packets @@ -82,6 +89,6 @@ module gpif_rd assign debug = { { 16'd0 }, { data_int[17:16], data_o[17:16], packet_count[3:0] }, - { 2'b0,final_rdy_data, final_rdy_resp, send_data_line, send_resp_line, src_rdy_int, dst_rdy_int} }; + { 2'b0,final_rdy_data, final_rdy_resp, consume_data_line, consume_resp_line, src_rdy_int, dst_rdy_int} }; endmodule // gpif_rd -- cgit v1.2.3 From a4dc4a539a61d94a2d18b4576371d230c0dc6514 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 18 Mar 2011 16:11:02 -0700 Subject: u1p: use 18 bit fifos and use full size of a block ram in the tx path --- usrp2/fifo/fifo_2clock.v | 19 ++++++++++++------- usrp2/gpif/gpif_wr.v | 13 +++++++------ 2 files changed, 19 insertions(+), 13 deletions(-) diff --git a/usrp2/fifo/fifo_2clock.v b/usrp2/fifo/fifo_2clock.v index 34c85ccb4..f3ed5324f 100644 --- a/usrp2/fifo/fifo_2clock.v +++ b/usrp2/fifo/fifo_2clock.v @@ -14,7 +14,8 @@ module fifo_2clock assign src_rdy_o = ~empty; assign write = src_rdy_i & dst_rdy_o; assign read = src_rdy_o & dst_rdy_i; - + wire dummy; + generate if(WIDTH==36) if(SIZE==9) @@ -37,12 +38,16 @@ module fifo_2clock (.rst(arst), .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); - else if((WIDTH==19)|(WIDTH==18)) - if(SIZE==4) - fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk - (.rst(arst), - .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if((WIDTH==19) & (SIZE==4)) + fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk + (.rst(arst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if((WIDTH==18) & (SIZE==4)) + fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk + (.rst(arst), + .wr_clk(wclk),.din({1'b0,datain}),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout({dummy,dataout}),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); endgenerate assign occupied = {{(16-SIZE-1){1'b0}},level_rclk}; diff --git a/usrp2/gpif/gpif_wr.v b/usrp2/gpif/gpif_wr.v index e9b3c72ea..bf95931dc 100644 --- a/usrp2/gpif/gpif_wr.v +++ b/usrp2/gpif/gpif_wr.v @@ -44,19 +44,20 @@ module gpif_wr else gpif_full_d <= fifo_space < 256; - wire [18:0] data_int; + wire [17:0] data_int; wire src_rdy_int, dst_rdy_int; - fifo_cascade #(.WIDTH(19), .SIZE(9)) wr_fifo + fifo_cascade #(.WIDTH(18), .SIZE(10)) wr_fifo (.clk(gpif_clk), .reset(gpif_rst), .clear(0), - .datain({1'b0,eop,sop,gpif_data_reg}), .src_rdy_i(~ep_reg & wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space), + .datain({eop,sop,gpif_data_reg}), .src_rdy_i(~ep_reg & wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied()); - fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) wr_fifo_2clk + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) wr_fifo_2clk (.wclk(gpif_clk), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), - .rclk(sys_clk), .dataout(data_o[18:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(), + .rclk(sys_clk), .dataout(data_o[17:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(), .arst(sys_rst)); - + assign data_o[18] = 1'b0; + // Control Path wire [15:0] ctrl_fifo_space; always @(posedge gpif_clk) -- cgit v1.2.3 From d71f8599d0698e951ccd35ee96da9cd2229a9987 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 23 Mar 2011 17:57:57 -0700 Subject: u1p:wr testbench --- usrp2/gpif/gpif_wr_tb.v | 86 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 usrp2/gpif/gpif_wr_tb.v diff --git a/usrp2/gpif/gpif_wr_tb.v b/usrp2/gpif/gpif_wr_tb.v new file mode 100644 index 000000000..6cfa13744 --- /dev/null +++ b/usrp2/gpif/gpif_wr_tb.v @@ -0,0 +1,86 @@ + +module gpif_wr_tb(); + + reg sys_clk = 0; + reg sys_rst = 1; + reg gpif_clk = 0; + reg gpif_rst = 1; + + reg [15:0] gpif_data; + reg WR = 0, EP = 0; + + wire CF, DF; + + wire gpif_full_d, gpif_full_c; + wire [18:0] data_o, ctrl_o; + wire src_rdy, dst_rdy; + wire ctrl_src_rdy, ctrl_dst_rdy; + + assign ctrl_dst_rdy = 1; + assign dst_rdy = 1; + + initial $dumpfile("gpif_wr_tb.vcd"); + initial $dumpvars(0,gpif_wr_tb); + + initial #1000 gpif_rst = 0; + initial #1000 sys_rst = 0; + always #64 gpif_clk <= ~gpif_clk; + always #47.9 sys_clk <= ~sys_clk; + + gpif_wr gpif_write + (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), + .gpif_data(gpif_data), .gpif_wr(WR), .gpif_ep(EP), + .gpif_full_d(DF), .gpif_full_c(CF), + + .sys_clk(sys_clk), .sys_rst(sys_rst), + .data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy), + .ctrl_o(ctrl_o), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy) ); + + always @(posedge sys_clk) + if(ctrl_src_rdy & ctrl_dst_rdy) + $display("CTRL: %x",ctrl_o); + + always @(posedge sys_clk) + if(src_rdy & dst_rdy) + begin + if(data_o[16]) + $display("<-------- DATA SOF--------->"); + $display("DATA: %x",data_o); + if(data_o[17]) + $display("<-------- DATA EOF--------->"); + end + + initial + begin + #10000; + repeat (1) + begin + WR <= 1; + gpif_data <= 150; // Length + @(posedge gpif_clk); + gpif_data <= 16'h00; + @(posedge gpif_clk); + repeat(254) + begin + gpif_data <= gpif_data + 1; + @(posedge gpif_clk); + end + WR <= 0; + repeat (20) + @(posedge gpif_clk); + WR <= 1; + gpif_data <= 16'hFF; + @(posedge gpif_clk); + repeat(254) + begin + gpif_data <= gpif_data - 1; + @(posedge gpif_clk); + end + + end + end // initial begin + + initial #100000 $finish; + + +endmodule // gpif_wr_tb -- cgit v1.2.3 From 88cc06c10e9aaf7db13557a581f0489b226e7e78 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 23 Mar 2011 18:51:36 -0700 Subject: u1p: better way of reframing the packets --- usrp2/gpif/gpif.v | 11 +++++++- usrp2/gpif/gpif_wr_tb.v | 15 ++++++++--- usrp2/gpif/packet_reframer.v | 62 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 83 insertions(+), 5 deletions(-) create mode 100644 usrp2/gpif/packet_reframer.v diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index 8cac8b466..4f0ed233b 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -61,9 +61,18 @@ module gpif .ctrl_o(ctrl_data), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy), .debug(debug_wr) ); + // join vita packets which are longer than one frame, drop frame padding + wire [18:0] refr_data; + wire refr_src_rdy, refr_dst_rdy; + + packet_reframer tx_packet_reframer + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .data_i(tx19_data), .src_rdy_i(tx19_src_rdy), .dst_rdy_o(tx19_dst_rdy), + .data_o(refr_data), .src_rdy_o(refr_src_rdy), .dst_rdy_i(refr_dst_rdy)); + fifo19_to_fifo36 #(.LE(1)) f19_to_f36 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .f19_datain(tx19_data), .f19_src_rdy_i(tx19_src_rdy), .f19_dst_rdy_o(tx19_dst_rdy), + .f19_datain(refr_data), .f19_src_rdy_i(refr_src_rdy), .f19_dst_rdy_o(refr_dst_rdy), .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 diff --git a/usrp2/gpif/gpif_wr_tb.v b/usrp2/gpif/gpif_wr_tb.v index 6cfa13744..134365c87 100644 --- a/usrp2/gpif/gpif_wr_tb.v +++ b/usrp2/gpif/gpif_wr_tb.v @@ -26,6 +26,9 @@ module gpif_wr_tb(); initial #1000 sys_rst = 0; always #64 gpif_clk <= ~gpif_clk; always #47.9 sys_clk <= ~sys_clk; + + wire [18:0] data_int; + wire src_rdy_int, dst_rdy_int; gpif_wr gpif_write (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), @@ -33,9 +36,14 @@ module gpif_wr_tb(); .gpif_full_d(DF), .gpif_full_c(CF), .sys_clk(sys_clk), .sys_rst(sys_rst), - .data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy), + .data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .ctrl_o(ctrl_o), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy) ); + packet_reframer tx_packet_reframer + (.clk(sys_clk), .reset(sys_rst), .clear(0), + .data_i(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), + .data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); + always @(posedge sys_clk) if(ctrl_src_rdy & ctrl_dst_rdy) $display("CTRL: %x",ctrl_o); @@ -56,7 +64,7 @@ module gpif_wr_tb(); repeat (1) begin WR <= 1; - gpif_data <= 150; // Length + gpif_data <= 10; // Length @(posedge gpif_clk); gpif_data <= 16'h00; @(posedge gpif_clk); @@ -69,14 +77,13 @@ module gpif_wr_tb(); repeat (20) @(posedge gpif_clk); WR <= 1; - gpif_data <= 16'hFF; + gpif_data <= 16'h5; @(posedge gpif_clk); repeat(254) begin gpif_data <= gpif_data - 1; @(posedge gpif_clk); end - end end // initial begin diff --git a/usrp2/gpif/packet_reframer.v b/usrp2/gpif/packet_reframer.v new file mode 100644 index 000000000..336c36369 --- /dev/null +++ b/usrp2/gpif/packet_reframer.v @@ -0,0 +1,62 @@ + +// Join vita packets longer than one GPIF frame, drop padding on short frames + +module packet_reframer + (input clk, input reset, input clear, + input [18:0] data_i, + input src_rdy_i, + output dst_rdy_o, + output [18:0] data_o, + output src_rdy_o, + input dst_rdy_i); + + reg [1:0] state; + reg [15:0] length; + + localparam RF_IDLE = 0; + localparam RF_PKT = 1; + localparam RF_DUMP = 2; + + always @(posedge clk) + if(reset | clear) + state <= 0; + else + if(src_rdy_i & dst_rdy_i) + case(state) + RF_IDLE : + begin + length <= {data_i[14:0],1'b0}; + state <= RF_PKT; + end + RF_PKT : + begin + if(length == 2) + if(data_i[17]) + state <= RF_IDLE; + else + state <= RF_DUMP; + else + length <= length - 1; + end + RF_DUMP : + if(data_i[17]) + state <= RF_IDLE; + default : + state<= RF_IDLE; + endcase // case (state) + + assign dst_rdy_o = dst_rdy_i; // this is a little pessimistic but ok + assign src_rdy_o = src_rdy_i & (state != RF_DUMP); + + wire occ_out = 0; + wire eof_out = (state == RF_PKT) & (length == 2); + wire sof_out = (state == RF_IDLE); + wire [15:0] data_out = data_i[15:0]; + assign data_o = {occ_out, eof_out, sof_out, data_out}; + + +endmodule // packet_reframer + + + + -- cgit v1.2.3 From b8f5df998505727321cd23d04d23a89fd616cb9c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 25 Mar 2011 15:31:59 -0700 Subject: u1p: unused signals --- usrp2/top/u1plus/u1plus_core.v | 4 ---- 1 file changed, 4 deletions(-) diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index 5b10b3260..f50d71c81 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -111,10 +111,6 @@ module u1plus_core .test_rate(test_rate), .test_ctrl(test_ctrl), .debug0(debug0), .debug1(debug1)); - wire rx_sof = rx_data[32]; - wire rx_eof = rx_data[33]; - wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int; - wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug; // ///////////////////////////////////////////////////////////////////////// -- cgit v1.2.3 From 9fe534886ce3515b08aca53cae5dff336e53147e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 25 Mar 2011 15:55:50 -0700 Subject: u1p: debug pins --- usrp2/gpif/gpif.v | 4 +++- usrp2/top/u1plus/u1plus_core.v | 5 +++-- usrp2/vrt/vita_rx_control.v | 6 +++--- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index 4f0ed233b..052a66bff 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -220,7 +220,9 @@ module gpif // //////////////////////////////////////////// // DEBUG - assign debug0 = { 5'd0, gpif_misc[2:0], gpif_ctl[3:0], gpif_rdy[3:0], gpif_d_copy[15:0] }; + assign debug0 = { rx19_src_rdy, rx19_dst_rdy, resp_src_rdy, resp_dst_rdy, gpif_ctl[3:0], gpif_rdy[3:0], + gpif_d_copy[15:0] }; + assign debug1 = { { debug_rd[15:8] }, { debug_rd[7:0] }, { rx_src_rdy_i, rx_dst_rdy_o, rx36_src_rdy, rx36_dst_rdy, rx19_src_rdy, rx19_dst_rdy, resp_src_rdy, resp_dst_rdy}, diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index f50d71c81..167f0d6b9 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -331,7 +331,7 @@ module u1plus_core .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( {io_tx,io_rx} ) ); + .gpio( /*{io_tx,io_rx}*/ ) ); // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #8 + 9 @@ -389,6 +389,7 @@ module u1plus_core assign debug = debug0; assign debug_gpio_0 = 0; assign debug_gpio_1 = 0; - + assign {io_tx,io_rx} = vrc_debug | vrf_debug; + endmodule // u1plus_core diff --git a/usrp2/vrt/vita_rx_control.v b/usrp2/vrt/vita_rx_control.v index 4c0cef50d..73d9b87fd 100644 --- a/usrp2/vrt/vita_rx_control.v +++ b/usrp2/vrt/vita_rx_control.v @@ -191,9 +191,9 @@ module vita_rx_control assign read_ctrl = ( (ibs_state == IBS_IDLE) | ((ibs_state == IBS_RUNNING) & strobe & ~full & (lines_left==1) & chain) ) & not_empty_ctrl; - assign debug_rx = { { ibs_state[2:0], command_queue_len }, + assign debug_rx = { { 8'd0 }, { 8'd0 }, - { go_now, too_late, run, strobe, read_ctrl, write_ctrl, 1'b0, ~not_empty_ctrl }, - { 2'b0, overrun, chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} }; + { go_now, too_late, run, strobe, read_ctrl, write_ctrl, overrun, ~not_empty_ctrl }, + { ibs_state[2:0], chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} }; endmodule // vita_rx_control -- cgit v1.2.3 From df88b4a540d0c293460316b9344cc34bfc464bbd Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 25 Mar 2011 16:08:49 -0700 Subject: u1p: modernize, fix warnings, debug pins --- usrp2/top/u1plus/u1plus_core.v | 32 ++++++++++---------------------- 1 file changed, 10 insertions(+), 22 deletions(-) diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index 167f0d6b9..aa9b289e6 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -111,37 +111,26 @@ module u1plus_core .test_rate(test_rate), .test_ctrl(test_ctrl), .debug0(debug0), .debug1(debug1)); - wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug; - // ///////////////////////////////////////////////////////////////////////// // DSP RX - wire [31:0] sample_rx, sample_tx; - wire strobe_rx, strobe_tx; - wire rx1_dst_rdy, rx1_src_rdy; - wire [100:0] rx1_data; - wire run_rx; - + wire [31:0] sample_rx; + wire strobe_rx, run_rx; + wire [31:0] debug_rx_dsp, vr_debug; + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx (.clk(wb_clk),.rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .adc_a({rx_i,2'b0}),.adc_ovf_a(0),.adc_b({rx_q,2'b0}),.adc_ovf_b(0), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), .debug(debug_rx_dsp) ); - - vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control - (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), + + vita_rx_chain #(.BASE(SR_RX_CTRL), .UNIT(0), .FIFOSIZE(9)) vita_rx_chain + (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .vita_time(vita_time), .overrun(rx_overrun_dsp), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy), - .debug_rx(vrc_debug)); - - vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer - (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy), - .data_o(rx_data), .dst_rdy_i(rx_dst_rdy), .src_rdy_o(rx_src_rdy), - .debug_rx(vrf_debug) ); + .rx_data_o(rx_data), .rx_dst_rdy_i(rx_dst_rdy), .rx_src_rdy_o(rx_src_rdy), + .debug(vr_debug) ); // /////////////////////////////////////////////////////////////////////////////////// // DSP TX @@ -389,7 +378,6 @@ module u1plus_core assign debug = debug0; assign debug_gpio_0 = 0; assign debug_gpio_1 = 0; - assign {io_tx,io_rx} = vrc_debug | vrf_debug; - + assign {io_tx,io_rx} = vr_debug; endmodule // u1plus_core -- cgit v1.2.3 From 8c8f38b06719ec47b210ae9003b65438858404ae Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 25 Mar 2011 16:17:19 -0700 Subject: u1p: add new file to build --- usrp2/gpif/Makefile.srcs | 1 + 1 file changed, 1 insertion(+) diff --git a/usrp2/gpif/Makefile.srcs b/usrp2/gpif/Makefile.srcs index 9bcbb29f3..d7eaf9fca 100644 --- a/usrp2/gpif/Makefile.srcs +++ b/usrp2/gpif/Makefile.srcs @@ -9,4 +9,5 @@ GPIF_SRCS = $(abspath $(addprefix $(BASE_DIR)/../gpif/, \ gpif.v \ gpif_wr.v \ gpif_rd.v \ +packet_reframer.v \ )) -- cgit v1.2.3 From a2764a787e47db7d4e1216366475c06646e57438 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 27 Mar 2011 22:04:27 -0700 Subject: u1p: modify dsp_framer36 to allow it to skip the udp prot eng headers. This way it works with u1e, u1p, as well as u2/u2p --- usrp2/top/u1plus/u1plus_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index aa9b289e6..44b9381e2 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -124,7 +124,7 @@ module u1plus_core .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), .debug(debug_rx_dsp) ); - vita_rx_chain #(.BASE(SR_RX_CTRL), .UNIT(0), .FIFOSIZE(9)) vita_rx_chain + vita_rx_chain #(.BASE(SR_RX_CTRL), .UNIT(0), .FIFOSIZE(9), .PROT_ENG_FLAGS(0)) vita_rx_chain (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .vita_time(vita_time), .overrun(rx_overrun_dsp), -- cgit v1.2.3 From dcabd7f30c60283533d28376fcf5cd38725fd437 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 28 Mar 2011 12:20:42 -0700 Subject: u1p: should fix underrun reporting --- usrp2/top/u1plus/u1plus_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index 44b9381e2..a3755b722 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -140,7 +140,7 @@ module u1plus_core vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), .REPORT_ERROR(1), .DO_FLOW_CONTROL(0), - .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(0), + .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0), .DSP_NUMBER(0)) vita_tx_chain (.clk(wb_clk), .reset(wb_rst), -- cgit v1.2.3 From d0bfde4213dcab7fe3c5db404ef0f01354d56f67 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 28 Mar 2011 15:09:30 -0700 Subject: u1p: do padding outside of gpif_rd, in packet_splitter --- usrp2/gpif/Makefile.srcs | 1 + usrp2/gpif/gpif.v | 13 ++++-- usrp2/gpif/gpif_rd.v | 11 +---- usrp2/gpif/gpif_tb.v | 98 ++++++++++++++++++++++++++++++++++++++++++++ usrp2/gpif/packet_splitter.v | 79 +++++++++++++++++++++++++++++++++++ 5 files changed, 188 insertions(+), 14 deletions(-) create mode 100644 usrp2/gpif/gpif_tb.v create mode 100644 usrp2/gpif/packet_splitter.v diff --git a/usrp2/gpif/Makefile.srcs b/usrp2/gpif/Makefile.srcs index d7eaf9fca..bf2b7f74d 100644 --- a/usrp2/gpif/Makefile.srcs +++ b/usrp2/gpif/Makefile.srcs @@ -10,4 +10,5 @@ gpif.v \ gpif_wr.v \ gpif_rd.v \ packet_reframer.v \ +packet_splitter.v \ )) diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index 052a66bff..2a9fd901e 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -85,8 +85,8 @@ module gpif wire [35:0] rx36_data, rx_data; wire rx36_src_rdy, rx36_dst_rdy, rx_src_rdy, rx_dst_rdy; - wire [18:0] rx19_data; - wire rx19_src_rdy, rx19_dst_rdy; + wire [18:0] rx19_data, splt_data; + wire rx19_src_rdy, rx19_dst_rdy, splt_src_rdy, splt_dst_rdy; wire [18:0] resp_data, resp_int1, resp_int2; wire resp_src_rdy, resp_dst_rdy; wire resp_src_rdy_int1, resp_dst_rdy_int1, resp_src_rdy_int2, resp_dst_rdy_int2; @@ -96,18 +96,23 @@ module gpif .datain(rx_data), .src_rdy_i(rx_src_rdy), .dst_rdy_o(rx_dst_rdy), .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); - fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // FIXME Endianness? + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), .f19_dataout(rx19_data), .f19_src_rdy_o(rx19_src_rdy), .f19_dst_rdy_i(rx19_dst_rdy) ); + packet_splitter #(.FRAME_LEN(256)) packet_splitter + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy), + .data_o(splt_data), .src_rdy_o(splt_src_rdy), .dst_rdy_i(splt_dst_rdy)); + gpif_rd gpif_rd (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_data(gpif_d_out), .gpif_rd(RD), .gpif_ep(EP), .gpif_empty_d(DE), .gpif_empty_c(CE), .sys_clk(fifo_clk), .sys_rst(fifo_rst), - .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy), + .data_i(splt_data), .src_rdy_i(splt_src_rdy), .dst_rdy_o(splt_dst_rdy), .resp_i(resp_data), .resp_src_rdy_i(resp_src_rdy), .resp_dst_rdy_o(resp_dst_rdy), .debug(debug_rd) ); diff --git a/usrp2/gpif/gpif_rd.v b/usrp2/gpif/gpif_rd.v index e79b275b3..ed0721a36 100644 --- a/usrp2/gpif/gpif_rd.v +++ b/usrp2/gpif/gpif_rd.v @@ -32,8 +32,7 @@ module gpif_rd .arst(sys_rst)); reg [7:0] packet_count; - reg do_padding; - wire consume_data_line = gpif_rd & ~gpif_ep & ~read_count[8] & ~do_padding; + wire consume_data_line = gpif_rd & ~gpif_ep & ~read_count[8]; wire produce_eop = src_rdy_int & dst_rdy_int & data_int[17]; wire consume_sop = consume_data_line & final_rdy_data & data_o[16]; wire consume_eop = consume_data_line & final_rdy_data & data_o[17]; @@ -52,14 +51,6 @@ module gpif_rd else if(consume_sop & ~produce_eop) packet_count <= packet_count - 1; - always @(negedge gpif_clk) - if(gpif_rst) - do_padding <= 0; - else if(~gpif_rd) - do_padding <= 0; - else if(consume_eop) - do_padding <= 1; - always @(negedge gpif_clk) if(gpif_rst) gpif_empty_d <= 1; diff --git a/usrp2/gpif/gpif_tb.v b/usrp2/gpif/gpif_tb.v new file mode 100644 index 000000000..1cb84e9fb --- /dev/null +++ b/usrp2/gpif/gpif_tb.v @@ -0,0 +1,98 @@ + +module gpif_tb(); + + reg sys_clk = 0; + reg sys_rst = 1; + reg gpif_clk = 0; + reg gpif_rst = 1; + + reg [15:0] gpif_data; + reg WR = 0, EP = 0; + + wire CF, DF; + + wire gpif_full_d, gpif_full_c; + wire [18:0] data_o, ctrl_o; + wire src_rdy, dst_rdy; + wire ctrl_src_rdy, ctrl_dst_rdy; + + assign ctrl_dst_rdy = 1; + assign dst_rdy = 1; + + initial $dumpfile("gpif_tb.vcd"); + initial $dumpvars(0,gpif_tb); + + initial #1000 gpif_rst = 0; + initial #1000 sys_rst = 0; + always #64 gpif_clk <= ~gpif_clk; + always #47.9 sys_clk <= ~sys_clk; + + wire [18:0] data_int; + wire src_rdy_int, dst_rdy_int; + + gpif_wr gpif_write + (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), + .gpif_data(gpif_data), .gpif_wr(WR), .gpif_ep(EP), + .gpif_full_d(DF), .gpif_full_c(CF), + + .sys_clk(sys_clk), .sys_rst(sys_rst), + .data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), + .ctrl_o(ctrl_o), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy) ); + + packet_reframer tx_packet_reframer + (.clk(sys_clk), .reset(sys_rst), .clear(0), + .data_i(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), + .data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); + + packet_splitter #(.FRAME_LEN(256)) rx_packet_splitter + (.clk(sys_clk), .reset(sys_rst), .clear(0), + .data_i(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), + .data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); + + always @(posedge sys_clk) + if(ctrl_src_rdy & ctrl_dst_rdy) + $display("CTRL: %x",ctrl_o); + + always @(posedge sys_clk) + if(src_rdy & dst_rdy) + begin + if(data_o[16]) + $display("<-------- DATA SOF--------->"); + $display("DATA: %x",data_o); + if(data_o[17]) + $display("<-------- DATA EOF--------->"); + end + + initial + begin + #10000; + repeat (1) + begin + WR <= 1; + gpif_data <= 10; // Length + @(posedge gpif_clk); + gpif_data <= 16'h00; + @(posedge gpif_clk); + repeat(254) + begin + gpif_data <= gpif_data + 1; + @(posedge gpif_clk); + end + WR <= 0; + repeat (20) + @(posedge gpif_clk); + WR <= 1; + gpif_data <= 16'h5; + @(posedge gpif_clk); + repeat(254) + begin + gpif_data <= gpif_data - 1; + @(posedge gpif_clk); + end + end + end // initial begin + + initial #100000 $finish; + + +endmodule // gpif_tb diff --git a/usrp2/gpif/packet_splitter.v b/usrp2/gpif/packet_splitter.v new file mode 100644 index 000000000..43515dd8b --- /dev/null +++ b/usrp2/gpif/packet_splitter.v @@ -0,0 +1,79 @@ + +// Split vita packets longer than one GPIF frame, add padding on short frames + +module packet_splitter + #(parameter FRAME_LEN=256) + (input clk, input reset, input clear, + input [18:0] data_i, + input src_rdy_i, + output dst_rdy_o, + output [18:0] data_o, + output src_rdy_o, + input dst_rdy_i); + + reg [1:0] state; + reg [15:0] length; + reg [15:0] frame_len; + + localparam PS_IDLE = 0; + localparam PS_FRAME = 1; + localparam PS_NEW_FRAME = 2; + localparam PS_PAD = 3; + + always @(posedge clk) + if(reset | clear) + state <= PS_IDLE; + else + case(state) + PS_IDLE : + if(src_rdy_i & dst_rdy_i) + begin + length <= { data_i[14:0],1'b0}; + frame_len <= FRAME_LEN; + state <= PS_FRAME; + end + PS_FRAME : + if(src_rdy_i & dst_rdy_i) + if(frame_len == 0) + if(length == 0) + state <= PS_IDLE; + else + begin + state <= PS_NEW_FRAME; + frame_len <= FRAME_LEN; + length <= length - 1; + end + else + if(length == 0) + begin + frame_len <= frame_len - 1; + state <= PS_PAD; + end + PS_NEW_FRAME : + if(src_rdy_i & dst_rdy_i) + begin + frame_len <= frame_len - 1; + state <= PS_FRAME; + end + PS_PAD : + if(dst_rdy_i) + if(frame_len == 0) + state <= PS_IDLE; + else + frame_len <= frame_len - 1; + + endcase // case (state) + + + + assign dst_rdy_o = dst_rdy_i & (state != PS_PAD); + assign src_rdy_o = src_rdy_i | (state == PS_PAD); + + wire occ_out = 0; + wire eof_out = (frame_len == 0) & (state != PS_IDLE); + wire sof_out = (state == PS_IDLE) | (state == PS_NEW_FRAME); + + wire [15:0] data_out = data_i[15:0]; + assign data_o = {occ_out, eof_out, sof_out, data_out}; + +endmodule // packet_splitter -- cgit v1.2.3 From b51ef6e5a461dd4d1c42252e902bdbedfa5dc8a7 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 28 Mar 2011 16:51:02 -0700 Subject: should split and reframe packets properly --- usrp2/gpif/gpif_tb.v | 46 ++++++++++++++++++++++++++++++++++---------- usrp2/gpif/packet_splitter.v | 39 +++++++++++++++++++++---------------- 2 files changed, 58 insertions(+), 27 deletions(-) diff --git a/usrp2/gpif/gpif_tb.v b/usrp2/gpif/gpif_tb.v index 1cb84e9fb..a71796d86 100644 --- a/usrp2/gpif/gpif_tb.v +++ b/usrp2/gpif/gpif_tb.v @@ -12,12 +12,11 @@ module gpif_tb(); wire CF, DF; wire gpif_full_d, gpif_full_c; - wire [18:0] data_o, ctrl_o; - wire src_rdy, dst_rdy; + wire [18:0] data_o, ctrl_o, data_splt; + wire src_rdy, dst_rdy, src_rdy_splt, dst_rdy_splt; wire ctrl_src_rdy, ctrl_dst_rdy; assign ctrl_dst_rdy = 1; - assign dst_rdy = 1; initial $dumpfile("gpif_tb.vcd"); initial $dumpvars(0,gpif_tb); @@ -29,6 +28,8 @@ module gpif_tb(); wire [18:0] data_int; wire src_rdy_int, dst_rdy_int; + + assign dst_rdy_splt = 1; gpif_wr gpif_write (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), @@ -47,19 +48,19 @@ module gpif_tb(); packet_splitter #(.FRAME_LEN(256)) rx_packet_splitter (.clk(sys_clk), .reset(sys_rst), .clear(0), .data_i(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), - .data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); + .data_o(data_splt), .src_rdy_o(src_rdy_splt), .dst_rdy_i(dst_rdy_splt)); always @(posedge sys_clk) if(ctrl_src_rdy & ctrl_dst_rdy) $display("CTRL: %x",ctrl_o); always @(posedge sys_clk) - if(src_rdy & dst_rdy) + if(src_rdy_splt & dst_rdy_splt) begin - if(data_o[16]) + if(data_splt[16]) $display("<-------- DATA SOF--------->"); - $display("DATA: %x",data_o); - if(data_o[17]) + $display("DATA: %x",data_splt); + if(data_splt[17]) $display("<-------- DATA EOF--------->"); end @@ -68,8 +69,10 @@ module gpif_tb(); #10000; repeat (1) begin + @(posedge gpif_clk); + WR <= 1; - gpif_data <= 10; // Length + gpif_data <= 256; // Length @(posedge gpif_clk); gpif_data <= 16'h00; @(posedge gpif_clk); @@ -79,20 +82,43 @@ module gpif_tb(); @(posedge gpif_clk); end WR <= 0; + + while(DF) + @(posedge gpif_clk); + repeat (16) + @(posedge gpif_clk); + + WR <= 1; + repeat(256) + begin + gpif_data <= gpif_data - 1; + @(posedge gpif_clk); + end + WR <= 0; + + +/* + while(DF) + @(posedge gpif_clk); + repeat (20) @(posedge gpif_clk); WR <= 1; gpif_data <= 16'h5; @(posedge gpif_clk); + gpif_data <= 16'h00; + @(posedge gpif_clk); repeat(254) begin gpif_data <= gpif_data - 1; @(posedge gpif_clk); end + WR <= 0; + */ end end // initial begin - initial #100000 $finish; + initial #200000 $finish; endmodule // gpif_tb diff --git a/usrp2/gpif/packet_splitter.v b/usrp2/gpif/packet_splitter.v index 43515dd8b..f8028a4df 100644 --- a/usrp2/gpif/packet_splitter.v +++ b/usrp2/gpif/packet_splitter.v @@ -19,6 +19,8 @@ module packet_splitter localparam PS_FRAME = 1; localparam PS_NEW_FRAME = 2; localparam PS_PAD = 3; + + wire eof_i = data_i[17]; always @(posedge clk) if(reset | clear) @@ -34,30 +36,33 @@ module packet_splitter end PS_FRAME : if(src_rdy_i & dst_rdy_i) - if(frame_len == 0) - if(length == 0) - state <= PS_IDLE; - else - begin - state <= PS_NEW_FRAME; - frame_len <= FRAME_LEN; - length <= length - 1; - end + if((frame_len == 2) & ((length == 2) | eof_i)) + state <= PS_IDLE; + else if(frame_len == 2) + begin + state <= PS_NEW_FRAME; + length <= length - 1; + end + else if((length == 2)|eof_i) + begin + frame_len <= frame_len - 1; + state <= PS_PAD; + end else - if(length == 0) - begin - frame_len <= frame_len - 1; - state <= PS_PAD; - end + begin + frame_len <= frame_len - 1; + length <= length - 1; + end PS_NEW_FRAME : if(src_rdy_i & dst_rdy_i) begin - frame_len <= frame_len - 1; + frame_len <= FRAME_LEN; state <= PS_FRAME; + length <= length - 1; end PS_PAD : if(dst_rdy_i) - if(frame_len == 0) + if(frame_len == 2) state <= PS_IDLE; else frame_len <= frame_len - 1; @@ -70,7 +75,7 @@ module packet_splitter assign src_rdy_o = src_rdy_i | (state == PS_PAD); wire occ_out = 0; - wire eof_out = (frame_len == 0) & (state != PS_IDLE); + wire eof_out = (frame_len == 2) & (state != PS_IDLE) & (state != PS_NEW_FRAME); wire sof_out = (state == PS_IDLE) | (state == PS_NEW_FRAME); wire [15:0] data_out = data_i[15:0]; -- cgit v1.2.3 From 37cffdd35ab72551696a8d36c16d501b6d502ff1 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 14 Apr 2011 14:42:40 -0700 Subject: u1p: vita packet generator for testing purposes --- usrp2/gpif/gpif.v | 6 +++--- usrp2/top/u1plus/u1plus_core.v | 3 ++- usrp2/vrt/Makefile.srcs | 1 + usrp2/vrt/vita_pkt_gen.v | 42 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 48 insertions(+), 4 deletions(-) create mode 100644 usrp2/vrt/vita_pkt_gen.v diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index 2a9fd901e..007bb41b3 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -20,7 +20,7 @@ module gpif input [35:0] tx_err_data_i, input tx_err_src_rdy_i, output tx_err_dst_rdy_o, output tx_underrun, output rx_overrun, - input [7:0] test_rate, input [3:0] test_ctrl, + input [15:0] test_len, input [7:0] test_rate, input [3:0] test_ctrl, output [31:0] debug0, output [31:0] debug1 ); @@ -211,9 +211,9 @@ module gpif .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); // Fixed rate RX traffic generator - packet_generator32 pktgen32 + vita_pkt_gen pktgen (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), - .header({len_err,seq_err,crc_err,total}), + .len(test_len), .data_o(timedrx_data), .src_rdy_o(timedrx_src_rdy_int), .dst_rdy_i(timedrx_dst_rdy_int)); fifo_pacer rx_pacer diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index a3755b722..6d6fa878c 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -108,7 +108,7 @@ module u1plus_core .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc), - .test_rate(test_rate), .test_ctrl(test_ctrl), + .test_len(test_len), .test_rate(test_rate), .test_ctrl(test_ctrl), .debug0(debug0), .debug1(debug1)); // ///////////////////////////////////////////////////////////////////////// @@ -258,6 +258,7 @@ module u1plus_core assign test_ctrl = xfer_rate[11:8]; assign test_rate = xfer_rate[7:0]; + assign test_len = reg_test[15:0]; assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; diff --git a/usrp2/vrt/Makefile.srcs b/usrp2/vrt/Makefile.srcs index 4851bc924..166ed44ef 100644 --- a/usrp2/vrt/Makefile.srcs +++ b/usrp2/vrt/Makefile.srcs @@ -14,4 +14,5 @@ vita_tx_deframer.v \ vita_tx_chain.v \ gen_context_pkt.v \ trigger_context_pkt.v \ +vita_pkt_gen.v \ )) diff --git a/usrp2/vrt/vita_pkt_gen.v b/usrp2/vrt/vita_pkt_gen.v new file mode 100644 index 000000000..fea312188 --- /dev/null +++ b/usrp2/vrt/vita_pkt_gen.v @@ -0,0 +1,42 @@ + + +module vita_pkt_gen + (input clk, input reset, input clear, + input [15:0] len, + output [35:0] data_o, output src_rdy_o, input dst_rdy_i); + + reg [15:0] state; + reg [31:0] seq, data; + + wire sof = (state == 0); + wire eof = (state == (len-1)); + wire consume = src_rdy_o & dst_rdy_i; + + assign src_rdy_o = 1; + + always @(posedge clk) + if(reset | clear) + begin + state <= 0; + seq <= 0; + end + else + if(consume) + if(eof) + begin + state <= 0; + seq <= seq + 1; + end + else + state <= state + 1; + + always @* + case(state) + 0 : data <= {24'h000,seq[3:0],len}; + 1 : data <= seq; + default : data <= {~state,state}; + endcase // case (state) + + assign data_o = {2'b00, eof, sof, data}; + +endmodule // vita_pkt_gen -- cgit v1.2.3 From e9a34b8bd51d639e08f31930266e3425de4f53b3 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 14 Apr 2011 15:35:31 -0700 Subject: u1p: need to declare wires --- usrp2/top/u1plus/u1plus_core.v | 1 + 1 file changed, 1 insertion(+) diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index 6d6fa878c..76a15b271 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -62,6 +62,7 @@ module u1plus_core .in(set_data),.out(),.changed(global_reset)); reset_sync reset_sync(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(wb_rst)); + wire [15:0] test_len; // ///////////////////////////////////////////////////////////////////////////////////// // GPIF Slave to Wishbone Master -- cgit v1.2.3 From 552e81bf1790c531cbbe4087d6ac93f3baab48d4 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sat, 16 Apr 2011 17:53:09 -0700 Subject: u1p: implement a signal to indicate a partially full usb lut, to flush it --- usrp2/gpif/gpif.v | 7 ++- usrp2/gpif/gpif_rd.v | 23 +++++--- usrp2/gpif/gpif_tb.v | 1 + usrp2/gpif/packet_splitter.v | 33 ++++++++--- usrp2/gpif/packet_splitter_tb.v | 120 ++++++++++++++++++++++++++++++++++++++++ usrp2/top/u1plus/u1plus.v | 4 +- usrp2/top/u1plus/u1plus_core.v | 9 ++- 7 files changed, 175 insertions(+), 22 deletions(-) create mode 100644 usrp2/gpif/packet_splitter_tb.v diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index 007bb41b3..13a549dc7 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -5,7 +5,7 @@ module gpif (// GPIF signals input gpif_clk, input gpif_rst, inout [15:0] gpif_d, input [3:0] gpif_ctl, output [3:0] gpif_rdy, - input [2:0] gpif_misc, + output [2:0] gpif_misc, // Wishbone signals input wb_clk, input wb_rst, @@ -20,7 +20,7 @@ module gpif input [35:0] tx_err_data_i, input tx_err_src_rdy_i, output tx_err_dst_rdy_o, output tx_underrun, output rx_overrun, - input [15:0] test_len, input [7:0] test_rate, input [3:0] test_ctrl, + input [7:0] frames_per_packet, input [15:0] test_len, input [7:0] test_rate, input [3:0] test_ctrl, output [31:0] debug0, output [31:0] debug1 ); @@ -103,13 +103,14 @@ module gpif packet_splitter #(.FRAME_LEN(256)) packet_splitter (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .frames_per_packet(), .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy), .data_o(splt_data), .src_rdy_o(splt_src_rdy), .dst_rdy_i(splt_dst_rdy)); gpif_rd gpif_rd (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_data(gpif_d_out), .gpif_rd(RD), .gpif_ep(EP), - .gpif_empty_d(DE), .gpif_empty_c(CE), + .gpif_empty_d(DE), .gpif_empty_c(CE), .gpif_flush(gpif_misc[0]), .sys_clk(fifo_clk), .sys_rst(fifo_rst), .data_i(splt_data), .src_rdy_i(splt_src_rdy), .dst_rdy_o(splt_dst_rdy), diff --git a/usrp2/gpif/gpif_rd.v b/usrp2/gpif/gpif_rd.v index ed0721a36..728b8be78 100644 --- a/usrp2/gpif/gpif_rd.v +++ b/usrp2/gpif/gpif_rd.v @@ -3,6 +3,7 @@ module gpif_rd (input gpif_clk, input gpif_rst, output [15:0] gpif_data, input gpif_rd, input gpif_ep, output reg gpif_empty_d, output reg gpif_empty_c, + output reg gpif_flush, input sys_clk, input sys_rst, input [18:0] data_i, input src_rdy_i, output dst_rdy_o, @@ -10,8 +11,9 @@ module gpif_rd output [31:0] debug ); - wire [17:0] data_o, resp_o; // drop occ bit from input data - wire final_rdy_data, final_rdy_resp; + wire [18:0] data_o; // occ bit indicates flush + wire [17:0] resp_o; // no occ bit + wire final_rdy_data, final_rdy_resp; // 33/257 Bug Fix reg [8:0] read_count; @@ -24,10 +26,10 @@ module gpif_rd read_count <= 0; // Data Path - wire [17:0] data_int; + wire [18:0] data_int; wire src_rdy_int, dst_rdy_int; - fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) rd_fifo_2clk - (.wclk(sys_clk), .datain(data_i[17:0]), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(), + fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) rd_fifo_2clk + (.wclk(sys_clk), .datain(data_i[18:0]), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(), .rclk(~gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(), .arst(sys_rst)); @@ -37,7 +39,7 @@ module gpif_rd wire consume_sop = consume_data_line & final_rdy_data & data_o[16]; wire consume_eop = consume_data_line & final_rdy_data & data_o[17]; - fifo_cascade #(.WIDTH(18), .SIZE(10)) rd_fifo + fifo_cascade #(.WIDTH(19), .SIZE(10)) rd_fifo (.clk(~gpif_clk), .reset(gpif_rst), .clear(0), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), .dataout(data_o), .src_rdy_o(final_rdy_data), .dst_rdy_i(consume_data_line), .occupied()); @@ -56,7 +58,14 @@ module gpif_rd gpif_empty_d <= 1; else gpif_empty_d <= ~|packet_count; - + + // Use occ bit to signal a gpif flush + always @(negedge gpif_clk) + if(gpif_rst) + gpif_flush <= 0; + else if(consume_eop & data_o[18]) + gpif_flush <= ~gpif_flush; + // Response Path wire [15:0] resp_fifolevel; wire consume_resp_line = gpif_rd & gpif_ep & ~read_count[4]; diff --git a/usrp2/gpif/gpif_tb.v b/usrp2/gpif/gpif_tb.v index a71796d86..fe12c83b3 100644 --- a/usrp2/gpif/gpif_tb.v +++ b/usrp2/gpif/gpif_tb.v @@ -47,6 +47,7 @@ module gpif_tb(); packet_splitter #(.FRAME_LEN(256)) rx_packet_splitter (.clk(sys_clk), .reset(sys_rst), .clear(0), + .frames_per_packet(2), .data_i(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), .data_o(data_splt), .src_rdy_o(src_rdy_splt), .dst_rdy_i(dst_rdy_splt)); diff --git a/usrp2/gpif/packet_splitter.v b/usrp2/gpif/packet_splitter.v index f8028a4df..1c289c2fa 100644 --- a/usrp2/gpif/packet_splitter.v +++ b/usrp2/gpif/packet_splitter.v @@ -4,6 +4,7 @@ module packet_splitter #(parameter FRAME_LEN=256) (input clk, input reset, input clear, + input [7:0] frames_per_packet, input [18:0] data_i, input src_rdy_i, output dst_rdy_o, @@ -14,6 +15,7 @@ module packet_splitter reg [1:0] state; reg [15:0] length; reg [15:0] frame_len; + reg [7:0] frame_count; localparam PS_IDLE = 0; localparam PS_FRAME = 1; @@ -24,7 +26,10 @@ module packet_splitter always @(posedge clk) if(reset | clear) - state <= PS_IDLE; + begin + state <= PS_IDLE; + frame_count <= 0; + end else case(state) PS_IDLE : @@ -33,6 +38,7 @@ module packet_splitter length <= { data_i[14:0],1'b0}; frame_len <= FRAME_LEN; state <= PS_FRAME; + frame_count <= 1; end PS_FRAME : if(src_rdy_i & dst_rdy_i) @@ -40,8 +46,9 @@ module packet_splitter state <= PS_IDLE; else if(frame_len == 2) begin - state <= PS_NEW_FRAME; length <= length - 1; + state <= PS_NEW_FRAME; + frame_count <= frame_count + 1; end else if((length == 2)|eof_i) begin @@ -57,9 +64,15 @@ module packet_splitter if(src_rdy_i & dst_rdy_i) begin frame_len <= FRAME_LEN; - state <= PS_FRAME; - length <= length - 1; - end + if((length == 2)|eof_i) + state <= PS_PAD; + else + begin + state <= PS_FRAME; + length <= length - 1; + end // else: !if((length == 2)|eof_i) + end // if (src_rdy_i & dst_rdy_i) + PS_PAD : if(dst_rdy_i) if(frame_len == 2) @@ -68,16 +81,20 @@ module packet_splitter frame_len <= frame_len - 1; endcase // case (state) - + + wire next_state_is_idle = dst_rdy_i & (frame_len==2) & + ( (state==PS_PAD) | ( (state==PS_FRAME) & src_rdy_i & ((length==2)|eof_i) ) ); + + assign dst_rdy_o = dst_rdy_i & (state != PS_PAD); assign src_rdy_o = src_rdy_i | (state == PS_PAD); - wire occ_out = 0; wire eof_out = (frame_len == 2) & (state != PS_IDLE) & (state != PS_NEW_FRAME); wire sof_out = (state == PS_IDLE) | (state == PS_NEW_FRAME); - + wire occ_out = eof_out & next_state_is_idle & (frames_per_packet != frame_count); + wire [15:0] data_out = data_i[15:0]; assign data_o = {occ_out, eof_out, sof_out, data_out}; diff --git a/usrp2/gpif/packet_splitter_tb.v b/usrp2/gpif/packet_splitter_tb.v new file mode 100644 index 000000000..d35f1c6d4 --- /dev/null +++ b/usrp2/gpif/packet_splitter_tb.v @@ -0,0 +1,120 @@ + +module packet_splitter_tb(); + + reg sys_clk = 0; + reg sys_rst = 1; + reg gpif_clk = 0; + reg gpif_rst = 1; + + reg [15:0] gpif_data; + reg WR = 0, EP = 0; + + wire CF, DF; + + wire gpif_full_d, gpif_full_c; + wire [18:0] data_o, ctrl_o, data_splt; + wire src_rdy, dst_rdy, src_rdy_splt, dst_rdy_splt; + wire ctrl_src_rdy, ctrl_dst_rdy; + + assign ctrl_dst_rdy = 1; + + initial $dumpfile("packet_splitter_tb.vcd"); + initial $dumpvars(0,packet_splitter_tb); + + initial #1000 gpif_rst = 0; + initial #1000 sys_rst = 0; + always #64 gpif_clk <= ~gpif_clk; + always #47.9 sys_clk <= ~sys_clk; + + wire [35:0] data_int; + wire src_rdy_int, dst_rdy_int; + + assign dst_rdy_splt = 1; + + vita_pkt_gen vita_pkt_gen + (.clk(sys_clk), .reset(sys_rst) , .clear(0), + .len(7),.data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int)); + + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 + (.clk(sys_clk), .reset(sys_rst), .clear(0), + .f36_datain(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int), + .f19_dataout(data_o), .f19_src_rdy_o(src_rdy), .f19_dst_rdy_i(dst_rdy)); + + packet_splitter #(.FRAME_LEN(13)) rx_packet_splitter + (.clk(sys_clk), .reset(sys_rst), .clear(0), + .frames_per_packet(3), + .data_i(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), + .data_o(data_splt), .src_rdy_o(src_rdy_splt), .dst_rdy_i(dst_rdy_splt)); + + always @(posedge sys_clk) + if(ctrl_src_rdy & ctrl_dst_rdy) + $display("CTRL: %x",ctrl_o); + + always @(posedge sys_clk) + if(src_rdy_splt & dst_rdy_splt) + begin + if(data_splt[16]) + $display("<-------- DATA SOF--------->"); + $display("DATA: %x",data_splt); + if(data_splt[17]) + $display("<-------- DATA EOF--------->"); + end + + initial + begin + #10000; + repeat (1) + begin + @(posedge gpif_clk); + + WR <= 1; + gpif_data <= 256; // Length + @(posedge gpif_clk); + gpif_data <= 16'h00; + @(posedge gpif_clk); + repeat(254) + begin + gpif_data <= gpif_data + 1; + @(posedge gpif_clk); + end + WR <= 0; + + while(DF) + @(posedge gpif_clk); + repeat (16) + @(posedge gpif_clk); + + WR <= 1; + repeat(256) + begin + gpif_data <= gpif_data - 1; + @(posedge gpif_clk); + end + WR <= 0; + + +/* + while(DF) + @(posedge gpif_clk); + + repeat (20) + @(posedge gpif_clk); + WR <= 1; + gpif_data <= 16'h5; + @(posedge gpif_clk); + gpif_data <= 16'h00; + @(posedge gpif_clk); + repeat(254) + begin + gpif_data <= gpif_data - 1; + @(posedge gpif_clk); + end + WR <= 0; + */ + end + end // initial begin + + initial #200000 $finish; + + +endmodule // packet_splitter_tb diff --git a/usrp2/top/u1plus/u1plus.v b/usrp2/top/u1plus/u1plus.v index 9d52353db..7e1bd2ea7 100644 --- a/usrp2/top/u1plus/u1plus.v +++ b/usrp2/top/u1plus/u1plus.v @@ -8,7 +8,7 @@ module u1plus // GPIF inout [15:0] GPIF_D, input [3:0] GPIF_CTL, output [3:0] GPIF_RDY, - input FX2_PA7_FLAGD, input FX2_PA6_PKTEND, input FX2_PA2_SLOE, + output FX2_PA7_FLAGD, output FX2_PA6_PKTEND, output FX2_PA2_SLOE, input IFCLK, inout SDA_FPGA, inout SCL_FPGA, // I2C @@ -141,7 +141,7 @@ module u1plus .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), .gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_rdy(GPIF_RDY), - .gpif_misc({FX2_PA7_FLAGD,FX_PA6_PKTEND,FX2_PA2_SLOE}), + .gpif_misc({FX2_PA7_FLAGD,FX2_PA6_PKTEND,FX2_PA2_SLOE}), .gpif_clk(IFCLK), .db_sda(SDA_FPGA), .db_scl(SCL_FPGA), diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index 76a15b271..a2147e463 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -7,7 +7,7 @@ module u1plus_core // GPIF inout [15:0] gpif_d, input [3:0] gpif_ctl, output [3:0] gpif_rdy, - input [2:0] gpif_misc, input gpif_clk, + output [2:0] gpif_misc, input gpif_clk, inout db_sda, inout db_scl, output sclk, output [15:0] sen, output mosi, input miso, @@ -54,6 +54,8 @@ module u1plus_core wire [31:0] debug_vt; wire rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc; + reg [7:0] frames_per_packet; + assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp; assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp; @@ -109,7 +111,7 @@ module u1plus_core .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc), - .test_len(test_len), .test_rate(test_rate), .test_ctrl(test_ctrl), + .frames_per_packet(frames_per_packet), .test_len(test_len), .test_rate(test_rate), .test_ctrl(test_ctrl), .debug0(debug0), .debug1(debug1)); // ///////////////////////////////////////////////////////////////////////// @@ -243,6 +245,7 @@ module u1plus_core reg_cgen_ctrl <= 2'b11; reg_test <= 0; xfer_rate <= 0; + frames_per_packet <= 0; end else if(s0_cyc & s0_stb & s0_we) @@ -253,6 +256,8 @@ module u1plus_core reg_cgen_ctrl <= s0_dat_mosi; REG_TEST : reg_test <= s0_dat_mosi; + REG_RX_FRAMELEN : + frames_per_packet <= s0_dat_mosi[7:0]; REG_XFER_RATE : xfer_rate <= s0_dat_mosi; endcase // case (s0_adr[6:0]) -- cgit v1.2.3 From 08149d4c4e904d3a224ac9e24814ce04f3d9c509 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 19 Apr 2011 00:16:39 -0700 Subject: u1p: connect frames per packet --- usrp2/gpif/gpif.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index 13a549dc7..d003c6b1c 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -103,7 +103,7 @@ module gpif packet_splitter #(.FRAME_LEN(256)) packet_splitter (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), - .frames_per_packet(), + .frames_per_packet(frames_per_packet), .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy), .data_o(splt_data), .src_rdy_o(splt_src_rdy), .dst_rdy_i(splt_dst_rdy)); -- cgit v1.2.3 From 42561353c372696337983e74a5c7b690afa2aedd Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 22 Apr 2011 15:17:36 -0700 Subject: u1p: reset gpif --- usrp2/gpif/packet_splitter_tb.v | 4 ++-- usrp2/top/u1plus/u1plus_core.v | 6 ++++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/usrp2/gpif/packet_splitter_tb.v b/usrp2/gpif/packet_splitter_tb.v index d35f1c6d4..877f6ae1c 100644 --- a/usrp2/gpif/packet_splitter_tb.v +++ b/usrp2/gpif/packet_splitter_tb.v @@ -33,7 +33,7 @@ module packet_splitter_tb(); vita_pkt_gen vita_pkt_gen (.clk(sys_clk), .reset(sys_rst) , .clear(0), - .len(7),.data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int)); + .len(512),.data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int)); fifo36_to_fifo19 #(.LE(1)) f36_to_f19 (.clk(sys_clk), .reset(sys_rst), .clear(0), @@ -42,7 +42,7 @@ module packet_splitter_tb(); packet_splitter #(.FRAME_LEN(13)) rx_packet_splitter (.clk(sys_clk), .reset(sys_rst), .clear(0), - .frames_per_packet(3), + .frames_per_packet(4), .data_i(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), .data_o(data_splt), .src_rdy_o(src_rdy_splt), .dst_rdy_i(dst_rdy_splt)); diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index a2147e463..26565afa6 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -53,6 +53,8 @@ module u1plus_core wire [31:0] debug1; wire [31:0] debug_vt; + wire gpif_rst; + wire rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc; reg [7:0] frames_per_packet; @@ -63,7 +65,8 @@ module u1plus_core (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(global_reset)); - reset_sync reset_sync(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(wb_rst)); + reset_sync reset_sync_wb(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(wb_rst)); + reset_sync reset_sync_gp(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(gpif_rst)); wire [15:0] test_len; // ///////////////////////////////////////////////////////////////////////////////////// @@ -84,7 +87,6 @@ module u1plus_core tx_err_src_rdy, tx_err_dst_rdy; wire bus_error; - wire gpif_rst = 0; wire clear_tx, clear_rx; setting_reg #(.my_addr(SR_CLEAR_RX_FIFO), .width(1)) sr_clear_rx -- cgit v1.2.3 From 56b133ea0d40de3a9bfcd5ed27fca083a809b084 Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Mon, 25 Apr 2011 16:26:02 -0700 Subject: B100: added some packet splitter debug pins, removed debug from GPIO port, swapped I&Q in interleaver --- usrp2/gpif/gpif.v | 19 +++++++++++-------- usrp2/gpif/gpif_rd.v | 2 +- usrp2/gpif/packet_splitter.v | 7 ++++++- usrp2/top/u1plus/u1plus.v | 8 ++++---- usrp2/top/u1plus/u1plus_core.v | 4 ++-- 5 files changed, 24 insertions(+), 16 deletions(-) diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index d003c6b1c..3649654ed 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -38,7 +38,7 @@ module gpif wire [15:0] gpif_d_copy = gpif_d; - wire [31:0] debug_rd, debug_wr; + wire [31:0] debug_rd, debug_wr, debug_split0, debug_split1; // //////////////////////////////////////////////////////////////////// // TX Data Path @@ -105,7 +105,8 @@ module gpif (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), .frames_per_packet(frames_per_packet), .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy), - .data_o(splt_data), .src_rdy_o(splt_src_rdy), .dst_rdy_i(splt_dst_rdy)); + .data_o(splt_data), .src_rdy_o(splt_src_rdy), .dst_rdy_i(splt_dst_rdy), + .debug0(debug_split0), .debug1(debug_split1)); gpif_rd gpif_rd (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), @@ -226,12 +227,14 @@ module gpif // //////////////////////////////////////////// // DEBUG - assign debug0 = { rx19_src_rdy, rx19_dst_rdy, resp_src_rdy, resp_dst_rdy, gpif_ctl[3:0], gpif_rdy[3:0], - gpif_d_copy[15:0] }; + //assign debug0 = { rx19_src_rdy, rx19_dst_rdy, resp_src_rdy, resp_dst_rdy, gpif_ctl[3:0], gpif_rdy[3:0], + // gpif_d_copy[15:0] }; - assign debug1 = { { debug_rd[15:8] }, - { debug_rd[7:0] }, - { rx_src_rdy_i, rx_dst_rdy_o, rx36_src_rdy, rx36_dst_rdy, rx19_src_rdy, rx19_dst_rdy, resp_src_rdy, resp_dst_rdy}, - { tx_src_rdy_o, tx_dst_rdy_i, tx19_src_rdy, tx19_dst_rdy, tx36_src_rdy, tx36_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy} }; + //assign debug1 = { { debug_rd[15:8] }, + // { debug_rd[7:0] }, + // { rx_src_rdy_i, rx_dst_rdy_o, rx36_src_rdy, rx36_dst_rdy, rx19_src_rdy, rx19_dst_rdy, resp_src_rdy, resp_dst_rdy}, + // { tx_src_rdy_o, tx_dst_rdy_i, tx19_src_rdy, tx19_dst_rdy, tx36_src_rdy, tx36_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy} }; + assign debug0 = { gpif_ctl[3:0], gpif_rdy[3:0], debug_split0[23:0] }; + assign debug1 = { gpif_misc[0], debug_rd[14:0], debug_split1[15:8], debug_split1[7:0] }; endmodule // gpif diff --git a/usrp2/gpif/gpif_rd.v b/usrp2/gpif/gpif_rd.v index 728b8be78..1639f0132 100644 --- a/usrp2/gpif/gpif_rd.v +++ b/usrp2/gpif/gpif_rd.v @@ -89,6 +89,6 @@ module gpif_rd assign debug = { { 16'd0 }, { data_int[17:16], data_o[17:16], packet_count[3:0] }, - { 2'b0,final_rdy_data, final_rdy_resp, consume_data_line, consume_resp_line, src_rdy_int, dst_rdy_int} }; + { consume_sop, consume_eop, final_rdy_data, data_o[18], consume_data_line, consume_resp_line, src_rdy_int, dst_rdy_int} }; endmodule // gpif_rd diff --git a/usrp2/gpif/packet_splitter.v b/usrp2/gpif/packet_splitter.v index 1c289c2fa..a55f4cb4f 100644 --- a/usrp2/gpif/packet_splitter.v +++ b/usrp2/gpif/packet_splitter.v @@ -10,7 +10,9 @@ module packet_splitter output dst_rdy_o, output [18:0] data_o, output src_rdy_o, - input dst_rdy_i); + input dst_rdy_i, + output [31:0] debug0, + output [31:0] debug1); reg [1:0] state; reg [15:0] length; @@ -98,4 +100,7 @@ module packet_splitter wire [15:0] data_out = data_i[15:0]; assign data_o = {occ_out, eof_out, sof_out, data_out}; + assign debug0 = { 8'd0, dst_rdy_o, src_rdy_o, next_state_is_idle, eof_out, sof_out, occ_out, state[1:0], frame_count[7:0], frames_per_packet[7:0] }; + assign debug1 = { length[15:0], frame_len[15:0] }; + endmodule // packet_splitter diff --git a/usrp2/top/u1plus/u1plus.v b/usrp2/top/u1plus/u1plus.v index 7e1bd2ea7..9aafef3ce 100644 --- a/usrp2/top/u1plus/u1plus.v +++ b/usrp2/top/u1plus/u1plus.v @@ -126,13 +126,13 @@ module u1plus always @(posedge clk_fpga) if(rxsync_0) begin - rx_i <= rx_a; - rx_q <= rx_b; + rx_i <= rx_b; + rx_q <= rx_a; end else begin - rx_i <= rx_b; - rx_q <= rx_a; + rx_i <= rx_a; + rx_q <= rx_b; end // ///////////////////////////////////////////////////////////////////////// diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index 26565afa6..898f5950c 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -329,7 +329,7 @@ module u1plus_core .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( /*{io_tx,io_rx}*/ ) ); + .gpio( {io_tx,io_rx} ) ); // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #8 + 9 @@ -387,6 +387,6 @@ module u1plus_core assign debug = debug0; assign debug_gpio_0 = 0; assign debug_gpio_1 = 0; - assign {io_tx,io_rx} = vr_debug; + //assign {io_tx,io_rx} = {debug1}; endmodule // u1plus_core -- cgit v1.2.3 From 795969261ce4abdc4e58ca0ca61900b3227779d9 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 26 May 2011 17:35:56 -0700 Subject: u2p-rebase: go back to versions on next --- usrp2/fifo/fifo36_mux.v | 3 +-- usrp2/vrt/vita_rx_control.v | 6 +++--- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/usrp2/fifo/fifo36_mux.v b/usrp2/fifo/fifo36_mux.v index 2b454abaf..7f0f803ff 100644 --- a/usrp2/fifo/fifo36_mux.v +++ b/usrp2/fifo/fifo36_mux.v @@ -74,5 +74,4 @@ module fifo36_mux (.clk(clk), .reset(reset), .clear(clear), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); - -endmodule // fifo36_mux +endmodule // fifo36_demux diff --git a/usrp2/vrt/vita_rx_control.v b/usrp2/vrt/vita_rx_control.v index 73d9b87fd..4c0cef50d 100644 --- a/usrp2/vrt/vita_rx_control.v +++ b/usrp2/vrt/vita_rx_control.v @@ -191,9 +191,9 @@ module vita_rx_control assign read_ctrl = ( (ibs_state == IBS_IDLE) | ((ibs_state == IBS_RUNNING) & strobe & ~full & (lines_left==1) & chain) ) & not_empty_ctrl; - assign debug_rx = { { 8'd0 }, + assign debug_rx = { { ibs_state[2:0], command_queue_len }, { 8'd0 }, - { go_now, too_late, run, strobe, read_ctrl, write_ctrl, overrun, ~not_empty_ctrl }, - { ibs_state[2:0], chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} }; + { go_now, too_late, run, strobe, read_ctrl, write_ctrl, 1'b0, ~not_empty_ctrl }, + { 2'b0, overrun, chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} }; endmodule // vita_rx_control -- cgit v1.2.3 From e7eb44d5abc1021972c07c4b867c98c8223eca2b Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 6 Jan 2011 11:07:30 -0800 Subject: first cut at using lvds for adc pins --- usrp2/top/u2plus/capture_ddrlvds.v | 4 ++-- usrp2/top/u2plus/u2plus.v | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u2plus/capture_ddrlvds.v b/usrp2/top/u2plus/capture_ddrlvds.v index b9f53ff8c..ff1b586e2 100644 --- a/usrp2/top/u2plus/capture_ddrlvds.v +++ b/usrp2/top/u2plus/capture_ddrlvds.v @@ -16,13 +16,13 @@ module capture_ddrlvds wire [(2*WIDTH)-1:0] out_pre1; reg [(2*WIDTH)-1:0] out_pre2; - IBUFGDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); + IBUFGDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("TRUE")) clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); genvar i; generate for(i = 0; i < WIDTH; i = i + 1) begin : gen_lvds_pins - IBUFDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) ibufds + IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("TRUE")) ibufds (.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) ); IDDR2 #(.DDR_ALIGNMENT("C1")) iddr2 (.Q0(out_pre1[2*i]), .Q1(out_pre1[(2*i)+1]), .C0(ssclk), .C1(~ssclk), diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index 7c2270df6..eb99de86c 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -1,4 +1,5 @@ `timescale 1ns / 1ps +`define LVDS 1 //`define DCM_FOR_RAMCLK ////////////////////////////////////////////////////////////////////////////////// -- cgit v1.2.3 From e2eca54dafc2f9040485d3f5658ce97dad66aa2b Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 6 Jan 2011 12:41:33 -0800 Subject: builds now --- usrp2/top/u2plus/Makefile | 1 + usrp2/top/u2plus/capture_ddrlvds.v | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u2plus/Makefile b/usrp2/top/u2plus/Makefile index 38400ce62..ed044d6a8 100644 --- a/usrp2/top/u2plus/Makefile +++ b/usrp2/top/u2plus/Makefile @@ -45,6 +45,7 @@ simulator "ISE Simulator (VHDL/Verilog)" \ # Sources ################################################## TOP_SRCS = \ +capture_ddrlvds.v \ u2plus_core.v \ u2plus.v \ u2plus.ucf diff --git a/usrp2/top/u2plus/capture_ddrlvds.v b/usrp2/top/u2plus/capture_ddrlvds.v index ff1b586e2..65635750e 100644 --- a/usrp2/top/u2plus/capture_ddrlvds.v +++ b/usrp2/top/u2plus/capture_ddrlvds.v @@ -16,13 +16,14 @@ module capture_ddrlvds wire [(2*WIDTH)-1:0] out_pre1; reg [(2*WIDTH)-1:0] out_pre2; - IBUFGDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("TRUE")) clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("FALSE")) + clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); genvar i; generate for(i = 0; i < WIDTH; i = i + 1) begin : gen_lvds_pins - IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("TRUE")) ibufds + IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("FALSE")) ibufds (.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) ); IDDR2 #(.DDR_ALIGNMENT("C1")) iddr2 (.Q0(out_pre1[2*i]), .Q1(out_pre1[(2*i)+1]), .C0(ssclk), .C1(~ssclk), -- cgit v1.2.3 From 58fe69310016580481d739cd3638633c446b5747 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 20 May 2011 21:01:12 -0700 Subject: u2p-lvds: remove unused nets --- usrp2/top/u2plus/capture_ddrlvds.v | 2 -- 1 file changed, 2 deletions(-) diff --git a/usrp2/top/u2plus/capture_ddrlvds.v b/usrp2/top/u2plus/capture_ddrlvds.v index 65635750e..2bf114988 100644 --- a/usrp2/top/u2plus/capture_ddrlvds.v +++ b/usrp2/top/u2plus/capture_ddrlvds.v @@ -10,8 +10,6 @@ module capture_ddrlvds output reg [(2*WIDTH)-1:0] out); wire [WIDTH-1:0] ddr_dat; - wire ssclk_regional; - wire ssclk_io; wire ssclk; wire [(2*WIDTH)-1:0] out_pre1; reg [(2*WIDTH)-1:0] out_pre2; -- cgit v1.2.3 From 9451cb630962216492496f2f13d43ab2d08bde5d Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 23 May 2011 18:21:09 -0700 Subject: u2p: FPGA internal termination on the clock line from ADC --- usrp2/top/u2plus/capture_ddrlvds.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u2plus/capture_ddrlvds.v b/usrp2/top/u2plus/capture_ddrlvds.v index 2bf114988..d263e0cfa 100644 --- a/usrp2/top/u2plus/capture_ddrlvds.v +++ b/usrp2/top/u2plus/capture_ddrlvds.v @@ -14,7 +14,7 @@ module capture_ddrlvds wire [(2*WIDTH)-1:0] out_pre1; reg [(2*WIDTH)-1:0] out_pre2; - IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("FALSE")) + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); genvar i; @@ -29,7 +29,7 @@ module capture_ddrlvds end endgenerate - always @(negedge clk) + always @(posedge clk) out_pre2 <= out_pre1; always @(posedge clk) -- cgit v1.2.3 From 4172aa82edd9bee3cc68426bb8714491e62f10cf Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Tue, 7 Jun 2011 15:56:24 -0700 Subject: N210: added makefiles in for rev 4 versions (use LVDS) --- usrp2/top/u2plus/Makefile | 99 -------------------------------------- usrp2/top/u2plus/Makefile.N200 | 98 -------------------------------------- usrp2/top/u2plus/Makefile.N200R3 | 98 ++++++++++++++++++++++++++++++++++++++ usrp2/top/u2plus/Makefile.N200R4 | 100 +++++++++++++++++++++++++++++++++++++++ usrp2/top/u2plus/Makefile.N210R3 | 98 ++++++++++++++++++++++++++++++++++++++ usrp2/top/u2plus/Makefile.N210R4 | 100 +++++++++++++++++++++++++++++++++++++++ usrp2/top/u2plus/rev4_defs.v | 1 + usrp2/top/u2plus/u2plus.v | 2 +- 8 files changed, 398 insertions(+), 198 deletions(-) delete mode 100644 usrp2/top/u2plus/Makefile delete mode 100644 usrp2/top/u2plus/Makefile.N200 create mode 100644 usrp2/top/u2plus/Makefile.N200R3 create mode 100644 usrp2/top/u2plus/Makefile.N200R4 create mode 100644 usrp2/top/u2plus/Makefile.N210R3 create mode 100644 usrp2/top/u2plus/Makefile.N210R4 create mode 100644 usrp2/top/u2plus/rev4_defs.v diff --git a/usrp2/top/u2plus/Makefile b/usrp2/top/u2plus/Makefile deleted file mode 100644 index ed044d6a8..000000000 --- a/usrp2/top/u2plus/Makefile +++ /dev/null @@ -1,99 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = u2plus -BUILD_DIR = $(abspath build$(ISE)) - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../extramfifo/Makefile.srcs - - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd3400a \ -package fg676 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -capture_ddrlvds.v \ -u2plus_core.v \ -u2plus.v \ -u2plus.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/u2plus/Makefile.N200 b/usrp2/top/u2plus/Makefile.N200 deleted file mode 100644 index 9175f9304..000000000 --- a/usrp2/top/u2plus/Makefile.N200 +++ /dev/null @@ -1,98 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = u2plus -BUILD_DIR = $(abspath build$(ISE)-N200) - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../extramfifo/Makefile.srcs - - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd1800a \ -package fg676 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -u2plus_core.v \ -u2plus.v \ -u2plus.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/u2plus/Makefile.N200R3 b/usrp2/top/u2plus/Makefile.N200R3 new file mode 100644 index 000000000..a525836ed --- /dev/null +++ b/usrp2/top/u2plus/Makefile.N200R3 @@ -0,0 +1,98 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u2plus +BUILD_DIR = $(abspath build$(ISE)-N200R3) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extramfifo/Makefile.srcs + + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u2plus_core.v \ +u2plus.v \ +u2plus.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/u2plus/Makefile.N200R4 b/usrp2/top/u2plus/Makefile.N200R4 new file mode 100644 index 000000000..955aadc59 --- /dev/null +++ b/usrp2/top/u2plus/Makefile.N200R4 @@ -0,0 +1,100 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u2plus +BUILD_DIR = $(abspath build$(ISE)-N200R4) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extramfifo/Makefile.srcs + + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +rev4_defs.v \ +capture_ddrlvds.v \ +u2plus_core.v \ +u2plus.v \ +u2plus.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/u2plus/Makefile.N210R3 b/usrp2/top/u2plus/Makefile.N210R3 new file mode 100644 index 000000000..e29251e1c --- /dev/null +++ b/usrp2/top/u2plus/Makefile.N210R3 @@ -0,0 +1,98 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u2plus +BUILD_DIR = $(abspath build$(ISE)-N210R3) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extramfifo/Makefile.srcs + + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd3400a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u2plus_core.v \ +u2plus.v \ +u2plus.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/u2plus/Makefile.N210R4 b/usrp2/top/u2plus/Makefile.N210R4 new file mode 100644 index 000000000..73747e544 --- /dev/null +++ b/usrp2/top/u2plus/Makefile.N210R4 @@ -0,0 +1,100 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u2plus +BUILD_DIR = $(abspath build$(ISE)-N210R4) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extramfifo/Makefile.srcs + + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd3400a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +rev4_defs.v \ +capture_ddrlvds.v \ +u2plus_core.v \ +u2plus.v \ +u2plus.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/u2plus/rev4_defs.v b/usrp2/top/u2plus/rev4_defs.v new file mode 100644 index 000000000..e37f34851 --- /dev/null +++ b/usrp2/top/u2plus/rev4_defs.v @@ -0,0 +1 @@ +`define LVDS 1 diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index eb99de86c..7bf467fde 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -1,5 +1,5 @@ `timescale 1ns / 1ps -`define LVDS 1 +//`define LVDS 1 //`define DCM_FOR_RAMCLK ////////////////////////////////////////////////////////////////////////////////// -- cgit v1.2.3 From addc1b743e7b88c4f97682b9eb195edc6cac0b7f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 7 Jun 2011 16:17:50 -0700 Subject: remove old iad stuff --- usrp2/top/u2_rev3_2rx_iad/Makefile | 253 ---------- usrp2/top/u2_rev3_2rx_iad/README | 32 -- usrp2/top/u2_rev3_2rx_iad/cmdfile | 4 - usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v | 212 -------- usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav | 106 ---- usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v | 233 --------- usrp2/top/u2_rev3_2rx_iad/impulse.v | 68 --- usrp2/top/u2_rev3_2rx_iad/u2_core.v | 789 ------------------------------ usrp2/top/u2_rev3_2rx_iad/wave.sh | 3 - usrp2/top/u2_rev3_iad/.gitignore | 4 - usrp2/top/u2_rev3_iad/Makefile | 253 ---------- usrp2/top/u2_rev3_iad/cmdfile | 4 - usrp2/top/u2_rev3_iad/dsp_core_rx.v | 158 ------ usrp2/top/u2_rev3_iad/dsp_core_tb.sav | 61 --- usrp2/top/u2_rev3_iad/dsp_core_tb.v | 196 -------- usrp2/top/u2_rev3_iad/impulse.v | 63 --- usrp2/top/u2_rev3_iad/wave.sh | 3 - 17 files changed, 2442 deletions(-) delete mode 100644 usrp2/top/u2_rev3_2rx_iad/Makefile delete mode 100644 usrp2/top/u2_rev3_2rx_iad/README delete mode 100644 usrp2/top/u2_rev3_2rx_iad/cmdfile delete mode 100644 usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v delete mode 100644 usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav delete mode 100644 usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v delete mode 100644 usrp2/top/u2_rev3_2rx_iad/impulse.v delete mode 100755 usrp2/top/u2_rev3_2rx_iad/u2_core.v delete mode 100755 usrp2/top/u2_rev3_2rx_iad/wave.sh delete mode 100644 usrp2/top/u2_rev3_iad/.gitignore delete mode 100644 usrp2/top/u2_rev3_iad/Makefile delete mode 100644 usrp2/top/u2_rev3_iad/cmdfile delete mode 100644 usrp2/top/u2_rev3_iad/dsp_core_rx.v delete mode 100644 usrp2/top/u2_rev3_iad/dsp_core_tb.sav delete mode 100644 usrp2/top/u2_rev3_iad/dsp_core_tb.v delete mode 100644 usrp2/top/u2_rev3_iad/impulse.v delete mode 100755 usrp2/top/u2_rev3_iad/wave.sh diff --git a/usrp2/top/u2_rev3_2rx_iad/Makefile b/usrp2/top/u2_rev3_2rx_iad/Makefile deleted file mode 100644 index 334089839..000000000 --- a/usrp2/top/u2_rev3_2rx_iad/Makefile +++ /dev/null @@ -1,253 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -################################################## -# xtclsh Shell and tcl Script Path -################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl - -################################################## -# Project Setup -################################################## -BUILD_DIR := build/ -export TOP_MODULE := u2_rev3 -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family Spartan3 \ -device xc3s2000 \ -package fg456 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ -control_lib/bin2gray.v \ -control_lib/buffer_int.v \ -control_lib/buffer_pool.v \ -control_lib/cascadefifo2.v \ -control_lib/dcache.v \ -control_lib/decoder_3_8.v \ -control_lib/dpram32.v \ -control_lib/fifo_2clock.v \ -control_lib/fifo_2clock_casc.v \ -control_lib/gray2bin.v \ -control_lib/gray_send.v \ -control_lib/icache.v \ -control_lib/longfifo.v \ -control_lib/mux4.v \ -control_lib/mux8.v \ -control_lib/nsgpio.v \ -control_lib/ram_2port.v \ -control_lib/ram_harv_cache.v \ -control_lib/ram_loader.v \ -control_lib/setting_reg.v \ -control_lib/settings_bus.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ -control_lib/srl.v \ -control_lib/system_control.v \ -control_lib/wb_1master.v \ -control_lib/wb_readback_mux.v \ -control_lib/simple_uart.v \ -control_lib/simple_uart_tx.v \ -control_lib/simple_uart_rx.v \ -control_lib/oneshot_2clk.v \ -control_lib/sd_spi.v \ -control_lib/sd_spi_wb.v \ -control_lib/wb_bridge_16_32.v \ -coregen/fifo_xlnx_2Kx36_2clk.v \ -coregen/fifo_xlnx_2Kx36_2clk.xco \ -coregen/fifo_xlnx_512x36_2clk.v \ -coregen/fifo_xlnx_512x36_2clk.xco \ -eth/mac_rxfifo_int.v \ -eth/mac_txfifo_int.v \ -eth/rtl/verilog/Clk_ctrl.v \ -eth/rtl/verilog/MAC_rx.v \ -eth/rtl/verilog/MAC_rx/Broadcast_filter.v \ -eth/rtl/verilog/MAC_rx/CRC_chk.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \ -eth/rtl/verilog/MAC_top.v \ -eth/rtl/verilog/MAC_tx.v \ -eth/rtl/verilog/MAC_tx/CRC_gen.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \ -eth/rtl/verilog/MAC_tx/Random_gen.v \ -eth/rtl/verilog/Phy_int.v \ -eth/rtl/verilog/RMON.v \ -eth/rtl/verilog/RMON/RMON_addr_gen.v \ -eth/rtl/verilog/RMON/RMON_ctrl.v \ -eth/rtl/verilog/Reg_int.v \ -eth/rtl/verilog/eth_miim.v \ -eth/rtl/verilog/flow_ctrl_rx.v \ -eth/rtl/verilog/flow_ctrl_tx.v \ -eth/rtl/verilog/miim/eth_clockgen.v \ -eth/rtl/verilog/miim/eth_outputcontrol.v \ -eth/rtl/verilog/miim/eth_shiftreg.v \ -opencores/8b10b/decode_8b10b.v \ -opencores/8b10b/encode_8b10b.v \ -opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -opencores/aemb/rtl/verilog/aeMB_core_BE.v \ -opencores/aemb/rtl/verilog/aeMB_ctrl.v \ -opencores/aemb/rtl/verilog/aeMB_edk32.v \ -opencores/aemb/rtl/verilog/aeMB_ibuf.v \ -opencores/aemb/rtl/verilog/aeMB_regf.v \ -opencores/aemb/rtl/verilog/aeMB_xecu.v \ -opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_defines.v \ -opencores/i2c/rtl/verilog/i2c_master_top.v \ -opencores/i2c/rtl/verilog/timescale.v \ -opencores/simple_pic/rtl/simple_pic.v \ -opencores/spi/rtl/verilog/spi_clgen.v \ -opencores/spi/rtl/verilog/spi_defines.v \ -opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ -sdr_lib/acc.v \ -sdr_lib/add2.v \ -sdr_lib/add2_and_round.v \ -sdr_lib/add2_and_round_reg.v \ -sdr_lib/add2_reg.v \ -sdr_lib/cic_dec_shifter.v \ -sdr_lib/cic_decim.v \ -sdr_lib/cic_int_shifter.v \ -sdr_lib/cic_interp.v \ -sdr_lib/cic_strober.v \ -sdr_lib/clip.v \ -sdr_lib/clip_reg.v \ -sdr_lib/cordic.v \ -sdr_lib/cordic_z24.v \ -sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_tx.v \ -sdr_lib/hb_dec.v \ -sdr_lib/hb_interp.v \ -sdr_lib/integrate.v \ -sdr_lib/round.v \ -sdr_lib/round_reg.v \ -sdr_lib/rx_control.v \ -sdr_lib/rx_dcoffset.v \ -sdr_lib/sign_extend.v \ -sdr_lib/small_hb_dec.v \ -sdr_lib/small_hb_int.v \ -sdr_lib/tx_control.v \ -serdes/serdes.v \ -serdes/serdes_fc_rx.v \ -serdes/serdes_fc_tx.v \ -serdes/serdes_rx.v \ -serdes/serdes_tx.v \ -timing/time_receiver.v \ -timing/time_sender.v \ -timing/time_sync.v \ -timing/timer.v \ -top/u2_rev3/u2_rev3.ucf \ -top/u2_rev3/u2_rev3.v \ -top/u2_rev3_2rx_iad/u2_core.v \ -top/u2_rev3_2rx_iad/dsp_core_rx.v - -################################################## -# Process Properties -################################################## -export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -export TRANSLATE_PROPERTIES := \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -export MAP_PROPERTIES := \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -export PLACE_ROUTE_PROPERTIES := \ -"Place & Route Effort Level (Overall)" High - -export STATIC_TIMING_PROPERTIES := \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -export GEN_PROG_FILE_PROPERTIES := \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, testbench, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -testbench: - iverilog -c cmdfile -o dsp_core_tb dsp_core_tb.v - -clean: - rm -rf $(BUILD_DIR) - rm -f dsp_core_tb - rm -f *.lx2 - rm -f *.dat - rm -f *.vcd diff --git a/usrp2/top/u2_rev3_2rx_iad/README b/usrp2/top/u2_rev3_2rx_iad/README deleted file mode 100644 index 3efc5305b..000000000 --- a/usrp2/top/u2_rev3_2rx_iad/README +++ /dev/null @@ -1,32 +0,0 @@ -This is a custom build for USRP2 FPGA. It allows using a BasicRX or -LFRX board and feed two independent, real signals. In addition, instead -of the CIC/HB decimator, which optimizes frequency response, it uses an -integrate and dump decimator, which optimizes for time-domain impulse -response. - -These changes have been made in dsp_core_rx.v: - -* A second DDC has been added, sharing a frequency register with - the existing DDC. - -* The output of the two DDCs are interleaved as I1 Q1 I2 Q2I ... - into the receive FIFO. This limits the host configured decimation - to 8 intead of 4. Use gr.deinterleave to recover the streams. - -* The ADCs are hardcoded: - - RX_A ==> DDC #1 I-input - 0 ==> DDC #1 Q-input - RX_B ==> DDC #2 I-input - 0 ==> DDC #2 Q-input - - Thus, the input mux has been disabled. - -* The CIC/HB decimator has been replaced by an integrate and dump at - the decimation rate. - -* To assist with meeting timing, the external RAM has been disabled. - -The basic application is to coherently sample two real IF streams and -downconvert to baseband, while minimizing the impulse response duration -of the resampling filters. diff --git a/usrp2/top/u2_rev3_2rx_iad/cmdfile b/usrp2/top/u2_rev3_2rx_iad/cmdfile deleted file mode 100644 index 34373a676..000000000 --- a/usrp2/top/u2_rev3_2rx_iad/cmdfile +++ /dev/null @@ -1,4 +0,0 @@ --y . --y ../../sdr_lib --y ../../control_lib --y ../../models diff --git a/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v b/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v deleted file mode 100644 index 4a945bd1a..000000000 --- a/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v +++ /dev/null @@ -1,212 +0,0 @@ -`define DSP_CORE_RX_BASE 160 -module dsp_core_rx - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - input [13:0] adc_a, input adc_ovf_a, - input [13:0] adc_b, input adc_ovf_b, - - input [15:0] io_rx, - - output reg [31:0] sample, - input run, - output strobe, - output [31:0] debug - ); - - wire [15:0] scale_i, scale_q; - wire [13:0] adc_a_ofs, adc_b_ofs; - reg [13:0] adc_i, adc_q; - wire [31:0] phase_inc; - reg [31:0] phase; - - wire [35:0] prod_i, prod_q; - wire [23:0] i_cordic_a, q_cordic_a, i_cordic_b, q_cordic_b; - wire [31:0] i_iad_a, q_iad_a, i_iad_b, q_iad_b; - wire [15:0] i_out_a, q_out_a, i_out_b, q_out_b; - - wire enable_hb1, enable_hb2; // Correspond to std firmware settings - wire [7:0] cic_decim; // for combined CIC/HB decimator - wire [9:0] decim_rate; // Reconstructed original decimation setting - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phase_inc),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({scale_i,scale_q}),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({enable_hb1,enable_hb2,cic_decim}),.changed()); - - rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_in(adc_a),.adc_out(adc_a_ofs)); - - rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_in(adc_b),.adc_out(adc_b_ofs)); - -`ifdef MUXCTRL - wire [3:0] muxctrl; - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(muxctrl),.changed()); -`endif - - wire [1:0] gpio_ena; - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(gpio_ena),.changed()); - - // The TVRX connects to what is called adc_b, thus A and B are - // swapped throughout the design. - // - // In the interest of expediency and keeping the s/w sane, we just remap them here. - // The I & Q fields are mapped the same: - // 0 -> "the real A" (as determined by the TVRX) - // 1 -> "the real B" - // 2 -> const zero - -`ifdef MUXCTRL - always @(posedge clk) - case(muxctrl[1:0]) // The I mapping - 0: adc_i <= adc_b_ofs; // "the real A" - 1: adc_i <= adc_a_ofs; - 2: adc_i <= 0; - default: adc_i <= 0; - endcase // case(muxctrl[1:0]) - - always @(posedge clk) - case(muxctrl[3:2]) // The Q mapping - 0: adc_q <= adc_b_ofs; // "the real A" - 1: adc_q <= adc_a_ofs; - 2: adc_q <= 0; - default: adc_q <= 0; - endcase // case(muxctrl[3:2]) -`else // !`ifdef MUXCTRL - always @(posedge clk) - begin - adc_i <= adc_a_ofs; - adc_q <= adc_b_ofs; - end -`endif // !`ifdef MUXCTRL - - always @(posedge clk) - if(rst) - phase <= 0; - else if(~run) - phase <= 0; - else - phase <= phase + phase_inc; - - MULT18X18S mult_i - (.P(prod_i), // 36-bit multiplier output - .A({{4{adc_i[13]}},adc_i} ), // 18-bit multiplier input - .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - MULT18X18S mult_q - (.P(prod_q), // 36-bit multiplier output - .A({{4{adc_q[13]}},adc_q} ), // 18-bit multiplier input - .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - - // Route I,0 to first CORDIC - cordic_z24 #(.bitwidth(24)) - cordic_a(.clock(clk), .reset(rst), .enable(run), - .xi(prod_i[24:1]),. yi(0), .zi(phase[31:8]), - .xo(i_cordic_a),.yo(q_cordic_a),.zo() ); - - // Route Q,0 to second CORDIC - cordic_z24 #(.bitwidth(24)) - cordic_b(.clock(clk), .reset(rst), .enable(run), - .xi(prod_q[24:1]),. yi(0), .zi(phase[31:8]), - .xo(i_cordic_b),.yo(q_cordic_b),.zo() ); - - // Reconstruct original decimation rate from standard firmware settings - assign decim_rate = enable_hb2 ? (enable_hb1 ? {cic_decim,2'b0} : - {1'b0,cic_decim,1'b0 }) : - cic_decim; - - cic_strober #(.WIDTH(10)) // Convenient reuse of strobe generator - cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate), - .strobe_fast(1),.strobe_slow(strobe_iad) ); - - wire strobe_iad_o; - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i_a - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(i_cordic_a), - .stb_o(strobe_iad_o),.integ_o(i_iad_a) ); - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q_a - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(q_cordic_a), - .stb_o(),.integ_o(q_iad_a) ); - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i_b - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(i_cordic_b), - .stb_o(),.integ_o(i_iad_b) ); - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q_b - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(q_cordic_b), - .stb_o(),.integ_o(q_iad_b) ); - - round #(.bits_in(32),.bits_out(16)) round_iout_a (.in(i_iad_a),.out(i_out_a)); - round #(.bits_in(32),.bits_out(16)) round_qout_a (.in(q_iad_a),.out(q_out_a)); - round #(.bits_in(32),.bits_out(16)) round_iout_b (.in(i_iad_b),.out(i_out_b)); - round #(.bits_in(32),.bits_out(16)) round_qout_b (.in(q_iad_b),.out(q_out_b)); - - reg [31:0] sample_out_a, sample_out_b, sample_out; - reg stb_d1, stb_d2, stb_d3, stb_d4, stb_d5; - reg strobe_out; - - // Register samples on strobe_iad - // Output A on d1 - // Output B on d5 - always @(posedge clk) - begin - stb_d1 <= strobe_iad_o; - stb_d2 <= stb_d1; - stb_d3 <= stb_d2; - stb_d4 <= stb_d3; - stb_d5 <= stb_d4; - end - - always @(posedge clk) - if (strobe_iad_o) - begin - // Streaming GPIO - // io_rx[15] => I channel LSB if gpio_ena[0] high - // io_rx[14] => Q channel LSB if gpio_ena[1] high - sample_out_a <= {i_out_a[15:1], gpio_ena[0] ? io_rx[15] : i_out_a[0], - q_out_a[15:1], gpio_ena[1] ? io_rx[14] : q_out_a[0] }; - sample_out_b <= {i_out_b[15:1], gpio_ena[0] ? io_rx[15] : i_out_b[0], - q_out_b[15:1], gpio_ena[1] ? io_rx[14] : q_out_b[0] }; - end - - always @(posedge clk) - begin - if (stb_d1) - sample <= sample_out_a; - else if (stb_d5) - sample <= sample_out_b; - strobe_out <= stb_d1|stb_d5; - end - - assign strobe = strobe_out; - assign debug = 0; - -endmodule // dsp_core_rx diff --git a/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav b/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav deleted file mode 100644 index 12f746860..000000000 --- a/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav +++ /dev/null @@ -1,106 +0,0 @@ -[size] 1680 975 -[pos] -1 -1 -*-17.007835 70679400 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] dsp_core_tb. -@200 --SYSCON -@28 -dsp_core_tb.clk -dsp_core_tb.rst -dsp_core_tb.run -@200 -- --Settings Bus -@22 -dsp_core_tb.set_addr[7:0] -@24 -dsp_core_tb.set_data[31:0] -@28 -dsp_core_tb.set_stb -@200 -- --RX DSP CORE -@22 -dsp_core_tb.rx_path.adc_a[13:0] -dsp_core_tb.rx_path.adc_b[13:0] -@28 -dsp_core_tb.rx_path.adc_ovf_a -dsp_core_tb.rx_path.adc_ovf_b -@22 -dsp_core_tb.rx_path.io_rx[15:0] -@200 -- -@22 -dsp_core_tb.rx_path.sample[31:0] -@28 -dsp_core_tb.rx_path.strobe -@200 -- -@22 -dsp_core_tb.rx_path.phase_inc[31:0] -dsp_core_tb.rx_path.scale_i[15:0] -dsp_core_tb.rx_path.scale_q[15:0] -@28 -dsp_core_tb.rx_path.enable_hb1 -dsp_core_tb.rx_path.enable_hb2 -@22 -dsp_core_tb.rx_path.cic_decim[7:0] -dsp_core_tb.rx_path.adc_a_ofs[13:0] -dsp_core_tb.rx_path.adc_b_ofs[13:0] -dsp_core_tb.rx_path.muxctrl[3:0] -@200 -- -@22 -dsp_core_tb.rx_path.adc_i[13:0] -dsp_core_tb.rx_path.adc_q[13:0] -dsp_core_tb.rx_path.phase[31:0] -dsp_core_tb.rx_path.prod_i[35:0] -dsp_core_tb.rx_path.prod_q[35:0] -@8420 -dsp_core_tb.rx_path.i_cordic_a[23:0] -dsp_core_tb.rx_path.q_cordic_a[23:0] -dsp_core_tb.rx_path.i_cordic_b[23:0] -dsp_core_tb.rx_path.q_cordic_b[23:0] -@22 -dsp_core_tb.rx_path.decim_rate[9:0] -@28 -dsp_core_tb.rx_path.strobe_iad -@22 -dsp_core_tb.rx_path.i_iad_a[31:0] -dsp_core_tb.rx_path.q_iad_a[31:0] -@23 -dsp_core_tb.rx_path.i_iad_b[31:0] -@22 -dsp_core_tb.rx_path.q_iad_b[31:0] -@28 -dsp_core_tb.rx_path.strobe_iad_o -@8420 -dsp_core_tb.rx_path.i_out_a[15:0] -dsp_core_tb.rx_path.q_out_a[15:0] -dsp_core_tb.rx_path.i_out_b[15:0] -dsp_core_tb.rx_path.q_out_b[15:0] -@28 -dsp_core_tb.rx_path.gpio_ena[1:0] -@22 -dsp_core_tb.rx_path.sample_out_a[31:0] -dsp_core_tb.rx_path.sample_out_b[31:0] -dsp_core_tb.rx_path.sample[31:0] -@28 -dsp_core_tb.rx_path.strobe_out -dsp_core_tb.rx_path.stb_d1 -dsp_core_tb.rx_path.stb_d2 -dsp_core_tb.rx_path.stb_d3 -dsp_core_tb.rx_path.stb_d4 -dsp_core_tb.rx_path.stb_d5 -@200 -- --FIFO Bus -@22 -dsp_core_tb.master_time[31:0] -dsp_core_tb.wr_dat[31:0] -@28 -dsp_core_tb.wr_done -dsp_core_tb.wr_error -dsp_core_tb.wr_full -dsp_core_tb.wr_ready -dsp_core_tb.wr_write diff --git a/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v b/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v deleted file mode 100644 index d947df40a..000000000 --- a/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v +++ /dev/null @@ -1,233 +0,0 @@ -`timescale 1ns / 100ps - -module dsp_core_tb; - -/////////////////////////////////////////////////////////////////////////////////// -// Sim-wide wires/busses // -/////////////////////////////////////////////////////////////////////////////////// - - // System control bus - reg clk = 0; - reg rst = 1; - - // Configuration bus - reg set_stb = 0; - reg [7:0] set_addr = 0; - reg [31:0] set_data = 0; - - // ADC input bus - wire signed [13:0] adc_a; - wire signed [13:0] adc_b; - wire adc_ovf_a; - wire adc_ovf_b; - - // RX sample bus - reg run = 1; - wire [31:0] sample; - wire stb; - -/////////////////////////////////////////////////////////////////////////////////// -// Simulation control // -/////////////////////////////////////////////////////////////////////////////////// - - // Set up output files - initial begin - $dumpfile("dsp_core_tb.vcd"); - $dumpvars(0,dsp_core_tb); - end - - // Update display every 10 us - always #1000 $monitor("Time in us ",$time/1000); - - // Generate master clock 50% @ 100 MHz - always - #5 clk = ~clk; - -/////////////////////////////////////////////////////////////////////////////////// -// Unit(s) under test // -/////////////////////////////////////////////////////////////////////////////////// - - reg [13:0] amplitude = 13'h1fff; - reg [15:0] impulse_len = 0; - reg [15:0] zero_len = 0; - reg adc_ena = 0; - - initial #500 @(posedge clk) adc_ena = 1; - - impulse adc - (.clk(clk),.rst(rst),.ena(adc_ena), - .dc_offset_a(0),.dc_offset_b(0), - .amplitude(amplitude), - .impulse_len(impulse_len),.zero_len(zero_len), - .adc_a(adc_a),.adc_b(adc_b), - .adc_ovf_a(adc_ovf_a),.adc_ovf_b(adc_ovf_b) ); - - initial rx_path.rx_dcoffset_a.integrator = 0; // so sim doesn't propagate X's - initial rx_path.rx_dcoffset_b.integrator = 0; // generated before reset - dsp_core_rx rx_path - (.clk(clk),.rst(rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a), - .adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .io_rx(16'b0), - .run(adc_ena),.sample(sample),.strobe(stb), - .debug() ); - - reg [31:0] master_time = 0; - always @(posedge clk) - master_time <= master_time + 1; - - reg wr_ready = 1; - reg wr_full = 0; - - wire [31:0] wr_dat; - wire wr_write; - wire wr_done; - wire wr_error; - wire [15:0] fifo_occupied; - wire fifo_full; - wire fifo_empty; - - rx_control rx_buffer - (.clk(clk),.rst(rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .master_time(master_time), - .overrun(), // unconnected output - .wr_dat_o(wr_dat), - .wr_write_o(wr_write), - .wr_done_o(wr_done), - .wr_error_o(wr_error), - .wr_ready_i(wr_ready), - .wr_full_i(wr_full), - .sample(sample), - .run(), // unconnected output, supposed to drive 'run' - .strobe(stb), - .fifo_occupied(fifo_occupied), - .fifo_full(fifo_full), - .fifo_empty(fifo_empty), - .debug_rx() // unconnected output - ); - - - -/////////////////////////////////////////////////////////////////////////////////// -// Simulation output/checking // -/////////////////////////////////////////////////////////////////////////////////// - - integer rx_file; - - initial - rx_file = $fopen("rx.dat", "wb"); - - always @(posedge clk) - begin - // Write RX sample I&Q in format Octave can load - if (stb) - begin - $fwrite(rx_file, sample[31:16]); - $fputc(32, rx_file); - $fwrite(rx_file, sample[15:0]); - $fputc(13, rx_file); - end - end - -/////////////////////////////////////////////////////////////////////////////////// -// Tasks // -/////////////////////////////////////////////////////////////////////////////////// - - task power_on; - begin - @(posedge clk) - rst = #1 1'b1; - @(posedge clk) - rst = #1 1'b0; - end - endtask // power_on - - task set_impulse_len; - input [15:0] len; - @(posedge clk) impulse_len = len-1; - endtask - - task set_zero_len; - input [15:0] len; - @(posedge clk) zero_len = len-1; - endtask - - // Strobe configuration bus with addr, data - task write_cfg_register; - input [7:0] regno; - input [31:0] value; - - begin - @(posedge clk); - set_addr <= regno; - set_data <= value; - set_stb <= 1'b1; - @(posedge clk); - set_stb <= 1'b0; - end - endtask // write_cfg_register - - // Set RX DDC frequency - task set_ddc_freq; - input [31:0] freq; - - write_cfg_register(160, freq); - endtask // set_ddc_freq - - // Set RX IQ scaling registers - task set_rx_scale_iq; - input [15:0] scale_i; - input [15:0] scale_q; - - write_cfg_register(161, {scale_i,scale_q}); - endtask // set_rx_scale_iq - - // Set RX MUX control - task set_rx_muxctrl; - input [3:0] muxctrl; - - write_cfg_register(168, muxctrl); - endtask // set_rx_muxctrl - - // Set RX CIC decim and halfband enables - task set_decim; - input hb1_ena; - input hb2_ena; - input [7:0] decim; - - write_cfg_register(162, {hb1_ena,hb2_ena,decim}); - endtask // set_decim - - -/////////////////////////////////////////////////////////////////////////////////// -// Individual tests // -/////////////////////////////////////////////////////////////////////////////////// - - task test_rx; - begin - set_impulse_len(10); - set_zero_len(990); - set_rx_muxctrl(1); - set_ddc_freq(32'h10000000); - set_rx_scale_iq(1243, 1243); - set_decim(1, 1, 1); - - #100000 $finish; - end - endtask // test_rx - - -/////////////////////////////////////////////////////////////////////////////////// -// Top-level test // -/////////////////////////////////////////////////////////////////////////////////// - - // Execute tests - initial - begin - power_on(); - test_rx(); - end - -endmodule // dsp_core_tb diff --git a/usrp2/top/u2_rev3_2rx_iad/impulse.v b/usrp2/top/u2_rev3_2rx_iad/impulse.v deleted file mode 100644 index fc5e3c1ed..000000000 --- a/usrp2/top/u2_rev3_2rx_iad/impulse.v +++ /dev/null @@ -1,68 +0,0 @@ -module impulse - (input clk, - input rst, - input ena, - - input [13:0] dc_offset_a, - input [13:0] dc_offset_b, - input [13:0] amplitude, - input [15:0] impulse_len, - input [15:0] zero_len, - - output [13:0] adc_a, - output [13:0] adc_b, - output adc_ovf_a, - output adc_ovf_b - ); - - reg [13:0] adc_a_int = 0; - reg [13:0] adc_b_int = 0; - - reg [15:0] count; - - localparam ST_ZERO = 0; - localparam ST_HIGH = 1; - reg state; - - always @(posedge clk) - if (rst | ~ena) - begin - adc_a_int <= 0; - adc_b_int <= 0; - count <= 0; - state <= ST_ZERO; - end - else - case(state) - ST_ZERO: - if (count == zero_len) - begin - adc_a_int <= amplitude; - adc_b_int <= amplitude >> 2; - state <= ST_HIGH; - count <= 0; - end - else - count <= count + 1; - - ST_HIGH: - if (count == impulse_len) - begin - adc_a_int <= 0; - adc_b_int <= 0; - state <= ST_ZERO; - count <= 0; - end - else - count <= count + 1; - - endcase // case (state) - - assign adc_a = adc_a_int + dc_offset_a; - assign adc_b = adc_b_int + dc_offset_b; - - // Ignore for now - assign adc_ovf_a = 0; - assign adc_ovf_b = 0; - -endmodule // impulse diff --git a/usrp2/top/u2_rev3_2rx_iad/u2_core.v b/usrp2/top/u2_rev3_2rx_iad/u2_core.v deleted file mode 100755 index 3d96a4e0e..000000000 --- a/usrp2/top/u2_rev3_2rx_iad/u2_core.v +++ /dev/null @@ -1,789 +0,0 @@ -// //////////////////////////////////////////////////////////////////////////////// -// Module Name: u2_core -// //////////////////////////////////////////////////////////////////////////////// - -module u2_core - #(parameter RAM_SIZE=32768) - (// Clocks - input dsp_clk, - input wb_clk, - output clock_ready, - input clk_to_mac, - input pps_in, - - // Misc, debug - output [7:0] leds, - output [31:0] debug, - output [1:0] debug_clk, - - // Expansion - input exp_pps_in, - output exp_pps_out, - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output [7:0] GMII_TXD, - output GMII_TX_EN, - output GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - output PHY_RESETn, - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output [15:0] ser_t, - output ser_tklsb, - output ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // CPLD interface - output cpld_start, - output cpld_mode, - output cpld_done, - input cpld_din, - input cpld_clk, - input cpld_detached, - output cpld_misc, - input cpld_init_b, - input por, - output config_success, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_on_a, - output adc_oe_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_on_b, - output adc_oe_b, - - // DAC - output [15:0] dac_a, - output [15:0] dac_b, - - // I2C - input scl_pad_i, - output scl_pad_o, - output scl_pad_oen_o, - input sda_pad_i, - output sda_pad_o, - output sda_pad_oen_o, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Generic SPI - output sclk, - output mosi, - input miso, - output sen_clk, - output sen_dac, - output sen_tx_db, - output sen_tx_adc, - output sen_tx_dac, - output sen_rx_db, - output sen_rx_adc, - output sen_rx_dac, - - // GPIO to DBoards - inout [15:0] io_tx, - inout [15:0] io_rx, - - // External RAM - inout [17:0] RAM_D, - output [18:0] RAM_A, - output RAM_CE1n, - output RAM_CENn, - output RAM_CLK, - output RAM_WEn, - output RAM_OEn, - output RAM_LDn, - - // Debug stuff - output uart_tx_o, - input uart_rx_i, - output uart_baud_o, - input sim_mode, - input [3:0] clock_divider - ); - - wire [7:0] set_addr; - wire [31:0] set_data; - wire set_stb; - - wire ram_loader_done; - wire ram_loader_rst, wb_rst, dsp_rst; - - wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; - wire bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int; - - wire [31:0] debug_gpio_0, debug_gpio_1; - wire [31:0] atr_lines; - - wire [31:0] debug_rx, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp; - - wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; - wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; - wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; - - wire serdes_link_up; - wire epoch; - - // /////////////////////////////////////////////////////////////////////////////////////////////// - // Wishbone Single Master INTERCON - localparam dw = 32; // Data bus width - localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space - localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. - - wire [dw-1:0] m0_dat_o, m0_dat_i; - wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, - s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, - s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i, s11_dat_i, s11_dat_o, - s12_dat_i, s12_dat_o, s13_dat_i, s13_dat_o, s14_dat_i, s14_dat_o; - wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr,s12_adr, s13_adr, s14_adr; - wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel,s12_sel, s13_sel, s14_sel; - wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack,s12_ack, s13_ack, s14_ack; - wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb,s12_stb, s13_stb, s14_stb; - wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc,s12_cyc, s13_cyc, s14_cyc; - wire m0_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err,s12_err, s13_err, s14_err; - wire m0_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty, s13_rty, s14_rty; - wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we,s13_we, s14_we; - - wb_1master #(.s0_addr_w(1),.s0_addr(1'b0),.s1_addr_w(2),.s1_addr(2'b10), - .s215_addr_w(6),.s2_addr(6'b1100_00),.s3_addr(6'b1100_01),.s4_addr(6'b1100_10), - .s5_addr(6'b1100_11),.s6_addr(6'b1101_00),.s7_addr(6'b1101_01),.s8_addr(6'b1101_10), - .s9_addr(6'b1101_11),.s10_addr(6'b1110_00),.s11_addr(6'b1110_01),.s12_addr(6'b1110_10), - .s13_addr(6'b1110_11),.s14_addr(6'b1111_00),.s15_addr(6'b1111_01), - .dw(dw),.aw(aw),.sw(sw)) wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty), - .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty), - .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty), - .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty), - .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty), - .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty), - .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty), - .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty), - .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), - .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(s8_err),.s8_rty_i(s8_rty), - .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), - .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(s9_err),.s9_rty_i(s9_rty), - .s10_dat_o(s10_dat_o),.s10_adr_o(s10_adr),.s10_sel_o(s10_sel),.s10_we_o(s10_we),.s10_cyc_o(s10_cyc),.s10_stb_o(s10_stb), - .s10_dat_i(s10_dat_i),.s10_ack_i(s10_ack),.s10_err_i(s10_err),.s10_rty_i(s10_rty), - .s11_dat_o(s11_dat_o),.s11_adr_o(s11_adr),.s11_sel_o(s11_sel),.s11_we_o(s11_we),.s11_cyc_o(s11_cyc),.s11_stb_o(s11_stb), - .s11_dat_i(s11_dat_i),.s11_ack_i(s11_ack),.s11_err_i(s11_err),.s11_rty_i(s11_rty), - .s12_dat_o(s12_dat_o),.s12_adr_o(s12_adr),.s12_sel_o(s12_sel),.s12_we_o(s12_we),.s12_cyc_o(s12_cyc),.s12_stb_o(s12_stb), - .s12_dat_i(s12_dat_i),.s12_ack_i(s12_ack),.s12_err_i(s12_err),.s12_rty_i(s12_rty), - .s13_dat_o(s13_dat_o),.s13_adr_o(s13_adr),.s13_sel_o(s13_sel),.s13_we_o(s13_we),.s13_cyc_o(s13_cyc),.s13_stb_o(s13_stb), - .s13_dat_i(s13_dat_i),.s13_ack_i(s13_ack),.s13_err_i(s13_err),.s13_rty_i(s13_rty), - .s14_dat_o(s14_dat_o),.s14_adr_o(s14_adr),.s14_sel_o(s14_sel),.s14_we_o(s14_we),.s14_cyc_o(s14_cyc),.s14_stb_o(s14_stb), - .s14_dat_i(s14_dat_i),.s14_ack_i(s14_ack),.s14_err_i(s14_err),.s14_rty_i(s14_rty), - .s15_dat_i(0),.s15_ack_i(0),.s15_err_i(0),.s15_rty_i(0) ); - - ////////////////////////////////////////////////////////////////////////////////////////// - // Reset Controller - system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), - .ram_loader_rst_o(ram_loader_rst), - .wb_rst_o(wb_rst), - .ram_loader_done_i(ram_loader_done)); - - assign config_success = ram_loader_done; - reg takeover = 0; - - wire cpld_start_int, cpld_mode_int, cpld_done_int; - - always @(posedge wb_clk) - if(ram_loader_done) - takeover = 1; - assign cpld_misc = ~takeover; - - wire sd_clk, sd_csn, sd_mosi, sd_miso; - - assign sd_miso = cpld_din; - assign cpld_start = takeover ? sd_clk : cpld_start_int; - assign cpld_mode = takeover ? sd_csn : cpld_mode_int; - assign cpld_done = takeover ? sd_mosi : cpld_done_int; - - // /////////////////////////////////////////////////////////////////// - // RAM Loader - - wire [31:0] ram_loader_dat, iwb_dat; - wire [15:0] ram_loader_adr, iwb_adr; - wire [3:0] ram_loader_sel; - wire ram_loader_stb, ram_loader_we, ram_loader_ack; - wire iwb_ack, iwb_stb; - ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) - ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), - // CPLD Interface - .cfg_clk_i(cpld_clk), - .cfg_data_i(cpld_din), - .start_o(cpld_start_int), - .mode_o(cpld_mode_int), - .done_o(cpld_done_int), - .detached_i(cpld_detached), - // Wishbone Interface - .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), - .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), - .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), - .ram_loader_done_o(ram_loader_done)); - - // Processor - aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) - aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), - // Instruction Wishbone bus to I-RAM - .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), - .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), - // Data Wishbone bus to system bus fabric - .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), - .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), - // Interrupts and exceptions - .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - assign bus_error = m0_err | m0_rty; - - // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone - // I-port connects directly to processor and ram loader - - wire flush_icache; - ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) - sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - - .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), - .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), - .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), - .ram_loader_done_i(ram_loader_done), - - .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), - .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), - - .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), - .flush_icache(flush_icache)); - - assign s0_err = 1'b0; - assign s0_rty = 1'b0; - - setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(flush_icache)); - - // Buffer Pool, slave #1 - wire rd0_read, rd0_sop, rd0_error, rd0_done, rd0_eop; - wire rd1_read, rd1_sop, rd1_error, rd1_done, rd1_eop; - wire rd2_read, rd2_sop, rd2_error, rd2_done, rd2_eop; - wire rd3_read, rd3_sop, rd3_error, rd3_done, rd3_eop; - wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; - - wire wr0_write, wr0_done, wr0_error, wr0_ready, wr0_full; - wire wr1_write, wr1_done, wr1_error, wr1_ready, wr1_full; - wire wr2_write, wr2_done, wr2_error, wr2_ready, wr2_full; - wire wr3_write, wr3_done, wr3_error, wr3_ready, wr3_full; - wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - buffer_pool buffer_pool - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), - .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .status(status),.sys_int_o(buffer_int), - - .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), - .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), - - // Write Interfaces - .wr0_dat_i(wr0_dat), .wr0_write_i(wr0_write), .wr0_done_i(wr0_done), - .wr0_error_i(wr0_error), .wr0_ready_o(wr0_ready), .wr0_full_o(wr0_full), - .wr1_dat_i(wr1_dat), .wr1_write_i(wr1_write), .wr1_done_i(wr1_done), - .wr1_error_i(wr1_error), .wr1_ready_o(wr1_ready), .wr1_full_o(wr1_full), - .wr2_dat_i(wr2_dat), .wr2_write_i(wr2_write), .wr2_done_i(wr2_done), - .wr2_error_i(wr2_error), .wr2_ready_o(wr2_ready), .wr2_full_o(wr2_full), - .wr3_dat_i(wr3_dat), .wr3_write_i(wr3_write), .wr3_done_i(wr3_done), - .wr3_error_i(wr3_error), .wr3_ready_o(wr3_ready), .wr3_full_o(wr3_full), - // Read Interfaces - .rd0_dat_o(rd0_dat), .rd0_read_i(rd0_read), .rd0_done_i(rd0_done), - .rd0_error_i(rd0_error), .rd0_sop_o(rd0_sop), .rd0_eop_o(rd0_eop), - .rd1_dat_o(rd1_dat), .rd1_read_i(rd1_read), .rd1_done_i(rd1_done), - .rd1_error_i(rd1_error), .rd1_sop_o(rd1_sop), .rd1_eop_o(rd1_eop), - .rd2_dat_o(rd2_dat), .rd2_read_i(rd2_read), .rd2_done_i(rd2_done), - .rd2_error_i(rd2_error), .rd2_sop_o(rd2_sop), .rd2_eop_o(rd2_eop), - .rd3_dat_o(rd3_dat), .rd3_read_i(rd3_read), .rd3_done_i(rd3_done), - .rd3_error_i(rd3_error), .rd3_sop_o(rd3_sop), .rd3_eop_o(rd3_eop) - ); - - // SPI -- Slave #2 - spi_top shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), - .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), - .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(s2_err),.wb_int_o(spi_int), - .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), - .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); - - assign s2_rty = 1'b0; - - // I2C -- Slave #3 - i2c_master_top #(.ARST_LVL(1)) - i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_dat_i[31:8] = 24'd0; - assign s3_err = 1'b0; - assign s3_rty = 1'b0; - - // GPIOs -- Slave #4 - nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), - .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), - .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( {io_tx,io_rx} ) ); - assign s4_err = 1'b0; - assign s4_rty = 1'b0; - - // Buffer Pool Status -- Slave #5 - wb_readback_mux buff_pool_status - (.wb_clk_i(wb_clk), - .wb_rst_i(wb_rst), - .wb_stb_i(s5_stb), - .wb_adr_i(s5_adr), - .wb_dat_o(s5_dat_i), - .wb_ack_o(s5_ack), - - .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), - .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), - .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0), - .word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0) - ); - - assign s5_err = 1'b0; - assign s5_rty = 1'b0; - - // Slave, #6 Ethernet MAC, see below - - // Settings Bus -- Slave #7 - settings_bus settings_bus - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), - .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), - .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data)); - - assign s7_err = 1'b0; - assign s7_rty = 1'b0; - assign s7_dat_i = 32'd0; - - // Output control lines - wire [7:0] clock_outs, serdes_outs, adc_outs; - assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; - assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; - assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; - - wire phy_reset; - assign PHY_RESETn = ~phy_reset; - - setting_reg #(.my_addr(0)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), - .in(set_data),.out(clock_outs),.changed()); - setting_reg #(.my_addr(1)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(serdes_outs),.changed()); - setting_reg #(.my_addr(2)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(adc_outs),.changed()); - setting_reg #(.my_addr(4)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phy_reset),.changed()); - - // ///////////////////////////////////////////////////////////////////////// - // LEDS - // register 8 determines whether leds are controlled by SW or not - // 1 = controlled by HW, 0 = by SW - // In Rev3 there are only 6 leds, and the highest one is on the ETH connector - - wire [7:0] led_src, led_sw; - wire [7:0] led_hw = {clk_status,serdes_link_up}; - - setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_sw),.changed()); - setting_reg #(.my_addr(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_src),.changed()); - - assign leds = (led_src & led_hw) | (~led_src & led_sw); - - // ///////////////////////////////////////////////////////////////////////// - // Ethernet MAC Slave #6 - - wire Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, Tx_mac_eop; - wire Rx_mac_empty, Rx_mac_rd, Rx_mac_sop, Rx_mac_eop, Rx_mac_err; - wire [31:0] Tx_mac_data, Rx_mac_data; - wire [1:0] Tx_mac_BE, Rx_mac_BE; - wire rst_mac; - - oneshot_2clk mac_rst_1shot (.clk_in(wb_clk),.in(wb_rst),.clk_out(clk_to_mac),.out(rst_mac)); - - MAC_top #(.TX_FF_DEPTH(9), .RX_FF_DEPTH(11)) - MAC_top - (.Clk_125M(clk_to_mac),.Clk_user(dsp_clk), - .rst_mac(rst_mac),.rst_user(dsp_rst), - .RST_I(wb_rst),.CLK_I(wb_clk),.STB_I(s6_stb),.CYC_I(s6_cyc),.ADR_I(s6_adr[8:2]), - .WE_I(s6_we),.DAT_I(s6_dat_o),.DAT_O(s6_dat_i),.ACK_O(s6_ack), - .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),.Rx_mac_BE(Rx_mac_BE), - .Rx_mac_sop(Rx_mac_sop),.Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err), - .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data), - .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop), - .Gtx_clk(GMII_GTX_CLK),.Tx_clk(GMII_TX_CLK),.Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD), - .Rx_clk(GMII_RX_CLK),.Rx_er(GMII_RX_ER),.Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD), - .Crs(GMII_CRS),.Col(GMII_COL), - .Mdio(MDIO),.Mdc(MDC), - .rx_fifo_occupied(eth_rx_occ2),.rx_fifo_full(eth_rx_full2),.rx_fifo_empty(eth_rx_empty2), - .tx_fifo_occupied(),.tx_fifo_full(),.tx_fifo_empty(), - .debug0(debug_mac0),.debug1(debug_mac1) ); - - assign s6_err = 1'b0; - assign s6_rty = 1'b0; - - mac_rxfifo_int mac_rxfifo_int - (.clk(dsp_clk),.rst(dsp_rst), - .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data), - .Rx_mac_BE(Rx_mac_BE),.Rx_mac_sop(Rx_mac_sop), - .Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err), - .wr_dat_o(wr2_dat),.wr_write_o(wr2_write),.wr_done_o(wr2_done), - .wr_error_o(wr2_error),.wr_ready_i(wr2_ready),.wr_full_i(wr2_full), - .fifo_occupied(eth_rx_occ),.fifo_full(eth_rx_full),.fifo_empty(eth_rx_empty) ); - - mac_txfifo_int mac_txfifo_int - (.clk(dsp_clk),.rst(dsp_rst),.mac_clk(clk_to_mac), - .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data), - .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop), - .rd_dat_i(rd2_dat),.rd_read_o(rd2_read),.rd_done_o(rd2_done), - .rd_error_o(rd2_error),.rd_sop_i(rd2_sop),.rd_eop_i(rd2_eop), - .fifo_occupied(eth_tx_occ),.fifo_full(eth_tx_full),.fifo_empty(eth_tx_empty) ); - - // ///////////////////////////////////////////////////////////////////////// - // Interrupt Controller, Slave #8 - - wire [15:0] irq={{4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, - {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}}; - - simple_pic #(.is(16),.dwidth(32)) simple_pic - (.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]), - .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), - .irq(irq) ); - assign s8_err = 0; - assign s8_rty = 0; - - // ///////////////////////////////////////////////////////////////////////// - // Master Timer, Slave #9 - - wire [31:0] master_time; - timer timer - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), - .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), - .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); - assign s9_err = 0; - assign s9_rty = 0; - - // ///////////////////////////////////////////////////////////////////////// - // UART, Slave #10 - - simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries - (.clk_i(wb_clk),.rst_i(wb_rst), - .we_i(s10_we),.stb_i(s10_stb),.cyc_i(s10_cyc),.ack_o(s10_ack), - .adr_i(s10_adr[4:2]),.dat_i(s10_dat_o),.dat_o(s10_dat_i), - .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), - .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); - - assign s10_err = 0; - assign s10_rty = 0; - - // ///////////////////////////////////////////////////////////////////////// - // ATR Controller, Slave #11 - - wire run_rx, run_tx; - reg run_rx_d1; - always @(posedge dsp_clk) - run_rx_d1 <= run_rx; - - atr_controller atr_controller - (.clk_i(wb_clk),.rst_i(wb_rst), - .adr_i(s11_adr[5:0]),.sel_i(s11_sel),.dat_i(s11_dat_o),.dat_o(s11_dat_i), - .we_i(s11_we),.stb_i(s11_stb),.cyc_i(s11_cyc),.ack_o(s11_ack), - .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); - assign s11_err = 0; - assign s11_rty = 0; - - // ////////////////////////////////////////////////////////////////////////// - // Time Sync, Slave #12 - - reg pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1; - always @(negedge dsp_clk) pps_negedge <= pps_in; - always @(posedge dsp_clk) pps_posedge <= pps_in; - always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge; - always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge; - - wire pps_o; - time_sync time_sync - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s12_cyc),.stb_i(s12_stb),.adr_i(s12_adr[4:2]), - .we_i(s12_we),.dat_i(s12_dat_o),.dat_o(s12_dat_i),.ack_o(s12_ack), - .sys_clk_i(dsp_clk),.master_time_o(master_time), - .pps_posedge(pps_posedge),.pps_negedge(pps_negedge), - .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out), - .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) ); - assign s12_err = 0; - assign s12_rty = 0; - - // ///////////////////////////////////////////////////////////////////////// - // SD Card Reader / Writer, Slave #13 - - sd_spi_wb sd_spi_wb - (.clk(wb_clk),.rst(wb_rst), - .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), - .wb_cyc_i(s13_cyc),.wb_stb_i(s13_stb),.wb_we_i(s13_we), - .wb_adr_i(s13_adr[3:2]),.wb_dat_i(s13_dat_o),.wb_dat_o(s13_dat_i), - .wb_ack_o(s13_ack) ); - assign s13_err = 0; - assign s13_rty = 0; - // ///////////////////////////////////////////////////////////////////////// - // DSP - wire [31:0] sample_rx, sample_tx; - wire strobe_rx, strobe_tx; - - rx_control #(.FIFOSIZE(10)) rx_control - (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .master_time(master_time),.overrun(overrun), - .wr_dat_o(wr1_dat), .wr_write_o(wr1_write), .wr_done_o(wr1_done), .wr_error_o(wr1_error), - .wr_ready_i(wr1_ready), .wr_full_i(wr1_full), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty), - .debug_rx(debug_rx) ); - - // dummy_rx dsp_core_rx - dsp_core_rx dsp_core_rx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .io_rx(io_rx),.sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), - .debug(debug_rx_dsp) ); - - tx_control #(.FIFOSIZE(10)) tx_control - (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .master_time(master_time),.underrun(underrun), - .rd_dat_i(rd1_dat), .rd_sop_i(rd1_sop), .rd_eop_i(rd1_eop), - .rd_read_o(rd1_read), .rd_done_o(rd1_done), .rd_error_o(rd1_error), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty), - .debug(debug_txc) ); - - dsp_core_tx dsp_core_tx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .dac_a(dac_a),.dac_b(dac_b), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_tx_dsp) ); - - assign dsp_rst = wb_rst; - - // /////////////////////////////////////////////////////////////////////////////////// - // SERDES - - serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes - (.clk(dsp_clk),.rst(dsp_rst), - .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .rd_dat_i(rd0_dat),.rd_read_o(rd0_read),.rd_done_o(rd0_done),.rd_error_o(rd0_error), - .rd_sop_i(rd0_sop),.rd_eop_i(rd0_eop), - .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .wr_dat_o(wr0_dat),.wr_write_o(wr0_write),.wr_done_o(wr0_done),.wr_error_o(wr0_error), - .wr_ready_i(wr0_ready),.wr_full_i(wr0_full), - .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), - .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), - .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); - -`ifdef EXTRAM - // /////////////////////////////////////////////////////////////////////////////////// - // External RAM Interface - - localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes - - wire [15:0] bus2ram, ram2bus; - wire [15:0] bridge_adr; - wire [1:0] bridge_sel; - wire bridge_stb, bridge_cyc, bridge_we, bridge_ack; - - wire [19:0] page; - wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]}; - setting_reg #(.my_addr(6)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(page),.changed()); - - wb_bridge_16_32 bridge - (.wb_clk(wb_clk),.wb_rst(wb_rst), - .A_cyc_i(s14_cyc),.A_stb_i(s14_stb),.A_we_i(s14_we),.A_sel_i(s14_sel), - .A_adr_i(s14_adr),.A_dat_i(s14_dat_o),.A_dat_o(s14_dat_i),.A_ack_o(s14_ack), - .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel), - .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack)); - - wb_zbt16_b wb_zbt16_b - (.clk(wb_clk),.rst(wb_rst), - .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel), - .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we), - .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn), - .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn), - .sram_mode(),.sram_zz() ); - - assign s14_err = 0; assign s14_rty = 0; - assign RAM_CE1n = 0; - assign RAM_D[17:16] = 2'bzz; -`endif - -`ifdef DEBUG - // ///////////////////////////////////////////////////////////////////////////////////////// - // Debug Pins - - // FIFO Level Debugging - reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo; - - always @(posedge dsp_clk) - serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]}, - {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} }; - - assign debug_clk[0] = 0; - assign debug_clk[1] = dsp_clk; - - assign debug = host_to_dsp_fifo; // debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; - assign debug_gpio_0 = eth_mac_debug; - assign debug_gpio_1 = 0; -`endif - -endmodule // u2_core - -// wire debug_mux; -// setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), -// .in(set_data),.out(debug_mux),.changed()); - -//assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; -//assign debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo; - -//assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a}, -// {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}}; - -//assign debug = debug_tx_dsp; -//assign debug = debug_serdes0; - -//assign debug_gpio_0 = 0; //debug_serdes0; -//assign debug_gpio_1 = 0; //debug_serdes1; - -// assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success}, -// {8'b0}, -// {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done }, -// {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} }; - -//assign debug = {dac_a,dac_b}; - -/* - assign debug = {{ram_loader_done, takeover, 6'd0}, - {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi}, - {8'd0}, - {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */ - -/*assign debug = host_to_dsp_fifo; - assign debug_gpio_0 = eth_mac_debug; - assign debug_gpio_1 = 0; - */ -// Assign various commonly used debug buses. -/* - wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV, - irq[7:0], - GMII_RXD, - GMII_TXD}; - - wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] }; - - wire [31:0] debug_time = {uart_tx_o, 7'b0, - irq[7:0], - 6'b0, GMII_RX_DV, GMII_TX_EN, - 4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int}; - - wire [31:0] debug_irq = {uart_tx_o, iwb_adr, iwb_ack, - irq[7:0], - proc_int, 7'b0 }; - - wire [31:0] debug_eth = - {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write}, - {8'd0}, - {8'd0}, - {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} }; - - assign debug_serdes0 = { { rd0_dat[7:0] }, - { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done }, - { ser_t[15:8] }, - { ser_t[7:0] } }; - - assign debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write}, - { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en }, - { ser_r[15:8] }, - { ser_r[7:0] } }; - - assign debug_gpio_1 = {uart_tx_o,7'd0, - 3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error, - debug_txc[15:0]}; - assign debug_gpio_1 = debug_rx; - assign debug_gpio_1 = debug_serdes1; - assign debug_gpio_1 = debug_eth; - - */ - diff --git a/usrp2/top/u2_rev3_2rx_iad/wave.sh b/usrp2/top/u2_rev3_2rx_iad/wave.sh deleted file mode 100755 index 626f224e5..000000000 --- a/usrp2/top/u2_rev3_2rx_iad/wave.sh +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/sh - -gtkwave dsp_core_tb.vcd dsp_core_tb.sav & diff --git a/usrp2/top/u2_rev3_iad/.gitignore b/usrp2/top/u2_rev3_iad/.gitignore deleted file mode 100644 index e4daaf1ea..000000000 --- a/usrp2/top/u2_rev3_iad/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -/build -/*.vcd -/dsp_core_tb -/*.dat diff --git a/usrp2/top/u2_rev3_iad/Makefile b/usrp2/top/u2_rev3_iad/Makefile deleted file mode 100644 index 15df9e43e..000000000 --- a/usrp2/top/u2_rev3_iad/Makefile +++ /dev/null @@ -1,253 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -################################################## -# xtclsh Shell and tcl Script Path -################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl - -################################################## -# Project Setup -################################################## -BUILD_DIR := build/ -export TOP_MODULE := u2_rev3 -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family Spartan3 \ -device xc3s2000 \ -package fg456 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ -control_lib/bin2gray.v \ -control_lib/buffer_int.v \ -control_lib/buffer_pool.v \ -control_lib/cascadefifo2.v \ -control_lib/dcache.v \ -control_lib/decoder_3_8.v \ -control_lib/dpram32.v \ -control_lib/fifo_2clock.v \ -control_lib/fifo_2clock_casc.v \ -control_lib/gray2bin.v \ -control_lib/gray_send.v \ -control_lib/icache.v \ -control_lib/longfifo.v \ -control_lib/mux4.v \ -control_lib/mux8.v \ -control_lib/nsgpio.v \ -control_lib/ram_2port.v \ -control_lib/ram_harv_cache.v \ -control_lib/ram_loader.v \ -control_lib/setting_reg.v \ -control_lib/settings_bus.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ -control_lib/srl.v \ -control_lib/system_control.v \ -control_lib/wb_1master.v \ -control_lib/wb_readback_mux.v \ -control_lib/simple_uart.v \ -control_lib/simple_uart_tx.v \ -control_lib/simple_uart_rx.v \ -control_lib/oneshot_2clk.v \ -control_lib/sd_spi.v \ -control_lib/sd_spi_wb.v \ -control_lib/wb_bridge_16_32.v \ -coregen/fifo_xlnx_2Kx36_2clk.v \ -coregen/fifo_xlnx_2Kx36_2clk.xco \ -coregen/fifo_xlnx_512x36_2clk.v \ -coregen/fifo_xlnx_512x36_2clk.xco \ -eth/mac_rxfifo_int.v \ -eth/mac_txfifo_int.v \ -eth/rtl/verilog/Clk_ctrl.v \ -eth/rtl/verilog/MAC_rx.v \ -eth/rtl/verilog/MAC_rx/Broadcast_filter.v \ -eth/rtl/verilog/MAC_rx/CRC_chk.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \ -eth/rtl/verilog/MAC_top.v \ -eth/rtl/verilog/MAC_tx.v \ -eth/rtl/verilog/MAC_tx/CRC_gen.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \ -eth/rtl/verilog/MAC_tx/Random_gen.v \ -eth/rtl/verilog/Phy_int.v \ -eth/rtl/verilog/RMON.v \ -eth/rtl/verilog/RMON/RMON_addr_gen.v \ -eth/rtl/verilog/RMON/RMON_ctrl.v \ -eth/rtl/verilog/Reg_int.v \ -eth/rtl/verilog/eth_miim.v \ -eth/rtl/verilog/flow_ctrl_rx.v \ -eth/rtl/verilog/flow_ctrl_tx.v \ -eth/rtl/verilog/miim/eth_clockgen.v \ -eth/rtl/verilog/miim/eth_outputcontrol.v \ -eth/rtl/verilog/miim/eth_shiftreg.v \ -opencores/8b10b/decode_8b10b.v \ -opencores/8b10b/encode_8b10b.v \ -opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -opencores/aemb/rtl/verilog/aeMB_core_BE.v \ -opencores/aemb/rtl/verilog/aeMB_ctrl.v \ -opencores/aemb/rtl/verilog/aeMB_edk32.v \ -opencores/aemb/rtl/verilog/aeMB_ibuf.v \ -opencores/aemb/rtl/verilog/aeMB_regf.v \ -opencores/aemb/rtl/verilog/aeMB_xecu.v \ -opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_defines.v \ -opencores/i2c/rtl/verilog/i2c_master_top.v \ -opencores/i2c/rtl/verilog/timescale.v \ -opencores/simple_pic/rtl/simple_pic.v \ -opencores/spi/rtl/verilog/spi_clgen.v \ -opencores/spi/rtl/verilog/spi_defines.v \ -opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ -sdr_lib/acc.v \ -sdr_lib/add2.v \ -sdr_lib/add2_and_round.v \ -sdr_lib/add2_and_round_reg.v \ -sdr_lib/add2_reg.v \ -sdr_lib/cic_dec_shifter.v \ -sdr_lib/cic_decim.v \ -sdr_lib/cic_int_shifter.v \ -sdr_lib/cic_interp.v \ -sdr_lib/cic_strober.v \ -sdr_lib/clip.v \ -sdr_lib/clip_reg.v \ -sdr_lib/cordic.v \ -sdr_lib/cordic_z24.v \ -sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_tx.v \ -sdr_lib/hb_dec.v \ -sdr_lib/hb_interp.v \ -sdr_lib/integrate.v \ -sdr_lib/round.v \ -sdr_lib/round_reg.v \ -sdr_lib/rx_control.v \ -sdr_lib/rx_dcoffset.v \ -sdr_lib/sign_extend.v \ -sdr_lib/small_hb_dec.v \ -sdr_lib/small_hb_int.v \ -sdr_lib/tx_control.v \ -serdes/serdes.v \ -serdes/serdes_fc_rx.v \ -serdes/serdes_fc_tx.v \ -serdes/serdes_rx.v \ -serdes/serdes_tx.v \ -timing/time_receiver.v \ -timing/time_sender.v \ -timing/time_sync.v \ -timing/timer.v \ -top/u2_core/u2_core.v \ -top/u2_rev3/u2_rev3.ucf \ -top/u2_rev3/u2_rev3.v \ -top/u2_rev3_iad/dsp_core_rx.v - -################################################## -# Process Properties -################################################## -export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -export TRANSLATE_PROPERTIES := \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -export MAP_PROPERTIES := \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -export PLACE_ROUTE_PROPERTIES := \ -"Place & Route Effort Level (Overall)" High - -export STATIC_TIMING_PROPERTIES := \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -export GEN_PROG_FILE_PROPERTIES := \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, testbench, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -testbench: - iverilog -c cmdfile -o dsp_core_tb dsp_core_tb.v - -clean: - rm -rf $(BUILD_DIR) - rm -f dsp_core_tb - rm -f *.lx2 - rm -f *.dat - rm -f *.vcd diff --git a/usrp2/top/u2_rev3_iad/cmdfile b/usrp2/top/u2_rev3_iad/cmdfile deleted file mode 100644 index 34373a676..000000000 --- a/usrp2/top/u2_rev3_iad/cmdfile +++ /dev/null @@ -1,4 +0,0 @@ --y . --y ../../sdr_lib --y ../../control_lib --y ../../models diff --git a/usrp2/top/u2_rev3_iad/dsp_core_rx.v b/usrp2/top/u2_rev3_iad/dsp_core_rx.v deleted file mode 100644 index 2882464ba..000000000 --- a/usrp2/top/u2_rev3_iad/dsp_core_rx.v +++ /dev/null @@ -1,158 +0,0 @@ -`define DSP_CORE_RX_BASE 160 -module dsp_core_rx - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - input [13:0] adc_a, input adc_ovf_a, - input [13:0] adc_b, input adc_ovf_b, - - input [15:0] io_rx, - - output [31:0] sample, - input run, - output strobe, - output [31:0] debug - ); - - wire [15:0] scale_i, scale_q; - wire [13:0] adc_a_ofs, adc_b_ofs; - reg [13:0] adc_i, adc_q; - wire [31:0] phase_inc; - reg [31:0] phase; - - wire [35:0] prod_i, prod_q; - wire [23:0] i_cordic, q_cordic; - wire [31:0] i_iad, q_iad; - wire [15:0] i_out, q_out; - - wire enable_hb1, enable_hb2; // Correspond to std firmware settings - wire [7:0] cic_decim; // for combined CIC/HB decimator - wire [9:0] decim_rate; // Reconstructed original decimation setting - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phase_inc),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({scale_i,scale_q}),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({enable_hb1,enable_hb2,cic_decim}),.changed()); - - rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_in(adc_a),.adc_out(adc_a_ofs)); - - rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_in(adc_b),.adc_out(adc_b_ofs)); - - wire [3:0] muxctrl; - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(muxctrl),.changed()); - - wire [1:0] gpio_ena; - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(gpio_ena),.changed()); - - // The TVRX connects to what is called adc_b, thus A and B are - // swapped throughout the design. - // - // In the interest of expediency and keeping the s/w sane, we just remap them here. - // The I & Q fields are mapped the same: - // 0 -> "the real A" (as determined by the TVRX) - // 1 -> "the real B" - // 2 -> const zero - - always @(posedge clk) - case(muxctrl[1:0]) // The I mapping - 0: adc_i <= adc_b_ofs; // "the real A" - 1: adc_i <= adc_a_ofs; - 2: adc_i <= 0; - default: adc_i <= 0; - endcase // case(muxctrl[1:0]) - - always @(posedge clk) - case(muxctrl[3:2]) // The Q mapping - 0: adc_q <= adc_b_ofs; // "the real A" - 1: adc_q <= adc_a_ofs; - 2: adc_q <= 0; - default: adc_q <= 0; - endcase // case(muxctrl[3:2]) - - always @(posedge clk) - if(rst) - phase <= 0; - else if(~run) - phase <= 0; - else - phase <= phase + phase_inc; - - MULT18X18S mult_i - (.P(prod_i), // 36-bit multiplier output - .A({{4{adc_i[13]}},adc_i} ), // 18-bit multiplier input - .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - MULT18X18S mult_q - (.P(prod_q), // 36-bit multiplier output - .A({{4{adc_q[13]}},adc_q} ), // 18-bit multiplier input - .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - - cordic_z24 #(.bitwidth(24)) - cordic(.clock(clk), .reset(rst), .enable(run), - .xi(prod_i[24:1]),. yi(prod_q[24:1]), .zi(phase[31:8]), - .xo(i_cordic),.yo(q_cordic),.zo() ); - - // Reconstruct original decimation rate from standard firmware settings - assign decim_rate = enable_hb2 ? (enable_hb1 ? {cic_decim,2'b0} : - {1'b0,cic_decim,1'b0 }) : - cic_decim; - - cic_strober #(.WIDTH(10)) // Convenient reuse of strobe generator - cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate), - .strobe_fast(1),.strobe_slow(strobe_iad) ); - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(i_cordic), - .stb_o(strobe),.integ_o(i_iad) ); - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(q_cordic), - .stb_o(),.integ_o(q_iad) ); - - round #(.bits_in(32),.bits_out(16)) round_iout (.in(i_iad),.out(i_out)); - round #(.bits_in(32),.bits_out(16)) round_qout (.in(q_iad),.out(q_out)); - - // Streaming GPIO - // - // io_rx[15] => I channel LSB if gpio_ena[0] high - // io_rx[14] => Q channel LSB if gpio_ena[1] high - - reg [31:0] sample_reg; - always @(posedge clk) - begin - sample_reg[31:17] <= i_out[15:1]; - sample_reg[15:1] <= q_out[15:1]; - sample_reg[16] <= gpio_ena[0] ? io_rx[15] : i_out[0]; - sample_reg[0] <= gpio_ena[1] ? io_rx[14] : q_out[0]; - end - - assign sample = sample_reg; - assign debug = {clk, rst, run, strobe}; - -endmodule // dsp_core_rx diff --git a/usrp2/top/u2_rev3_iad/dsp_core_tb.sav b/usrp2/top/u2_rev3_iad/dsp_core_tb.sav deleted file mode 100644 index 17c90cdd7..000000000 --- a/usrp2/top/u2_rev3_iad/dsp_core_tb.sav +++ /dev/null @@ -1,61 +0,0 @@ -[size] 1680 975 -[pos] -1 -1 -*-24.007835 13660000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] dsp_core_tb. -@200 --SYSCON -@28 -dsp_core_tb.clk -dsp_core_tb.rst -dsp_core_tb.run -@200 -- --Settings Bus -@22 -dsp_core_tb.set_addr[7:0] -@24 -dsp_core_tb.set_data[31:0] -@28 -dsp_core_tb.set_stb -@200 -- --RX DSP CORE -- -@24 -dsp_core_tb.rx_path.decim_rate[9:0] -@200 -- -@8420 -dsp_core_tb.adc_a[13:0] -@20000 -- -@200 -- -@8420 -dsp_core_tb.rx_path.adc_a_ofs[13:0] -@20000 -- -@200 -- -@8022 -dsp_core_tb.rx_path.i_cordic[23:0] -@20000 -- -@200 -- -@8022 -dsp_core_tb.rx_path.i_iad[31:0] -@20000 -- -@200 -- -@8420 -dsp_core_tb.rx_path.i_out[15:0] -@20000 -- -@200 -- -@28 -dsp_core_tb.stb -@200 -- diff --git a/usrp2/top/u2_rev3_iad/dsp_core_tb.v b/usrp2/top/u2_rev3_iad/dsp_core_tb.v deleted file mode 100644 index 4d5a5b537..000000000 --- a/usrp2/top/u2_rev3_iad/dsp_core_tb.v +++ /dev/null @@ -1,196 +0,0 @@ -`timescale 1ns / 100ps - -module dsp_core_tb; - -/////////////////////////////////////////////////////////////////////////////////// -// Sim-wide wires/busses // -/////////////////////////////////////////////////////////////////////////////////// - - // System control bus - reg clk = 0; - reg rst = 1; - - // Configuration bus - reg set_stb = 0; - reg [7:0] set_addr = 0; - reg [31:0] set_data = 0; - - // ADC input bus - wire signed [13:0] adc_a; - wire signed [13:0] adc_b; - wire adc_ovf_a; - wire adc_ovf_b; - - // RX sample bus - reg run = 1; - wire [31:0] sample; - wire stb; - -/////////////////////////////////////////////////////////////////////////////////// -// Simulation control // -/////////////////////////////////////////////////////////////////////////////////// - - // Set up output files - initial begin - $dumpfile("dsp_core_tb.vcd"); - $dumpvars(0,dsp_core_tb); - end - - // Update display every 10 us - always #1000 $monitor("Time in us ",$time/1000); - - // Generate master clock 50% @ 100 MHz - always - #5 clk = ~clk; - -/////////////////////////////////////////////////////////////////////////////////// -// Unit(s) under test // -/////////////////////////////////////////////////////////////////////////////////// - - reg [13:0] amplitude = 13'h1fff; - reg [15:0] impulse_len = 0; - reg [15:0] zero_len = 0; - reg adc_ena = 0; - - initial #500 @(posedge clk) adc_ena = 1; - - impulse adc - (.clk(clk),.rst(rst),.ena(adc_ena), - .dc_offset_a(0),.dc_offset_b(0), - .amplitude(amplitude), - .impulse_len(impulse_len),.zero_len(zero_len), - .adc_a(adc_a),.adc_b(adc_b), - .adc_ovf_a(adc_ovf_a),.adc_ovf_b(adc_ovf_b) ); - - initial rx_path.rx_dcoffset_a.integrator = 0; // so sim doesn't propagate X's - initial rx_path.rx_dcoffset_b.integrator = 0; // generated before reset - dsp_core_rx rx_path - (.clk(clk),.rst(rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a), - .adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .io_rx(16'b0), - .run(adc_ena),.sample(sample),.strobe(stb), - .debug() ); - -/////////////////////////////////////////////////////////////////////////////////// -// Simulation output/checking // -/////////////////////////////////////////////////////////////////////////////////// - - integer rx_file; - - initial - rx_file = $fopen("rx.dat", "wb"); - - always @(posedge clk) - begin - // Write RX sample I&Q in format Octave can load - if (stb) - begin - $fwrite(rx_file, sample[31:16]); - $fputc(32, rx_file); - $fwrite(rx_file, sample[15:0]); - $fputc(13, rx_file); - end - end - -/////////////////////////////////////////////////////////////////////////////////// -// Tasks // -/////////////////////////////////////////////////////////////////////////////////// - - task power_on; - begin - @(posedge clk) - rst = #1 1'b1; - @(posedge clk) - rst = #1 1'b0; - end - endtask // power_on - - task set_impulse_len; - input [15:0] len; - @(posedge clk) impulse_len = len-1; - endtask - - task set_zero_len; - input [15:0] len; - @(posedge clk) zero_len = len-1; - endtask - - // Strobe configuration bus with addr, data - task write_cfg_register; - input [7:0] regno; - input [31:0] value; - - begin - @(posedge clk); - set_addr <= regno; - set_data <= value; - set_stb <= 1'b1; - @(posedge clk); - set_stb <= 1'b0; - end - endtask // write_cfg_register - - // Set RX DDC frequency - task set_ddc_freq; - input [31:0] freq; - - write_cfg_register(160, freq); - endtask // set_ddc_freq - - // Set RX IQ scaling registers - task set_rx_scale_iq; - input [15:0] scale_i; - input [15:0] scale_q; - - write_cfg_register(161, {scale_i,scale_q}); - endtask // set_rx_scale_iq - - // Set RX MUX control - task set_rx_muxctrl; - input [3:0] muxctrl; - - write_cfg_register(168, muxctrl); - endtask // set_rx_muxctrl - - // Set RX CIC decim and halfband enables - task set_decim; - input hb1_ena; - input hb2_ena; - input [7:0] decim; - - write_cfg_register(162, {hb1_ena,hb2_ena,decim}); - endtask // set_decim - - -/////////////////////////////////////////////////////////////////////////////////// -// Individual tests // -/////////////////////////////////////////////////////////////////////////////////// - - task test_rx; - begin - set_impulse_len(1); - set_zero_len(999); - set_rx_muxctrl(1); - set_ddc_freq(0); - set_rx_scale_iq(1243, 1243); - set_decim(0, 1, 3); - - #100000 $finish; - end - endtask // test_rx - - -/////////////////////////////////////////////////////////////////////////////////// -// Top-level test // -/////////////////////////////////////////////////////////////////////////////////// - - // Execute tests - initial - begin - power_on(); - test_rx(); - end - -endmodule // dsp_core_tb diff --git a/usrp2/top/u2_rev3_iad/impulse.v b/usrp2/top/u2_rev3_iad/impulse.v deleted file mode 100644 index 7f0cdc9be..000000000 --- a/usrp2/top/u2_rev3_iad/impulse.v +++ /dev/null @@ -1,63 +0,0 @@ -module impulse - (input clk, - input rst, - input ena, - - input [13:0] dc_offset_a, - input [13:0] dc_offset_b, - input [13:0] amplitude, - input [15:0] impulse_len, - input [15:0] zero_len, - - output [13:0] adc_a, - output [13:0] adc_b, - output adc_ovf_a, - output adc_ovf_b - ); - - reg [13:0] adc_a_int = 0; - reg [15:0] count; - - localparam ST_ZERO = 0; - localparam ST_HIGH = 1; - reg state; - - always @(posedge clk) - if (rst | ~ena) - begin - adc_a_int <= 0; - count <= 0; - state <= ST_ZERO; - end - else - case(state) - ST_ZERO: - if (count == zero_len) - begin - adc_a_int <= amplitude; - state <= ST_HIGH; - count <= 0; - end - else - count <= count + 1; - - ST_HIGH: - if (count == impulse_len) - begin - adc_a_int <= 0; - state <= ST_ZERO; - count <= 0; - end - else - count <= count + 1; - - endcase // case (state) - - assign adc_a = adc_a_int + dc_offset_a; - - // Ignore for now - assign adc_b = dc_offset_b; - assign adc_ovf_a = 0; - assign adc_ovf_b = 0; - -endmodule // impulse diff --git a/usrp2/top/u2_rev3_iad/wave.sh b/usrp2/top/u2_rev3_iad/wave.sh deleted file mode 100755 index 626f224e5..000000000 --- a/usrp2/top/u2_rev3_iad/wave.sh +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/sh - -gtkwave dsp_core_tb.vcd dsp_core_tb.sav & -- cgit v1.2.3 From 6d0fa9acb1aa9cf98ccd2cce2985eab560924b17 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 7 Jun 2011 16:23:48 -0700 Subject: removed bit-rotted test harness --- usrp2/top/eth_test/.gitignore | 43 ---- usrp2/top/eth_test/eth_sim_top.v | 437 --------------------------------------- usrp2/top/eth_test/eth_tb.v | 257 ----------------------- 3 files changed, 737 deletions(-) delete mode 100644 usrp2/top/eth_test/.gitignore delete mode 100644 usrp2/top/eth_test/eth_sim_top.v delete mode 100644 usrp2/top/eth_test/eth_tb.v diff --git a/usrp2/top/eth_test/.gitignore b/usrp2/top/eth_test/.gitignore deleted file mode 100644 index b30397081..000000000 --- a/usrp2/top/eth_test/.gitignore +++ /dev/null @@ -1,43 +0,0 @@ -/xst -/_ngo -/_xmsgs -/*.stx -/*.tspec -/*.xml -/*.gyd -/*.ngr -/*.tim -/*.err -/*.lso -/*.bld -/*.cmd_log -/*.ise_ISE_Backup -/*.mfd -/*.vm6 -/*.syr -/*.xst -/*.csv -/*.html -/*.jed -/*.pad -/*.ng* -/*.pnx -/*.rpt -/*.prj -/*_html -/*_log -/*.lfp -/*.bit -/*.bin -/*.vcd -/*.unroutes -/*.drc -/*_map.* -/*_guide.* -/*.twr -/*.twx -/a.out -/*.xpi -/*_pad.txt -/*.bgn -/*.par diff --git a/usrp2/top/eth_test/eth_sim_top.v b/usrp2/top/eth_test/eth_sim_top.v deleted file mode 100644 index 640a4e60f..000000000 --- a/usrp2/top/eth_test/eth_sim_top.v +++ /dev/null @@ -1,437 +0,0 @@ -////////////////////////////////////////////////////////////////////////////////// -// Module Name: u2_basic -////////////////////////////////////////////////////////////////////////////////// - -module eth_sim_top - (// Clocks - input dsp_clk, - input wb_clk, - output clock_ready, - input clk_to_mac, - input pps_in, - - // Misc, debug - output led1, - output led2, - output [31:0] debug, - output [1:0] debug_clk, - - // Expansion - input exp_pps_in, - output exp_pps_out, - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output [7:0] GMII_TXD, - output GMII_TX_EN, - output GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - input PHY_RESETn, - input PHY_CLK, // possibly use on-board osc - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output [15:0] ser_t, - output ser_tklsb, - output ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // CPLD interface - output cpld_start, - output cpld_mode, - output cpld_done, - input cpld_din, - input cpld_clk, - input cpld_detached, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_oen_a, - output adc_pdn_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_oen_b, - output adc_pdn_b, - - // DAC - output [15:0] dac_a, - output [15:0] dac_b, - - // I2C - input scl_pad_i, - output scl_pad_o, - output scl_pad_oen_o, - input sda_pad_i, - output sda_pad_o, - output sda_pad_oen_o, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Generic SPI - output sclk, - output mosi, - input miso, - output sen_clk, - output sen_dac, - output sen_tx_db, - output sen_tx_adc, - output sen_tx_dac, - output sen_rx_db, - output sen_rx_adc, - output sen_rx_dac, - - // GPIO to DBoards - inout [15:0] io_tx, - inout [15:0] io_rx - ); - - wire [7:0] set_addr; - wire [31:0] set_data; - wire set_stb; - - wire ram_loader_done; - wire ram_loader_rst, wb_rst, dsp_rst; - - wire [31:0] ser_debug; - - ////////////////////////////////////////////////////////////////////////////////////////////////// - // Wishbone Single Master INTERCON - parameter dw = 32; // Data bus width - parameter aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space - parameter sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. - - wire [dw-1:0] m0_dat_o, m1_dat_o, m0_dat_i, m1_dat_i; - wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, - s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i; - wire [aw-1:0] m0_adr, m1_adr, s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr; - wire [sw-1:0] m0_sel, m1_sel, s0_sel, s1_sel, s2_sel, s3_sel, s4_sel, s5_sel, s6_sel, s7_sel; - wire m0_ack, m1_ack, s0_ack, s1_ack, s2_ack, s3_ack, s4_ack, s5_ack, s6_ack, s7_ack; - wire m0_stb, m1_stb, s0_stb, s1_stb, s2_stb, s3_stb, s4_stb, s5_stb, s6_stb, s7_stb; - wire m0_cyc, m1_cyc, s0_cyc, s1_cyc, s2_cyc, s3_cyc, s4_cyc, s5_cyc, s6_cyc, s7_cyc; - wire m0_err, m1_err, s0_err, s1_err, s2_err, s3_err, s4_err, s5_err, s6_err, s7_err; - wire m0_rty, m1_rty, s0_rty, s1_rty, s2_rty, s3_rty, s4_rty, s5_rty, s6_rty, s7_rty; - wire m0_we, m1_we, s0_we, s1_we, s2_we, s3_we, s4_we, s5_we, s6_we, s7_we; - - wb_1master #(.s0_addr_w(2),.s0_addr(2'b00),.s1_addr_w(2),.s1_addr(2'b01), - .s27_addr_w(4),.s2_addr(4'b1000),.s3_addr(4'b1001),.s4_addr(4'b1010), - .s5_addr(4'b1011),.s6_addr(4'b1100),.s7_addr(4'b1101), - .dw(dw),.aw(aw),.sw(sw)) wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - - .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty), - .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty), - .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty), - .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty), - .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty), - .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty), - .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty), - .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty) - ); - - ////////////////////////////////////////////////////////////////////////////////////////// - // Reset Controller - system_control sysctrl (.wb_clk_i(wb_clk), - .ram_loader_rst_o(ram_loader_rst), - .wb_rst_o(wb_rst), - .ram_loader_done_i(ram_loader_done)); - - // /////////////////////////////////////////////////////////////////// - // RAM Loader - wire iram_wr_stb, iram_rd_stb, iram_wr_ack, iram_rd_ack, iram_ack, iram_wr_we; - wire [3:0] iram_wr_sel; - wire [aw-1:0] iram_wr_adr, iram_rd_adr; - wire [dw-1:0] iram_wr_dat, iram_rd_dat; - - wire bus_error, proc_int; - - assign iram_rd_ack = ram_loader_done ? iram_ack : 1'b0; - assign iram_wr_ack = ram_loader_done ? 1'b0 : iram_ack; - - ram_loader #(.AWIDTH(16)) - ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), - // CPLD Interface - .cfg_clk_i(cpld_clk), - .cfg_data_i(cpld_din), - .start_o(cpld_start), - .mode_o(cpld_mode), - .done_o(cpld_done), - .detached_i(cpld_detached), - // Wishbone Interface - .wb_dat_o(iram_wr_dat),.wb_adr_o(iram_wr_adr), - .wb_stb_o(iram_wr_stb),.wb_cyc_o(),.wb_sel_o(iram_wr_sel), - .wb_we_o(iram_wr_we),.wb_ack_i(iram_wr_ack), - .ram_loader_done_o(ram_loader_done)); - - // Processor - aeMB_core_BE #(.ISIZ(16),.DSIZ(16)) - aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), - // Instruction Wishbone bus to I-RAM - .iwb_stb_o(iram_rd_stb),.iwb_adr_o(iram_rd_adr), - .iwb_dat_i(iram_rd_dat),.iwb_ack_i(iram_rd_ack), - // Data Wishbone bus to system bus fabric - .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), - .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), - // Interrupts and exceptions - .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - assign bus_error = m0_err | m0_rty; - assign proc_int = 1'b0; - - // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone - // I-port connects directly to processor and ram loader - - ram_wb_harvard #(.AWIDTH(14)) - ID_ram (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - - .iwb_adr_i(ram_loader_done ? iram_rd_adr : iram_wr_adr),.iwb_dat_i(iram_wr_dat),.iwb_dat_o(iram_rd_dat), - .iwb_we_i(iram_wr_we),.iwb_ack_o(iram_ack),.iwb_stb_i(ram_loader_done ? iram_rd_stb : iram_wr_stb), - .iwb_sel_i(ram_loader_done ? 4'b1111 : iram_wr_sel), - - .dwb_adr_i(s0_adr),.dwb_dat_i(s0_dat_o),.dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we),.dwb_ack_o(s0_ack),.dwb_stb_i(s0_stb),.dwb_sel_i(s0_sel)); - - assign s0_err = 1'b0; - assign s0_rty = 1'b0; - - // Buffer Pool, slave #1 - wire rd0_read, rd0_ready, rd0_done, rd0_empty; - wire rd1_read, rd1_ready, rd1_done, rd1_empty; - wire rd2_read, rd2_ready, rd2_done, rd2_empty; - wire rd3_read, rd3_ready, rd3_done, rd3_empty; - wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; - - wire wr0_write, wr0_done, wr0_ready, wr0_full; - wire wr1_write, wr1_done, wr1_ready, wr1_full; - wire wr2_write, wr2_done, wr2_ready, wr2_full; - wire wr3_write, wr3_done, wr3_ready, wr3_full; - wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - -/* - buffer_pool buffer_pool - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), - .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty), - - .stream_clk(dsp_clk),.stream_rst(dsp_rst), - // Write Interfaces - .wr0_dat_i(),.wr0_write_i(),.wr0_done_i(),.wr0_ready_o(),.wr0_full_o(), - .wr1_dat_i(),.wr1_write_i(),.wr1_done_i(),.wr1_ready_o(),.wr1_full_o(), - .wr2_dat_i(),.wr2_write_i(),.wr2_done_i(),.wr2_ready_o(),.wr2_full_o(), - .wr3_dat_i(),.wr3_write_i(),.wr3_done_i(),.wr3_ready_o(),.wr3_full_o(), - // Read Interfaces - .rd0_dat_o(rd0_dat),.rd0_read_i(rd0_read),.rd0_done_i(),.rd0_ready_o(rd0_ready),.rd0_empty_o(rd0_empty), - .rd1_dat_o(rd1_dat),.rd1_read_i(rd1_read),.rd1_done_i(),.rd1_ready_o(rd1_ready),.rd1_empty_o(rd1_empty), - .rd2_dat_o(rd2_dat),.rd2_read_i(rd2_read),.rd2_done_i(),.rd2_ready_o(rd2_ready),.rd2_empty_o(rd2_empty), - .rd3_dat_o(rd3_dat),.rd3_read_i(rd3_read),.rd3_done_i(),.rd3_ready_o(rd3_ready),.rd3_empty_o(rd3_empty) - ); -*/ - // SPI -- Slave #2 - spi_top shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr),.wb_dat_i(s2_dat_o),.wb_dat_o(s2_dat_i), - .wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),.wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack), - - .wb_err_o(s2_err),.wb_int_o(s2_int), - .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), - .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); - - assign s2_rty = 1'b0; - - // I2C -- Slave #3 - i2c_master_top #(.ARST_LVL(1)) - i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr),.wb_dat_i(s3_dat_o),.wb_dat_o(s3_dat_i), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(st_int), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_err = 1'b0; - assign s3_rty = 1'b0; - - // GPIOs -- Slave #4 - wire s4_ack_a, s4_ack_b, s4_ack_c, s4_ack_d; - assign s4_ack = s4_ack_a | s4_ack_b | s4_ack_c | s4_ack_d; - - simple_gpio gpio_a(.clk_i(wb_clk),.rst_i(~wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[0]),.adr_i(s4_adr[2]),.we_i(s4_we), - .dat_i(s4_dat_o[7:0]),.dat_o(s4_dat_i[7:0]),.ack_o(s4_ack_a), - .gpio(/* io_tx[7:0]*/) ); - - simple_gpio gpio_b(.clk_i(wb_clk),.rst_i(~wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[1]),.adr_i(s4_adr[2]),.we_i(s4_we), - .dat_i(s4_dat_o[15:8]),.dat_o(s4_dat_i[15:8]),.ack_o(s4_ack_b), - .gpio(/* io_tx[15:8] */) ); - - simple_gpio gpio_c(.clk_i(wb_clk),.rst_i(~wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[2]),.adr_i(s4_adr[2]),.we_i(s4_we), - .dat_i(s4_dat_o[23:16]),.dat_o(s4_dat_i[23:16]),.ack_o(s4_ack_c), - .gpio(/* io_rx[7:0] */) ); - - simple_gpio gpio_d(.clk_i(wb_clk),.rst_i(~wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[3]),.adr_i(s4_adr[2]),.we_i(s4_we), - .dat_i(s4_dat_o[31:24]),.dat_o(s4_dat_i[31:24]),.ack_o(s4_ack_d), - .gpio(/* io_rx[15:8]*/) ); - - assign s4_err = 1'b0; - assign s4_rty = 1'b0; - - // Output control lines, SLAVE #5 - wire [7:0] clock_outs, serdes_outs, adc_outs, misc_outs; - assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; - assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; - assign { adc_oen_a, adc_pdn_a, adc_oen_b, adc_pdn_b } = adc_outs[3:0]; - assign {led2, led1} = misc_outs[1:0]; - - wb_output_pins32 control_lines - (.wb_rst_i(wb_rst),.wb_clk_i(wb_clk),.wb_dat_i(s5_dat_o),.wb_dat_o(s5_dat_i), - .wb_we_i(s5_we),.wb_sel_i(s5_sel),.wb_stb_i(s5_stb),.wb_ack_o(s5_ack),.wb_cyc_i(s5_cyc), - .port_output( {clock_outs,serdes_outs,adc_outs,misc_outs} ) ); - - assign s5_err = 1'b0; - assign s5_rty = 1'b0; - - // Ethernet slave, #6 - eth_wrapper eth_wrapper - (.Reset(wb_rst),.Clk_125M(),.Clk_user(stream_clk),.Clk_reg(wb_clk),.Speed(), - .Gtx_clk(GMII_GTX_CLK),.Rx_clk(GMII_RX_CLK),.Tx_clk(GMII_TX_CLK),//used only in MII mode - .Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD),.Rx_er(GMII_RX_ER), - .Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD),.Crs(GMII_CRS),.Col(GMII_COL), - .Mdio(MDIO),.Mdc(MDC), - // FIFO Interfaces - .wr_dat_o(),.wr_write_o(),.wr_done_o(),.wr_ready_i(),.wr_full_i(), - .rd_dat_i(),.rd_read_o(),.rd_done_o(),.rd_ready_i(),.rd_empty_i(), - // Wishbone - .wb_dat_i(s6_dat_o),.wb_dat_o(s6_dat_i),.wb_adr_i(s6_adr),.wb_stb_i(s6_stb),.wb_we_i(s6_we),.wb_ack_o(s6_ack) - ); - - assign s6_err = 1'b0; - assign s6_rty = 1'b0; - - // Settings Bus -- Slave #7 - settings_bus settings_bus - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), - .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), - .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data)); - - assign s7_err = 1'b0; - assign s7_rty = 1'b0; - assign s7_dat_i = 32'd0; - - /////////////////////////////////////////////////////////////////////////// - // DSP - reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2; - reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2; - - always @(posedge dsp_clk) - begin - adc_a_reg1 <= adc_a; - adc_a_reg2 <= adc_a_reg1; - adc_b_reg1 <= adc_b; - adc_b_reg2 <= adc_b_reg1; - adc_ovf_a_reg1 <= adc_ovf_a; - adc_ovf_a_reg2 <= adc_ovf_a_reg1; - adc_ovf_b_reg1 <= adc_ovf_b; - adc_ovf_b_reg2 <= adc_ovf_b_reg1; - end // always @ (posedge dsp_clk) - - dsp_core_rx dsp_core_rx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .rx_dat_o(wr1_dat),.rx_write_o(wr1_write),.rx_done_o(wr1_done), - .rx_ready_i(wr1_ready),.rx_full_i(wr1_full), - .overrun() ); - - dsp_core_tx dsp_core_tx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .dac_a(dac_a),.dac_b(dac_b), - .tx_dat_i(rd1_dat),.tx_read_o(rd1_read),.tx_done_o(rd1_done), - .tx_ready_i(rd1_ready),.tx_empty_i(rd1_empty), - .underrun() ); - - assign dsp_rst = wb_rst; - - ///////////////////////////////////////////////////////////////////////////////////// - // SERDES - serdes_tx serdes_tx - (.clk(dsp_clk),.rst(dsp_rst), - .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .fifo_data_i(rd0_dat),.fifo_read_o(rd0_read),.fifo_done_o(rd0_done), - .fifo_ready_i(rd0_ready),.fifo_empty_i(rd0_empty) - ); - - serdes_rx serdes_rx - (.clk(dsp_clk),.rst(dsp_rst), - .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .fifo_data_o(wr0_dat),.fifo_wr_o(wr0_write),.fifo_ready_i(wr0_ready),.fifo_done_i(wr0_done) - ); - - // Debug Pins - wire [31:0] debug1={{1'b0,ram_loader_done,clock_ready,dsp_clk,wb_clk,ram_loader_rst,wb_rst,dsp_rst}, - {1'b0,cpld_start,cpld_mode,cpld_done,1'b0,cpld_din,cpld_clk,cpld_detached}, - {8'hAF}, - {2'b0, clk_status, sen_dac, sen_clk, sclk, mosi, miso}}; - - wire [31:0] debug_wb={{iram_wr_we,ram_loader_done,clock_ready,iram_wr_ack,iram_wr_stb,ram_loader_rst,wb_rst,dsp_rst}, - {iram_rd_adr[15:8]}, - {iram_rd_adr[7:0]}, - {serdes_outs}}; - - assign io_rx = ser_debug[31:16]; - assign io_tx = ser_debug[15:0]; - - assign debug = debug_wb; - - assign debug_clk[0] = wb_clk; - assign debug_clk[1] = dsp_clk; - -endmodule // eth_test - - -// Local Variables: -// verilog-library-directories:("." "subdir" "subdir2") -// verilog-library-files:("/home/matt/u2f/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v") -// verilog-library-extensions:(".v" ".h") -// End: diff --git a/usrp2/top/eth_test/eth_tb.v b/usrp2/top/eth_test/eth_tb.v deleted file mode 100644 index 451ce1e7e..000000000 --- a/usrp2/top/eth_test/eth_tb.v +++ /dev/null @@ -1,257 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -// Nearly everything is an input - -module eth_tb(); - // Misc, debug - wire led1; - wire led2; - wire [31:0] debug; - wire [1:0] debug_clk; - - // Expansion - wire exp_pps_in; - wire exp_pps_out; - - // GMII - // GMII-CTRL - wire GMII_COL; - wire GMII_CRS; - - // GMII-TX - wire [7:0] GMII_TXD; - wire GMII_TX_EN; - wire GMII_TX_ER; - wire GMII_GTX_CLK; - wire GMII_TX_CLK; // 100mbps clk - - // GMII-RX - wire [7:0] GMII_RXD; - wire GMII_RX_CLK; - wire GMII_RX_DV; - wire GMII_RX_ER; - - // GMII-Management - wire MDIO; - wire MDC; - wire PHY_INTn; // open drain - wire PHY_RESETn; - wire PHY_CLK; // possibly use on-board osc - - // RAM - wire [17:0] RAM_D; - wire [18:0] RAM_A; - wire RAM_CE1n; - wire RAM_CENn; - wire RAM_CLK; - wire RAM_WEn; - wire RAM_OEn; - wire RAM_LDn; - - // SERDES - wire ser_enable; - wire ser_prbsen; - wire ser_loopen; - wire ser_rx_en; - - wire ser_tx_clk; - wire [15:0] ser_t; - wire ser_tklsb; - wire ser_tkmsb; - - wire ser_rx_clk; - wire [15:0] ser_r; - wire ser_rklsb; - wire ser_rkmsb; - - // CPLD interface - wire cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done; - - // ADC - wire [13:0] adc_a; - wire adc_ovf_a; - wire adc_oen_a; - wire adc_pdn_a; - - wire [13:0] adc_b; - wire adc_ovf_b; - wire adc_oen_b; - wire adc_pdn_b; - - // DAC - wire [15:0] dac_a; - wire [15:0] dac_b; - - // I2C - wire SCL; - wire SDA; - - // Clock Gen Control - wire [1:0] clk_en; - wire [1:0] clk_sel; - wire clk_func; // FIXME is an input to control the 9510 - wire clk_status; - - // Clocks - reg clk_fpga; - wire clk_to_mac; - wire pps_in; - - // Generic SPI - wire sclk, mosi, miso; - wire sen_clk; - wire sen_dac; - wire sen_tx_db; - wire sen_tx_adc; - wire sen_tx_dac; - wire sen_rx_db; - wire sen_rx_adc; - wire sen_rx_dac; - - // GPIO to DBoards - wire [15:0] io_tx; - wire [15:0] io_rx; - - wire wb_clk, wb_rst; - wire start, clock_ready; - - reg aux_clk; - - initial aux_clk= 1'b0; - always #25 aux_clk = ~aux_clk; - - initial clk_fpga = 1'bx; - initial #3007 clk_fpga = 1'b0; - always #7 clk_fpga = ~clk_fpga; - - - wire div_clk; - reg [2:0] div_ctr = 0; - - always @(posedge clk_fpga or negedge clk_fpga) - if(div_ctr==5) - div_ctr = 0; - else - div_ctr = div_ctr + 1; - assign div_clk = (div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2); - - assign dsp_clk = clk_fpga; - assign wb_clk = clock_ready ? div_clk : aux_clk; - - initial - $monitor($time, ,clock_ready); - - initial begin - $dumpfile("eth_tb.vcd"); - $dumpvars(0,eth_tb); - end - - initial #10000000 $finish; - - cpld_model - cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done), - .dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached)); - - eth_sim_top eth_sim_top(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), - .led1 (led1), - .led2 (led2), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_pps_in), - .exp_pps_out (exp_pps_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD[7:0]), - .GMII_TX_EN (GMII_TX_EN), - .GMII_TX_ER (GMII_TX_ER), - .GMII_GTX_CLK (GMII_GTX_CLK), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .PHY_CLK (PHY_CLK), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk), - .ser_t (ser_t[15:0]), - .ser_tklsb (ser_tklsb), - .ser_tkmsb (ser_tkmsb), - .ser_rx_clk (ser_rx_clk), - .ser_r (ser_r[15:0]), - .ser_rklsb (ser_rklsb), - .ser_rkmsb (ser_rkmsb), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .adc_a (adc_a[13:0]), - .adc_ovf_a (adc_ovf_a), - .adc_oen_a (adc_oen_a), - .adc_pdn_a (adc_pdn_a), - .adc_b (adc_b[13:0]), - .adc_ovf_b (adc_ovf_b), - .adc_oen_b (adc_oen_b), - .adc_pdn_b (adc_pdn_b), - .dac_a (dac_a[15:0]), - .dac_b (dac_b[15:0]), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0])); - - // Experimental printf-like function - always @(posedge wb_clk) - begin - if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC000)) - $write("%x",eth_sim_top.m0_dat_i); - if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC100)) - $display("%x",eth_sim_top.m0_dat_i); - if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC004)) - $write("%c",eth_sim_top.m0_dat_i); - if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC104)) - $display("%c",eth_sim_top.m0_dat_i); - if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC008)) - $display(""); - end - - -endmodule // u2_sim_top - -// Local Variables: -// verilog-library-directories:("." "subdir" "subdir2") -// verilog-library-files:("/home/matt/u2f/top/u2_basic/u2_basic.v") -// verilog-library-extensions:(".v" ".h") -// End: -- cgit v1.2.3 From f0a9f021120eae604321edb9a97a7a5d8716da47 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 7 Jun 2011 16:26:30 -0700 Subject: remove old ethernet tester, no longer needed or working --- usrp2/top/u1e_ethdebug/.gitignore | 6 --- usrp2/top/u1e_ethdebug/Makefile | 83 ------------------------------------ usrp2/top/u1e_ethdebug/u1e.ucf | 88 --------------------------------------- usrp2/top/u1e_ethdebug/u1e.v | 28 ------------- 4 files changed, 205 deletions(-) delete mode 100644 usrp2/top/u1e_ethdebug/.gitignore delete mode 100644 usrp2/top/u1e_ethdebug/Makefile delete mode 100644 usrp2/top/u1e_ethdebug/u1e.ucf delete mode 100644 usrp2/top/u1e_ethdebug/u1e.v diff --git a/usrp2/top/u1e_ethdebug/.gitignore b/usrp2/top/u1e_ethdebug/.gitignore deleted file mode 100644 index 8d872713e..000000000 --- a/usrp2/top/u1e_ethdebug/.gitignore +++ /dev/null @@ -1,6 +0,0 @@ -*~ -build -*.log -*.cmd -tb_u1e -*.lxt diff --git a/usrp2/top/u1e_ethdebug/Makefile b/usrp2/top/u1e_ethdebug/Makefile deleted file mode 100644 index 751b52970..000000000 --- a/usrp2/top/u1e_ethdebug/Makefile +++ /dev/null @@ -1,83 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = u1e -BUILD_DIR = $(abspath build$(ISE)) - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd1800a \ -package cs484 \ -speed -4 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -u1e.v \ -u1e.ucf - -SOURCES = $(abspath $(TOP_SRCS)) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 \ -"Unused IOB Pins" "Pull Up" - -SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/u1e_ethdebug/u1e.ucf b/usrp2/top/u1e_ethdebug/u1e.ucf deleted file mode 100644 index d6a2ea4ed..000000000 --- a/usrp2/top/u1e_ethdebug/u1e.ucf +++ /dev/null @@ -1,88 +0,0 @@ - -## GPMC -NET "EM_D<15>" LOC = "D13" ; -NET "EM_D<14>" LOC = "D15" ; -NET "EM_D<13>" LOC = "C16" ; -NET "EM_D<12>" LOC = "B20" ; -NET "EM_D<11>" LOC = "A19" ; -NET "EM_D<10>" LOC = "A17" ; -NET "EM_D<9>" LOC = "E15" ; -NET "EM_D<8>" LOC = "F15" ; -NET "EM_D<7>" LOC = "E16" ; -NET "EM_D<6>" LOC = "F16" ; -NET "EM_D<5>" LOC = "B17" ; -NET "EM_D<4>" LOC = "C17" ; -NET "EM_D<3>" LOC = "B19" ; -NET "EM_D<2>" LOC = "D19" ; -NET "EM_D<1>" LOC = "C19" ; -NET "EM_D<0>" LOC = "A20" ; - -NET "EM_A<10>" LOC = "C14" ; -NET "EM_A<9>" LOC = "C10" ; -NET "EM_A<8>" LOC = "C5" ; -NET "EM_A<7>" LOC = "A18" ; -NET "EM_A<6>" LOC = "A15" ; -NET "EM_A<5>" LOC = "A12" ; -NET "EM_A<4>" LOC = "A10" ; -NET "EM_A<3>" LOC = "E7" ; -NET "EM_A<2>" LOC = "A7" ; -NET "EM_A<1>" LOC = "C15" ; - -NET "EM_NCS6" LOC = "E17" ; -NET "EM_NCS5" LOC = "E10" ; -NET "EM_NCS4" LOC = "E6" ; -#NET "EM_NCS1" LOC = "D18" ; -#NET "EM_NCS0" LOC = "D17" ; - -NET "EM_CLK" LOC = "F11" ; -NET "EM_WAIT0" LOC = "F14" ; -#NET "EM_NBE<1>" LOC = "D14" ; -#NET "EM_NBE<0>" LOC = "A13" ; -NET "EM_NWE" LOC = "B13" ; -NET "EM_NOE" LOC = "A14" ; -NET "EM_NADV_ALE" LOC = "B15" ; -#NET "EM_NWP" LOC = "F13" ; -NET "overo_gpio64" LOC = "A4" ; # nRESET -NET "overo_gpio176" LOC = "B4" ; # IRQ - -## Debug pins -NET "debug_led<3>" LOC = "Y15" ; -NET "debug_led<2>" LOC = "K16" ; -NET "debug_led<1>" LOC = "J17" ; -NET "debug_led<0>" LOC = "H22" ; -NET "debug<0>" LOC = "G22" ; -NET "debug<1>" LOC = "H17" ; -NET "debug<2>" LOC = "H18" ; -NET "debug<3>" LOC = "K20" ; -NET "debug<4>" LOC = "J20" ; -NET "debug<5>" LOC = "K19" ; -NET "debug<6>" LOC = "K18" ; -NET "debug<7>" LOC = "L22" ; -NET "debug<8>" LOC = "K22" ; -NET "debug<9>" LOC = "N22" ; -NET "debug<10>" LOC = "M22" ; -NET "debug<11>" LOC = "N20" ; -NET "debug<12>" LOC = "N19" ; -NET "debug<13>" LOC = "R22" ; -NET "debug<14>" LOC = "P22" ; -NET "debug<15>" LOC = "N17" ; -NET "debug<16>" LOC = "P16" ; -NET "debug<17>" LOC = "U22" ; -NET "debug<18>" LOC = "P19" ; -NET "debug<19>" LOC = "R18" ; -NET "debug<20>" LOC = "U20" ; -NET "debug<21>" LOC = "T20" ; -NET "debug<22>" LOC = "R19" ; -NET "debug<23>" LOC = "R20" ; -NET "debug<24>" LOC = "W22" ; -NET "debug<25>" LOC = "Y22" ; -NET "debug<26>" LOC = "T18" ; -NET "debug<27>" LOC = "T17" ; -NET "debug<28>" LOC = "W19" ; -NET "debug<29>" LOC = "V20" ; -NET "debug<30>" LOC = "Y21" ; -NET "debug<31>" LOC = "AA22" ; -NET "debug_clk<0>" LOC = "N18" ; -NET "debug_clk<1>" LOC = "M17" ; - -NET "debug_pb" LOC = "C22" ; diff --git a/usrp2/top/u1e_ethdebug/u1e.v b/usrp2/top/u1e_ethdebug/u1e.v deleted file mode 100644 index 2a543a313..000000000 --- a/usrp2/top/u1e_ethdebug/u1e.v +++ /dev/null @@ -1,28 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -//`define DCM 1 - -module u1e - (output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - input debug_pb, - - // GPMC - input EM_CLK, input [15:0] EM_D, input [10:1] EM_A, - input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, input EM_NWE, input EM_NOE, - input EM_NADV_ALE, - - input overo_gpio64, input overo_gpio176 - ); - - assign debug_clk = {EM_CLK, EM_NADV_ALE}; - - assign debug_led = {1'b0, EM_A[9], EM_A[8], debug_pb}; - - assign debug = { {overo_gpio64, overo_gpio176, EM_WAIT0, EM_NCS4, EM_NCS5, EM_NCS6, EM_NWE, EM_NOE }, - { EM_A[10], EM_A[7:1] }, - { EM_D[15:8] }, - { EM_D[7:0] } }; - - -endmodule // u1e -- cgit v1.2.3 From e4be5c906e8c1f0901ff7206b4b965a0abc7d8d2 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 7 Jun 2011 16:48:30 -0700 Subject: lots of renaming and moving around of toplevel directories to reflect product names --- usrp2/testbench/single_u2_sim.v | 324 +++++++++++++++ usrp2/top/B100/.gitignore | 1 + usrp2/top/B100/Makefile | 97 +++++ usrp2/top/B100/core_compile | 1 + usrp2/top/B100/timing.ucf | 5 + usrp2/top/B100/u1plus.ucf | 203 +++++++++ usrp2/top/B100/u1plus.v | 156 +++++++ usrp2/top/B100/u1plus_core.v | 392 ++++++++++++++++++ usrp2/top/E1x0/.gitignore | 6 + usrp2/top/E1x0/Makefile | 100 +++++ usrp2/top/E1x0/Makefile.passthru | 98 +++++ usrp2/top/E1x0/README | 4 + usrp2/top/E1x0/cmdfile | 20 + usrp2/top/E1x0/core_compile | 3 + usrp2/top/E1x0/make.sim | 7 + usrp2/top/E1x0/passthru.ucf | 6 + usrp2/top/E1x0/passthru.v | 18 + usrp2/top/E1x0/tb_u1e.v | 41 ++ usrp2/top/E1x0/timing.ucf | 13 + usrp2/top/E1x0/u1e.ucf | 259 ++++++++++++ usrp2/top/E1x0/u1e.v | 141 +++++++ usrp2/top/E1x0/u1e_core.v | 421 +++++++++++++++++++ usrp2/top/N2x0/.gitignore | 1 + usrp2/top/N2x0/Makefile.N200R3 | 98 +++++ usrp2/top/N2x0/Makefile.N200R4 | 100 +++++ usrp2/top/N2x0/Makefile.N210R3 | 98 +++++ usrp2/top/N2x0/Makefile.N210R4 | 100 +++++ usrp2/top/N2x0/bootloader.rmi | 512 +++++++++++++++++++++++ usrp2/top/N2x0/capture_ddrlvds.v | 38 ++ usrp2/top/N2x0/rev4_defs.v | 1 + usrp2/top/N2x0/u2plus.ucf | 424 +++++++++++++++++++ usrp2/top/N2x0/u2plus.v | 454 ++++++++++++++++++++ usrp2/top/N2x0/u2plus_core.v | 708 ++++++++++++++++++++++++++++++++ usrp2/top/USRP2/.gitignore | 57 +++ usrp2/top/USRP2/Makefile | 98 +++++ usrp2/top/USRP2/u2_core.v | 707 +++++++++++++++++++++++++++++++ usrp2/top/USRP2/u2_rev3.ucf | 336 +++++++++++++++ usrp2/top/USRP2/u2_rev3.v | 572 ++++++++++++++++++++++++++ usrp2/top/safe_u1plus/.gitignore | 1 - usrp2/top/safe_u1plus/Makefile | 122 ------ usrp2/top/safe_u1plus/safe_u1plus.ucf | 171 -------- usrp2/top/safe_u1plus/safe_u1plus.v | 28 -- usrp2/top/safe_u2plus/.gitignore | 2 - usrp2/top/safe_u2plus/Makefile | 245 ----------- usrp2/top/safe_u2plus/safe_u2plus.v | 23 -- usrp2/top/safe_u2plus/u2plus.ucf | 401 ------------------ usrp2/top/single_u2_sim/single_u2_sim.v | 324 --------------- usrp2/top/u1e/.gitignore | 6 - usrp2/top/u1e/Makefile | 100 ----- usrp2/top/u1e/README | 4 - usrp2/top/u1e/cmdfile | 20 - usrp2/top/u1e/core_compile | 3 - usrp2/top/u1e/make.sim | 7 - usrp2/top/u1e/tb_u1e.v | 41 -- usrp2/top/u1e/timing.ucf | 13 - usrp2/top/u1e/u1e.ucf | 259 ------------ usrp2/top/u1e/u1e.v | 141 ------- usrp2/top/u1e/u1e_core.v | 421 ------------------- usrp2/top/u1e_passthru/.gitignore | 1 - usrp2/top/u1e_passthru/Makefile | 98 ----- usrp2/top/u1e_passthru/passthru.ucf | 6 - usrp2/top/u1e_passthru/passthru.v | 18 - usrp2/top/u1plus/.gitignore | 1 - usrp2/top/u1plus/Makefile | 97 ----- usrp2/top/u1plus/core_compile | 1 - usrp2/top/u1plus/timing.ucf | 5 - usrp2/top/u1plus/u1plus.ucf | 203 --------- usrp2/top/u1plus/u1plus.v | 156 ------- usrp2/top/u1plus/u1plus_core.v | 392 ------------------ usrp2/top/u2_rev3/.gitignore | 57 --- usrp2/top/u2_rev3/Makefile | 98 ----- usrp2/top/u2_rev3/u2_core.v | 707 ------------------------------- usrp2/top/u2_rev3/u2_rev3.ucf | 336 --------------- usrp2/top/u2_rev3/u2_rev3.v | 572 -------------------------- usrp2/top/u2plus/.gitignore | 1 - usrp2/top/u2plus/Makefile.N200R3 | 98 ----- usrp2/top/u2plus/Makefile.N200R4 | 100 ----- usrp2/top/u2plus/Makefile.N210R3 | 98 ----- usrp2/top/u2plus/Makefile.N210R4 | 100 ----- usrp2/top/u2plus/bootloader.rmi | 512 ----------------------- usrp2/top/u2plus/capture_ddrlvds.v | 38 -- usrp2/top/u2plus/rev4_defs.v | 1 - usrp2/top/u2plus/u2plus.ucf | 424 ------------------- usrp2/top/u2plus/u2plus.v | 454 -------------------- usrp2/top/u2plus/u2plus_core.v | 708 -------------------------------- 85 files changed, 6620 insertions(+), 7614 deletions(-) create mode 100644 usrp2/testbench/single_u2_sim.v create mode 100644 usrp2/top/B100/.gitignore create mode 100644 usrp2/top/B100/Makefile create mode 100755 usrp2/top/B100/core_compile create mode 100644 usrp2/top/B100/timing.ucf create mode 100644 usrp2/top/B100/u1plus.ucf create mode 100644 usrp2/top/B100/u1plus.v create mode 100644 usrp2/top/B100/u1plus_core.v create mode 100644 usrp2/top/E1x0/.gitignore create mode 100644 usrp2/top/E1x0/Makefile create mode 100644 usrp2/top/E1x0/Makefile.passthru create mode 100644 usrp2/top/E1x0/README create mode 100644 usrp2/top/E1x0/cmdfile create mode 100755 usrp2/top/E1x0/core_compile create mode 100644 usrp2/top/E1x0/make.sim create mode 100644 usrp2/top/E1x0/passthru.ucf create mode 100644 usrp2/top/E1x0/passthru.v create mode 100644 usrp2/top/E1x0/tb_u1e.v create mode 100644 usrp2/top/E1x0/timing.ucf create mode 100644 usrp2/top/E1x0/u1e.ucf create mode 100644 usrp2/top/E1x0/u1e.v create mode 100644 usrp2/top/E1x0/u1e_core.v create mode 100644 usrp2/top/N2x0/.gitignore create mode 100644 usrp2/top/N2x0/Makefile.N200R3 create mode 100644 usrp2/top/N2x0/Makefile.N200R4 create mode 100644 usrp2/top/N2x0/Makefile.N210R3 create mode 100644 usrp2/top/N2x0/Makefile.N210R4 create mode 100644 usrp2/top/N2x0/bootloader.rmi create mode 100644 usrp2/top/N2x0/capture_ddrlvds.v create mode 100644 usrp2/top/N2x0/rev4_defs.v create mode 100755 usrp2/top/N2x0/u2plus.ucf create mode 100644 usrp2/top/N2x0/u2plus.v create mode 100644 usrp2/top/N2x0/u2plus_core.v create mode 100644 usrp2/top/USRP2/.gitignore create mode 100644 usrp2/top/USRP2/Makefile create mode 100644 usrp2/top/USRP2/u2_core.v create mode 100644 usrp2/top/USRP2/u2_rev3.ucf create mode 100644 usrp2/top/USRP2/u2_rev3.v delete mode 100644 usrp2/top/safe_u1plus/.gitignore delete mode 100644 usrp2/top/safe_u1plus/Makefile delete mode 100644 usrp2/top/safe_u1plus/safe_u1plus.ucf delete mode 100644 usrp2/top/safe_u1plus/safe_u1plus.v delete mode 100644 usrp2/top/safe_u2plus/.gitignore delete mode 100644 usrp2/top/safe_u2plus/Makefile delete mode 100644 usrp2/top/safe_u2plus/safe_u2plus.v delete mode 100755 usrp2/top/safe_u2plus/u2plus.ucf delete mode 100644 usrp2/top/single_u2_sim/single_u2_sim.v delete mode 100644 usrp2/top/u1e/.gitignore delete mode 100644 usrp2/top/u1e/Makefile delete mode 100644 usrp2/top/u1e/README delete mode 100644 usrp2/top/u1e/cmdfile delete mode 100755 usrp2/top/u1e/core_compile delete mode 100644 usrp2/top/u1e/make.sim delete mode 100644 usrp2/top/u1e/tb_u1e.v delete mode 100644 usrp2/top/u1e/timing.ucf delete mode 100644 usrp2/top/u1e/u1e.ucf delete mode 100644 usrp2/top/u1e/u1e.v delete mode 100644 usrp2/top/u1e/u1e_core.v delete mode 100644 usrp2/top/u1e_passthru/.gitignore delete mode 100644 usrp2/top/u1e_passthru/Makefile delete mode 100644 usrp2/top/u1e_passthru/passthru.ucf delete mode 100644 usrp2/top/u1e_passthru/passthru.v delete mode 100644 usrp2/top/u1plus/.gitignore delete mode 100644 usrp2/top/u1plus/Makefile delete mode 100755 usrp2/top/u1plus/core_compile delete mode 100644 usrp2/top/u1plus/timing.ucf delete mode 100644 usrp2/top/u1plus/u1plus.ucf delete mode 100644 usrp2/top/u1plus/u1plus.v delete mode 100644 usrp2/top/u1plus/u1plus_core.v delete mode 100644 usrp2/top/u2_rev3/.gitignore delete mode 100644 usrp2/top/u2_rev3/Makefile delete mode 100644 usrp2/top/u2_rev3/u2_core.v delete mode 100644 usrp2/top/u2_rev3/u2_rev3.ucf delete mode 100644 usrp2/top/u2_rev3/u2_rev3.v delete mode 100644 usrp2/top/u2plus/.gitignore delete mode 100644 usrp2/top/u2plus/Makefile.N200R3 delete mode 100644 usrp2/top/u2plus/Makefile.N200R4 delete mode 100644 usrp2/top/u2plus/Makefile.N210R3 delete mode 100644 usrp2/top/u2plus/Makefile.N210R4 delete mode 100644 usrp2/top/u2plus/bootloader.rmi delete mode 100644 usrp2/top/u2plus/capture_ddrlvds.v delete mode 100644 usrp2/top/u2plus/rev4_defs.v delete mode 100755 usrp2/top/u2plus/u2plus.ucf delete mode 100644 usrp2/top/u2plus/u2plus.v delete mode 100644 usrp2/top/u2plus/u2plus_core.v diff --git a/usrp2/testbench/single_u2_sim.v b/usrp2/testbench/single_u2_sim.v new file mode 100644 index 000000000..2a7b24849 --- /dev/null +++ b/usrp2/testbench/single_u2_sim.v @@ -0,0 +1,324 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module single_u2_sim(); + // Misc, debug + wire [7:0] leds; + wire [31:0] debug; + wire [1:0] debug_clk; + + // Expansion + wire exp_pps_in; + wire exp_pps_out; + + // GMII + // GMII-CTRL + wire GMII_COL; + wire GMII_CRS; + + // GMII-TX + wire [7:0] GMII_TXD; + wire GMII_TX_EN; + wire GMII_TX_ER; + wire GMII_GTX_CLK; + wire GMII_TX_CLK; // 100mbps clk + + // GMII-RX + wire [7:0] GMII_RXD; + wire GMII_RX_CLK; + wire GMII_RX_DV; + wire GMII_RX_ER; + + // GMII-Management + wire MDIO; + wire MDC; + wire PHY_INTn; // open drain + wire PHY_RESETn; + wire PHY_CLK; // possibly use on-board osc + + // RAM + wire [17:0] RAM_D; + wire [18:0] RAM_A; + wire RAM_CE1n; + wire RAM_CENn; + wire RAM_CLK; + wire RAM_WEn; + wire RAM_OEn; + wire RAM_LDn; + + // SERDES + wire ser_enable; + wire ser_prbsen; + wire ser_loopen; + wire ser_rx_en; + + wire ser_tx_clk; + wire [15:0] ser_t; + wire ser_tklsb; + wire ser_tkmsb; + + wire ser_rx_clk; + wire [15:0] ser_r; + wire ser_rklsb; + wire ser_rkmsb; + + // CPLD interface + wire cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done; + + // ADC + wire [13:0] adc_a; + wire adc_ovf_a; + wire adc_on_a, adc_oe_a; + + wire [13:0] adc_b; + wire adc_ovf_b; + wire adc_on_b, adc_oe_b; + + // DAC + wire [15:0] dac_a; + wire [15:0] dac_b; + + // I2C + wire SCL; + wire SDA; + + // Clock Gen Control + wire [1:0] clk_en; + wire [1:0] clk_sel; + wire clk_func; // FIXME is an input to control the 9510 + wire clk_status; + + // Clocks + reg clk_fpga; + reg clk_to_mac; + wire pps_in; + + // Generic SPI + wire sclk, mosi, miso; + wire sen_clk; + wire sen_dac; + wire sen_tx_db; + wire sen_tx_adc; + wire sen_tx_dac; + wire sen_rx_db; + wire sen_rx_adc; + wire sen_rx_dac; + + // GPIO to DBoards + wire [15:0] io_tx; + wire [15:0] io_rx; + + wire wb_clk; + wire start, clock_ready; + + reg aux_clk; + + initial aux_clk= 1'b0; + always #6 aux_clk = ~aux_clk; + + initial clk_fpga = 1'bx; + initial #3007 clk_fpga = 1'b0; + always #5 clk_fpga = ~clk_fpga; + + initial clk_to_mac = 0; + always #4 clk_to_mac = ~clk_to_mac; + + wire div_clk, dsp_clk; + reg [7:0] div_ctr = 0; + + assign dsp_clk = clock_ready ? clk_fpga : aux_clk; + assign wb_clk = div_clk; + +`define CLK_DIV_2 1 +//`define CLK_DIV_3 + +`ifdef CLK_DIV_2 + localparam clock_divider = 4'd2; + always @(posedge dsp_clk) + div_ctr <= div_ctr + 1; + assign div_clk = div_ctr[0]; +`endif + +`ifdef CLK_DIV_3 + localparam clock_divider = 2; + always @(posedge dsp_clk or negedge dsp_clk) + if(div_ctr == 5) + div_ctr <= 0; + else + div_ctr <= div_ctr + 1; + assign div_clk = ((div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2)); +`endif + + initial + $monitor($time, ,clock_ready); + + always #1000000 $monitor("Time in ns ",$time); + + initial begin + @(negedge cpld_done); + @(posedge cpld_done); + $dumpfile("single_u2_sim.lxt"); + $dumpvars(0,single_u2_sim); + end + + initial #10000000 $finish; + + cpld_model + cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done), + .dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached)); + + serdes_model serdes_model + (.ser_tx_clk(ser_tx_clk), .ser_tkmsb(ser_tkmsb), .ser_tklsb(ser_tklsb), .ser_t(ser_t), + .ser_rx_clk(ser_rx_clk), .ser_rkmsb(ser_rkmsb), .ser_rklsb(ser_rklsb), .ser_r(ser_r), + .even(0),.error(0) ); + + adc_model adc_model + (.clk(dsp_clk),.rst(0), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_on_a(adc_on_a),.adc_oe_a(adc_oe_a), + .adc_b(adc_b),.adc_ovf_b(adc_ovf_b),.adc_on_b(adc_on_b),.adc_oe_b(adc_oe_b) ); + + wire [2:0] speed; + phy_sim phy_model + (.Gtx_clk(GMII_GTX_CLK), . Rx_clk(GMII_RX_CLK), .Tx_clk(GMII_TX_CLK), + .Tx_er(GMII_TX_ER), .Tx_en(GMII_TX_EN), .Txd(GMII_TXD), + .Rx_er(GMII_RX_ER), .Rx_dv(GMII_RX_DV), .Rxd(GMII_RXD), + .Crs(GMII_CRS), .Col(GMII_COL), + .Speed(speed), .Done(0) ); + pullup p3(MDIO); + + miim_model miim_model + (.mdc_i(MDC),.mdio(MDIO),.phy_resetn_i(PHY_RESETn),.phy_clk_i(PHY_CLK), + .phy_intn_o(PHY_INTn),.speed_o(speed) ); + + xlnx_glbl glbl (.GSR(),.GTS()); + + wire RAM_MODE = 1'b0; + cy1356 ram_model(.d(RAM_D),.clk(RAM_CLK),.a(RAM_A), + .bws(2'b00),.we_b(RAM_WEn),.adv_lb(RAM_LDn), + .ce1b(RAM_CE1n),.ce2(1'b1),.ce3b(1'b0), + .oeb(RAM_OEn),.cenb(RAM_CENn),.mode(RAM_MODE) ); + + M24LC024B eeprom_model(.A0(0),.A1(0),.A2(0),.WP(0), + .SDA(SDA),.SCL(SCL),.RESET(0)); + + wire scl_pad_i, scl_pad_o, scl_pad_oen_o; + wire sda_pad_i, sda_pad_o, sda_pad_oen_o; + + pullup p1(SCL); + pullup p2(SDA); + + assign scl_pad_i = SCL; + assign sda_pad_i = SDA; + + assign SCL = scl_pad_oen_o ? 1'bz : scl_pad_o; + assign SDA = sda_pad_oen_o ? 1'bz : sda_pad_o; + + // printf output + wire uart_baud_o, uart_tx_o, uart_rx_i; + assign uart_rx_i = 1'b1; + + uart_rx uart_rx(.baudclk(uart_baud_o),.rxd(uart_tx_o)); + + // End the simulation + always @(posedge wb_clk) + if((u2_core.m0_we == 1'd1)&&(u2_core.m0_adr == 16'hC2F0)) + begin + $display($time, "Finish called.",); + $finish; + end + + u2_core #(.RAM_SIZE(32768)) + u2_core(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .leds (leds), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_pps_in), + .exp_pps_out (exp_pps_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD[7:0]), + .GMII_TX_EN (GMII_TX_EN), + .GMII_TX_ER (GMII_TX_ER), + .GMII_GTX_CLK (GMII_GTX_CLK), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk), + .ser_t (ser_t[15:0]), + .ser_tklsb (ser_tklsb), + .ser_tkmsb (ser_tkmsb), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r[15:0]), + .ser_rklsb (ser_rklsb), + .ser_rkmsb (ser_rkmsb), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .cpld_init_b (1), + .por (0), + .adc_a (adc_a[13:0]), + .adc_ovf_a (adc_ovf_a), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b[13:0]), + .adc_ovf_b (adc_ovf_b), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (dac_a[15:0]), + .dac_b (dac_b[15:0]), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D (RAM_D), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (uart_tx_o), + .uart_rx_i (uart_rx_i), + .uart_baud_o (uart_baud_o), + .sim_mode (1'b1), + .clock_divider (clock_divider) + ); + +endmodule // single_u2_sim diff --git a/usrp2/top/B100/.gitignore b/usrp2/top/B100/.gitignore new file mode 100644 index 000000000..1b2211df0 --- /dev/null +++ b/usrp2/top/B100/.gitignore @@ -0,0 +1 @@ +build* diff --git a/usrp2/top/B100/Makefile b/usrp2/top/B100/Makefile new file mode 100644 index 000000000..ca6ec9320 --- /dev/null +++ b/usrp2/top/B100/Makefile @@ -0,0 +1,97 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := u1plus +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../gpif/Makefile.srcs + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan3A" \ +device XC3S1400A \ +package ft256 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u1plus.v \ +u1plus_core.v \ +u1plus.ucf \ +timing.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ +$(GPIF_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/B100/core_compile b/usrp2/top/B100/core_compile new file mode 100755 index 000000000..b2ccc8b49 --- /dev/null +++ b/usrp2/top/B100/core_compile @@ -0,0 +1 @@ +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models diff --git a/usrp2/top/B100/timing.ucf b/usrp2/top/B100/timing.ucf new file mode 100644 index 000000000..b2a455f6d --- /dev/null +++ b/usrp2/top/B100/timing.ucf @@ -0,0 +1,5 @@ +NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; +TIMESPEC "TS_CLK_FPGA_P" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; + +NET "IFCLK" TNM_NET = "IFCLK"; +TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20833 ps HIGH 50 %; diff --git a/usrp2/top/B100/u1plus.ucf b/usrp2/top/B100/u1plus.ucf new file mode 100644 index 000000000..cd89878e3 --- /dev/null +++ b/usrp2/top/B100/u1plus.ucf @@ -0,0 +1,203 @@ +## Main Clock +NET "CLK_FPGA_P" LOC = "R7" ; +NET "CLK_FPGA_N" LOC = "T7" ; + +## UART +NET "FPGA_TXD" LOC = "H16" ; +NET "FPGA_RXD" LOC = "H12" ; + +## I2C +NET "SDA_FPGA" LOC = "T13" ; +NET "SCL_FPGA" LOC = "R13" ; + +## CGEN +NET "cgen_st_ld" LOC = "M13" ; +NET "cgen_st_refmon" LOC = "J14" ; +NET "cgen_st_status" LOC = "P6" ; +NET "cgen_ref_sel" LOC = "T2" ; +NET "cgen_sync_b" LOC = "H15" ; + +## FPGA Config +#NET "fpga_cfg_din" LOC = "T14" ; +#NET "fpga_cfg_cclk" LOC = "R14" ; +#NET "fpga_cfg_init_b" LOC = "T12" ; + +## MISC +#NET "mystery_bus<2>" LOC = "T11" ; +#NET "mystery_bus<1>" LOC = "C4" ; +#NET "mystery_bus<0>" LOC = "E7" ; +NET "reset_n" LOC = "D5" ; +NET "PPS_IN" LOC = "M14" ; +NET "reset_codec" LOC = "B14" ; + +## GPIF +NET "GPIF_D<15>" LOC = "P7" ; +NET "GPIF_D<14>" LOC = "N8" ; +NET "GPIF_D<13>" LOC = "T5" ; +NET "GPIF_D<12>" LOC = "T6" ; +NET "GPIF_D<11>" LOC = "N6" ; +NET "GPIF_D<10>" LOC = "P5" ; +NET "GPIF_D<9>" LOC = "R3" ; +NET "GPIF_D<8>" LOC = "T3" ; +NET "GPIF_D<7>" LOC = "N12" ; +NET "GPIF_D<6>" LOC = "P13" ; +NET "GPIF_D<5>" LOC = "P11" ; +NET "GPIF_D<4>" LOC = "R9" ; +NET "GPIF_D<3>" LOC = "T9" ; +NET "GPIF_D<2>" LOC = "N9" ; +NET "GPIF_D<1>" LOC = "P9" ; +NET "GPIF_D<0>" LOC = "P8" ; + +NET "GPIF_CTL<3>" LOC = "N5" ; +NET "GPIF_CTL<2>" LOC = "M11" ; +NET "GPIF_CTL<1>" LOC = "M9" ; +NET "GPIF_CTL<0>" LOC = "M7" ; + +NET "GPIF_RDY<3>" LOC = "N11" ; +NET "GPIF_RDY<2>" LOC = "T10" ; +NET "GPIF_RDY<1>" LOC = "T4" ; +NET "GPIF_RDY<0>" LOC = "R5" ; + +NET "FX2_PA7_FLAGD" LOC = "P12" ; +NET "FX2_PA6_PKTEND" LOC = "R11" ; +NET "FX2_PA2_SLOE" LOC = "P10" ; + +NET "IFCLK" LOC = "T8" ; + +## LEDs +NET "debug_led<2>" LOC = "R2" ; +NET "debug_led<1>" LOC = "N4" ; +NET "debug_led<0>" LOC = "P4" ; + +## Debug bus +NET "debug_clk<0>" LOC = "K15" ; +NET "debug_clk<1>" LOC = "K14" ; +NET "debug<0>" LOC = "K16" ; +NET "debug<1>" LOC = "J16" ; +NET "debug<2>" LOC = "C16" ; +NET "debug<3>" LOC = "C15" ; +NET "debug<4>" LOC = "E13" ; +NET "debug<5>" LOC = "D14" ; +NET "debug<6>" LOC = "D16" ; +NET "debug<7>" LOC = "D15" ; +NET "debug<8>" LOC = "E14" ; +NET "debug<9>" LOC = "F13" ; +NET "debug<10>" LOC = "G13" ; +NET "debug<11>" LOC = "F14" ; +NET "debug<12>" LOC = "E16" ; +NET "debug<13>" LOC = "F15" ; +NET "debug<14>" LOC = "H13" ; +NET "debug<15>" LOC = "G14" ; +NET "debug<16>" LOC = "G16" ; +NET "debug<17>" LOC = "F16" ; +NET "debug<18>" LOC = "J12" ; +NET "debug<19>" LOC = "J13" ; +NET "debug<20>" LOC = "L14" ; +NET "debug<21>" LOC = "L16" ; +NET "debug<22>" LOC = "M15" ; +NET "debug<23>" LOC = "M16" ; +NET "debug<24>" LOC = "L13" ; +NET "debug<25>" LOC = "K13" ; +NET "debug<26>" LOC = "P16" ; +NET "debug<27>" LOC = "N16" ; +NET "debug<28>" LOC = "R15" ; +NET "debug<29>" LOC = "P15" ; +NET "debug<30>" LOC = "N13" ; +NET "debug<31>" LOC = "N14" ; + +## ADC +NET "adc<11>" LOC = "B15" ; +NET "adc<10>" LOC = "A8" ; +NET "adc<9>" LOC = "B8" ; +NET "adc<8>" LOC = "C8" ; +NET "adc<7>" LOC = "D8" ; +NET "adc<6>" LOC = "C9" ; +NET "adc<5>" LOC = "A9" ; +NET "adc<4>" LOC = "C10" ; +NET "adc<3>" LOC = "D9" ; +NET "adc<2>" LOC = "A3" ; +NET "adc<1>" LOC = "B3" ; +NET "adc<0>" LOC = "A4" ; +NET "RXSYNC" LOC = "D10" ; + +## DAC +NET "TXBLANK" LOC = "K1" ; +NET "TXSYNC" LOC = "J2" ; +NET "dac<0>" LOC = "J1" ; +NET "dac<1>" LOC = "H3" ; +NET "dac<2>" LOC = "J3" ; +NET "dac<3>" LOC = "G2" ; +NET "dac<4>" LOC = "H1" ; +NET "dac<5>" LOC = "N3" ; +NET "dac<6>" LOC = "M4" ; +NET "dac<7>" LOC = "R1" ; +NET "dac<8>" LOC = "P2" ; +NET "dac<9>" LOC = "P1" ; +NET "dac<10>" LOC = "M1" ; +NET "dac<11>" LOC = "N1" ; +NET "dac<12>" LOC = "M3" ; +NET "dac<13>" LOC = "L4" ; + +## TX DB +NET "io_tx<0>" LOC = "K4" ; +NET "io_tx<1>" LOC = "L3" ; +NET "io_tx<2>" LOC = "L2" ; +NET "io_tx<3>" LOC = "F1" ; +NET "io_tx<4>" LOC = "F3" ; +NET "io_tx<5>" LOC = "G3" ; +NET "io_tx<6>" LOC = "E3" ; +NET "io_tx<7>" LOC = "E2" ; +NET "io_tx<8>" LOC = "E4" ; +NET "io_tx<9>" LOC = "F4" ; +NET "io_tx<10>" LOC = "D1" ; +NET "io_tx<11>" LOC = "E1" ; +NET "io_tx<12>" LOC = "D4" ; +NET "io_tx<13>" LOC = "D3" ; +NET "io_tx<14>" LOC = "C2" ; +NET "io_tx<15>" LOC = "C1" ; + +## RX DB +NET "io_rx<0>" LOC = "D7" ; +NET "io_rx<1>" LOC = "C6" ; +NET "io_rx<2>" LOC = "A6" ; +NET "io_rx<3>" LOC = "B6" ; +NET "io_rx<4>" LOC = "E9" ; +NET "io_rx<5>" LOC = "A7" ; +NET "io_rx<6>" LOC = "C7" ; +NET "io_rx<7>" LOC = "B10" ; +NET "io_rx<8>" LOC = "A10" ; +NET "io_rx<9>" LOC = "C11" ; +NET "io_rx<10>" LOC = "A11" ; +NET "io_rx<11>" LOC = "D11" ; +NET "io_rx<12>" LOC = "B12" ; +NET "io_rx<13>" LOC = "A12" ; +NET "io_rx<14>" LOC = "A14" ; +NET "io_rx<15>" LOC = "A13" ; + +## SPI +#NET "SEN_AUX" LOC = "C12" ; +#NET "SCLK_AUX" LOC = "D12" ; +#NET "MISO_AUX" LOC = "J5" ; +NET "SCLK_CODEC" LOC = "K3" ; +NET "SEN_CODEC" LOC = "D13" ; +NET "MOSI_CODEC" LOC = "C13" ; +NET "MISO_CODEC" LOC = "G4" ; + +NET "MISO_RX_DB" LOC = "E6" ; +NET "SEN_RX_DB" LOC = "B4" ; +NET "MOSI_RX_DB" LOC = "A5" ; +NET "SCLK_RX_DB" LOC = "C5" ; + +NET "MISO_TX_DB" LOC = "J4" ; +NET "SEN_TX_DB" LOC = "N2" ; +NET "MOSI_TX_DB" LOC = "L1" ; +NET "SCLK_TX_DB" LOC = "G1" ; + +## Dedicated pins +#NET "TMS" LOC = "B2" ; +#NET "TDO" LOC = "B16" ; +#NET "TDI" LOC = "B1" ; +#NET "TCK" LOC = "A15" ; + +##NET "fpga_cfg_prog_b" LOC = "A2" ; +##NET "fpga_cfg_done" LOC = "T15" ; diff --git a/usrp2/top/B100/u1plus.v b/usrp2/top/B100/u1plus.v new file mode 100644 index 000000000..9aafef3ce --- /dev/null +++ b/usrp2/top/B100/u1plus.v @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u1plus + (input CLK_FPGA_P, input CLK_FPGA_N, // Diff + output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + output FPGA_TXD, input FPGA_RXD, + + // GPIF + inout [15:0] GPIF_D, input [3:0] GPIF_CTL, output [3:0] GPIF_RDY, + output FX2_PA7_FLAGD, output FX2_PA6_PKTEND, output FX2_PA2_SLOE, + input IFCLK, + + inout SDA_FPGA, inout SCL_FPGA, // I2C + + output SCLK_TX_DB, output SEN_TX_DB, output MOSI_TX_DB, input MISO_TX_DB, // DB TX SPI + output SCLK_RX_DB, output SEN_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, // DB TX SPI + output SCLK_CODEC, output SEN_CODEC, output MOSI_CODEC, input MISO_CODEC, // AD9862 main SPI + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, + + inout [15:0] io_tx, inout [15:0] io_rx, + + output [13:0] dac, output TXSYNC, output TXBLANK, + input [11:0] adc, input RXSYNC, + + input PPS_IN, + input reset_n, output reset_codec + ); + + assign reset_codec = 1; // Believed to be active low + + // ///////////////////////////////////////////////////////////////////////// + // Clocking + wire clk_fpga, clk_fpga_in, reset; + + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) + clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + + BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga)); + + reset_sync reset_sync(.clk(clk_fpga), .reset_in(~reset_n), .reset_out(reset)); + + // ///////////////////////////////////////////////////////////////////////// + // SPI + wire mosi, sclk, miso; + assign { SCLK_TX_DB, MOSI_TX_DB } = ~SEN_TX_DB ? {sclk,mosi} : 2'b0; + assign { SCLK_RX_DB, MOSI_RX_DB } = ~SEN_RX_DB ? {sclk,mosi} : 2'b0; + assign { SCLK_CODEC, MOSI_CODEC } = ~SEN_CODEC ? {sclk,mosi} : 2'b0; + assign miso = (~SEN_TX_DB & MISO_TX_DB) | (~SEN_RX_DB & MISO_RX_DB) | + (~SEN_CODEC & MISO_CODEC); + + // ///////////////////////////////////////////////////////////////////////// + // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL + + assign TXBLANK = 0; + wire [13:0] tx_i, tx_q; + + genvar i; + generate + for(i=0;i<14;i=i+1) + begin : gen_dacout + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_inst (.Q(dac[i]), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(tx_i[i]), // 1-bit data input (associated with C0) + .D1(tx_q[i]), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + end // block: gen_dacout + endgenerate + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(1'b0), // 1-bit data input (associated with C0) + .D1(1'b1), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + + // ///////////////////////////////////////////////////////////////////////// + // RX ADC -- handles deinterleaving + + reg [11:0] rx_i, rx_q; + wire [11:0] rx_a, rx_b; + + genvar j; + generate + for(j=0;j<12;j=j+1) + begin : gen_adcin + IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1 + .INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + IDDR2_inst (.Q0(rx_a[j]), // 1-bit output captured with C0 clock + .Q1(rx_b[j]), // 1-bit output captured with C1 clock + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D(adc[j]), // 1-bit DDR data input + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + end // block: gen_adcin + endgenerate + + IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1 + .INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + IDDR2_sync (.Q0(rxsync_0), // 1-bit output captured with C0 clock + .Q1(rxsync_1), // 1-bit output captured with C1 clock + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D(RXSYNC), // 1-bit DDR data input + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + + always @(posedge clk_fpga) + if(rxsync_0) + begin + rx_i <= rx_b; + rx_q <= rx_a; + end + else + begin + rx_i <= rx_a; + rx_q <= rx_b; + end + + // ///////////////////////////////////////////////////////////////////////// + // Main U1E Core + u1plus_core u1p_c(.clk_fpga(clk_fpga), .rst_fpga(reset), + .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), + .gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_rdy(GPIF_RDY), + .gpif_misc({FX2_PA7_FLAGD,FX2_PA6_PKTEND,FX2_PA2_SLOE}), + .gpif_clk(IFCLK), + + .db_sda(SDA_FPGA), .db_scl(SCL_FPGA), + .sclk(sclk), .sen({SEN_CODEC,SEN_TX_DB,SEN_RX_DB}), .mosi(mosi), .miso(miso), + .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), + .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel), + .io_tx(io_tx), .io_rx(io_rx), + .tx_i(tx_i), .tx_q(tx_q), + .rx_i(rx_i), .rx_q(rx_q), + .pps_in(PPS_IN) ); + +endmodule // u1plus diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v new file mode 100644 index 000000000..898f5950c --- /dev/null +++ b/usrp2/top/B100/u1plus_core.v @@ -0,0 +1,392 @@ + + +module u1plus_core + (input clk_fpga, input rst_fpga, + output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + output debug_txd, input debug_rxd, + + // GPIF + inout [15:0] gpif_d, input [3:0] gpif_ctl, output [3:0] gpif_rdy, + output [2:0] gpif_misc, input gpif_clk, + + inout db_sda, inout db_scl, + output sclk, output [15:0] sen, output mosi, input miso, + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, + output tx_underrun, output rx_overrun, + inout [15:0] io_tx, inout [15:0] io_rx, + output [13:0] tx_i, output [13:0] tx_q, + input [11:0] rx_i, input [11:0] rx_q, + input pps_in + ); + + localparam TXFIFOSIZE = 11; + localparam RXFIFOSIZE = 11; + + // 64 total regs in address space + localparam SR_RX_CTRL = 0; // 9 regs (+0 to +8) + localparam SR_RX_DSP = 16; // 7 regs (+0 to +6) + localparam SR_TX_CTRL = 24; // 6 regs (+0 to +5) + localparam SR_TX_DSP = 32; // 5 regs (+0 to +4) + localparam SR_TIME64 = 40; // 6 regs (+0 to +5) + localparam SR_CLEAR_RX_FIFO = 48; // 1 reg + localparam SR_CLEAR_TX_FIFO = 49; // 1 reg + localparam SR_GLOBAL_RESET = 50; // 1 reg + localparam SR_REG_TEST32 = 52; // 1 reg + + wire [7:0] COMPAT_NUM = 8'd3; + + wire wb_clk = clk_fpga; + wire wb_rst, global_reset; + + wire pps_int; + wire [63:0] vita_time, vita_time_pps; + reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; + wire [7:0] test_rate; + wire [3:0] test_ctrl; + + wire [7:0] set_addr; + wire [31:0] set_data; + wire set_stb; + + wire [31:0] debug0; + wire [31:0] debug1; + + wire [31:0] debug_vt; + wire gpif_rst; + + wire rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc; + reg [7:0] frames_per_packet; + + assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp; + assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp; + + setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(global_reset)); + + reset_sync reset_sync_wb(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(wb_rst)); + reset_sync reset_sync_gp(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(gpif_rst)); + wire [15:0] test_len; + + // ///////////////////////////////////////////////////////////////////////////////////// + // GPIF Slave to Wishbone Master + localparam dw = 16; + localparam aw = 11; + localparam sw = 2; + + wire [dw-1:0] m0_dat_mosi, m0_dat_miso; + wire [aw-1:0] m0_adr; + wire [sw-1:0] m0_sel; + wire m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty; + + wire [31:0] debug_gpmc; + + wire [35:0] tx_data, rx_data, tx_err_data; + wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, + tx_err_src_rdy, tx_err_dst_rdy; + + wire bus_error; + wire clear_tx, clear_rx; + + setting_reg #(.my_addr(SR_CLEAR_RX_FIFO), .width(1)) sr_clear_rx + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_rx)); + + setting_reg #(.my_addr(SR_CLEAR_TX_FIFO), .width(1)) sr_clear_tx + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_tx)); + + gpif #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE)) + gpif (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_d(gpif_d), + .gpif_ctl(gpif_ctl), .gpif_rdy(gpif_rdy), .gpif_misc(gpif_misc), + + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), + .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), + .wb_ack_i(m0_ack), .triggers(8'd0), + + .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx), + .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), + .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), + .tx_err_data_i(tx_err_data), .tx_err_src_rdy_i(tx_err_src_rdy), .tx_err_dst_rdy_o(tx_err_dst_rdy), + + .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc), + + .frames_per_packet(frames_per_packet), .test_len(test_len), .test_rate(test_rate), .test_ctrl(test_ctrl), + .debug0(debug0), .debug1(debug1)); + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX + wire [31:0] sample_rx; + wire strobe_rx, run_rx; + wire [31:0] debug_rx_dsp, vr_debug; + + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx + (.clk(wb_clk),.rst(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a({rx_i,2'b0}),.adc_ovf_a(0),.adc_b({rx_q,2'b0}),.adc_ovf_b(0), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + vita_rx_chain #(.BASE(SR_RX_CTRL), .UNIT(0), .FIFOSIZE(9), .PROT_ENG_FLAGS(0)) vita_rx_chain + (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time), .overrun(rx_overrun_dsp), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .rx_data_o(rx_data), .rx_dst_rdy_i(rx_dst_rdy), .rx_src_rdy_o(rx_src_rdy), + .debug(vr_debug) ); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [15:0] tx_i_int, tx_q_int; + wire run_tx; + + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(1), .DO_FLOW_CONTROL(0), + .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0), + .DSP_NUMBER(0)) + vita_tx_chain + (.clk(wb_clk), .reset(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), + .dac_a(tx_i_int),.dac_b(tx_q_int), + .underrun(tx_underrun_dsp), .run(run_tx), + .debug(debug_vt)); + + assign tx_i = tx_i_int[15:2]; + assign tx_q = tx_q_int[15:2]; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Wishbone Intercon, single master + wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, + s4_dat_mosi, s5_dat_mosi, s4_dat_miso, s5_dat_miso, s6_dat_mosi, s7_dat_mosi, s6_dat_miso, s7_dat_miso, + s8_dat_mosi, s9_dat_mosi, s8_dat_miso, s9_dat_miso, sa_dat_mosi, sb_dat_mosi, sa_dat_miso, sb_dat_miso, + sc_dat_mosi, sd_dat_mosi, sc_dat_miso, sd_dat_miso, se_dat_mosi, sf_dat_mosi, se_dat_miso, sf_dat_miso; + wire [aw-1:0] s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr; + wire [aw-1:0] s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; + wire [sw-1:0] s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel; + wire [sw-1:0] s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; + wire s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack; + wire s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; + wire s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb; + wire s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; + wire s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc; + wire s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; + wire s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we; + wire s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we, sf_we; + + wb_1master #(.dw(dw), .aw(aw), .sw(sw), .decode_w(4), + .s0_addr(4'h0), .s0_mask(4'hF), .s1_addr(4'h1), .s1_mask(4'hF), + .s2_addr(4'h2), .s2_mask(4'hF), .s3_addr(4'h3), .s3_mask(4'hF), + .s4_addr(4'h4), .s4_mask(4'hF), .s5_addr(4'h5), .s5_mask(4'hF), + .s6_addr(4'h6), .s6_mask(4'hF), .s7_addr(4'h7), .s7_mask(4'hF), + .s8_addr(4'h8), .s8_mask(4'hE), .s9_addr(4'hf), .s9_mask(4'hF), // slave 8 is double wide + .sa_addr(4'ha), .sa_mask(4'hF), .sb_addr(4'hb), .sb_mask(4'hF), + .sc_addr(4'hc), .sc_mask(4'hF), .sd_addr(4'hd), .sd_mask(4'hF), + .se_addr(4'he), .se_mask(4'hF), .sf_addr(4'hf), .sf_mask(4'hF)) + wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_miso),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_mosi), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_mosi),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_miso),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_mosi),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_miso),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_mosi),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_miso),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_mosi),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_miso),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_mosi),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_miso),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_mosi),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_miso),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_mosi),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_miso),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_mosi),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_miso),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_mosi),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_miso),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_mosi),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_miso),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_mosi),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_miso),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_mosi),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_miso),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_mosi),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_miso),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_mosi),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_miso),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_mosi),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_miso),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), + .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); + + assign s5_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; + assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 0, Misc LEDs, Switches, controls + + localparam REG_LEDS = 7'd0; // out + localparam REG_CGEN_CTRL = 7'd4; // out + localparam REG_CGEN_ST = 7'd6; // in + localparam REG_TEST = 7'd8; // out + localparam REG_RX_FRAMELEN = 7'd10; // in + localparam REG_TX_FRAMELEN = 7'd12; // out + localparam REG_XFER_RATE = 7'd14; // out + localparam REG_COMPAT = 7'd16; // in + + always @(posedge wb_clk) + if(wb_rst) + begin + reg_leds <= 0; + reg_cgen_ctrl <= 2'b11; + reg_test <= 0; + xfer_rate <= 0; + frames_per_packet <= 0; + end + else + if(s0_cyc & s0_stb & s0_we) + case(s0_adr[6:0]) + REG_LEDS : + reg_leds <= s0_dat_mosi; + REG_CGEN_CTRL : + reg_cgen_ctrl <= s0_dat_mosi; + REG_TEST : + reg_test <= s0_dat_mosi; + REG_RX_FRAMELEN : + frames_per_packet <= s0_dat_mosi[7:0]; + REG_XFER_RATE : + xfer_rate <= s0_dat_mosi; + endcase // case (s0_adr[6:0]) + + assign test_ctrl = xfer_rate[11:8]; + assign test_rate = xfer_rate[7:0]; + assign test_len = reg_test[15:0]; + + assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board + assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; + + assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : + (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : + (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : + (s0_adr[6:0] == REG_TEST) ? reg_test : + (s0_adr[6:0] == REG_COMPAT) ? { 8'd0, COMPAT_NUM } : + 16'hBEEF; + + assign s0_ack = s0_stb & s0_cyc; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 1, UART + // depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack), + .adr_i(s1_adr[3:1]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso), + .rx_int_o(),.tx_int_o(), + .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o()); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 2, SPI + + spi_top16 shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_mosi), + .wb_dat_o(s2_dat_miso),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(), + .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // Slave 3, I2C + + wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o; + i2c_master_top #(.ARST_LVL(1)) i2c + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[3:1]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_miso[15:8] = 8'd0; + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + + wire [31:0] atr_lines; + wire [31:0] debug_gpio_0, debug_gpio_1; + + nsgpio16LE + nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio( {io_tx,io_rx} ) ); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #8 + 9 + + // only have 64 regs, 32 bits each with current setup... + settings_bus_16LE #(.AWIDTH(11),.RWIDTH(6)) settings_bus_16LE + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr[10:0]),.wb_dat_i(s8_dat_mosi), + .wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack), + .strobe(set_stb),.addr(set_addr),.data(set_data) ); + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller -- Slave #6 + + atr_controller16 atr_controller16 + (.clk_i(wb_clk), .rst_i(wb_rst), + .adr_i(s6_adr[5:0]), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), + .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), + .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines)); + + // ///////////////////////////////////////////////////////////////////////// + // Readback mux 32 -- Slave #7 + + wire [31:0] reg_test32; + + setting_reg #(.my_addr(SR_REG_TEST32)) sr_reg_test32 + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(reg_test32),.changed()); + + wb_readback_mux_16LE readback_mux_32 + (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s7_stb), + .wb_adr_i({5'b0,s7_adr}), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack), + + .word00(vita_time[63:32]), .word01(vita_time[31:0]), + .word02(vita_time_pps[63:32]), .word03(vita_time_pps[31:0]), + .word04(reg_test32), .word05(32'b0), + .word06(32'b0), .word07(32'b0), + .word08(32'b0), .word09(32'b0), + .word10(32'b0), .word11(32'b0), + .word12(32'b0), .word13(32'b0), + .word14(32'b0), .word15(32'b0) + ); + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing + + time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit + (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), + .exp_time_in(0)); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Debug circuitry + + assign debug_clk = { gpif_clk, clk_fpga }; + assign debug = debug0; + assign debug_gpio_0 = 0; + assign debug_gpio_1 = 0; + //assign {io_tx,io_rx} = {debug1}; + +endmodule // u1plus_core diff --git a/usrp2/top/E1x0/.gitignore b/usrp2/top/E1x0/.gitignore new file mode 100644 index 000000000..8d872713e --- /dev/null +++ b/usrp2/top/E1x0/.gitignore @@ -0,0 +1,6 @@ +*~ +build +*.log +*.cmd +tb_u1e +*.lxt diff --git a/usrp2/top/E1x0/Makefile b/usrp2/top/E1x0/Makefile new file mode 100644 index 000000000..5d721979b --- /dev/null +++ b/usrp2/top/E1x0/Makefile @@ -0,0 +1,100 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u1e +BUILD_DIR = $(abspath build$(ISE)) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../gpmc/Makefile.srcs + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u1e_core.v \ +u1e.v \ +u1e.ucf \ +timing.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ +$(GPMC_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/E1x0/Makefile.passthru b/usrp2/top/E1x0/Makefile.passthru new file mode 100644 index 000000000..f2d835608 --- /dev/null +++ b/usrp2/top/E1x0/Makefile.passthru @@ -0,0 +1,98 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = passthru +BUILD_DIR = $(abspath build$(ISE)) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../gpmc/Makefile.srcs + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +passthru.v \ +passthru.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) \ +$(GPMC_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/E1x0/README b/usrp2/top/E1x0/README new file mode 100644 index 000000000..14c7a4955 --- /dev/null +++ b/usrp2/top/E1x0/README @@ -0,0 +1,4 @@ + +make clean +make sim +./tb_u1e -lxt2 diff --git a/usrp2/top/E1x0/cmdfile b/usrp2/top/E1x0/cmdfile new file mode 100644 index 000000000..291c723b8 --- /dev/null +++ b/usrp2/top/E1x0/cmdfile @@ -0,0 +1,20 @@ + +# My stuff +-y . +-y ../../control_lib +-y ../../control_lib/newfifo +-y ../../sdr_lib +-y ../../timing +-y ../../coregen +-y ../../gpmc + +# Models +-y ../../models +-y /opt/Xilinx/10.1/ISE/verilog/src/unisims + +# Open Cores +-y ../../opencores/spi/rtl/verilog ++incdir+../../opencores/spi/rtl/verilog +-y ../../opencores/i2c/rtl/verilog ++incdir+../../opencores/i2c/rtl/verilog + diff --git a/usrp2/top/E1x0/core_compile b/usrp2/top/E1x0/core_compile new file mode 100755 index 000000000..dc0cd081e --- /dev/null +++ b/usrp2/top/E1x0/core_compile @@ -0,0 +1,3 @@ +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models + + diff --git a/usrp2/top/E1x0/make.sim b/usrp2/top/E1x0/make.sim new file mode 100644 index 000000000..1c163884c --- /dev/null +++ b/usrp2/top/E1x0/make.sim @@ -0,0 +1,7 @@ +all: sim + +sim: + iverilog -Wimplicit -Wportbind -c cmdfile tb_u1e.v -o tb_u1e + +clean: + rm -f tb_u1e *.vcd *.lxt a.out diff --git a/usrp2/top/E1x0/passthru.ucf b/usrp2/top/E1x0/passthru.ucf new file mode 100644 index 000000000..64e6f0440 --- /dev/null +++ b/usrp2/top/E1x0/passthru.ucf @@ -0,0 +1,6 @@ +NET "overo_gpio145" LOC = "C7" ; +NET "cgen_mosi" LOC = "E22" ; +NET "cgen_sclk" LOC = "J19" ; +NET "cgen_sen_b" LOC = "H20" ; +NET "fpga_cfg_din" LOC = "W17" ; +NET "fpga_cfg_cclk" LOC = "V17" ; diff --git a/usrp2/top/E1x0/passthru.v b/usrp2/top/E1x0/passthru.v new file mode 100644 index 000000000..12e4db017 --- /dev/null +++ b/usrp2/top/E1x0/passthru.v @@ -0,0 +1,18 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module passthru + (input overo_gpio145, + output cgen_sclk, + output cgen_sen_b, + output cgen_mosi, + input fpga_cfg_din, + input fpga_cfg_cclk + ); + + assign cgen_sclk = fpga_cfg_cclk; + assign cgen_sen_b = overo_gpio145; + assign cgen_mosi = fpga_cfg_din; + + +endmodule // passthru diff --git a/usrp2/top/E1x0/tb_u1e.v b/usrp2/top/E1x0/tb_u1e.v new file mode 100644 index 000000000..5fc8134fb --- /dev/null +++ b/usrp2/top/E1x0/tb_u1e.v @@ -0,0 +1,41 @@ +`timescale 1ps / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module tb_u1e(); + + wire [2:0] debug_led; + wire [31:0] debug; + wire [1:0] debug_clk; + + xlnx_glbl glbl (.GSR(),.GTS()); + + initial begin + $dumpfile("tb_u1e.lxt"); + $dumpvars(0,tb_u1e); + end + + // GPMC + wire EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE; + wire [15:0] EM_D; + wire [10:1] EM_A; + wire [1:0] EM_NBE; + + reg clk_fpga = 0, rst_fpga = 1; + always #15625 clk_fpga = ~clk_fpga; + + initial #200000 + @(posedge clk_fpga) + rst_fpga <= 0; + + u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(rst_fpga), + .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); + + gpmc_model_async gpmc_model_async + (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); + +endmodule // tb_u1e diff --git a/usrp2/top/E1x0/timing.ucf b/usrp2/top/E1x0/timing.ucf new file mode 100644 index 000000000..8df28c9d3 --- /dev/null +++ b/usrp2/top/E1x0/timing.ucf @@ -0,0 +1,13 @@ + +NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; + + + + +#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; +#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; +#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; + +#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; +#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; diff --git a/usrp2/top/E1x0/u1e.ucf b/usrp2/top/E1x0/u1e.ucf new file mode 100644 index 000000000..0c487a601 --- /dev/null +++ b/usrp2/top/E1x0/u1e.ucf @@ -0,0 +1,259 @@ + +NET "CLK_FPGA_P" LOC = "Y11" ; +NET "CLK_FPGA_N" LOC = "Y10" ; + +## GPMC +NET "EM_D<15>" LOC = "D13" ; +NET "EM_D<14>" LOC = "D15" ; +NET "EM_D<13>" LOC = "C16" ; +NET "EM_D<12>" LOC = "B20" ; +NET "EM_D<11>" LOC = "A19" ; +NET "EM_D<10>" LOC = "A17" ; +NET "EM_D<9>" LOC = "E15" ; +NET "EM_D<8>" LOC = "F15" ; +NET "EM_D<7>" LOC = "E16" ; +NET "EM_D<6>" LOC = "F16" ; +NET "EM_D<5>" LOC = "B17" ; +NET "EM_D<4>" LOC = "C17" ; +NET "EM_D<3>" LOC = "B19" ; +NET "EM_D<2>" LOC = "D19" ; +NET "EM_D<1>" LOC = "C19" ; +NET "EM_D<0>" LOC = "A20" ; + +NET "EM_A<10>" LOC = "C14" ; +NET "EM_A<9>" LOC = "C10" ; +NET "EM_A<8>" LOC = "C5" ; +NET "EM_A<7>" LOC = "A18" ; +NET "EM_A<6>" LOC = "A15" ; +NET "EM_A<5>" LOC = "A12" ; +NET "EM_A<4>" LOC = "A10" ; +NET "EM_A<3>" LOC = "E7" ; +NET "EM_A<2>" LOC = "A7" ; +NET "EM_A<1>" LOC = "C15" ; + +NET "EM_NCS6" LOC = "E17" ; +NET "EM_NCS5" LOC = "E10" ; +NET "EM_NCS4" LOC = "E6" ; +#NET "EM_NCS1" LOC = "D18" ; +#NET "EM_NCS0" LOC = "D17" ; + +NET "EM_CLK" LOC = "F11" ; +NET "EM_WAIT0" LOC = "F14" ; +NET "EM_NBE<1>" LOC = "D14" ; +NET "EM_NBE<0>" LOC = "A13" ; +NET "EM_NWE" LOC = "B13" ; +NET "EM_NOE" LOC = "A14" ; +#NET "EM_NADV_ALE" LOC = "B15" ; +#NET "EM_NWP" LOC = "F13" ; + +## Overo GPIO +NET "overo_gpio0" LOC = "F9" ; # MISC GPIO for debug +NET "overo_gpio14" LOC = "C4" ; # MISC GPIO for debug +NET "overo_gpio21" LOC = "D5" ; # MISC GPIO for debug +NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug +NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug +NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug +NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug + +NET "overo_gpio127" LOC = "C8" ; # Changed name to gpio10 +NET "overo_gpio128" LOC = "G8" ; # Changed name to gpio186 + +NET "overo_gpio144" LOC = "A5" ; # tx_have_space +NET "overo_gpio145" LOC = "C7" ; # tx_underrun +NET "overo_gpio146" LOC = "A6" ; # rx_have_data +NET "overo_gpio147" LOC = "B6" ; # rx_overrun +NET "overo_gpio163" LOC = "D7" ; # MISC GPIO for debug +NET "overo_gpio170" LOC = "E8" ; # MISC GPIO for debug +NET "overo_gpio176" LOC = "B4" ; # MISC GPIO for debug + +## Overo UART +#NET "overo_txd1" LOC = "C6" ; +#NET "overo_rxd1" LOC = "D6" ; + +## FTDI UART to USB converter +NET "FPGA_TXD" LOC = "G19" ; +NET "FPGA_RXD" LOC = "F20" ; + +#NET "SYSEN" LOC = "C11" ; + +## I2C +NET "db_scl" LOC = "F19" ; +NET "db_sda" LOC = "F18" ; + +## SPI +### DBoard SPI +NET "db_sclk_rx" LOC = "D21" ; +NET "db_miso_rx" LOC = "D22" ; +NET "db_mosi_rx" LOC = "D20" ; +NET "db_sen_rx" LOC = "E19" ; +NET "db_sclk_tx" LOC = "F21" ; +NET "db_miso_tx" LOC = "E20" ; +NET "db_mosi_tx" LOC = "G17" ; +NET "db_sen_tx" LOC = "G18" ; + +### AD9862 SPI and aux SPI Interfaces +#NET "aux_sdi_codec" LOC = "G3" ; +#NET "aux_sdo_codec" LOC = "F3" ; +#NET "aux_sclk_codec" LOC = "C1" ; +NET "sen_codec" LOC = "F5" |IOSTANDARD = LVCMOS33; +NET "mosi_codec" LOC = "F4" |IOSTANDARD = LVCMOS33; +NET "miso_codec" LOC = "H4" ; +NET "sclk_codec" LOC = "H3" |IOSTANDARD = LVCMOS33; + +### Clock Gen SPI +NET "cgen_miso" LOC = "F22" ; +NET "cgen_mosi" LOC = "E22" ; +NET "cgen_sclk" LOC = "J19" ; +NET "cgen_sen_b" LOC = "H20" ; + +## Clock gen control +NET "cgen_st_status" LOC = "P20" ; +NET "cgen_st_ld" LOC = "R17" ; +NET "cgen_st_refmon" LOC = "P17" ; +NET "cgen_sync_b" LOC = "U18" ; +NET "cgen_ref_sel" LOC = "U19" ; + +## Debug pins +NET "debug_led<3>" LOC = "Y15" ; +NET "debug_led<2>" LOC = "K16" ; +NET "debug_led<1>" LOC = "J17" ; +NET "debug_led<0>" LOC = "H22" ; +NET "debug<0>" LOC = "G22" ; +NET "debug<1>" LOC = "H17" ; +NET "debug<2>" LOC = "H18" ; +NET "debug<3>" LOC = "K20" ; +NET "debug<4>" LOC = "J20" ; +NET "debug<5>" LOC = "K19" ; +NET "debug<6>" LOC = "K18" ; +NET "debug<7>" LOC = "L22" ; +NET "debug<8>" LOC = "K22" ; +NET "debug<9>" LOC = "N22" ; +NET "debug<10>" LOC = "M22" ; +NET "debug<11>" LOC = "N20" ; +NET "debug<12>" LOC = "N19" ; +NET "debug<13>" LOC = "R22" ; +NET "debug<14>" LOC = "P22" ; +NET "debug<15>" LOC = "N17" ; +NET "debug<16>" LOC = "P16" ; +NET "debug<17>" LOC = "U22" ; +NET "debug<18>" LOC = "P19" ; +NET "debug<19>" LOC = "R18" ; +NET "debug<20>" LOC = "U20" ; +NET "debug<21>" LOC = "T20" ; +NET "debug<22>" LOC = "R19" ; +NET "debug<23>" LOC = "R20" ; +NET "debug<24>" LOC = "W22" ; +NET "debug<25>" LOC = "Y22" ; +NET "debug<26>" LOC = "T18" ; +NET "debug<27>" LOC = "T17" ; +NET "debug<28>" LOC = "W19" ; +NET "debug<29>" LOC = "V20" ; +NET "debug<30>" LOC = "Y21" ; +NET "debug<31>" LOC = "AA22" ; +NET "debug_clk<0>" LOC = "N18" ; +NET "debug_clk<1>" LOC = "M17" ; + +NET "debug_pb" LOC = "C22" ; + +#NET "reset_codec" LOC = "C2" ; + +NET "RXSYNC" LOC = "F2" ; +NET "DB<11>" LOC = "G6" ; +NET "DB<10>" LOC = "G5" ; +NET "DB<9>" LOC = "E4" ; +NET "DB<8>" LOC = "E3" ; +NET "DB<7>" LOC = "H6" ; +NET "DB<6>" LOC = "H5" ; +NET "DB<5>" LOC = "H1" ; +NET "DB<4>" LOC = "G1" ; +NET "DB<3>" LOC = "K5" ; +NET "DB<2>" LOC = "K4" ; +NET "DB<1>" LOC = "H2" ; +NET "DB<0>" LOC = "L5" ; + +NET "DA<11>" LOC = "K6" ; +NET "DA<10>" LOC = "K3" ; +NET "DA<9>" LOC = "K2" ; +NET "DA<8>" LOC = "N1" ; +NET "DA<7>" LOC = "N5" ; +NET "DA<6>" LOC = "N6" ; +NET "DA<5>" LOC = "P2" ; +NET "DA<4>" LOC = "P1" ; +NET "DA<3>" LOC = "R6" ; +NET "DA<2>" LOC = "P6" ; +NET "DA<1>" LOC = "R1" ; +NET "DA<0>" LOC = "R2" ; + +NET "TX<13>" LOC = "T6" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<12>" LOC = "U1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<11>" LOC = "T1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<10>" LOC = "R5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<9>" LOC = "V1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<8>" LOC = "U2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<7>" LOC = "T4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<6>" LOC = "R3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<5>" LOC = "W1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<4>" LOC = "Y1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<3>" LOC = "V3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<2>" LOC = "V4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<1>" LOC = "W2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<0>" LOC = "W3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TXSYNC" LOC = "U5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TXBLANK" LOC = "U4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; + +NET "PPS_IN" LOC = "M5" ; + +NET "io_tx<0>" LOC = "AB20" ; +NET "io_tx<1>" LOC = "Y17" ; +NET "io_tx<2>" LOC = "Y16" ; +NET "io_tx<3>" LOC = "U16" ; +NET "io_tx<4>" LOC = "V16" ; +NET "io_tx<5>" LOC = "AB19" ; +NET "io_tx<6>" LOC = "AA19" ; +NET "io_tx<7>" LOC = "U14" ; +NET "io_tx<8>" LOC = "U15" ; +NET "io_tx<9>" LOC = "AB17" ; +NET "io_tx<10>" LOC = "AB18" ; +NET "io_tx<11>" LOC = "Y13" ; +NET "io_tx<12>" LOC = "W14" ; +NET "io_tx<13>" LOC = "U13" ; +NET "io_tx<14>" LOC = "AA15" ; +NET "io_tx<15>" LOC = "AB14" ; + +NET "io_rx<0>" LOC = "Y8" ; +NET "io_rx<1>" LOC = "Y9" ; +NET "io_rx<2>" LOC = "V7" ; +NET "io_rx<3>" LOC = "U8" ; +NET "io_rx<4>" LOC = "V10" ; +NET "io_rx<5>" LOC = "U9" ; +NET "io_rx<6>" LOC = "AB7" ; +NET "io_rx<7>" LOC = "AA8" ; +NET "io_rx<8>" LOC = "W8" ; +NET "io_rx<9>" LOC = "V8" ; +NET "io_rx<10>" LOC = "AB5" ; +NET "io_rx<11>" LOC = "AB6" ; +NET "io_rx<12>" LOC = "AB4" ; +NET "io_rx<13>" LOC = "AA4" ; +NET "io_rx<14>" LOC = "W5" ; +NET "io_rx<15>" LOC = "Y4" ; + +#NET "CLKOUT2_CODEC" LOC = "U12" ; +#NET "CLKOUT1_CODEC" LOC = "V12" ; + +## FPGA Config Pins +#NET "fpga_cfg_prog_b" LOC = "A2" ; +#NET "fpga_cfg_done" LOC = "AB21" ; +#NET "fpga_cfg_din" LOC = "W17" ; +#NET "fpga_cfg_cclk" LOC = "V17" ; +#NET "fpga_cfg_init_b" LOC = "W15" ; + +## Unused +#NET "unnamed_net53" LOC = "B1" ; # TMS +#NET "unnamed_net52" LOC = "B22" ; # TDO +#NET "unnamed_net51" LOC = "D2" ; # TDI +#NET "unnamed_net50" LOC = "A21" ; # TCK +#NET "unnamed_net59" LOC = "F7" ; # PUDC_B +#NET "unnamed_net58" LOC = "V6" ; # M2 +#NET "unnamed_net57" LOC = "AA3" ; # M1 +#NET "unnamed_net56" LOC = "AB3" ; # M0 +#NET "GND" LOC = "V19" ; # Suspend, unused diff --git a/usrp2/top/E1x0/u1e.v b/usrp2/top/E1x0/u1e.v new file mode 100644 index 000000000..445b14a03 --- /dev/null +++ b/usrp2/top/E1x0/u1e.v @@ -0,0 +1,141 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u1e + (input CLK_FPGA_P, input CLK_FPGA_N, // Diff + output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + input debug_pb, output FPGA_TXD, input FPGA_RXD, + + // GPMC + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, + input EM_NWE, input EM_NOE, + + inout db_sda, inout db_scl, // I2C + + output db_sclk_tx, output db_sen_tx, output db_mosi_tx, input db_miso_tx, // DB TX SPI + output db_sclk_rx, output db_sen_rx, output db_mosi_rx, input db_miso_rx, // DB TX SPI + output sclk_codec, output sen_codec, output mosi_codec, input miso_codec, // AD9862 main SPI + output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso, // Clock gen SPI + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, + + output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls + input overo_gpio0, input overo_gpio14, input overo_gpio21, input overo_gpio22, // Misc GPIO + input overo_gpio23, input overo_gpio64, input overo_gpio65, input overo_gpio127, // Misc GPIO + input overo_gpio128, input overo_gpio163, input overo_gpio170, input overo_gpio176, // Misc GPIO + + inout [15:0] io_tx, inout [15:0] io_rx, + + output [13:0] TX, output TXSYNC, output TXBLANK, + input [11:0] DA, input [11:0] DB, input RXSYNC, + + input PPS_IN + ); + + // ///////////////////////////////////////////////////////////////////////// + // Clocking + wire clk_fpga, clk_fpga_in; + + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) + clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + + wire clk_2x, dcm_rst, dcm_locked, clk_fb; + DCM #(.CLK_FEEDBACK ( "1X" ), + .CLKDV_DIVIDE ( 2 ), + .CLKFX_DIVIDE ( 2 ), + .CLKFX_MULTIPLY ( 2 ), + .CLKIN_DIVIDE_BY_2 ( "FALSE" ), + .CLKIN_PERIOD ( 15.625 ), + .CLKOUT_PHASE_SHIFT ( "NONE" ), + .DESKEW_ADJUST ( "SYSTEM_SYNCHRONOUS" ), + .DFS_FREQUENCY_MODE ( "LOW" ), + .DLL_FREQUENCY_MODE ( "LOW" ), + .DUTY_CYCLE_CORRECTION ( "TRUE" ), + .FACTORY_JF ( 16'h8080 ), + .PHASE_SHIFT ( 0 ), + .STARTUP_WAIT ( "FALSE" )) + clk_doubler (.CLKFB(clk_fb), .CLKIN(clk_fpga_in), .RST(dcm_rst), + .DSSEN(0), .PSCLK(0), .PSEN(0), .PSINCDEC(0), .PSDONE(), + .CLKDV(), .CLKFX(), .CLKFX180(), + .CLK2X(), .CLK2X180(), + .CLK0(clk_fb), .CLK90(clk_fpga), .CLK180(), .CLK270(), + .LOCKED(dcm_locked), .STATUS()); + + // ///////////////////////////////////////////////////////////////////////// + // SPI + wire mosi, sclk, miso; + assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0; + assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0; + assign { sclk_codec, mosi_codec } = ~sen_codec ? {sclk,mosi} : 2'b0; + assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0; + assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) | + (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso); + + // ///////////////////////////////////////////////////////////////////////// + // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL + + assign TXBLANK = 0; + wire [13:0] tx_i, tx_q; + + reg[13:0] delay_q; + always @(posedge clk_fpga) + delay_q <= tx_q; + + genvar i; + generate + for(i=0;i<14;i=i+1) + begin : gen_dacout + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_inst (.Q(TX[i]), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(tx_i[i]), // 1-bit data input (associated with C0) + .D1(delay_q[i]), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + end // block: gen_dacout + endgenerate + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(1'b0), // 1-bit data input (associated with C0) + .D1(1'b1), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + + // ///////////////////////////////////////////////////////////////////////// + // Main U1E Core + u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb), + .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS5(EM_NCS5), + .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), + .db_sda(db_sda), .db_scl(db_scl), + .sclk(sclk), .sen({cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso), + .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), + .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel), + .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), + .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), + .io_tx(io_tx), .io_rx(io_rx), + .tx_i(tx_i), .tx_q(tx_q), + .rx_i(DA), .rx_q(DB), + .misc_gpio( {{overo_gpio128,overo_gpio163,overo_gpio170,overo_gpio176}, + {overo_gpio0,overo_gpio14,overo_gpio21,overo_gpio22}, + {overo_gpio23,overo_gpio64,overo_gpio65,overo_gpio127}}), + .pps_in(PPS_IN) ); + + // ///////////////////////////////////////////////////////////////////////// + // Local Debug + // assign debug_clk = {clk_fpga, clk_2x }; + // assign debug = { TXSYNC, TXBLANK, TX }; + +endmodule // u1e diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v new file mode 100644 index 000000000..d10a3ab30 --- /dev/null +++ b/usrp2/top/E1x0/u1e_core.v @@ -0,0 +1,421 @@ + + +module u1e_core + (input clk_fpga, input rst_fpga, + output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + output debug_txd, input debug_rxd, + + // GPMC + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, + input EM_NWE, input EM_NOE, + + inout db_sda, inout db_scl, + output sclk, output [15:0] sen, output mosi, input miso, + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, + output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, + inout [15:0] io_tx, inout [15:0] io_rx, + output [13:0] tx_i, output [13:0] tx_q, + input [11:0] rx_i, input [11:0] rx_q, + + input [11:0] misc_gpio, input pps_in + ); + + localparam TXFIFOSIZE = 13; + localparam RXFIFOSIZE = 13; + + // 64 total regs in address space + localparam SR_RX_CTRL = 0; // 9 regs (+0 to +8) + localparam SR_RX_DSP = 16; // 7 regs (+0 to +6) + localparam SR_TX_CTRL = 24; // 6 regs (+0 to +5) + localparam SR_TX_DSP = 32; // 5 regs (+0 to +4) + localparam SR_TIME64 = 40; // 6 regs (+0 to +5) + localparam SR_CLEAR_RX_FIFO = 48; // 1 reg + localparam SR_CLEAR_TX_FIFO = 49; // 1 reg + localparam SR_GLOBAL_RESET = 50; // 1 reg + localparam SR_REG_TEST32 = 52; // 1 reg + + wire [7:0] COMPAT_NUM = 8'd4; + + wire wb_clk = clk_fpga; + wire wb_rst, global_reset; + + wire pps_int; + wire [63:0] vita_time, vita_time_pps; + reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; + wire [7:0] test_rate; + wire [3:0] test_ctrl; + + wire [7:0] set_addr; + wire [31:0] set_data; + wire set_stb; + + wire [31:0] debug_vt; + wire rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc; + assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp; + assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp; + + setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(global_reset)); + + reset_sync reset_sync(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(wb_rst)); + + // ///////////////////////////////////////////////////////////////////////////////////// + // GPMC Slave to Wishbone Master + localparam dw = 16; + localparam aw = 11; + localparam sw = 2; + + wire [dw-1:0] m0_dat_mosi, m0_dat_miso; + wire [aw-1:0] m0_adr; + wire [sw-1:0] m0_sel; + wire m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty; + + wire [31:0] debug_gpmc; + + wire [35:0] tx_data, rx_data, tx_err_data; + wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, + tx_err_src_rdy, tx_err_dst_rdy; + reg [15:0] tx_frame_len; + wire [15:0] rx_frame_len; + + wire bus_error; + wire clear_tx, clear_rx; + + setting_reg #(.my_addr(SR_CLEAR_RX_FIFO), .width(1)) sr_clear_rx + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_rx)); + + setting_reg #(.my_addr(SR_CLEAR_TX_FIFO), .width(1)) sr_clear_tx + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_tx)); + + gpmc_async #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE)) + gpmc (.arst(wb_rst), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), + .EM_NOE(EM_NOE), + + .rx_have_data(rx_have_data), .tx_have_space(tx_have_space), + .bus_error(bus_error), .bus_reset(0), + + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), + .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), + .wb_ack_i(m0_ack), + + .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx), + .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), + .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), + + .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), + .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc), + + .test_rate(test_rate), .test_ctrl(test_ctrl), + .debug(debug_gpmc)); + + wire rx_sof = rx_data[32]; + wire rx_eof = rx_data[33]; + wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int; + + wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug, vr_debug; + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX + wire [31:0] sample_rx; + wire strobe_rx, run_rx; + wire [35:0] vita_rx_data; + wire vita_rx_src_rdy, vita_rx_dst_rdy; + + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx + (.clk(wb_clk),.rst(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a({rx_i,2'b0}),.adc_ovf_a(0),.adc_b({rx_q,2'b0}),.adc_ovf_b(0), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + vita_rx_chain #(.BASE(SR_RX_CTRL), .UNIT(0), .FIFOSIZE(9), .PROT_ENG_FLAGS(0)) vita_rx_chain + (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time), .overrun(rx_overrun_dsp), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .rx_data_o(vita_rx_data), .rx_dst_rdy_i(vita_rx_dst_rdy), .rx_src_rdy_o(vita_rx_src_rdy), + .debug(vr_debug) ); + + fifo36_mux #(.prio(0)) mux_err_stream + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .data0_i(vita_rx_data), .src0_rdy_i(vita_rx_src_rdy), .dst0_rdy_o(vita_rx_dst_rdy), + .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), + .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [15:0] tx_i_int, tx_q_int; + wire run_tx; + + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(1), .DO_FLOW_CONTROL(0), + .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0), + .DSP_NUMBER(0)) + vita_tx_chain + (.clk(wb_clk), .reset(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), + .dac_a(tx_i_int),.dac_b(tx_q_int), + .underrun(tx_underrun_dsp), .run(run_tx), + .debug(debug_vt)); + + assign tx_i = tx_i_int[15:2]; + assign tx_q = tx_q_int[15:2]; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Wishbone Intercon, single master + wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, + s4_dat_mosi, s5_dat_mosi, s4_dat_miso, s5_dat_miso, s6_dat_mosi, s7_dat_mosi, s6_dat_miso, s7_dat_miso, + s8_dat_mosi, s9_dat_mosi, s8_dat_miso, s9_dat_miso, sa_dat_mosi, sb_dat_mosi, sa_dat_miso, sb_dat_miso, + sc_dat_mosi, sd_dat_mosi, sc_dat_miso, sd_dat_miso, se_dat_mosi, sf_dat_mosi, se_dat_miso, sf_dat_miso; + wire [aw-1:0] s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr; + wire [aw-1:0] s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; + wire [sw-1:0] s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel; + wire [sw-1:0] s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; + wire s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack; + wire s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; + wire s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb; + wire s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; + wire s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc; + wire s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; + wire s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we; + wire s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we, sf_we; + + wb_1master #(.dw(dw), .aw(aw), .sw(sw), .decode_w(4), + .s0_addr(4'h0), .s0_mask(4'hF), .s1_addr(4'h1), .s1_mask(4'hF), + .s2_addr(4'h2), .s2_mask(4'hF), .s3_addr(4'h3), .s3_mask(4'hF), + .s4_addr(4'h4), .s4_mask(4'hF), .s5_addr(4'h5), .s5_mask(4'hF), + .s6_addr(4'h6), .s6_mask(4'hF), .s7_addr(4'h7), .s7_mask(4'hF), + .s8_addr(4'h8), .s8_mask(4'hE), .s9_addr(4'hf), .s9_mask(4'hF), // slave 8 is double wide + .sa_addr(4'ha), .sa_mask(4'hF), .sb_addr(4'hb), .sb_mask(4'hF), + .sc_addr(4'hc), .sc_mask(4'hF), .sd_addr(4'hd), .sd_mask(4'hF), + .se_addr(4'he), .se_mask(4'hF), .sf_addr(4'hf), .sf_mask(4'hF)) + wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_miso),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_mosi), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_mosi),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_miso),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_mosi),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_miso),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_mosi),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_miso),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_mosi),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_miso),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_mosi),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_miso),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_mosi),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_miso),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_mosi),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_miso),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_mosi),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_miso),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_mosi),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_miso),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_mosi),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_miso),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_mosi),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_miso),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_mosi),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_miso),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_mosi),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_miso),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_mosi),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_miso),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_mosi),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_miso),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), + .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); + + assign s5_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; + assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 0, Misc LEDs, Switches, controls + + localparam REG_LEDS = 7'd0; // out + localparam REG_CGEN_CTRL = 7'd4; // out + localparam REG_CGEN_ST = 7'd6; // in + localparam REG_TEST = 7'd8; // out + localparam REG_RX_FRAMELEN = 7'd10; // in + localparam REG_TX_FRAMELEN = 7'd12; // out + localparam REG_XFER_RATE = 7'd14; // out + localparam REG_COMPAT = 7'd16; // in + + always @(posedge wb_clk) + if(wb_rst) + begin + reg_leds <= 0; + reg_cgen_ctrl <= 2'b11; + reg_test <= 0; + tx_frame_len <= 0; + xfer_rate <= 0; + end + else + if(s0_cyc & s0_stb & s0_we) + case(s0_adr[6:0]) + REG_LEDS : + reg_leds <= s0_dat_mosi; + REG_CGEN_CTRL : + reg_cgen_ctrl <= s0_dat_mosi; + REG_TEST : + reg_test <= s0_dat_mosi; + REG_TX_FRAMELEN : + tx_frame_len <= s0_dat_mosi; + REG_XFER_RATE : + xfer_rate <= s0_dat_mosi; + endcase // case (s0_adr[6:0]) + + assign test_ctrl = xfer_rate[11:8]; + assign test_rate = xfer_rate[7:0]; + + assign { debug_led[3:0] } = ~{run_rx,run_tx,reg_leds[1:0]}; + assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; + + assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : + (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : + (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : + (s0_adr[6:0] == REG_TEST) ? reg_test : + (s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len : + (s0_adr[6:0] == REG_COMPAT) ? { 8'd0, COMPAT_NUM } : + 16'hBEEF; + + assign s0_ack = s0_stb & s0_cyc; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 1, UART + // depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack), + .adr_i(s1_adr[3:1]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso), + .rx_int_o(),.tx_int_o(), + .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o()); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 2, SPI + + spi_top16 shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_mosi), + .wb_dat_o(s2_dat_miso),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(), + .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // Slave 3, I2C + + wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o; + i2c_master_top #(.ARST_LVL(1)) i2c + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_miso[15:8] = 8'd0; + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + + wire [31:0] atr_lines; + wire [31:0] debug_gpio_0, debug_gpio_1; + + nsgpio16LE + nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio( {io_tx,io_rx} ) ); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #8 + 9 + + // only have 64 regs, 32 bits each with current setup... + settings_bus_16LE #(.AWIDTH(11),.RWIDTH(6)) settings_bus_16LE + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr),.wb_dat_i(s8_dat_mosi), + .wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack), + .strobe(set_stb),.addr(set_addr),.data(set_data) ); + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller -- Slave #6 + + atr_controller16 atr_controller16 + (.clk_i(wb_clk), .rst_i(wb_rst), + .adr_i(s6_adr[5:0]), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), + .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), + .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines)); + + // ///////////////////////////////////////////////////////////////////////// + // Readback mux 32 -- Slave #7 + + wire [31:0] reg_test32; + + setting_reg #(.my_addr(SR_REG_TEST32)) sr_reg_test32 + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(reg_test32),.changed()); + + wb_readback_mux_16LE readback_mux_32 + (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s7_stb), + .wb_adr_i({5'b0,s7_adr}), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack), + + .word00(vita_time[63:32]), .word01(vita_time[31:0]), + .word02(vita_time_pps[63:32]), .word03(vita_time_pps[31:0]), + .word04(reg_test32), .word05(32'b0), + .word06(32'b0), .word07(32'b0), + .word08(32'b0), .word09(32'b0), + .word10(32'b0), .word11(32'b0), + .word12(32'b0), .word13(32'b0), + .word14(32'b0), .word15(32'b0) + ); + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing + + time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit + (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), + .exp_time_in(0)); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Debug circuitry + + assign debug_clk = { EM_CLK, clk_fpga }; + +/* + assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun }, + { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int }, + { EM_D } }; + +*/ + assign debug = debug_gpmc; + + assign debug_gpio_0 = { {run_tx, 1'b0, run_rx, strobe_rx, tx_i[11:0]}, + {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; + + assign debug_gpio_1 = debug_vt; + +/* + assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy}, + {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy}, + {rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0}, + {2'b0, bus_error, debug_gpmc[4:0] }, + {misc_gpio[7:0]} }; + */ +endmodule // u1e_core diff --git a/usrp2/top/N2x0/.gitignore b/usrp2/top/N2x0/.gitignore new file mode 100644 index 000000000..1b2211df0 --- /dev/null +++ b/usrp2/top/N2x0/.gitignore @@ -0,0 +1 @@ +build* diff --git a/usrp2/top/N2x0/Makefile.N200R3 b/usrp2/top/N2x0/Makefile.N200R3 new file mode 100644 index 000000000..a525836ed --- /dev/null +++ b/usrp2/top/N2x0/Makefile.N200R3 @@ -0,0 +1,98 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u2plus +BUILD_DIR = $(abspath build$(ISE)-N200R3) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extramfifo/Makefile.srcs + + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u2plus_core.v \ +u2plus.v \ +u2plus.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/N2x0/Makefile.N200R4 b/usrp2/top/N2x0/Makefile.N200R4 new file mode 100644 index 000000000..955aadc59 --- /dev/null +++ b/usrp2/top/N2x0/Makefile.N200R4 @@ -0,0 +1,100 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u2plus +BUILD_DIR = $(abspath build$(ISE)-N200R4) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extramfifo/Makefile.srcs + + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +rev4_defs.v \ +capture_ddrlvds.v \ +u2plus_core.v \ +u2plus.v \ +u2plus.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/N2x0/Makefile.N210R3 b/usrp2/top/N2x0/Makefile.N210R3 new file mode 100644 index 000000000..e29251e1c --- /dev/null +++ b/usrp2/top/N2x0/Makefile.N210R3 @@ -0,0 +1,98 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u2plus +BUILD_DIR = $(abspath build$(ISE)-N210R3) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extramfifo/Makefile.srcs + + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd3400a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u2plus_core.v \ +u2plus.v \ +u2plus.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/N2x0/Makefile.N210R4 b/usrp2/top/N2x0/Makefile.N210R4 new file mode 100644 index 000000000..73747e544 --- /dev/null +++ b/usrp2/top/N2x0/Makefile.N210R4 @@ -0,0 +1,100 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u2plus +BUILD_DIR = $(abspath build$(ISE)-N210R4) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extramfifo/Makefile.srcs + + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd3400a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +rev4_defs.v \ +capture_ddrlvds.v \ +u2plus_core.v \ +u2plus.v \ +u2plus.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/N2x0/bootloader.rmi b/usrp2/top/N2x0/bootloader.rmi new file mode 100644 index 000000000..e5be670fb --- /dev/null +++ b/usrp2/top/N2x0/bootloader.rmi @@ -0,0 +1,512 @@ +defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_d6cd0400_3a0b0b80_80e29c0c_82700b0b_0b0b0b0b; +defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_80d7972d_88080b0b_80088408; +defparam bootram.RAM0.INIT_02=256'h00000000_00000000_04000000_ffff0652_832b2a83_81058205_72830609_71fd0608; +defparam bootram.RAM0.INIT_03=256'h83a70400_0b0b0b0b_7383ffff_2b2b0906_05820583_83060981_83ffff73_71fd0608; +defparam bootram.RAM0.INIT_04=256'h00000000_00000000_53510400_070a8106_73097306_09060906_72057373_72098105; +defparam bootram.RAM0.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722473; +defparam bootram.RAM0.INIT_06=256'h00000000_53510400_81065151_0a31050a_0a720a10_30720a10_71068106_71737109; +defparam bootram.RAM0.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722673; +defparam bootram.RAM0.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_c4040000_0b0b0b88; +defparam bootram.RAM0.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_0a535104_720a722b; +defparam bootram.RAM0.INIT_0B=256'h00000000_00000000_00000000_00000000_05040000_0b0b88a7_0981050b_72729f06; +defparam bootram.RAM0.INIT_0C=256'h00000000_00000000_04000000_06075351_8106ff05_0974090a_739f062a_72722aff; +defparam bootram.RAM0.INIT_0D=256'h00000000_0c515104_0772fc06_832b0b2b_81058205_73830609_020d0406_71715351; +defparam bootram.RAM0.INIT_0E=256'h00000000_00000000_00000000_51040000_0a810653_81050906_72050970_72098105; +defparam bootram.RAM0.INIT_0F=256'h00000000_00000000_00000000_53510400_0a098106_81050906_72050970_72098105; +defparam bootram.RAM0.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_52040000_71098105; +defparam bootram.RAM0.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_04000000_05055351_72720981; +defparam bootram.RAM0.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_07535104_73730906_72097206; +defparam bootram.RAM0.INIT_13=256'h00000000_00000000_04000000_81ff0652_1010102a_81058305_72830609_71fc0608; +defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88aa0400_060b0b0b_10100508_88738306_0b0b80e2_71fc0608; +defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_ee2d5050_0b0b80cd_88087575_80088408; +defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_a02d5050_0b0b80cf_88087575_80088408; +defparam bootram.RAM0.INIT_17=256'h04000000_07515151_05ff0506_73097274_70547106_8106ff05_0509060a_72097081; +defparam bootram.RAM0.INIT_18=256'h51040000_06075151_7405ff05_06730972_05705471_098106ff_0509060a_72097081; +defparam bootram.RAM0.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_05ff0504; +defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_80e2980c_810b0b0b; +defparam bootram.RAM0.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_04000000_71810552; +defparam bootram.RAM0.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_04000000_10100552_02840572; +defparam bootram.RAM0.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_020d0400_05715351_717105ff; +defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_cf943f04_82813f80; +defparam bootram.RAM0.INIT_21=256'hfc060c51_102b0772_83051010_06098105_ff067383_51047381_10101053_10101010; +defparam bootram.RAM0.INIT_22=256'h51535104_72ed3851_0a100a53_71105272_09720605_8106ff05_72728072_51043c04; +defparam bootram.RAM0.INIT_23=256'h800b80e2_f40c82a0_0b0b80e2_8380800b_822ebd38_80e29c08_802ea438_80e29808; +defparam bootram.RAM0.INIT_24=256'h0b80e2f8_80808280_e2f40cf8_0b0b0b80_808080a4_fc0c04f8_800b80e2_f80c8290; +defparam bootram.RAM0.INIT_25=256'h940b80e2_80c0a880_80e2f40c_8c0b0b0b_80c0a880_e2fc0c04_84800b80_0cf88080; +defparam bootram.RAM0.INIT_26=256'h70085252_80e2a408_5170a738_80e38033_04ff3d0d_80e2fc0c_80d7c80b_f80c0b0b; +defparam bootram.RAM0.INIT_27=256'h8034833d_810b80e3_5270ee38_08700852_2d80e2a4_e2a40c70_38841280_70802e94; +defparam bootram.RAM0.INIT_28=256'h38823d0d_09810685_800b802e_0b0b0b0b_802e8e38_80e2f008_3d0d0b0b_0d040480; +defparam bootram.RAM0.INIT_29=256'h852eb238_5a798380_0d973d22_0404ee3d_3f823d0d_0b0bf5d4_e2f0510b_040b0b80; +defparam bootram.RAM0.INIT_2A=256'h5a953d22_819d3980_862e8f38_39798380_8e3881a7_8380842e_248b3879_79838085; +defparam bootram.RAM0.INIT_2B=256'h7053963d_f423923d_3d2280e4_39815a95_e4f8238a_953d2280_9539825a_80e4fc23; +defparam bootram.RAM0.INIT_2C=256'h7b1d7f1d_3d415e5c_0b883d99_5b5f4080_0284057b_ae3f8008_abdc3f8b_84055241; +defparam bootram.RAM0.INIT_2D=256'h79337b34_7d055b5b_7b1d963d_901f5e5c_ef38800b_5c887c26_7b34811c_5b5b7933; +defparam bootram.RAM0.INIT_2E=256'h7c26ef38_811c5c86_79337b34_601d5b5b_5e5c7b1d_800b881f_7c26ed38_811c5c88; +defparam bootram.RAM0.INIT_2F=256'h3d0d686a_3d0d04ee_9d903f94_7c26ef38_811c5c86_79337b34_611d5b5b_805c7b1e; +defparam bootram.RAM0.INIT_30=256'ha23f80e1_d7cc5198_538a5280_2e8f3875_0856758a_27973876_5a578379_8412085a; +defparam bootram.RAM0.INIT_31=256'h9f185675_17085dff_5ba05c88_3fa0588a_9c51988f_a45280d8_8e387853_5878a326; +defparam bootram.RAM0.INIT_32=256'h39951733_085e82f2_cc3f8008_80c15c8a_56750804_80da8c05_38758429_95268388; +defparam bootram.RAM0.INIT_33=256'h55961733_5a515677_2a848006_70307096_3380f232_92389417_7580f22e_56888058; +defparam bootram.RAM0.INIT_34=256'h80085f80_5199b83f_38815877_75782e83_18335758_52800b97_538c1708_54901708; +defparam bootram.RAM0.INIT_35=256'h398d1733_c95c81dd_8fdb3f80_18335256_ea05538c_7054953d_398d1733_d35c82aa; +defparam bootram.RAM0.INIT_36=256'h75822488_822ea038_17335675_81c7399c_3f80c85c_525690e7_538c1833_70548e18; +defparam bootram.RAM0.INIT_37=256'h17085692_5695398c_1808710c_8c170890_8106a038_75842e09_a138a839_3875812e; +defparam bootram.RAM0.INIT_38=256'h9e387582_5675822e_399c1733_d05c81ba_33763480_08569317_8a398c17_17227623; +defparam bootram.RAM0.INIT_39=256'h17087022_5691398c_08700840_9a388c17_2e098106_a2397584_812e9d38_24883875; +defparam bootram.RAM0.INIT_3A=256'h7553943d_83389456_56947625_398d1733_d25c80fe_33405680_8c170870_40568839; +defparam bootram.RAM0.INIT_3B=256'h94762583_8d173356_3480d739_8405b505_5c800802_bc3f80d6_1733518b_ea05528c; +defparam bootram.RAM0.INIT_3C=256'h05b50534_5c750284_9d3f80d5_1733518a_8e17528c_993f7553_1733518d_3894568c; +defparam bootram.RAM0.INIT_3D=256'h57577533_963d7905_5a587719_800b833d_3ddc0554_17085594_80cc5c8c_ad39785e; +defparam bootram.RAM0.INIT_3E=256'h19963d79_3d5a5877_54800b83_943ddc05_a05ca455_ed38a439_58887826_77348118; +defparam bootram.RAM0.INIT_3F=256'h0d747053_0d04fe3d_a63f943d_8080519d_26ed3883_18588878_33773481_05575775; +defparam bootram.RAM1.INIT_00=256'h8d39a052_3f9db93f_815191ea_5188953f_38a052a0_72802e92_5394b83f_80d8e852; +defparam bootram.RAM1.INIT_01=256'h5280d9a4_89b53f86_80d98851_0d82b53f_0d04fa3d_d93f843d_3f725191_72518884; +defparam bootram.RAM1.INIT_02=256'h92b43f88_3f800851_bd3f85df_85cb3f86_3fa7f13f_c45193f3_8a5280d9_5193fc3f; +defparam bootram.RAM1.INIT_03=256'h96db3f86_52800851_85c13f73_3f800854_8c3f86b1_92ce3f88_3f800851_983f86bd; +defparam bootram.RAM1.INIT_04=256'h83808451_3f8ab252_805197a1_fb528380_96e53f8b_5190bf3f_84528008_a03f8380; +defparam bootram.RAM1.INIT_05=256'h825196f9_dd528380_97833fbe_83808651_3f8ab252_8551978d_b2528380_97973f8a; +defparam bootram.RAM1.INIT_06=256'h802e80c9_08568008_90b43f80_3dfc0551_aabb3f88_51a8a93f_bd3f8ffa_3f805190; +defparam bootram.RAM1.INIT_07=256'h055180c3_52800890_5380d9e8_06ad3884_ee2e0981_557382fd_8e052255_38768008; +defparam bootram.RAM1.INIT_08=256'h3f883974_735185dd_3f86e23f_525491a4_3f941670_f05192b3_9a3880d9_853f8008; +defparam bootram.RAM1.INIT_09=256'h8d38a00b_5573802e_81065155_70852a70_82808c08_3f8eae3f_b43f8fb9_5275519c; +defparam bootram.RAM1.INIT_0A=256'h808c0c80_80c00b82_2efef838_51547380_2a708106_9d3f7486_80d55186_82808c0c; +defparam bootram.RAM1.INIT_0B=256'h3f9f5280_aa3f89d8_889f3f8d_3f82b73f_f53f93c5_fe3d0d85_3ffee839_cf518682; +defparam bootram.RAM1.INIT_0C=256'hcf3f8852_82ac518c_5185913f_3f845284_ac518cdc_859e3f82_9f528051_5185c23f; +defparam bootram.RAM1.INIT_0D=256'h805184e8_82539f52_518cb53f_f73f82ac_52905184_8cc23f90_3f82ac51_88518584; +defparam bootram.RAM1.INIT_0E=256'h9f529e51_8025df38_ff135372_518c993f_db3f80e4_529c5184_8ca63f9f_3f80e451; +defparam bootram.RAM1.INIT_0F=256'h808c0870_803d0d82_843d0d04_810b800c_81e0840c_bf3f890b_52815184_84e33f9f; +defparam bootram.RAM1.INIT_10=256'h82055a57_30708025_a7053370_7f028c05_3d0d7a7d_3d0d04f9_800c5182_8b2a8106; +defparam bootram.RAM1.INIT_11=256'h30709f2a_388a5573_88557383_832e8838_88055575_38728025_75822e93_57585957; +defparam bootram.RAM1.INIT_12=256'h842b0751_fe057072_05777131_76812cff_802e9738_38725472_8177259e_51538054; +defparam bootram.RAM1.INIT_13=256'h73528118_51ac9a3f_ff065277_a43f7281_527b51ac_81805474_86397353_54548054; +defparam bootram.RAM1.INIT_14=256'h54bd5378_815580ca_9f053356_fb3d0d02_893d0d04_51ac8a3f_815280da_51ac923f; +defparam bootram.RAM1.INIT_15=256'hff3ffeb8_51d63f90_3f815281_c551abe1_0d815280_0d04fe3d_e63f873d_527551fe; +defparam bootram.RAM1.INIT_16=256'hfa3d0d78_843d0d04_e0800c53_70900781_81e08008_802ef338_ff065372_3f800881; +defparam bootram.RAM1.INIT_17=256'h33527181_38805471_70802e83_70335252_9e387217_53727627_70565480_7a575781; +defparam bootram.RAM1.INIT_18=256'h04fe3d0d_0c883d0d_81517080_802e8338_74075170_53df3974_80558113_ff2e8338; +defparam bootram.RAM1.INIT_19=256'h88335574_3d0d80e3_3d0d04f9_bcac3f84_80e2ac51_80dae852_88348653_810b80e3; +defparam bootram.RAM1.INIT_1A=256'h80d051ab_54568252_54873d70_24b63886_08558075_3481b8a4_0b80e388_80c63881; +defparam bootram.RAM1.INIT_1B=256'h38865375_0655748c_800881ff_51fee93f_38865275_74802e9c_81ff0655_d53f8008; +defparam bootram.RAM1.INIT_1C=256'h80e2a80c_80dae408_80e38434_0d04810b_800c893d_80e2ac0b_51bbd73f_5280e2ac; +defparam bootram.RAM1.INIT_1D=256'h38845487_807524b3_b8a40855_e3843481_38810b80_557480c3_80e38433_04fb3d0d; +defparam bootram.RAM1.INIT_1E=256'h0551fdfc_52873dfc_2e993884_06557480_800881ff_51aaeb3f_8c5280d0_3dfc0553; +defparam bootram.RAM1.INIT_1F=256'h77568454_04fb3d0d_0c873d0d_e2a80b80_e2a80c80_86387580_ff065574_3f800881; +defparam bootram.RAM1.INIT_20=256'h0b80e384_e2a80c81_38750880_74802e8d_81ff0655_b13f8008_80d051a9_75538c52; +defparam bootram.RAM1.INIT_21=256'h81e08c0c_80e38c0c_08060770_7180e38c_09737506_803d0d73_873d0d04_3474800c; +defparam bootram.RAM1.INIT_22=256'h0c51823d_0c81e098_7080e390_90080607_067180e3_73097375_04803d0d_51823d0d; +defparam bootram.RAM1.INIT_23=256'h8a528051_04ff3d0d_0c843d0d_c93f7280_53805182_0d747053_3f04fe3d_0d0482b1; +defparam bootram.RAM1.INIT_24=256'h157481ff_2e903881_54547280_7081ff06_56567433_3d0d7779_3d0d04fb_82b83f83; +defparam bootram.RAM1.INIT_25=256'h75335556_59565880_0d797b7d_0d04f93d_800c873d_e539800b_5582933f_06537652; +defparam bootram.RAM1.INIT_26=256'h8b387581_5473802e_e53f7433_78525581_81157453_77259d38_38815680_73762ea4; +defparam bootram.RAM1.INIT_27=256'h04fe3d0d_3f833d0d_8051ff8f_3d0d7352_3d0d04ff_75800c89_7324e538_17575376; +defparam bootram.RAM1.INIT_28=256'h528051dd_ff3d0d73_843d0d04_800b800c_5181ab3f_3f8a5272_5253feff_74765370; +defparam bootram.RAM1.INIT_29=256'h73348008_c23f8008_53755181_84398113_56575556_77797b71_04fb3d0d_3f833d0d; +defparam bootram.RAM1.INIT_2A=256'h7431800c_80733472_7224db38_74315274_2e8a3872_387181ff_718a2e90_81ff0652; +defparam bootram.RAM1.INIT_2B=256'h14708429_0d738429_0d04ff3d_1234823d_3380e2b4_51028f05_803d0d72_873d0d04; +defparam bootram.RAM1.INIT_2C=256'hb4133352_805380e2_04fe3d0d_51833d0d_720c5451_f0057022_761080da_82908005; +defparam bootram.RAM1.INIT_2D=256'h0d767856_0d04fc3d_e538843d_53827325_c93f8113_33527251_80e2b813_7251c13f; +defparam bootram.RAM1.INIT_2E=256'h3f738429_527351de_0687388d_812e0981_14335372_3880e2b4_09810695_54748a2e; +defparam bootram.RAM1.INIT_2F=256'h3d0d7484_3d0d04fe_8c150c86_2ef83874_08537280_55538414_82908005_14708429; +defparam bootram.RAM1.INIT_30=256'h800c843d_12085372_2e853890_ff537080_52535181_05881108_29829080_29157084; +defparam bootram.RAM1.INIT_31=256'h38901208_70732e91_52545253_05881108_29829080_29167084_0d807584_0d04fe3d; +defparam bootram.RAM1.INIT_32=256'h0c81b8a4_0b81a888_ff3d0d80_843d0d04_3872800c_545170f1_88140852_7081ff06; +defparam bootram.RAM1.INIT_33=256'h0c70882a_0681a880_227081ff_e2bc0570_51701080_25833884_51518471_08708f06; +defparam bootram.RAM1.INIT_34=256'h55535481_05970533_76780288_04fd3d0d_0c833d0d_0b81a888_51518180_81a8840c; +defparam bootram.RAM1.INIT_35=256'ha88c0c81_10810781_70f13872_06515151_862a7081_a8900870_81863881_5171802e; +defparam bootram.RAM1.INIT_36=256'h2a708106_90087087_f13881a8_51515170_2a708106_90087081_900c81a8_900b81a8; +defparam bootram.RAM1.INIT_37=256'h81a8900c_38a05170_71812e83_3880e851_71802eb1_802eba38_51515170_70813251; +defparam bootram.RAM1.INIT_38=256'hff1252cc_81055634_51707470_81a88c08_5170f138_81065151_70812a70_81a89008; +defparam bootram.RAM1.INIT_39=256'h05335553_02880597_3d0d7678_3d0d04fd_70800c85_81a8900c_3980c00b_39815188; +defparam bootram.RAM1.INIT_3A=256'h2e843881_d0517180_a88c0c81_38721081_515170f1_70810651_0870862a_5481a890; +defparam bootram.RAM1.INIT_3B=256'h872a7081_a8900870_70f13881_06515151_812a7081_a8900870_a8900c81_90517081; +defparam bootram.RAM1.INIT_3C=256'h5171812e_8c0c80d0_733381a8_2e80c538_cf387180_70802e80_51515151_06708132; +defparam bootram.RAM1.INIT_3D=256'h0870872a_3881a890_515170f1_70810651_0870812a_0c81a890_7081a890_83389051; +defparam bootram.RAM1.INIT_3E=256'h80c00b81_81518a39_54ffb739_14ff1353_2e8e3881_51517080_81325151_70810670; +defparam bootram.RAM1.INIT_3F=256'ha2387052_51525470_70810a06_81b8a408_fd3d0d75_853d0d04_5170800c_a8900c80; +defparam bootram.RAM2.INIT_00=256'h52e23985_f1388112_8d9f7127_31515186_ac087074_085381b8_3881b8ac_7174259b; +defparam bootram.RAM2.INIT_01=256'h808c0c80_0cff0b82_0b828084_80800cef_81e20b82_8280880c_3d0dff0b_3d0d04ff; +defparam bootram.RAM2.INIT_02=256'h82808808_04fb3d0d_38833d0d_708025f1_0cff1151_70840554_51a1c972_e4d45287; +defparam bootram.RAM2.INIT_03=256'h38725173_71802e8f_74760652_e4d45555_53810b80_58515280_8c087106_70098280; +defparam bootram.RAM2.INIT_04=256'h04ff3d0d_38873d0d_877325dc_10575553_13841576_0c8f3981_7482808c_0852712d; +defparam bootram.RAM2.INIT_05=256'h72068280_80880870_2b700982_0c518172_d4057571_842980e4_269f3871_73527187; +defparam bootram.RAM2.INIT_06=256'h0c833d0d_5281e0c8_81e0c40c_22747008_0d029205_0404ff3d_52833d0d_880c5351; +defparam bootram.RAM2.INIT_07=256'hcc0c823d_820b81e0_802ef338_06515170_a0087084_cc0c81b8_810b81e0_04803d0d; +defparam bootram.RAM2.INIT_08=256'hb8a00875_2e933881_54527280_08708106_0d81b8a0_0c04fe3d_7181e0c0_0d04de3f; +defparam bootram.RAM2.INIT_09=256'hfc51f7af_8b3880da_5271802e_70810651_3971812a_8080529a_0c535381_71902a71; +defparam bootram.RAM2.INIT_0A=256'h2ef23881_51517080_7080c006_81b8a008_04803d0d_0c843d0d_72527180_3fff9e3f; +defparam bootram.RAM2.INIT_0B=256'ha0087090_0c5281b8_0781e0cc_70902b88_028e0522_04ff3d0d_0c823d0d_80800b80; +defparam bootram.RAM2.INIT_0C=256'h8638ba51_5372802e_0d755480_0d04fd3d_cc0c833d_840b81e0_802ef338_06515170; +defparam bootram.RAM2.INIT_0D=256'h83113356_fb3d0d77_853d0d04_7327e638_81135385_52a1ca3f_14703352_f5c43f72; +defparam bootram.RAM2.INIT_0E=256'h61630290_3d0d7c7e_3d0d04f6_80ed3f87_80db8051_70335356_81113354_82113355; +defparam bootram.RAM2.INIT_0F=256'had51782d_8a387952_3875802e_7680258f_5d5b5957_2a515b5f_7030709f_05bb0533; +defparam bootram.RAM2.INIT_10=256'h527651a9_ffbd3f77_3f800851_7651a990_80537752_79557854_77269438_76305777; +defparam bootram.RAM2.INIT_11=256'h3d0d04f7_f4ac3f82_8b053351_803d0d02_8c3d0d04_3351782d_80db8c05_a83f8008; +defparam bootram.RAM2.INIT_12=256'h387681ff_802e81d1_06575775_337081ff_5c5a5878_5208a4b0_70708405_3d0d8c3d; +defparam bootram.RAM2.INIT_13=256'ha0387580_7580f024_2e80fb38_597580f0_19703357_80db3881_2e098106_065675a5; +defparam bootram.RAM2.INIT_14=256'h397580f5_c638818b_80e42e80_81953975_2e819e38_8a387580_7580e324_e32eb938; +defparam bootram.RAM2.INIT_15=256'h77841983_3880ec39_80f82eba_80f53975_2e80db38_387580f3_80f5248b_2eac3875; +defparam bootram.RAM2.INIT_16=256'h53903977_a4b05480_59568055_19710852_da397784_51792d80_56805275_12335259; +defparam bootram.RAM2.INIT_17=256'ha4b05480_59568055_19710852_92397784_81538a52_55a4b054_52595680_84197108; +defparam bootram.RAM2.INIT_18=256'h76708105_8e388052_5675802e_59567633_19710859_9e397784_51fdd03f_53905275; +defparam bootram.RAM2.INIT_19=256'h803d0d81_a0940c04_04810b81_0c8b3d0d_39800b80_1959fea3_2dec3981_58335179; +defparam bootram.RAM2.INIT_1A=256'hff067b8c_05337980_3d0d0297_3d0d04fd_70f13882_06515151_882a7081_a0900870; +defparam bootram.RAM2.INIT_1B=256'h81a0900c_a0800c72_980c7781_ff0681a0_3f7683ff_555354d0_80c08007_80060770; +defparam bootram.RAM2.INIT_1C=256'h3d0d04fc_70800c85_a0800851_ffaa3f81_802e8938_0c735173_0781a090_7180c280; +defparam bootram.RAM2.INIT_1D=256'h3971902a_555351ee_73058115_10157022_278f3872_80537274_7a545555_3d0d7678; +defparam bootram.RAM2.INIT_1E=256'h86537552_04fd3d0d_0c863d0d_ec397180_902a0552_ffff0672_8d387183_5170802e; +defparam bootram.RAM2.INIT_1F=256'h80720c88_a8528551_3d0d80e3_3d0d04ff_a00c5485_700880e3_aaf83f76_80e39851; +defparam bootram.RAM2.INIT_20=256'h52702254_80e3a452_2253800b_0d029605_0d04fd3d_f338833d_52708025_12ff1252; +defparam bootram.RAM2.INIT_21=256'h787a7183_04fa3d0d_0c853d0d_80517080_7225ee38_12525285_38811288_72742e8e; +defparam bootram.RAM2.INIT_22=256'h80e3a455_80e3a80b_ad398008_0884050c_89387680_8008802e_5856c73f_ffff0653; +defparam bootram.RAM2.INIT_23=256'h73237684_988c3f75_7525eb38_14545585_38811588_71802e8f_88155552_55557308; +defparam bootram.RAM2.INIT_24=256'h88055291_7353923d_54a9c73f_3dd60552_933d5392_0d867054_0d04f13d_140c883d; +defparam bootram.RAM2.INIT_25=256'h23800b8c_8405a605_3d238002_8a800b8b_a2052381_80028405_a9b83f90_3ddc0551; +defparam bootram.RAM2.INIT_26=256'h5e80538a_23685d66_8405ae05_3d238002_c0910b8d_aa052380_80028405_3d238180; +defparam bootram.RAM2.INIT_27=256'h05ba0523_3d220284_903d2396_23983d22_8405ae05_3f800802_0551fdb7_52913de4; +defparam bootram.RAM2.INIT_28=256'h9a903f91_e6840551_80c02981_d4055269_ac53913d_05be0523_23800284_800b913d; +defparam bootram.RAM2.INIT_29=256'h80e39852_a53f8653_f20551a8_3d529a3d_2386539b_800b973d_3d0d805b_3d0d04e8; +defparam bootram.RAM2.INIT_2A=256'h5a800b9b_08800858_f7f73f80_80e20523_22028405_0280f205_51a8973f_9a3df805; +defparam bootram.RAM2.INIT_2B=256'ha33d0840_a13d085f_905d6e5e_4659845c_45a33d08_44a13d08_f005436e_3dc41143; +defparam bootram.RAM2.INIT_2C=256'h75085473_3873760c_73752784_51565a55_90807131_1a787c31_58750870_8c3d5684; +defparam bootram.RAM2.INIT_2D=256'h3f750853_a851eedc_883880db_5473802e_16088306_738c3894_73830654_802e9a38; +defparam bootram.RAM2.INIT_2E=256'h26843880_ac3878bf_778025ff_ff195957_05570817_3f757084_765198e6_94160852; +defparam bootram.RAM2.INIT_2F=256'h1f94055a_943d237f_818a800b_6b6e4040_04ea3d0d_3f9a3d0d_2a51f781_c0597882; +defparam bootram.RAM2.INIT_30=256'h5a79963d_80c08007_ce052369_02840580_23818080_800b953d_80ca0523_79028405; +defparam bootram.RAM2.INIT_31=256'h8008095a_5cfae43f_933d7052_80538a52_08466847_2380e3a0_0580d205_23800284; +defparam bootram.RAM2.INIT_32=256'h923880db_ff065a79_3f800881_5c5e8a8e_983d7053_913d7053_80d20523_79028405; +defparam bootram.RAM2.INIT_33=256'h54908053_5d94557b_60586b57_7f5a6d59_3fa93902_cf3fec8d_3f7a51f6_d451f7db; +defparam bootram.RAM2.INIT_34=256'h3d0d7f58_3d0d04f7_fd8d3f98_7c26ef38_811c5c86_79337b34_7c1f5b5b_805c7b1d; +defparam bootram.RAM2.INIT_35=256'h05237756_028405a6_8b3d2380_88185776_05a20523_3d220284_8a3d238d_02ae0522; +defparam bootram.RAM2.INIT_36=256'h90800284_0b8e3d23_ee3d0d81_8b3d0d04_51fe9e3f_5391527d_8b3df805_7e558854; +defparam bootram.RAM2.INIT_37=256'h80085294_be3f8653_b60523e8_81028405_05b50534_34840284_860b8f3d_05b20523; +defparam bootram.RAM2.INIT_38=256'h3df60551_53805294_a4c83f86_3df20551_80085294_983f8453_a4d83fe9_3dec0551; +defparam bootram.RAM2.INIT_39=256'h8653805b_e4055490_9c55943d_80578056_80598058_0843025c_fc3f8008_a5d53fe8; +defparam bootram.RAM2.INIT_3A=256'haa3d088e_04d93d0d_3f943d0d_ef38fbcf_5b867b26_7a34811b_dba01b33_7a1c5a80; +defparam bootram.RAM2.INIT_3B=256'h8d387952_5b799b26_29f2055b_ac3d0884_9d38901d_09810682_7d90862e_11225f5d; +defparam bootram.RAM2.INIT_3C=256'h802e0981_225a7990_a838821b_09810686_5a79812e_b4397a22_f5b93f86_80dc8451; +defparam bootram.RAM2.INIT_3D=256'h85ff389e_2e098106_225a7981_8c38861b_09810686_798c842e_841b225a_06869a38; +defparam bootram.RAM2.INIT_3E=256'h0551a28a_a93dffa8_80e3a052_08438453_87c33f80_1d70525f_87cb3fa8_1d705240; +defparam bootram.RAM2.INIT_3F=256'h821b2202_22a13d23_a2e83f7a_98527951_865380e3_38a73d5a_800885d5_3f80085c; +defparam bootram.RAM3.INIT_00=256'h05238653_84058182_05348202_84058181_851b3302_33a23d34_0523841b_840580fe; +defparam bootram.RAM3.INIT_01=256'h5b865398_02818e05_5aa2a73f_3dea0552_547f53aa_b53f8470_e40551a2_7952a93d; +defparam bootram.RAM3.INIT_02=256'ha2803f02_7a527e51_3d5f8653_a28c3f9e_3df40551_537f52a9_a2983f79_1d527a51; +defparam bootram.RAM3.INIT_03=256'h811c5c86_79337b34_7f1d5b5b_7d537b1d_3ddc0554_5d9c55a9_7c587c57_7c5a7c59; +defparam bootram.RAM3.INIT_04=256'h5b5b6084_708c2a43_901d7022_0684aa38_802e0981_b4397d90_f99d3f84_7c26ef38; +defparam bootram.RAM3.INIT_05=256'hffff065e_861b2280_06848638_852e0981_06515a79_882a708f_84973879_2e098106; +defparam bootram.RAM3.INIT_06=256'h5580e3a0_7d901c62_8338815f_993f8008_821d51a0_80dba052_7d5f8653_7d83fa38; +defparam bootram.RAM3.INIT_07=256'h5183fe3f_1d529c1d_83c73888_387b802e_815c7e87_80088338_5ca0833f_5470535b; +defparam bootram.RAM3.INIT_08=256'h087a08a4_a4388c1b_09810683_387f912e_812e81bb_415d407f_1c22ec11_891b3382; +defparam bootram.RAM3.INIT_09=256'h1de41d82_838339ac_51f2883f_5280dca4_3879537e_7e7a2e8f_5d5d4240_1f841122; +defparam bootram.RAM3.INIT_0A=256'h3d405a88_499a3d99_993d237f_ec387a22_08802e82_80084280_5df5c73f_1d22535d; +defparam bootram.RAM3.INIT_0B=256'h8853a93d_3d236047_821b2297_519feb3f_5379527f_9c3d4088_519ff73f_537e5279; +defparam bootram.RAM3.INIT_0C=256'h1d7f1d5b_3d5e5c7b_7c557d84_cd3f7b56_527e519f_3f885379_79519fd6_ffb40552; +defparam bootram.RAM3.INIT_0D=256'h887b26ef_34811b5b_0284051c_1b5a7933_38805b7f_887c26ef_34811c5c_5b79337b; +defparam bootram.RAM3.INIT_0E=256'h2e818138_8a387e88_427e832e_7033415b_1b08a41e_81f3398c_085a792d_38618405; +defparam bootram.RAM3.INIT_0F=256'h810681bd_79912e09_1e335b5b_80c01db5_0680e838_832e0981_1a335a79_81db3981; +defparam bootram.RAM3.INIT_10=256'h840c7d81_0c7d81e1_0b81e180_9438810a_2e098106_5c5a797b_80e4fc22_38821b22; +defparam bootram.RAM3.INIT_11=256'hc40c7d81_0c7d81e2_0b81e2c0_9438810a_2e098106_225b797b_3980e4f8_e1880cb3; +defparam bootram.RAM3.INIT_12=256'h3f80de39_e951e48a_e4d00c80_86387d81_2e098106_225b797b_3980e4f4_e2c80c93; +defparam bootram.RAM3.INIT_13=256'h22963d23_0523841a_840580ce_05347d02_840580cd_3d347d02_5d5d7d95_ac1de41d; +defparam bootram.RAM3.INIT_14=256'h527c51f1_537b812a_8a3f8008_70525bf2_6052943d_05237d53_840580d2_861a2202; +defparam bootram.RAM3.INIT_15=256'h3fa93d0d_6151f6b1_7a537f52_7c557e54_05237b56_840580ce_095a7902_fe3f8008; +defparam bootram.RAM3.INIT_16=256'h8c135351_56517108_80e3dc54_38767008_727427a4_d4085553_800b80e3_04fc3d0d; +defparam bootram.RAM3.INIT_17=256'h04fb3d0d_0c863d0d_ff517080_7326e738_81135373_72518b39_81068538_70752e09; +defparam bootram.RAM3.INIT_18=256'he3d40c8e_38811480_73872689_e3d40854_25ba3880_3f800880_5755ffb9_77797153; +defparam bootram.RAM3.INIT_19=256'h54865375_dc120c51_760880e3_1470822b_0c547310_0680e3d8_08811187_3980e3d8; +defparam bootram.RAM3.INIT_1A=256'h813f873d_e005519c_842980e3_53755273_08055486_80081080_14519439_5280e3e0; +defparam bootram.RAM3.INIT_1B=256'h842980e3_54865373_10800805_99388008_73800824_d83f8054_0d7551fe_0d04fd3d; +defparam bootram.RAM3.INIT_1C=256'h2b71902b_12337198_75703381_04fd3d0d_0c853d0d_81547380_519bd73f_e0055276; +defparam bootram.RAM3.INIT_1D=256'h0d883d70_0d04ea3d_5452853d_52535456_7107800c_07831633_70882b72_07821433; +defparam bootram.RAM3.INIT_1E=256'h9d387381_7381ff2e_70335154_57557417_84059d05_b43f8002_52685194_545780c0; +defparam bootram.RAM3.INIT_1F=256'h55be7527_8b398115_85388154_2e098106_54738199_16703351_06943874_aa2e0981; +defparam bootram.RAM3.INIT_20=256'h845380dc_e43f8055_52795193_70545484_3d0d863d_3d0d04f9_73800c98_d1388054; +defparam bootram.RAM3.INIT_21=256'he0940c04_04810b81_0c893d0d_81557480_81068338_08752e09_99c43f80_c8527351; +defparam bootram.RAM3.INIT_22=256'h81065151_708d2a70_81b8b408_5189bb3f_ff065580_3f800881_d13f8abc_fc3d0d8d; +defparam bootram.RAM3.INIT_23=256'h8008802e_51febf3f_3fb0800a_8451e1a4_b53880dd_81833974_80dccc51_54738838; +defparam bootram.RAM3.INIT_24=256'hdde85180_84b53f80_b0800a51_51e6d93f_813f82ac_3f815189_b051e190_9a3880dd; +defparam bootram.RAM3.INIT_25=256'hff529880_805380ff_e33f8380_deb451e0_2ebb3880_3f800880_0a51fee3_cc399880; +defparam bootram.RAM3.INIT_26=256'h82ac51e6_51e0bd3f_3f80df84_9b3ffee5_82ac51e6_51e0cd3f_3f80dee0_0a5192b9; +defparam bootram.RAM3.INIT_27=256'h0d757053_0c04fd3d_7180e4bc_863d0d04_51e0a93f_3980dfc0_83e93f88_8b3f8051; +defparam bootram.RAM3.INIT_28=256'h2d853d0d_38735172_72802e85_e4bc0853_de9a3f80_a052a051_54eab83f_80e08c52; +defparam bootram.RAM3.INIT_29=256'h04fc3d0d_2d843d0d_38805172_72802e85_e4bc0853_ddfe3f80_a0528051_04fe3d0d; +defparam bootram.RAM3.INIT_2A=256'h08868006_38820b80_802e80ec_54815571_81065153_08862a70_3fff0b80_9a518987; +defparam bootram.RAM3.INIT_2B=256'h54718480_8a3987e8_802e8e38_388a5471_8280248a_2e9b3871_54718280_535580e4; +defparam bootram.RAM3.INIT_2C=256'h83067207_088a2c70_2a8c0680_ba3f7188_52855188_c23f8008_54845188_2e8338ff; +defparam bootram.RAM3.INIT_2D=256'hc8110852_8c0680e2_3f71822b_5452debb_c4555351_c80c80e0_337080e4_80e18411; +defparam bootram.RAM3.INIT_2E=256'ha338fec1_2e098106_a6387481_0c74822e_7480e4c0_082e9838_7480e4c0_52ded53f; +defparam bootram.RAM3.INIT_2F=256'h51fdfb3f_fea73f73_80e4c40c_2e8e3873_80e4c408_06963873_822e0981_3f9e3974; +defparam bootram.RAM3.INIT_30=256'h0b80e4c4_e4c00cff_3f800b80_0851879c_daa93f80_04fd3d0d_3f863d0d_995187c7; +defparam bootram.RAM3.INIT_31=256'he03f8451_528451e4_c73fbabd_529c5187_3f81ae80_985187d0_a63f8d52_0c995187; +defparam bootram.RAM3.INIT_32=256'h8d388008_7380082e_5186f43f_87aa3f84_53548451_f49f0670_08908007_87893f80; +defparam bootram.RAM3.INIT_33=256'h0d04fd3d_833f853d_52805187_08848007_86dd3f80_d63f8051_e0dc51e7_53735280; +defparam bootram.RAM3.INIT_34=256'h73109006_71730707_812a8806_2a840672_2a077183_82067187_3370852a_0d029705; +defparam bootram.RAM3.INIT_35=256'hff0682c0_2b077081_72077887_80c00670_0676852b_077081ff_06717307_74832ba0; +defparam bootram.RAM3.INIT_36=256'hff51ff9e_0a075381_0a0681d0_3d0d74d0_3d0d04fe_55555285_53515552_800c5152; +defparam bootram.RAM3.INIT_37=256'h813f7288_80e151ff_51ff873f_ff8c3fb2_3f819951_aa51ff92_ff983f81_3f81ff51; +defparam bootram.RAM3.INIT_38=256'h3f72982a_8151fee2_fee83f81_ed3fb251_ff0651fe_f53f7281_065252fe_2a7081ff; +defparam bootram.RAM3.INIT_39=256'h51febf3f_fec43f80_3f81a151_b051feca_53fecf3f_81ff0652_72902a70_51fedb3f; +defparam bootram.RAM3.INIT_3A=256'h04ffaf3d_3f843d0d_8051fea6_51feab3f_feb03fa0_b53f8051_3fa051fe_8e51feba; +defparam bootram.RAM3.INIT_3B=256'h9451e5bf_945280e1_38775382_82932690_58595777_08841208_0880da3d_0d80d83d; +defparam bootram.RAM3.INIT_3C=256'h80ca3875_7580e426_2e80e938_387580e4_80e62698_80cc3875_7580e62e_3f81d039; +defparam bootram.RAM3.INIT_3D=256'h81953975_2e80f738_387580f2_80f3268b_819b3875_7580f32e_3881ac39_80e12ea5; +defparam bootram.RAM3.INIT_3E=256'h8c943f80_3f800841_80398c90_08084181_d7d33f80_3980c15f_da38818b_80f72e80; +defparam bootram.RAM3.INIT_3F=256'h5f80d639_f93f80c5_e0055189_80d33dfd_8c170852_90170853_5f80ee39_084280c6; +defparam bootram.RAM4.INIT_00=256'h5fb73994_bc3980c2_3880c45f_75802e86_81ff0656_bb3f8008_e005518a_80d33dfd; +defparam bootram.RAM4.INIT_01=256'h528c1708_53901708_3dfe8005_a43980d3_3f80d75f_085188dd_08528c17_17539017; +defparam bootram.RAM4.INIT_02=256'hec055480_80d33dfd_5f829455_3f8339a0_8051fcff_3980d35f_80d25f8d_518bba3f; +defparam bootram.RAM4.INIT_03=256'h8251ec9b_ec388380_58887826_77348118_57577533_d53d7905_58771980_0b833d5a; +defparam bootram.RAM4.INIT_04=256'h028405ab_02a70533_3ff93d0d_ff518398_51d8e03f_0d80e1e0_0d04803d_3f80d33d; +defparam bootram.RAM4.INIT_05=256'h0d7a7c7f_0d04f83d_9e3f893d_528051e5_54755381_88805598_2b075757_05337188; +defparam bootram.RAM4.INIT_06=256'h58330284_76708105_738a3d34_81175754_25b73875_56548074_5874ff16_7f5a5757; +defparam bootram.RAM4.INIT_07=256'hef3f7380_548a51dd_0881ff06_dcc13f80_81ff0651_fc055277_82538a3d_05a10534; +defparam bootram.RAM4.INIT_08=256'hdc567588_56748338_335580de_0d02a305_0d04fa3d_800c8a3d_39815473_2e8538c1; +defparam bootram.RAM4.INIT_09=256'hab053389_0d7c5702_0d04f93d_893f883d_80d051ff_5381f752_883dfc05_3d348154; +defparam bootram.RAM4.INIT_0A=256'h802e9e38_70565473_0881ff06_dbe13f80_33705256_5202a705_893dfc05_3d348153; +defparam bootram.RAM4.INIT_0B=256'h5574800c_2e833881_56547380_81ff0670_a43f8008_527551da_3876537b_80772597; +defparam bootram.RAM4.INIT_0C=256'h56567480_0b883d33_ffa03f80_5280d051_055381f7_54883dfc_fa3d0d81_893d0d04; +defparam bootram.RAM4.INIT_0D=256'h0ca60b81_0b81c080_940c80eb_990b81c0_883d0d04_5675800c_06833881_de2e0981; +defparam bootram.RAM4.INIT_0E=256'h820b81c0_c0980c51_70810781_2bbe8006_3d0d7288_b00c0480_b00b81c0_c0ac0c89; +defparam bootram.RAM4.INIT_0F=256'h803d0d72_823d0d04_a808800c_f13881c0_51515170_2a708106_a4087081_a00c81c0; +defparam bootram.RAM4.INIT_10=256'h70812a70_81c0a408_81c0a00c_9c0c840b_517381c0_81c0980c_06708107_882bbe80; +defparam bootram.RAM4.INIT_11=256'h91387583_55575771_72830655_0d787a7c_ff39fa3d_823d0d04_5170f138_81065151; +defparam bootram.RAM4.INIT_12=256'h94387382_55737527_822a7255_88ca3f72_86388151_5271802e_38728306_0652718a; +defparam bootram.RAM4.INIT_13=256'h708f0680_7470842a_04fe3d0d_39883d0d_811454e9_0c525452_12700872_2b771177; +defparam bootram.RAM4.INIT_14=256'h803d0d82_843d0d04_53d3cf3f_ec113352_8f0680e1_d3dc3f72_54515353_e1ec1133; +defparam bootram.RAM4.INIT_15=256'hff067a8c_05337880_3d0d0293_3d0d04fe_70f13882_06515151_882a7081_e0900870; +defparam bootram.RAM4.INIT_16=256'h800c7182_387682e0_515170f1_70810651_0870882a_5382e090_c0800753_80060780; +defparam bootram.RAM4.INIT_17=256'h90087088_963882e0_5172802e_e0900c72_82800782_e0980c71_81ff0682_e0900c75; +defparam bootram.RAM4.INIT_18=256'he0940c88_0d810b82_0d04fc3d_800c843d_80085170_f13882e0_51515170_2a708106; +defparam bootram.RAM4.INIT_19=256'h81528151_548a8053_88805590_04fc3d0d_3f863d0d_8051ff87_80538052_80558854; +defparam bootram.RAM4.INIT_1A=256'hfed53f86_81528051_88548653_0d888055_0d04fc3d_800c863d_0881ff06_fef13f80; +defparam bootram.RAM4.INIT_1B=256'hff065170_3f800881_803d0deb_823d0d04_8106800c_80088132_3d0dca3f_3d0d0480; +defparam bootram.RAM4.INIT_1C=256'h8055a054_ffb43f88_9b38dd3f_75800826_5684e33f_fb3d0d77_823d0d04_802ef438; +defparam bootram.RAM4.INIT_1D=256'h80cb3d08_80c93d08_ffba3d0d_873d0d04_51fe843f_53815280_069b0a07_75fe9b0a; +defparam bootram.RAM4.INIT_1E=256'h805381ff_81a73882_73800826_54849f3f_b4387517_81ff2681_57805573_ff115657; +defparam bootram.RAM4.INIT_1F=256'h9f3f7482_fed43ffd_3ffefd3f_73518aea_cb3d0852_3f755380_52548c8f_52883d70; +defparam bootram.RAM4.INIT_20=256'h0c88a00b_0b82e098_e0800c81_c00a0782_c00a0680_900c76fe_800b82e0_e0980c88; +defparam bootram.RAM4.INIT_21=256'h0c54fe84_0882e08c_fe801570_3d558f56_ef3f80c8_e0900cfc_8aa00b82_82e0900c; +defparam bootram.RAM4.INIT_22=256'h88800b82_e0800c54_15700882_0c54fe8c_0882e084_fe881570_e0880c54_15700882; +defparam bootram.RAM4.INIT_23=256'he0980c81_38800b82_8025ffbc_16565675_3fff1690_900cfcb0_800b82e0_e0900c8a; +defparam bootram.RAM4.INIT_24=256'h082680cb_80577380_5682db3f_12575a56_797b7d72_04f93d0d_80c83d0d_5574800c; +defparam bootram.RAM4.INIT_25=256'h27833876_55577675_80743175_2ea23882_06547380_387581ff_802e80c3_38815774; +defparam bootram.RAM4.INIT_26=256'h807527e1_38745482_74802e8e_31575956_74197676_eb3f7316_527551fd_54775373; +defparam bootram.RAM4.INIT_27=256'h802e8d38_56545573_0d76787a_0d04fc3d_800c893d_3f815776_dc39fd8c_38828054; +defparam bootram.RAM4.INIT_28=256'hcb3f8008_0ca63981_160c8075_0c800b84_800b8816_74279038_ed3f8008_73135481; +defparam bootram.RAM4.INIT_29=256'h51fcc93f_88160c71_84160c71_760c7406_80083072_5281bd3f_ff165651_30707406; +defparam bootram.RAM4.INIT_2A=256'h14088415_38815388_71802e9f_06705452_800881ff_54fc983f_fd3d0d75_863d0d04; +defparam bootram.RAM4.INIT_2B=256'h0d04fc3d_800c853d_3f805372_0c51fc94_05708816_14088008_81823f88_082e9438; +defparam bootram.RAM4.INIT_2C=256'h04ff3d0d_0c863d0d_800a0680_3f8008fe_8151faa3_0a538152_a05481f9_0d888055; +defparam bootram.RAM4.INIT_2D=256'h81069338_70a02e09_06545151_800881ff_7081ff06_8008882a_a038d73f_80e4cc08; +defparam bootram.RAM4.INIT_2E=256'hc03f8008_833d0d04_3f71800c_8438f5b2_52827127_08ea1152_0c80e4cc_7180e4cc; +defparam bootram.RAM4.INIT_2F=256'h04f63d0d_082b800c_3f810b80_0c04ffa9_80082b80_f33f810b_33800c04_80e2c205; +defparam bootram.RAM4.INIT_30=256'he0800c81_7c882b82_82e0840c_900c8b0b_800b82e0_e0980c88_3f800b82_7d56f998; +defparam bootram.RAM4.INIT_31=256'h2780d338_80547376_e73f7e55_e0900cf8_8aa80b82_82e0900c_0c88a80b_0b82e098; +defparam bootram.RAM4.INIT_32=256'he084085a_88085982_085882e0_3f82e08c_900cf8cc_800b82e0_e0900c8a_88800b82; +defparam bootram.RAM4.INIT_33=256'h71175170_73279138_53805271_27833870_90537073_75315257_5b883d76_82e08008; +defparam bootram.RAM4.INIT_34=256'h803d0d72_8c3d0d04_82e0980c_a939800b_721454ff_1252ec39_05573481_33757081; +defparam bootram.RAM4.INIT_35=256'h3f800870_085182de_8c088805_8c050852_80538c08_0cfd3d0d_8c08028c_51f7893f; +defparam bootram.RAM4.INIT_36=256'h05085182_528c0888_088c0508_0d81538c_8c0cfd3d_048c0802_3d0d8c0c_800c5485; +defparam bootram.RAM4.INIT_37=256'h0c8c0888_8c08fc05_3d0d800b_028c0cf9_0c048c08_853d0d8c_70800c54_b93f8008; +defparam bootram.RAM4.INIT_38=256'h08883881_8c08fc05_08f4050c_0c800b8c_8c088805_88050830_ab388c08_05088025; +defparam bootram.RAM4.INIT_39=256'h0508308c_388c088c_088025ab_8c088c05_08fc050c_f405088c_050c8c08_0b8c08f4; +defparam bootram.RAM4.INIT_3A=256'h05088c08_0c8c08f0_8c08f005_8838810b_08fc0508_f0050c8c_800b8c08_088c050c; +defparam bootram.RAM4.INIT_3B=256'h548c08fc_08f8050c_8008708c_5181a73f_08880508_0508528c_538c088c_fc050c80; +defparam bootram.RAM4.INIT_3C=256'h0d8c0c04_0c54893d_05087080_0c8c08f8_8c08f805_f8050830_8c388c08_0508802e; +defparam bootram.RAM4.INIT_3D=256'h08308c08_8c088805_80259338_08880508_fc050c8c_800b8c08_0cfb3d0d_8c08028c; +defparam bootram.RAM4.INIT_3E=256'h050c8153_308c088c_088c0508_258c388c_8c050880_050c8c08_0b8c08fc_88050c81; +defparam bootram.RAM4.INIT_3F=256'h802e8c38_08fc0508_050c548c_708c08f8_ad3f8008_88050851_08528c08_8c088c05; +defparam bootram.RAM5.INIT_00=256'h028c0cfd_0c048c08_873d0d8c_70800c54_08f80508_f8050c8c_08308c08_8c08f805; +defparam bootram.RAM5.INIT_01=256'h388c08fc_050827ac_088c0888_8c088c05_08f8050c_0c800b8c_8c08fc05_3d0d810b; +defparam bootram.RAM5.INIT_02=256'h08fc0508_8c050c8c_08108c08_8c088c05_08249938_8c088c05_a338800b_0508802e; +defparam bootram.RAM5.INIT_03=256'h26a1388c_08880508_8c05088c_c9388c08_08802e80_8c08fc05_050cc939_108c08fc; +defparam bootram.RAM5.INIT_04=256'hf8050c8c_08078c08_8c08fc05_08f80508_88050c8c_08318c08_8c088c05_08880508; +defparam bootram.RAM5.INIT_05=256'h90050880_af398c08_8c050cff_812a8c08_088c0508_fc050c8c_812a8c08_08fc0508; +defparam bootram.RAM5.INIT_06=256'h518c08f4_08f4050c_0508708c_398c08f8_050c518d_708c08f4_08880508_2e8f388c; +defparam bootram.RAM5.INIT_07=256'h06517080_74740783_72278c38_56565283_0d787779_0c04fc3d_853d0d8c_0508800c; +defparam bootram.RAM5.INIT_08=256'h15ff1454_38811581_098106bd_5372712e_33743352_2ea03874_125271ff_2eb038ff; +defparam bootram.RAM5.INIT_09=256'h81068f38_73082e09_54517008_0d047474_800c863d_e238800b_2e098106_555571ff; +defparam bootram.RAM5.INIT_0A=256'h0d04fc3d_800c863d_39727131_5555ffaf_e9387073_51718326_fc145454_84118414; +defparam bootram.RAM5.INIT_0B=256'h71ff2e98_38ff1252_70802ea7_07830651_8c387275_558f7227_7b555555_0d767079; +defparam bootram.RAM5.INIT_0C=256'h3d0d0474_74800c86_8106ea38_71ff2e09_34ff1252_70810556_05543374_38727081; +defparam bootram.RAM5.INIT_0D=256'h05540871_0c727084_70840553_05540871_0c727084_70840553_05540871_51727084; +defparam bootram.RAM5.INIT_0E=256'h95387270_38837227_718f26c9_0cf01252_70840553_05540871_0c727084_70840553; +defparam bootram.RAM5.INIT_0F=256'h71028c05_3d0d7679_ff8339fc_ed387054_52718326_530cfc12_71708405_84055408; +defparam bootram.RAM5.INIT_10=256'h38737370_71ff2e93_38ff1252_70802ea2_74830651_72278a38_55535583_9f053357; +defparam bootram.RAM5.INIT_11=256'h7071902b_882b7507_0d047474_800c863d_06ef3874_ff2e0981_ff125271_81055534; +defparam bootram.RAM5.INIT_12=256'h530c7271_71708405_05530c72_72717084_8405530c_38727170_8f7227a5_07515451; +defparam bootram.RAM5.INIT_13=256'h718326f2_0cfc1252_70840553_90387271_38837227_718f26dd_0cf01252_70840553; +defparam bootram.RAM5.INIT_14=256'h5170802e_74078306_80d93871_5272802e_70545555_0d787a7c_9039fa3d_387053ff; +defparam bootram.RAM5.INIT_15=256'h81873870_3872802e_098106a9_5174712e_33743356_2eb13871_135372ff_80d438ff; +defparam bootram.RAM5.INIT_16=256'h33743356_06d13871_ff2e0981_55555272_8115ff15_fc388112_70802e80_81ff0651; +defparam bootram.RAM5.INIT_17=256'h27883871_57558373_0d047174_800c883d_51525270_06717131_067581ff_517081ff; +defparam bootram.RAM5.INIT_18=256'hff120670_09f7fbfd_38740870_72802eb1_39fc1353_5552ff97_88387476_0874082e; +defparam bootram.RAM5.INIT_19=256'hd0387476_0876082e_27d03874_57558373_84158417_51709a38_80065151_f8848281; +defparam bootram.RAM5.INIT_1A=256'h387380e4_72812e9e_9c085454_800b80e2_04fd3d0d_0c883d0d_39800b80_5552fedf; +defparam bootram.RAM5.INIT_1B=256'he4d00cff_a33f7280_800851f6_ffb9bb3f_dc528151_973f80e2_fb3fffb1_d00cffb1; +defparam bootram.RAM5.INIT_1C=256'h0d80e2e4_ff39ff3d_f6863f00_3f800851_51ffb99e_e2dc5281_b0fa3f80_b1de3fff; +defparam bootram.RAM5.INIT_1D=256'h833d0d04_8106f138_70ff2e09_70085252_702dfc12_ff2e9138_08525270_0bfc0570; +defparam bootram.RAM5.INIT_1E=256'h6c207061_6e74726f_6e20636f_6f722069_21457272_00000040_3f040000_04ffb289; +defparam bootram.RAM5.INIT_1F=256'h74696269_6f6d7061_65642063_70656374_3a204578_646c6572_2068616e_636b6574; +defparam bootram.RAM5.INIT_20=256'h21457272_25640a00_676f7420_62757420_25642c20_62657220_206e756d_6c697479; +defparam bootram.RAM5.INIT_21=256'h3a204578_646c6572_2068616e_636b6574_6c207061_6e74726f_6e20636f_6f722069; +defparam bootram.RAM5.INIT_22=256'h7420676f_2c206275_68202564_656e6774_6164206c_61796c6f_65642070_70656374; +defparam bootram.RAM5.INIT_23=256'h70656564_643a2073_616e6765_6b206368_206c696e_0a657468_0a000000_74202564; +defparam bootram.RAM5.INIT_24=256'h6f616465_6f6f746c_44502062_31302055_50204e32_0a555352_640a0000_203d2025; +defparam bootram.RAM5.INIT_25=256'h723a2025_756d6265_7479206e_62696c69_70617469_20636f6d_46504741_720a0000; +defparam bootram.RAM5.INIT_26=256'h756d6265_7479206e_62696c69_70617469_20636f6d_77617265_4669726d_640a0000; +defparam bootram.RAM5.INIT_27=256'h65727920_65636f76_69702072_476f7420_00000000_61646472_640a0000_723a2025; +defparam bootram.RAM5.INIT_28=256'h000007cc_000007cc_000007cc_000007cc_00000650_00000000_65743a20_7061636b; +defparam bootram.RAM5.INIT_29=256'h000007cc_000007a2_000007cc_000007cc_000006a5_000006bd_000007cc_000007cc; +defparam bootram.RAM5.INIT_2A=256'h00000778_000007cc_0000065d_00000715_000007cc_000006d3_000007cc_000007cc; +defparam bootram.RAM5.INIT_2B=256'h45000000_01b200d9_05160364_14580a2c_3fff0000_0050c285_c0a80a02_00000751; +defparam bootram.RAM5.INIT_2C=256'h00000000_43444546_38394142_34353637_30313233_2e256400_642e2564_25642e25; +defparam bootram.RAM5.INIT_2D=256'h656e7420_69676e6d_6420616c_3a206261_5f706b74_73656e64_ffff0000_ffffffff; +defparam bootram.RAM5.INIT_2E=256'h6f6e3a20_636f6d6d_6e65745f_66000000_72206275_6e642f6f_656e2061_6f66206c; +defparam bootram.RAM5.INIT_2F=256'h666f7220_696e6720_6c6f6f6b_63686520_74206361_6f206869_65642074_6661696c; +defparam bootram.RAM5.INIT_30=256'h3d202564_697a6520_72642073_20776569_6172703a_646c655f_0a68616e_00000000; +defparam bootram.RAM5.INIT_31=256'h3a202564_67746873_206c656e_74656e74_6e736973_696e636f_55445020_0a000000; +defparam bootram.RAM5.INIT_32=256'h696e2073_50322b20_20555352_74696e67_53746172_0b0b0b0b_00000000_2025640a; +defparam bootram.RAM5.INIT_33=256'h6172652e_69726d77_66652066_67207361_6164696e_2e204c6f_6d6f6465_61666520; +defparam bootram.RAM5.INIT_34=256'h6374696f_726f6475_69642070_2076616c_20666f72_6b696e67_43686563_00000000; +defparam bootram.RAM5.INIT_35=256'h74696f6e_6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650; +defparam bootram.RAM5.INIT_36=256'h6720746f_7074696e_7474656d_642e2041_666f756e_61676520_4120696d_20465047; +defparam bootram.RAM5.INIT_37=256'h46504741_696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f; +defparam bootram.RAM5.INIT_38=256'h6820746f_726f7567_67207468_6c6c696e_2e0a4661_6f756e64_67652066_20696d61; +defparam bootram.RAM5.INIT_39=256'h6f647563_64207072_56616c69_72652e00_726d7761_6e206669_6c742d69_20627569; +defparam bootram.RAM5.INIT_3A=256'h2e2e2e00_64696e67_204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e; +defparam bootram.RAM5.INIT_3B=256'h6d616765_6e672069_61727469_2e205374_64696e67_206c6f61_73686564_46696e69; +defparam bootram.RAM5.INIT_3C=256'h70726f67_61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f_2e000000; +defparam bootram.RAM5.INIT_3D=256'h6e210000_61707065_65722068_206e6576_6f756c64_73207368_20546869_72616d21; +defparam bootram.RAM5.INIT_3E=256'h20666f75_77617265_6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076; +defparam bootram.RAM5.INIT_3F=256'h2d696e20_75696c74_746f2062_75676820_7468726f_696e6720_46616c6c_6e642e20; +defparam bootram.RAM6.INIT_00=256'h00000000_2025640a_7420746f_64207365_53706565_2e000000_77617265_6669726d; +defparam bootram.RAM6.INIT_01=256'h45545249_53594d4d_58000000_57455f52_58000000_57455f54_00000000_4e4f4e45; +defparam bootram.RAM6.INIT_02=256'h5048595f_6c3a2000_6e74726f_7720636f_20666c6f_726e6574_65746865_43000000; +defparam bootram.RAM6.INIT_03=256'h20307825_20676f74_7825782c_74652030_2077726f_4144563a_4e45475f_4155544f; +defparam bootram.RAM6.INIT_04=256'h6e207570_6f722069_21457272_00030203_00000001_00030003_00000000_780a0000; +defparam bootram.RAM6.INIT_05=256'h64207061_65637465_20457870_6c65723a_68616e64_6b657420_20706163_64617465; +defparam bootram.RAM6.INIT_06=256'h00000000_2025640a_20676f74_20627574_2025642c_6e677468_64206c65_796c6f61; +defparam bootram.RAM6.INIT_07=256'h64756d6d_43444546_38394142_34353637_30313233_00000000_6f72740a_0a0a6162; +defparam bootram.RAM6.INIT_08=256'h00000000_00000000_ffffff00_ffff00ff_ff00ffff_00ffffff_65000000_792e6578; +defparam bootram.RAM6.INIT_09=256'hffff0031_05050400_01010100_3fff0000_0050c285_c0a80a02_0000316c_00000000; +defparam bootram.RAM6.INIT_0A=256'h000030fc_10101200_00003038_00003030_00003028_00003020_000b0000_0018000f; +defparam bootram.RAM6.INIT_0B=256'h00000000_00000000_00000000_00000000_00000000_ffffffff_00000000_ffffffff; +defparam bootram.RAM6.INIT_0C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_0F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_37=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_38=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_00=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_02=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_03=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_04=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_06=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_37=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_38=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; diff --git a/usrp2/top/N2x0/capture_ddrlvds.v b/usrp2/top/N2x0/capture_ddrlvds.v new file mode 100644 index 000000000..d263e0cfa --- /dev/null +++ b/usrp2/top/N2x0/capture_ddrlvds.v @@ -0,0 +1,38 @@ + + +module capture_ddrlvds + #(parameter WIDTH=7) + (input clk, + input ssclk_p, + input ssclk_n, + input [WIDTH-1:0] in_p, + input [WIDTH-1:0] in_n, + output reg [(2*WIDTH)-1:0] out); + + wire [WIDTH-1:0] ddr_dat; + wire ssclk; + wire [(2*WIDTH)-1:0] out_pre1; + reg [(2*WIDTH)-1:0] out_pre2; + + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) + clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); + + genvar i; + generate + for(i = 0; i < WIDTH; i = i + 1) + begin : gen_lvds_pins + IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("FALSE")) ibufds + (.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) ); + IDDR2 #(.DDR_ALIGNMENT("C1")) iddr2 + (.Q0(out_pre1[2*i]), .Q1(out_pre1[(2*i)+1]), .C0(ssclk), .C1(~ssclk), + .CE(1'b1), .D(ddr_dat[i]), .R(1'b0), .S(1'b0)); + end + endgenerate + + always @(posedge clk) + out_pre2 <= out_pre1; + + always @(posedge clk) + out <= out_pre2; + +endmodule // capture_ddrlvds diff --git a/usrp2/top/N2x0/rev4_defs.v b/usrp2/top/N2x0/rev4_defs.v new file mode 100644 index 000000000..e37f34851 --- /dev/null +++ b/usrp2/top/N2x0/rev4_defs.v @@ -0,0 +1 @@ +`define LVDS 1 diff --git a/usrp2/top/N2x0/u2plus.ucf b/usrp2/top/N2x0/u2plus.ucf new file mode 100755 index 000000000..5fbe55c26 --- /dev/null +++ b/usrp2/top/N2x0/u2plus.ucf @@ -0,0 +1,424 @@ +## Main 100 MHz Clock +NET "CLK_FPGA_P" LOC = "AA13" ; +NET "CLK_FPGA_N" LOC = "Y13" ; + +## ADC +NET "ADC_clkout_p" LOC = "P1" ; +NET "ADC_clkout_n" LOC = "P2" ; +NET "ADCA_12_p" LOC = "Y1" ; +NET "ADCA_12_n" LOC = "Y2" ; +NET "ADCA_10_p" LOC = "W3" ; +NET "ADCA_10_n" LOC = "W4" ; +NET "ADCA_8_p" LOC = "T7" ; +NET "ADCA_8_n" LOC = "U6" ; +NET "ADCA_6_p" LOC = "U5" ; +NET "ADCA_6_n" LOC = "V5" ; +NET "ADCA_4_p" LOC = "T10" ; +NET "ADCA_4_n" LOC = "T9" ; +NET "ADCA_2_p" LOC = "V1" ; +NET "ADCA_2_n" LOC = "V2" ; +NET "ADCA_0_p" LOC = "R8" ; +NET "ADCA_0_n" LOC = "R7" ; +NET "ADCB_2_p" LOC = "U7" ; +NET "ADCB_2_n" LOC = "U8" ; +NET "ADCB_0_p" LOC = "AA2" ; +NET "ADCB_0_n" LOC = "AA3" ; +NET "ADCB_4_p" LOC = "AE1" ; +NET "ADCB_4_n" LOC = "AE2" ; +NET "ADCB_6_p" LOC = "W1" ; +NET "ADCB_6_n" LOC = "W2" ; +NET "ADCB_8_p" LOC = "U3" ; +NET "ADCB_8_n" LOC = "V4" ; +NET "ADCB_10_p" LOC = "J1" ; +NET "ADCB_10_n" LOC = "K1" ; +NET "ADCB_12_p" LOC = "J3" ; +NET "ADCB_12_n" LOC = "J2" ; + +## DAC +NET "DAC_LOCK" LOC = "P4" ; +NET "DACA<0>" LOC = "P8" ; +NET "DACA<1>" LOC = "P9" ; +NET "DACA<2>" LOC = "R5" ; +NET "DACA<3>" LOC = "R6" ; +NET "DACA<4>" LOC = "P7" ; +NET "DACA<5>" LOC = "P6" ; +NET "DACA<6>" LOC = "T3" ; +NET "DACA<7>" LOC = "T4" ; +NET "DACA<8>" LOC = "R3" ; +NET "DACA<9>" LOC = "R4" ; +NET "DACA<10>" LOC = "R2" ; +NET "DACA<11>" LOC = "N1" ; +NET "DACA<12>" LOC = "N2" ; +NET "DACA<13>" LOC = "N5" ; +NET "DACA<14>" LOC = "N4" ; +NET "DACA<15>" LOC = "M2" ; +NET "DACB<0>" LOC = "M5" ; +NET "DACB<1>" LOC = "M6" ; +NET "DACB<2>" LOC = "M4" ; +NET "DACB<3>" LOC = "M3" ; +NET "DACB<4>" LOC = "M8" ; +NET "DACB<5>" LOC = "M7" ; +NET "DACB<6>" LOC = "L4" ; +NET "DACB<7>" LOC = "L3" ; +NET "DACB<8>" LOC = "K3" ; +NET "DACB<9>" LOC = "K2" ; +NET "DACB<10>" LOC = "K5" ; +NET "DACB<11>" LOC = "K4" ; +NET "DACB<12>" LOC = "M10" ; +NET "DACB<13>" LOC = "M9" ; +NET "DACB<14>" LOC = "J5" ; +NET "DACB<15>" LOC = "J4" ; + +## TX DB GPIO +NET "io_tx<15>" LOC = "K6" ; +NET "io_tx<14>" LOC = "L7" ; +NET "io_tx<13>" LOC = "H2" ; +NET "io_tx<12>" LOC = "H1" ; +NET "io_tx<11>" LOC = "L10" ; +NET "io_tx<10>" LOC = "L9" ; +NET "io_tx<9>" LOC = "G3" ; +NET "io_tx<8>" LOC = "F3" ; +NET "io_tx<7>" LOC = "K7" ; +NET "io_tx<6>" LOC = "J6" ; +NET "io_tx<5>" LOC = "E1" ; +NET "io_tx<4>" LOC = "F2" ; +NET "io_tx<3>" LOC = "J7" ; +NET "io_tx<2>" LOC = "H6" ; +NET "io_tx<1>" LOC = "F5" ; +NET "io_tx<0>" LOC = "G4" ; + +## RX DB GPIO +NET "io_rx<15>" LOC = "AD1" ; +NET "io_rx<14>" LOC = "AD2" ; +NET "io_rx<13>" LOC = "AC2" ; +NET "io_rx<12>" LOC = "AC3" ; +NET "io_rx<11>" LOC = "W7" ; +NET "io_rx<10>" LOC = "W6" ; +NET "io_rx<9>" LOC = "U9" ; +NET "io_rx<8>" LOC = "V8" ; +NET "io_rx<7>" LOC = "AB1" ; +NET "io_rx<6>" LOC = "AC1" ; +NET "io_rx<5>" LOC = "V7" ; +NET "io_rx<4>" LOC = "V6" ; +NET "io_rx<3>" LOC = "Y5" ; +NET "io_rx<2>" LOC = "R10" ; +NET "io_rx<1>" LOC = "R1" ; +NET "io_rx<0>" LOC = "M1" ; + +## MISC +NET "leds<5>" LOC = "AF25" ; +NET "leds<4>" LOC = "AE25" ; +NET "leds<3>" LOC = "AF23" ; +NET "leds<2>" LOC = "AE23" ; +NET "leds<1>" LOC = "AB18" ; +NET "FPGA_RESET" LOC = "K24" ; + +## Debug +NET "debug_clk<0>" LOC = "AA10" ; +NET "debug_clk<1>" LOC = "AD11" ; +NET "debug<0>" LOC = "AC19" ; +NET "debug<1>" LOC = "AF20" ; +NET "debug<2>" LOC = "AE20" ; +NET "debug<3>" LOC = "AC16" ; +NET "debug<4>" LOC = "AB16" ; +NET "debug<5>" LOC = "AF19" ; +NET "debug<6>" LOC = "AE19" ; +NET "debug<7>" LOC = "V15" ; +NET "debug<8>" LOC = "U15" ; +NET "debug<9>" LOC = "AE17" ; +NET "debug<10>" LOC = "AD17" ; +NET "debug<11>" LOC = "V14" ; +NET "debug<12>" LOC = "W15" ; +NET "debug<13>" LOC = "AC15" ; +NET "debug<14>" LOC = "AD14" ; +NET "debug<15>" LOC = "AC14" ; +NET "debug<16>" LOC = "AC11" ; +NET "debug<17>" LOC = "AB12" ; +NET "debug<18>" LOC = "AC12" ; +NET "debug<19>" LOC = "V13" ; +NET "debug<20>" LOC = "W13" ; +NET "debug<21>" LOC = "AE8" ; +NET "debug<22>" LOC = "AF8" ; +NET "debug<23>" LOC = "V12" ; +NET "debug<24>" LOC = "W12" ; +NET "debug<25>" LOC = "AB9" ; +NET "debug<26>" LOC = "AC9" ; +NET "debug<27>" LOC = "AC8" ; +NET "debug<28>" LOC = "AB7" ; +NET "debug<29>" LOC = "V11" ; +NET "debug<30>" LOC = "U11" ; +NET "debug<31>" LOC = "Y10" ; + +## UARTS +NET "TXD<3>" LOC = "AD20" ; +NET "TXD<2>" LOC = "AC20" ; +NET "TXD<1>" LOC = "AD19" ; +NET "RXD<3>" LOC = "AF17" ; +NET "RXD<2>" LOC = "AF15" ; +NET "RXD<1>" LOC = "AD12" ; + +## AD9510 +NET "clk_status" LOC = "AD22" ; +NET "CLK_FUNC" LOC = "AC21" ; +NET "clk_sel<0>" LOC = "AE21" ; +NET "clk_sel<1>" LOC = "AD21" ; +NET "clk_en<1>" LOC = "AA17" ; +NET "clk_en<0>" LOC = "Y17" ; + +## I2C +NET "SDA" LOC = "V16" ; +NET "SCL" LOC = "U16" ; + +## Timing +NET "PPS_IN" LOC = "AB6" ; +NET "PPS2_IN" LOC = "AA20" ; + +## SPI +NET "SEN_CLK" LOC = "AA18" ; +NET "MOSI_CLK" LOC = "W17" ; +NET "SCLK_CLK" LOC = "V17" ; +NET "MISO_CLK" LOC = "AC10" ; + +NET "SEN_DAC" LOC = "AE7" ; +NET "SCLK_DAC" LOC = "AF5" ; +NET "MOSI_DAC" LOC = "AE6" ; +NET "MISO_DAC" LOC = "Y3" ; + +NET "SCLK_ADC" LOC = "B1" ; +NET "MOSI_ADC" LOC = "J8" ; +NET "SEN_ADC" LOC = "J9" ; + +NET "MOSI_TX_ADC" LOC = "V10" ; +NET "SEN_TX_ADC" LOC = "W10" ; +NET "SCLK_TX_ADC" LOC = "AC6" ; +NET "MISO_TX_ADC" LOC = "G1" ; + +NET "MOSI_TX_DAC" LOC = "AD6" ; +NET "SEN_TX_DAC" LOC = "AE4" ; +NET "SCLK_TX_DAC" LOC = "AF4" ; + +NET "SCLK_TX_DB" LOC = "AE3" ; +NET "MOSI_TX_DB" LOC = "AF3" ; +NET "SEN_TX_DB" LOC = "W9" ; +NET "MISO_TX_DB" LOC = "AA5" ; + +NET "MOSI_RX_ADC" LOC = "E3" ; +NET "SCLK_RX_ADC" LOC = "F4" ; +NET "SEN_RX_ADC" LOC = "D3" ; +NET "MISO_RX_ADC" LOC = "C1" ; + +NET "SCLK_RX_DAC" LOC = "E4" ; +NET "SEN_RX_DAC" LOC = "K9" ; +NET "MOSI_RX_DAC" LOC = "K8" ; + +NET "SCLK_RX_DB" LOC = "G6" ; +NET "MOSI_RX_DB" LOC = "H7" ; +NET "SEN_RX_DB" LOC = "B2" ; +NET "MISO_RX_DB" LOC = "H4" ; + +## ETH PHY +NET "CLK_TO_MAC" LOC = "P26" ; + +NET "GMII_TXD<7>" LOC = "G21" ; +NET "GMII_TXD<6>" LOC = "C26" ; +NET "GMII_TXD<5>" LOC = "C25" ; +NET "GMII_TXD<4>" LOC = "J21" ; +NET "GMII_TXD<3>" LOC = "H21" ; +NET "GMII_TXD<2>" LOC = "D25" ; +NET "GMII_TXD<1>" LOC = "D24" ; +NET "GMII_TXD<0>" LOC = "E26" ; +NET "GMII_TX_EN" LOC = "D26" ; +NET "GMII_TX_ER" LOC = "J19" ; +NET "GMII_GTX_CLK" LOC = "J20" ; +NET "GMII_TX_CLK" LOC = "P25" ; + +NET "GMII_RX_CLK" LOC = "P21" ; +NET "GMII_RXD<7>" LOC = "G22" ; +NET "GMII_RXD<6>" LOC = "K19" ; +NET "GMII_RXD<5>" LOC = "K18" ; +NET "GMII_RXD<4>" LOC = "E24" ; +NET "GMII_RXD<3>" LOC = "F23" ; +NET "GMII_RXD<2>" LOC = "L18" ; +NET "GMII_RXD<1>" LOC = "L17" ; +NET "GMII_RXD<0>" LOC = "F25" ; +NET "GMII_RX_DV" LOC = "F24" ; +NET "GMII_RX_ER" LOC = "L20" ; +NET "GMII_CRS" LOC = "K20" ; +NET "GMII_COL" LOC = "G23" ; + +NET "PHY_INTn" LOC = "L22" ; +NET "MDIO" LOC = "K21" ; +NET "MDC" LOC = "J23" ; +NET "PHY_RESETn" LOC = "J22" ; +NET "ETH_LED" LOC = "H20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; + +## MIMO Interface +NET "exp_time_out_p" LOC = "Y14" ; +NET "exp_time_out_n" LOC = "AA14" ; +NET "exp_time_in_p" LOC = "N18" ; +NET "exp_time_in_n" LOC = "N17" ; +NET "exp_user_out_p" LOC = "AF14" ; +NET "exp_user_out_n" LOC = "AE14" ; +NET "exp_user_in_p" LOC = "L24" ; +NET "exp_user_in_n" LOC = "M23" ; + +## SERDES +NET "ser_enable" LOC = "R20" ; +NET "ser_prbsen" LOC = "U23" ; +NET "ser_loopen" LOC = "R19" ; +NET "ser_rx_en" LOC = "Y21" ; +NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK +NET "ser_t<15>" LOC = "V23" ; +NET "ser_t<14>" LOC = "U22" ; +NET "ser_t<13>" LOC = "V24" ; +NET "ser_t<12>" LOC = "V25" ; +NET "ser_t<11>" LOC = "W23" ; +NET "ser_t<10>" LOC = "V22" ; +NET "ser_t<9>" LOC = "T18" ; +NET "ser_t<8>" LOC = "T17" ; +NET "ser_t<7>" LOC = "Y24" ; +NET "ser_t<6>" LOC = "Y25" ; +NET "ser_t<5>" LOC = "U21" ; +NET "ser_t<4>" LOC = "T20" ; +NET "ser_t<3>" LOC = "Y22" ; +NET "ser_t<2>" LOC = "Y23" ; +NET "ser_t<1>" LOC = "U19" ; +NET "ser_t<0>" LOC = "U18" ; +NET "ser_tkmsb" LOC = "AA24" ; +NET "ser_tklsb" LOC = "AA25" ; +NET "ser_rx_clk" LOC = "P18" ; +NET "ser_r<15>" LOC = "V21" ; +NET "ser_r<14>" LOC = "U20" ; +NET "ser_r<13>" LOC = "AA22" ; +NET "ser_r<12>" LOC = "AA23" ; +NET "ser_r<11>" LOC = "V18" ; +NET "ser_r<10>" LOC = "V19" ; +NET "ser_r<9>" LOC = "AB23" ; +NET "ser_r<8>" LOC = "AC26" ; +NET "ser_r<7>" LOC = "AB26" ; +NET "ser_r<6>" LOC = "AD26" ; +NET "ser_r<5>" LOC = "AC25" ; +NET "ser_r<4>" LOC = "W20" ; +NET "ser_r<3>" LOC = "W21" ; +NET "ser_r<2>" LOC = "AC23" ; +NET "ser_r<1>" LOC = "AC24" ; +NET "ser_r<0>" LOC = "AE26" ; +NET "ser_rkmsb" LOC = "AD25" ; +NET "ser_rklsb" LOC = "Y20" ; + +## SRAM +NET "RAM_D<35>" LOC = "K16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<34>" LOC = "D20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<33>" LOC = "C20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<32>" LOC = "E21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<31>" LOC = "D21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<30>" LOC = "C21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<29>" LOC = "B21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<28>" LOC = "H17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<27>" LOC = "G17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<26>" LOC = "B23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<25>" LOC = "A22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<24>" LOC = "D23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<23>" LOC = "C23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<22>" LOC = "D22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<21>" LOC = "C22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<20>" LOC = "F19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<19>" LOC = "G20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<18>" LOC = "F20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<17>" LOC = "F7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<16>" LOC = "E7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<15>" LOC = "G9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<14>" LOC = "H9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<13>" LOC = "G10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<12>" LOC = "H10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<11>" LOC = "A4" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<10>" LOC = "B4" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<9>" LOC = "C5" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<8>" LOC = "D6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<7>" LOC = "J11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<6>" LOC = "K11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<5>" LOC = "B7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<4>" LOC = "C7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<3>" LOC = "B6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<2>" LOC = "C6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<1>" LOC = "C8" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<0>" LOC = "D8" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<0>" LOC = "C11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<1>" LOC = "E12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<2>" LOC = "F12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<3>" LOC = "D13" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<4>" LOC = "C12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<5>" LOC = "A12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<6>" LOC = "B12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<7>" LOC = "E14" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<8>" LOC = "F14" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<9>" LOC = "B15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<10>" LOC = "A15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<11>" LOC = "D16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<12>" LOC = "C15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<13>" LOC = "D17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<14>" LOC = "C16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<15>" LOC = "F15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<16>" LOC = "C17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<17>" LOC = "B17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<18>" LOC = "B18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<19>" LOC = "A18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<20>" LOC = "D18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<3>" LOC = "D9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<2>" LOC = "A9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<1>" LOC = "B9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<0>" LOC = "G12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_ZZ" LOC = "J12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_LDn" LOC = "H12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_OEn" LOC = "C10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_WEn" LOC = "D10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_CENn" LOC = "B10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_CLK" LOC = "A10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; + +## SPI Flash +NET "flash_miso" LOC = "AF24" ; +NET "flash_clk" LOC = "AE24" ; +NET "flash_mosi" LOC = "AB15" ; +NET "flash_cs" LOC = "AA7" ; + +## MISC FPGA, unused for now +#NET "PROG_B" LOC = "A2" ; +#NET "PUDC_B" LOC = "G8" ; +#NET "DONE" LOC = "AB21" ; +#NET "INIT_B" LOC = "AA15" ; + + +#NET "unnamed_net19" LOC = "AE9" ; # VS1 +#NET "unnamed_net18" LOC = "AF9" ; # VS0 +#NET "unnamed_net17" LOC = "AA12" ; # VS2 +#NET "unnamed_net16" LOC = "Y7" ; # M2 +#NET "unnamed_net15" LOC = "AC4" ; # M1 +#NET "unnamed_net14" LOC = "AD4" ; # M0 +#NET "unnamed_net13" LOC = "D4" ; # TMS +#NET "unnamed_net12" LOC = "E23" ; # TDO +#NET "unnamed_net11" LOC = "G7" ; # TDI +#NET "unnamed_net10" LOC = "A25" ; # TCK +#NET "unnamed_net20" LOC = "V20" ; # SUSPEND + + +NET "clk_to_mac" TNM_NET = "clk_to_mac"; +TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; + +NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; + +NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; +TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; + +NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; +TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; + +TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns; + +#NET "CLK_FPGA_P" CLOCK_DEDICATED_ROUTE = FALSE; +#PIN "DCM_INST/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; + +#NET "RAM_CLK" CLOCK_DEDICATED_ROUTE = FALSE; +#PIN "DCM_INST1/DCM_SP.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE; + + diff --git a/usrp2/top/N2x0/u2plus.v b/usrp2/top/N2x0/u2plus.v new file mode 100644 index 000000000..7bf467fde --- /dev/null +++ b/usrp2/top/N2x0/u2plus.v @@ -0,0 +1,454 @@ +`timescale 1ns / 1ps +//`define LVDS 1 +//`define DCM_FOR_RAMCLK +////////////////////////////////////////////////////////////////////////////////// + +module u2plus + ( + input CLK_FPGA_P, input CLK_FPGA_N, // Diff + + // ADC + input ADC_clkout_p, input ADC_clkout_n, + input ADCA_12_p, input ADCA_12_n, + input ADCA_10_p, input ADCA_10_n, + input ADCA_8_p, input ADCA_8_n, + input ADCA_6_p, input ADCA_6_n, + input ADCA_4_p, input ADCA_4_n, + input ADCA_2_p, input ADCA_2_n, + input ADCA_0_p, input ADCA_0_n, + input ADCB_12_p, input ADCB_12_n, + input ADCB_10_p, input ADCB_10_n, + input ADCB_8_p, input ADCB_8_n, + input ADCB_6_p, input ADCB_6_n, + input ADCB_4_p, input ADCB_4_n, + input ADCB_2_p, input ADCB_2_n, + input ADCB_0_p, input ADCB_0_n, + + // DAC + output reg [15:0] DACA, + output reg [15:0] DACB, + input DAC_LOCK, // unused for now + + // DB IO Pins + inout [15:0] io_tx, + inout [15:0] io_rx, + + // Misc, debug + output [5:1] leds, // LED4 is shared w/INIT_B + input FPGA_RESET, + output [1:0] debug_clk, + output [31:0] debug, + output [3:1] TXD, input [3:1] RXD, // UARTs + //input [3:0] dipsw, // Forgot DIP Switches... + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input CLK_FUNC, // FIXME is an input to control the 9510 + input clk_status, + + inout SCL, inout SDA, // I2C + + // PPS + input PPS_IN, input PPS2_IN, + + // SPI + output SEN_CLK, output SCLK_CLK, output MOSI_CLK, input MISO_CLK, + output SEN_DAC, output SCLK_DAC, output MOSI_DAC, input MISO_DAC, + output SEN_ADC, output SCLK_ADC, output MOSI_ADC, + output SEN_TX_DB, output SCLK_TX_DB, output MOSI_TX_DB, input MISO_TX_DB, + output SEN_TX_DAC, output SCLK_TX_DAC, output MOSI_TX_DAC, + output SEN_TX_ADC, output SCLK_TX_ADC, output MOSI_TX_ADC, input MISO_TX_ADC, + output SEN_RX_DB, output SCLK_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, + output SEN_RX_DAC, output SCLK_RX_DAC, output MOSI_RX_DAC, + output SEN_RX_ADC, output SCLK_RX_ADC, output MOSI_RX_ADC, input MISO_RX_ADC, + + // GigE PHY + input CLK_TO_MAC, + + output reg [7:0] GMII_TXD, + output reg GMII_TX_EN, + output reg GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + input GMII_RX_CLK, + input [7:0] GMII_RXD, + input GMII_RX_DV, + input GMII_RX_ER, + input GMII_COL, + input GMII_CRS, + + input PHY_INTn, // open drain + inout MDIO, + output MDC, + output PHY_RESETn, + output ETH_LED, + +// input POR, + + // Expansion + input exp_time_in_p, input exp_time_in_n, // Diff + output exp_time_out_p, output exp_time_out_n, // Diff + input exp_user_in_p, input exp_user_in_n, // Diff + output exp_user_out_p, output exp_user_out_n, // Diff + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output reg [15:0] ser_t, + output reg ser_tklsb, + output reg ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // SRAM + inout [35:0] RAM_D, + output [20:0] RAM_A, + output [3:0] RAM_BWn, + output RAM_ZZ, + output RAM_LDn, + output RAM_OEn, + output RAM_WEn, + output RAM_CENn, + output RAM_CLK, + + // SPI Flash + output flash_cs, + output flash_clk, + output flash_mosi, + input flash_miso + ); + + wire CLK_TO_MAC_int, CLK_TO_MAC_int2; + IBUFG phyclk (.O(CLK_TO_MAC_int), .I(CLK_TO_MAC)); + BUFG phyclk2 (.O(CLK_TO_MAC_int2), .I(CLK_TO_MAC_int)); + + // FPGA-specific pins connections + wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + wire exp_time_in; + IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); + defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_time_out; + OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); + defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; + + wire exp_user_in; + IBUFDS exp_user_in_pin (.O(exp_user_in),.I(exp_user_in_p),.IB(exp_user_in_n)); + defparam exp_user_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_user_out; + OBUFDS exp_user_out_pin (.O(exp_user_out_p),.OB(exp_user_out_n),.I(exp_user_out)); + defparam exp_user_out_pin.IOSTANDARD = "LVDS_25"; + + reg [5:0] clock_ready_d; + always @(posedge clk_fpga) + clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; + wire dcm_rst = ~&clock_ready_d & |clock_ready_d; + + // ADC A is inverted on the schematic to facilitate a clean layout + // We account for that here by inverting it +`ifdef LVDS + wire [13:0] adc_a, adc_a_inv, adc_b; + capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds + (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), + .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p}, + {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), + .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n}, + {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), + .out({adc_a_inv,adc_b})); + assign adc_a = ~adc_a_inv; +`else + reg [13:0] adc_a, adc_b; + always @(posedge dsp_clk) + begin + adc_a <= ~{ADCA_12_p,ADCA_12_n, ADCA_10_p,ADCA_10_n, ADCA_8_p,ADCA_8_n, ADCA_6_p,ADCA_6_n, + ADCA_4_p,ADCA_4_n, ADCA_2_p,ADCA_2_n, ADCA_0_p,ADCA_0_n }; + adc_b <= {ADCB_12_p,ADCB_12_n, ADCB_10_p,ADCB_10_n, ADCB_8_p,ADCB_8_n, ADCB_6_p,ADCB_6_n, + ADCB_4_p,ADCB_4_n, ADCB_2_p,ADCB_2_n, ADCB_0_p,ADCB_0_n }; + end +`endif // !`ifdef LVDS + + // Handle Clocks + DCM DCM_INST (.CLKFB(dsp_clk), + .CLKIN(clk_fpga), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(), + .CLK180(), + .CLK270(clk270_100), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 10.000; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + // Create clock for external SRAM thats -90degree phase to DSPCLK (i.e) 2nS earlier at 100MHz. + BUFG clk270_100_buf_i1 (.I(clk270_100), + .O(clk270_100_buf)); + OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK), + .C0(clk270_100_buf), + .C1(~clk270_100_buf), + .CE(1'b1), + .D0(1'b1), + .D1(1'b0), + .R(1'b0), + .S(1'b0)); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // LEDs are active low outputs + wire [5:0] leds_int; + assign {ETH_LED,leds} = {6'b011111 ^ leds_int}; // drive low to turn on leds + + // SPI + wire miso, mosi, sclk; + + assign {SCLK_CLK,MOSI_CLK} = ~SEN_CLK ? {sclk,mosi} : 2'B0; + assign {SCLK_DAC,MOSI_DAC} = ~SEN_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_ADC,MOSI_ADC} = ~SEN_ADC ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_DAC,MOSI_TX_DAC} = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_ADC,MOSI_TX_ADC} = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_DAC,MOSI_RX_DAC} = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_ADC,MOSI_RX_ADC} = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0; + + assign miso = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) | + (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) | + (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC); + + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; + wire [7:0] GMII_TXD_unreg; + wire GMII_GTX_CLK_int; + + always @(posedge GMII_GTX_CLK_int) + begin + GMII_TX_EN <= GMII_TX_EN_unreg; + GMII_TX_ER <= GMII_TX_ER_unreg; + GMII_TXD <= GMII_TXD_unreg; + end + + OFDDRRSE OFDDRRSE_gmii_inst + (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) + .C0(GMII_GTX_CLK_int), // 0 degree clock input + .C1(~GMII_GTX_CLK_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + + wire ser_tklsb_unreg, ser_tkmsb_unreg; + wire [15:0] ser_t_unreg; + wire ser_tx_clk_int; + + always @(posedge ser_tx_clk_int) + begin + ser_tklsb <= ser_tklsb_unreg; + ser_tkmsb <= ser_tkmsb_unreg; + ser_t <= ser_t_unreg; + end + + assign ser_tx_clk = clk_fpga; + + reg [15:0] ser_r_int; + reg ser_rklsb_int, ser_rkmsb_int; + + always @(posedge ser_rx_clk) + begin + ser_r_int <= ser_r; + ser_rklsb_int <= ser_rklsb; + ser_rkmsb_int <= ser_rkmsb; + end + + /* + OFDDRRSE OFDDRRSE_serdes_inst + (.Q(ser_tx_clk), // Data output (connect directly to top-level port) + .C0(ser_tx_clk_int), // 0 degree clock input + .C1(~ser_tx_clk_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + */ + + + // + // Instantiate IO for Bidirectional bus to SRAM + // + wire [35:0] RAM_D_pi; + wire [35:0] RAM_D_po; + wire RAM_D_poe; + + genvar i; + + generate + for (i=0;i<36;i=i+1) + begin : gen_RAM_D_IO + + IOBUF #( + .DRIVE(12), + .IOSTANDARD("LVCMOS25"), + .SLEW("FAST") + ) + RAM_D_i ( + .O(RAM_D_pi[i]), + .I(RAM_D_po[i]), + .IO(RAM_D[i]), + .T(RAM_D_poe) + ); + end // block: gen_RAM_D_IO + endgenerate + + + + wire [15:0] dac_a_int, dac_b_int; + // DAC A and B are swapped in schematic to facilitate clean layout + // DAC A is also inverted in schematic to facilitate clean layout + always @(negedge dsp_clk) DACA <= ~dac_b_int; + always @(negedge dsp_clk) DACB <= dac_a_int; + + wire pps; + assign pps = PPS_IN ^ PPS2_IN; + + u2plus_core u2p_c(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (CLK_TO_MAC_int2), + .pps_in (pps), + .leds (leds_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_time_in (exp_time_in), + .exp_time_out (exp_time_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .adc_a (adc_a[13:0]), + .adc_ovf_a (1'b0), + .adc_on_a (), + .adc_oe_a (), + .adc_b (adc_b[13:0]), + .adc_ovf_b (1'b0), + .adc_on_b (), + .adc_oe_b (), + .dac_a (dac_a_int[15:0]), + .dac_b (dac_b_int[15:0]), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk), + .mosi (mosi), + .miso (miso), + .sen_clk (SEN_CLK), + .sen_dac (SEN_DAC), + .sen_adc (SEN_ADC), + .sen_tx_db (SEN_TX_DB), + .sen_tx_adc (SEN_TX_ADC), + .sen_tx_dac (SEN_TX_DAC), + .sen_rx_db (SEN_RX_DB), + .sen_rx_adc (SEN_RX_ADC), + .sen_rx_dac (SEN_RX_DAC), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D_po (RAM_D_po), + .RAM_D_pi (RAM_D_pi), + .RAM_D_poe (RAM_D_poe), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (TXD[3:1]), + .uart_rx_i ({1'b1,RXD[3:1]}), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2), + .button (FPGA_RESET), + .spiflash_cs (flash_cs), + .spiflash_clk (flash_clk), + .spiflash_miso (flash_miso), + .spiflash_mosi (flash_mosi) + ); + + // Drive low so that RAM does not sleep. + assign RAM_ZZ = 0; + // Byte Writes are qualified by the global write enable + // Always do 36bit operations to extram. + assign RAM_BWn = 4'b0000; + +endmodule // u2plus diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v new file mode 100644 index 000000000..ee5d7efcd --- /dev/null +++ b/usrp2/top/N2x0/u2plus_core.v @@ -0,0 +1,708 @@ +// //////////////////////////////////////////////////////////////////////////////// +// Module Name: u2_core +// //////////////////////////////////////////////////////////////////////////////// + +module u2plus_core + (// Clocks + input dsp_clk, + input wb_clk, + output clock_ready, + input clk_to_mac, + input pps_in, + + // Misc, debug + output [7:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + + // Expansion + input exp_time_in, + output exp_time_out, + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output [7:0] GMII_TXD, + output GMII_TX_EN, + output GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output [15:0] ser_t, + output ser_tklsb, + output ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + input por, + output config_success, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_on_a, + output adc_oe_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_on_b, + output adc_oe_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + + // I2C + input scl_pad_i, + output scl_pad_o, + output scl_pad_oen_o, + input sda_pad_i, + output sda_pad_o, + output sda_pad_oen_o, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Generic SPI + output sclk, + output mosi, + input miso, + output sen_clk, + output sen_dac, + output sen_adc, + output sen_tx_db, + output sen_tx_adc, + output sen_tx_dac, + output sen_rx_db, + output sen_rx_adc, + output sen_rx_dac, + + // GPIO to DBoards + inout [15:0] io_tx, + inout [15:0] io_rx, + + // External RAM + input [35:0] RAM_D_pi, + output [35:0] RAM_D_po, + output RAM_D_poe, + output [20:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // Debug stuff + output [3:0] uart_tx_o, + input [3:0] uart_rx_i, + output [3:0] uart_baud_o, + input sim_mode, + input [3:0] clock_divider, + input button, + + output spiflash_cs, output spiflash_clk, input spiflash_miso, output spiflash_mosi + ); + + localparam SR_MISC = 0; // 7 regs + localparam SR_SIMTIMER = 8; // 2 + localparam SR_TIME64 = 10; // 6 + localparam SR_BUF_POOL = 16; // 4 + + localparam SR_RX_FRONT = 24; // 5 + localparam SR_RX_CTRL0 = 32; // 9 + localparam SR_RX_DSP0 = 48; // 7 + localparam SR_RX_CTRL1 = 80; // 9 + localparam SR_RX_DSP1 = 96; // 7 + + localparam SR_TX_FRONT = 128; // ? + localparam SR_TX_CTRL = 144; // 6 + localparam SR_TX_DSP = 160; // 5 + + localparam SR_UDP_SM = 192; // 64 + + // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 + // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs + // localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo + localparam DSP_RX_FIFOSIZE = 10; + localparam ETH_TX_FIFOSIZE = 9; + localparam ETH_RX_FIFOSIZE = 11; + localparam SERDES_TX_FIFOSIZE = 9; + localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? + + wire [7:0] set_addr, set_addr_dsp; + wire [31:0] set_data, set_data_dsp; + wire set_stb, set_stb_dsp; + + reg wb_rst; + wire dsp_rst = wb_rst; + + wire [31:0] status; + wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; + wire proc_int, overrun0, overrun1, underrun; + wire [3:0] uart_tx_int, uart_rx_int; + + wire [31:0] debug_gpio_0, debug_gpio_1; + wire [31:0] atr_lines; + + wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2; + + wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; + wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; + wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; + + wire serdes_link_up; + wire epoch; + wire [31:0] irq; + wire [63:0] vita_time, vita_time_pps; + + wire run_rx0, run_rx1, run_tx; + reg run_rx0_d1, run_rx1_d1; + + // /////////////////////////////////////////////////////////////////////////////////////////////// + // Wishbone Single Master INTERCON + localparam dw = 32; // Data bus width + localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space + localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. + + wire [dw-1:0] m0_dat_o, m0_dat_i; + wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, + s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, + s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, + sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o, sf_dat_i, sf_dat_o; + wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; + wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; + wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; + wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; + wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; + wire m0_err, m0_rty; + wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we; + + wb_1master #(.decode_w(8), + .s0_addr(8'b0000_0000),.s0_mask(8'b1100_0000), // Main RAM (0-16K) + .s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000), // Packet Router (16-20K) + .s2_addr(8'b0101_0000),.s2_mask(8'b1111_1100), // SPI + .s3_addr(8'b0101_0100),.s3_mask(8'b1111_1100), // I2C + .s4_addr(8'b0101_1000),.s4_mask(8'b1111_1100), // GPIO + .s5_addr(8'b0101_1100),.s5_mask(8'b1111_1100), // Readback + .s6_addr(8'b0110_0000),.s6_mask(8'b1111_0000), // Ethernet MAC + .s7_addr(8'b0111_0000),.s7_mask(8'b1111_0000), // 20K-24K, Settings Bus (only uses 1K) + .s8_addr(8'b1000_0000),.s8_mask(8'b1111_1100), // PIC + .s9_addr(8'b1000_0100),.s9_mask(8'b1111_1100), // Unused + .sa_addr(8'b1000_1000),.sa_mask(8'b1111_1100), // UART + .sb_addr(8'b1000_1100),.sb_mask(8'b1111_1100), // ATR + .sc_addr(8'b1001_0000),.sc_mask(8'b1111_0000), // Unused + .sd_addr(8'b1010_0000),.sd_mask(8'b1111_0000), // ICAP + .se_addr(8'b1011_0000),.se_mask(8'b1111_0000), // SPI Flash + .sf_addr(8'b1100_0000),.sf_mask(8'b1100_0000), // 48K-64K, Boot RAM + .dw(dw),.aw(aw),.sw(sw)) wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), + .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0)); + + // //////////////////////////////////////////////////////////////////////////////////////// + // Reset Controller + + reg cpu_bldr_ctrl_state; + localparam CPU_BLDR_CTRL_WAIT = 0; + localparam CPU_BLDR_CTRL_DONE = 1; + + wire bldr_done; + wire por_rst; + wire [aw-1:0] cpu_adr; + + // Swap boot ram and main ram when in bootloader mode + assign m0_adr = (^cpu_adr[15:14] | (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_DONE)) ? cpu_adr : + cpu_adr ^ 16'hC000; + + system_control sysctrl + (.wb_clk_i(wb_clk), .wb_rst_o(por_rst), .ram_loader_done_i(1'b1) ); + + always @(posedge wb_clk) + if(por_rst) begin + cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_WAIT; + wb_rst <= 1'b1; + end + else begin + case(cpu_bldr_ctrl_state) + + CPU_BLDR_CTRL_WAIT: begin + wb_rst <= 1'b0; + if (bldr_done == 1'b1) begin //set by the bootloader + cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_DONE; + wb_rst <= 1'b1; + end + end + + CPU_BLDR_CTRL_DONE: begin //stay here forever + wb_rst <= 1'b0; + end + + endcase //cpu_bldr_ctrl_state + end + + // ///////////////////////////////////////////////////////////////////////// + // Processor + + assign bus_error = m0_err | m0_rty; + + wire [63:0] zpu_status; + zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) + zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(~wb_rst), + // Data Wishbone bus to system bus fabric + .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(cpu_adr), + .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), + // Interrupts and exceptions + .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); + + // ///////////////////////////////////////////////////////////////////////// + // Dual Ported Boot RAM -- D-Port is Slave #0 on main Wishbone + // Dual Ported Main RAM -- D-Port is Slave #F on main Wishbone + // I-port connects directly to processor + + bootram bootram(.clk(wb_clk), .reset(wb_rst), + .if_adr(14'b0), .if_data(), + .dwb_adr_i(sf_adr[13:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i), + .dwb_we_i(sf_we), .dwb_ack_o(sf_ack), .dwb_stb_i(sf_stb), .dwb_sel_i(sf_sel)); + +////blinkenlights v0.1 +//defparam bootram.RAM0.INIT_00=256'hbc32fff0_aa43502b_b00000fe_30630001_80000000_10600000_a48500ff_10a00000; +//defparam bootram.RAM0.INIT_01=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_308000ff_be23000c_a4640001; + +`include "bootloader.rmi" + + ram_harvard2 #(.AWIDTH(14),.RAM_SIZE(16384)) + sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .if_adr(14'b0), .if_data(), + .dwb_adr_i(s0_adr[13:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool, slave #1 + wire rd0_ready_i, rd0_ready_o; + wire rd1_ready_i, rd1_ready_o; + wire rd2_ready_i, rd2_ready_o; + wire rd3_ready_i, rd3_ready_o; + wire [35:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + + wire wr0_ready_i, wr0_ready_o; + wire wr1_ready_i, wr1_ready_o; + wire wr2_ready_i, wr2_ready_o; + wire wr3_ready_i, wr3_ready_o; + wire [35:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + + wire [35:0] tx_err_data; + wire tx_err_src_rdy, tx_err_dst_rdy; + + wire [31:0] router_debug; + + packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), + + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0), + + .status(status), .sys_int_o(buffer_int), .debug(router_debug), + + .ser_inp_data(wr0_dat), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), + .dsp0_inp_data(wr1_dat), .dsp0_inp_valid(wr1_ready_i), .dsp0_inp_ready(wr1_ready_o), + .dsp1_inp_data(wr3_dat), .dsp1_inp_valid(wr3_ready_i), .dsp1_inp_ready(wr3_ready_o), + .eth_inp_data(wr2_dat), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), + .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy), + + .ser_out_data(rd0_dat), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), + .dsp_out_data(rd1_dat), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), + .eth_out_data(rd2_dat), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) + ); + + // ///////////////////////////////////////////////////////////////////////// + // SPI -- Slave #2 + spi_top shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), + .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), + .ss_pad_o({sen_adc, sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // I2C -- Slave #3 + i2c_master_top #(.ARST_LVL(1)) + i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_i[31:8] = 24'd0; + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio({io_tx,io_rx}) ); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool Status -- Slave #5 + + //compatibility number -> increment when the fpga has been sufficiently altered + localparam compat_num = 32'd6; + + wb_readback_mux buff_pool_status + (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), + .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), + + .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), + .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), + .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq), + .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]) + ); + + // ///////////////////////////////////////////////////////////////////////// + // Ethernet MAC Slave #6 + + simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE), + .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper + (.clk125(clk_to_mac), .reset(wb_rst), + .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), + .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), + .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), + .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), + .sys_clk(dsp_clk), + .rx_f36_data(wr2_dat), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), + .tx_f36_data(rd2_dat), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), + .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), + .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), + .mdio(MDIO), .mdc(MDC), + .debug(debug_mac)); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #7 + settings_bus settings_bus + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), + .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), + .strobe(set_stb),.addr(set_addr),.data(set_data)); + + assign s7_dat_i = 32'd0; + + settings_bus_crossclock settings_bus_crossclock + (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), + .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); + + // Output control lines + wire [7:0] clock_outs, serdes_outs, adc_outs; + assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; + assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; + assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; + + wire phy_reset; + assign PHY_RESETn = ~phy_reset; + + setting_reg #(.my_addr(SR_MISC+0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), + .in(set_data),.out(clock_outs),.changed()); + setting_reg #(.my_addr(SR_MISC+1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(serdes_outs),.changed()); + setting_reg #(.my_addr(SR_MISC+2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(adc_outs),.changed()); + setting_reg #(.my_addr(SR_MISC+4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phy_reset),.changed()); + setting_reg #(.my_addr(SR_MISC+5),.width(1)) sr_bld (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(bldr_done),.changed()); + + // ///////////////////////////////////////////////////////////////////////// + // LEDS + // register 8 determines whether leds are controlled by SW or not + // 1 = controlled by HW, 0 = by SW + // In Rev3 there are only 6 leds, and the highest one is on the ETH connector + + wire [7:0] led_src, led_sw; + wire [7:0] led_hw = {run_tx, (run_rx0_d1 | run_rx1_d1), clk_status, serdes_link_up, 1'b0}; + + setting_reg #(.my_addr(SR_MISC+3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_sw),.changed()); + + setting_reg #(.my_addr(SR_MISC+6),.width(8), .at_reset(8'b0001_1110)) + sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed()); + + assign leds = (led_src & led_hw) | (~led_src & led_sw); + + // ///////////////////////////////////////////////////////////////////////// + // Interrupt Controller, Slave #8 + + // Pass interrupts on dsp_clk to wb_clk. These need edge triggering in the pic + wire underrun_wb, overrun_wb, pps_wb; + + oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb)); + oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun0 | overrun1), .clk_out(wb_clk), .out(overrun_wb)); + oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb)); + + assign irq= {{8'b0}, + {uart_tx_int[3:0], uart_rx_int[3:0]}, + {2'b0, button, periodic_int, clk_status, serdes_link_up, 2'b00}, + {pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; + + pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), + .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), + .irq(irq) ); + + // ///////////////////////////////////////////////////////////////////////// + // Master Timer, Slave #9 + + // No longer used, replaced with simple_timer below + assign s9_ack = 0; + + // ///////////////////////////////////////////////////////////////////////// + // Simple Timer interrupts + + simple_timer #(.BASE(SR_SIMTIMER)) simple_timer + (.clk(wb_clk), .reset(wb_rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .onetime_int(onetime_int), .periodic_int(periodic_int)); + + // ///////////////////////////////////////////////////////////////////////// + // UART, Slave #10 + + quad_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), + .adr_i(sa_adr[6:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), + .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), + .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller, Slave #11 + + atr_controller atr_controller + (.clk_i(wb_clk),.rst_i(wb_rst), + .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), + .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), + .run_rx(run_rx0_d1 | run_rx1_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); + + // ////////////////////////////////////////////////////////////////////////// + // Time Sync, Slave #12 + + // No longer used, see time_64bit. Still need to handle mimo time, though + assign sc_ack = 0; + + // ///////////////////////////////////////////////////////////////////////// + // ICAP for reprogramming the FPGA, Slave #13 (D) + + s3a_icap_wb s3a_icap_wb + (.clk(wb_clk), .reset(wb_rst), .cyc_i(sd_cyc), .stb_i(sd_stb), + .we_i(sd_we), .ack_o(sd_ack), .dat_i(sd_dat_o), .dat_o(sd_dat_i)); + + // ///////////////////////////////////////////////////////////////////////// + // SPI for Flash -- Slave #14 (E) + spi_top flash_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(se_adr[4:0]),.wb_dat_i(se_dat_o), + .wb_dat_o(se_dat_i),.wb_sel_i(se_sel),.wb_we_i(se_we),.wb_stb_i(se_stb), + .wb_cyc_i(se_cyc),.wb_ack_o(se_ack),.wb_err_o(se_err),.wb_int_o(spiflash_int), + .ss_pad_o(spiflash_cs), + .sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX 0 + wire [31:0] sample_rx0; + wire clear_rx0, strobe_rx0; + + always @(posedge dsp_clk) + run_rx0_d1 <= run_rx0; + + dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0 + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0), + .debug() ); + + setting_reg #(.my_addr(SR_RX_CTRL0+3)) sr_clear_rx0 + (.clk(dsp_clk),.rst(dsp_rst), + .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), + .out(),.changed(clear_rx0)); + + vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0 + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), .overrun(overrun0), + .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), + .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o), + .debug() ); + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX 1 + wire [31:0] sample_rx1; + wire clear_rx1, strobe_rx1; + + always @(posedge dsp_clk) + run_rx1_d1 <= run_rx1; + + dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1), + .debug() ); + + setting_reg #(.my_addr(SR_RX_CTRL1+3)) sr_clear_rx1 + (.clk(dsp_clk),.rst(dsp_rst), + .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), + .out(),.changed(clear_rx1)); + + vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1 + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), .overrun(overrun1), + .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), + .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o), + .debug() ); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [35:0] tx_data; + wire tx_src_rdy, tx_dst_rdy; + wire [31:0] debug_vt; + wire clear_tx; + + setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_tx)); + + assign RAM_A[20:18] = 3'b0; + + ext_fifo #(.EXT_WIDTH(36),.INT_WIDTH(36),.RAM_DEPTH(18),.FIFO_DEPTH(18)) + ext_fifo_i1 + (.int_clk(dsp_clk), + .ext_clk(dsp_clk), + .rst(dsp_rst | clear_tx), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A[17:0]), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .datain(rd1_dat), + .src_rdy_i(rd1_ready_o), + .dst_rdy_o(rd1_ready_i), + .dataout(tx_data), + .src_rdy_o(tx_src_rdy), + .dst_rdy_i(tx_dst_rdy), + .debug(debug_extfifo), + .debug2(debug_extfifo2) ); + + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), + .DSP_NUMBER(0)) + vita_tx_chain + (.clk(dsp_clk), .reset(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), + .dac_a(dac_a),.dac_b(dac_b), + .underrun(underrun), .run(run_tx), + .debug(debug_vt)); + + // /////////////////////////////////////////////////////////////////////////////////// + // SERDES + + serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes + (.clk(dsp_clk),.rst(dsp_rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .rd_dat_i(rd0_dat[31:0]),.rd_flags_i(rd0_dat[35:32]),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .wr_dat_o(wr0_dat[31:0]),.wr_flags_o(wr0_dat[35:32]),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), + .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), + .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), + .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing + + wire [31:0] debug_sync; + + time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit + (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), + .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), + .debug(debug_sync)); + + // ///////////////////////////////////////////////////////////////////////////////////////// + // Debug Pins + + assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; + assign debug = 32'd0; + assign debug_gpio_0 = 32'd0; + assign debug_gpio_1 = 32'd0; + +endmodule // u2_core diff --git a/usrp2/top/USRP2/.gitignore b/usrp2/top/USRP2/.gitignore new file mode 100644 index 000000000..f50a2b7e5 --- /dev/null +++ b/usrp2/top/USRP2/.gitignore @@ -0,0 +1,57 @@ +/*.ptwx +/*.xrpt +/*.zip +/*_xdb +/templates +/netgen +/_ngo +/_xmsgs +/_pace.ucf +/*.cmd +/*.ibs +/*.lfp +/*.mfp +/*.bit +/*.bin +/*.stx +/*.par +/*.unroutes +/*.ntrc_log +/*.ngr +/*.mrp +/*.html +/*.lso +/*.twr +/*.bld +/*.ncd +/*.txt +/*.cmd_log +/*.drc +/*.map +/*.twr +/*.xml +/*.syr +/*.ngm +/*.xst +/*.csv +/*.html +/*.lock +/*.ncd +/*.twx +/*.ise_ISE_Backup +/*.xml +/*.ut +/*.xpi +/*.ngd +/*.ncd +/*.pad +/*.bgn +/*.ngc +/*.pcf +/*.ngd +/xst +/*.log +/*.rpt +/*.cel +/*.restore +/build* diff --git a/usrp2/top/USRP2/Makefile b/usrp2/top/USRP2/Makefile new file mode 100644 index 000000000..e9b43491a --- /dev/null +++ b/usrp2/top/USRP2/Makefile @@ -0,0 +1,98 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u2_rev3 +BUILD_DIR = $(abspath build) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extramfifo/Makefile.srcs + + +################################################## +# Project Properties +################################################## +PROJECT_PROPERTIES = \ +family Spartan3 \ +device xc3s2000 \ +package fg456 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u2_core.v \ +u2_rev3.v \ +u2_rev3.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v new file mode 100644 index 000000000..0e6120ec6 --- /dev/null +++ b/usrp2/top/USRP2/u2_core.v @@ -0,0 +1,707 @@ +// //////////////////////////////////////////////////////////////////////////////// +// Module Name: u2_core +// //////////////////////////////////////////////////////////////////////////////// + +module u2_core + (// Clocks + input dsp_clk, + input wb_clk, + output clock_ready, + input clk_to_mac, + input pps_in, + + // Misc, debug + output [7:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + + // Expansion + input exp_time_in, + output exp_time_out, + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output [7:0] GMII_TXD, + output GMII_TX_EN, + output GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output [15:0] ser_t, + output ser_tklsb, + output ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // CPLD interface + output cpld_start, + output cpld_mode, + output cpld_done, + input cpld_din, + input cpld_clk, + input cpld_detached, + output cpld_misc, + input cpld_init_b, + input por, + output config_success, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_on_a, + output adc_oe_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_on_b, + output adc_oe_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + + // I2C + input scl_pad_i, + output scl_pad_o, + output scl_pad_oen_o, + input sda_pad_i, + output sda_pad_o, + output sda_pad_oen_o, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Generic SPI + output sclk, + output mosi, + input miso, + output sen_clk, + output sen_dac, + output sen_tx_db, + output sen_tx_adc, + output sen_tx_dac, + output sen_rx_db, + output sen_rx_adc, + output sen_rx_dac, + + // GPIO to DBoards + inout [15:0] io_tx, + inout [15:0] io_rx, + + // External RAM + input [17:0] RAM_D_pi, + output [17:0] RAM_D_po, + output RAM_D_poe, + output [18:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // Debug stuff + output uart_tx_o, + input uart_rx_i, + output uart_baud_o, + input sim_mode, + input [3:0] clock_divider + ); + + localparam SR_MISC = 0; // 7 regs + localparam SR_SIMTIMER = 8; // 2 + localparam SR_TIME64 = 10; // 6 + localparam SR_BUF_POOL = 16; // 4 + + localparam SR_RX_FRONT = 24; // 5 + localparam SR_RX_CTRL0 = 32; // 9 + localparam SR_RX_DSP0 = 48; // 7 + localparam SR_RX_CTRL1 = 80; // 9 + localparam SR_RX_DSP1 = 96; // 7 + + localparam SR_TX_FRONT = 128; // ? + localparam SR_TX_CTRL = 144; // 6 + localparam SR_TX_DSP = 160; // 5 + + localparam SR_UDP_SM = 192; // 64 + + // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 + // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs + // localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo + localparam DSP_RX_FIFOSIZE = 10; + localparam ETH_TX_FIFOSIZE = 9; + localparam ETH_RX_FIFOSIZE = 11; + localparam SERDES_TX_FIFOSIZE = 9; + localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? + + wire [7:0] set_addr, set_addr_dsp; + wire [31:0] set_data, set_data_dsp; + wire set_stb, set_stb_dsp; + + wire ram_loader_done, ram_loader_rst; + wire wb_rst; + wire dsp_rst = wb_rst; + + wire [31:0] status; + wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; + wire proc_int, overrun0, overrun1, underrun; + wire uart_tx_int, uart_rx_int; + + wire [31:0] debug_gpio_0, debug_gpio_1; + wire [31:0] atr_lines; + + wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2; + + wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; + wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; + wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; + + wire serdes_link_up; + wire epoch; + wire [31:0] irq; + wire [63:0] vita_time, vita_time_pps; + + wire run_rx0, run_rx1, run_tx; + reg run_rx0_d1, run_rx1_d1; + + // /////////////////////////////////////////////////////////////////////////////////////////////// + // Wishbone Single Master INTERCON + localparam dw = 32; // Data bus width + localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space + localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. + + wire [dw-1:0] m0_dat_o, m0_dat_i; + wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, + s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, + s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, + sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o, sf_dat_i, sf_dat_o; + wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; + wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; + wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; + wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; + wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; + wire m0_err, m0_rty; + wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we; + + wb_1master #(.decode_w(8), + .s0_addr(8'b0000_0000),.s0_mask(8'b1100_0000), // Main RAM (0-16K) + .s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000), // Packet Router (16-20K) + .s2_addr(8'b0101_0000),.s2_mask(8'b1111_1100), // SPI + .s3_addr(8'b0101_0100),.s3_mask(8'b1111_1100), // I2C + .s4_addr(8'b0101_1000),.s4_mask(8'b1111_1100), // GPIO + .s5_addr(8'b0101_1100),.s5_mask(8'b1111_1100), // Readback + .s6_addr(8'b0110_0000),.s6_mask(8'b1111_0000), // Ethernet MAC + .s7_addr(8'b0111_0000),.s7_mask(8'b1111_0000), // 20K-24K, Settings Bus (only uses 1K) + .s8_addr(8'b1000_0000),.s8_mask(8'b1111_1100), // PIC + .s9_addr(8'b1000_0100),.s9_mask(8'b1111_1100), // Unused + .sa_addr(8'b1000_1000),.sa_mask(8'b1111_1100), // UART + .sb_addr(8'b1000_1100),.sb_mask(8'b1111_1100), // ATR + .sc_addr(8'b1001_0000),.sc_mask(8'b1111_0000), // Unused + .sd_addr(8'b1010_0000),.sd_mask(8'b1111_0000), // SD Card access + .se_addr(8'b1011_0000),.se_mask(8'b1111_0000), // Unused + .sf_addr(8'b1100_0000),.sf_mask(8'b1100_0000), // Unused + .dw(dw),.aw(aw),.sw(sw)) wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), + .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0)); + + ////////////////////////////////////////////////////////////////////////////////////////// + // Reset Controller + system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), + .ram_loader_rst_o(ram_loader_rst), + .wb_rst_o(wb_rst), + .ram_loader_done_i(ram_loader_done)); + + assign config_success = ram_loader_done; + reg takeover = 0; + + wire cpld_start_int, cpld_mode_int, cpld_done_int; + + always @(posedge wb_clk) + if(ram_loader_done) + takeover = 1; + assign cpld_misc = ~takeover; + + wire sd_clk, sd_csn, sd_mosi, sd_miso; + + assign sd_miso = cpld_din; + assign cpld_start = takeover ? sd_clk : cpld_start_int; + assign cpld_mode = takeover ? sd_csn : cpld_mode_int; + assign cpld_done = takeover ? sd_mosi : cpld_done_int; + + // /////////////////////////////////////////////////////////////////// + // RAM Loader + + wire [31:0] ram_loader_dat; + wire [15:0] ram_loader_adr; + wire [3:0] ram_loader_sel; + wire ram_loader_stb, ram_loader_we; + ram_loader #(.AWIDTH(aw),.RAM_SIZE(16384)) + ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst), + .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr), + .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel), + .wb_we(ram_loader_we), + .ram_loader_done(ram_loader_done), + // CPLD Interface + .cpld_clk(cpld_clk), + .cpld_din(cpld_din), + .cpld_start(cpld_start_int), + .cpld_mode(cpld_mode_int), + .cpld_done(cpld_done_int), + .cpld_detached(cpld_detached)); + + // ///////////////////////////////////////////////////////////////////////// + // Processor + + assign bus_error = m0_err | m0_rty; + + wire [63:0] zpu_status; + zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) + zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(ram_loader_done), + // Data Wishbone bus to system bus fabric + .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr), + .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), + // Interrupts and exceptions + .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); + + // ///////////////////////////////////////////////////////////////////////// + // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone + // I-port connects directly to processor and ram loader + + ram_harvard #(.AWIDTH(14),.RAM_SIZE(16384),.ICWIDTH(7),.DCWIDTH(6)) + sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + + .ram_loader_adr_i(ram_loader_adr[13:0]), .ram_loader_dat_i(ram_loader_dat), + .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), + .ram_loader_we_i(ram_loader_we), + .ram_loader_done_i(ram_loader_done), + + .if_adr(16'b0), .if_data(), + + .dwb_adr_i(s0_adr[13:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool, slave #1 + wire rd0_ready_i, rd0_ready_o; + wire rd1_ready_i, rd1_ready_o; + wire rd2_ready_i, rd2_ready_o; + wire rd3_ready_i, rd3_ready_o; + wire [35:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + + wire wr0_ready_i, wr0_ready_o; + wire wr1_ready_i, wr1_ready_o; + wire wr2_ready_i, wr2_ready_o; + wire wr3_ready_i, wr3_ready_o; + wire [35:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + + wire [35:0] tx_err_data; + wire tx_err_src_rdy, tx_err_dst_rdy; + + wire [31:0] router_debug; + + packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), + + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0), + + .status(status), .sys_int_o(buffer_int), .debug(router_debug), + + .ser_inp_data(wr0_dat), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), + .dsp0_inp_data(wr1_dat), .dsp0_inp_valid(wr1_ready_i), .dsp0_inp_ready(wr1_ready_o), + .dsp1_inp_data(wr3_dat), .dsp1_inp_valid(wr3_ready_i), .dsp1_inp_ready(wr3_ready_o), + .eth_inp_data(wr2_dat), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), + .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy), + + .ser_out_data(rd0_dat), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), + .dsp_out_data(rd1_dat), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), + .eth_out_data(rd2_dat), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) + ); + + // ///////////////////////////////////////////////////////////////////////// + // SPI -- Slave #2 + spi_top shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), + .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), + .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // I2C -- Slave #3 + i2c_master_top #(.ARST_LVL(1)) + i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_i[31:8] = 24'd0; + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio({io_tx,io_rx}) ); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool Status -- Slave #5 + + //compatibility number -> increment when the fpga has been sufficiently altered + localparam compat_num = 32'd6; + + wb_readback_mux buff_pool_status + (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), + .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), + + .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), + .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), + .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq), + .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]) + ); + + // ///////////////////////////////////////////////////////////////////////// + // Ethernet MAC Slave #6 + + simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE), + .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper + (.clk125(clk_to_mac), .reset(wb_rst), + .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), + .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), + .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), + .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), + .sys_clk(dsp_clk), + .rx_f36_data(wr2_dat), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), + .tx_f36_data(rd2_dat), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), + .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), + .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), + .mdio(MDIO), .mdc(MDC), + .debug(debug_mac)); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #7 + settings_bus settings_bus + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), + .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), + .strobe(set_stb),.addr(set_addr),.data(set_data)); + + assign s7_dat_i = 32'd0; + + settings_bus_crossclock settings_bus_crossclock + (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), + .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); + + // Output control lines + wire [7:0] clock_outs, serdes_outs, adc_outs; + assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; + assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; + assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; + + wire phy_reset; + assign PHY_RESETn = ~phy_reset; + + setting_reg #(.my_addr(SR_MISC+0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), + .in(set_data),.out(clock_outs),.changed()); + setting_reg #(.my_addr(SR_MISC+1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(serdes_outs),.changed()); + setting_reg #(.my_addr(SR_MISC+2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(adc_outs),.changed()); + setting_reg #(.my_addr(SR_MISC+4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phy_reset),.changed()); + + // ///////////////////////////////////////////////////////////////////////// + // LEDS + // register 8 determines whether leds are controlled by SW or not + // 1 = controlled by HW, 0 = by SW + // In Rev3 there are only 6 leds, and the highest one is on the ETH connector + + wire [7:0] led_src, led_sw; + wire [7:0] led_hw = {run_tx, (run_rx0_d1 | run_rx1_d1), clk_status, serdes_link_up, 1'b0}; + + setting_reg #(.my_addr(SR_MISC+3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_sw),.changed()); + + setting_reg #(.my_addr(SR_MISC+6),.width(8), .at_reset(8'b0001_1110)) + sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed()); + + assign leds = (led_src & led_hw) | (~led_src & led_sw); + + // ///////////////////////////////////////////////////////////////////////// + // Interrupt Controller, Slave #8 + + // Pass interrupts on dsp_clk to wb_clk. These need edge triggering in the pic + wire underrun_wb, overrun_wb, pps_wb; + + oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb)); + oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun0 | overrun1), .clk_out(wb_clk), .out(overrun_wb)); + oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb)); + + assign irq= {{8'b0}, + {8'b0}, + {3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, + {pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; + + pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), + .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), + .irq(irq) ); + + // ///////////////////////////////////////////////////////////////////////// + // Master Timer, Slave #9 + + // No longer used, replaced with simple_timer below + assign s9_ack = 0; + + // ///////////////////////////////////////////////////////////////////////// + // Simple Timer interrupts + + simple_timer #(.BASE(SR_SIMTIMER)) simple_timer + (.clk(wb_clk), .reset(wb_rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .onetime_int(onetime_int), .periodic_int(periodic_int)); + + // ///////////////////////////////////////////////////////////////////////// + // UART, Slave #10 + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), + .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), + .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), + .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller, Slave #11 + + atr_controller atr_controller + (.clk_i(wb_clk),.rst_i(wb_rst), + .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), + .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), + .run_rx(run_rx0_d1 | run_rx1_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); + + // ////////////////////////////////////////////////////////////////////////// + // Time Sync, Slave #12 + + // No longer used, see time_64bit. Still need to handle mimo time, though + assign sc_ack = 0; + + // ///////////////////////////////////////////////////////////////////////// + // SD Card Reader / Writer, Slave #13 + + sd_spi_wb sd_spi_wb + (.clk(wb_clk),.rst(wb_rst), + .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), + .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we), + .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o[7:0]),.wb_dat_o(sd_dat_i[7:0]), + .wb_ack_o(sd_ack) ); + + assign sd_dat_i[31:8] = 0; + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX 0 + wire [31:0] sample_rx0; + wire clear_rx0, strobe_rx0; + + always @(posedge dsp_clk) + run_rx0_d1 <= run_rx0; + + dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0 + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0), + .debug() ); + + setting_reg #(.my_addr(SR_RX_CTRL0+3)) sr_clear_rx0 + (.clk(dsp_clk),.rst(dsp_rst), + .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), + .out(),.changed(clear_rx0)); + + vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0 + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), .overrun(overrun0), + .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), + .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o), + .debug() ); + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX 1 + wire [31:0] sample_rx1; + wire clear_rx1, strobe_rx1; + + always @(posedge dsp_clk) + run_rx1_d1 <= run_rx1; + + dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1), + .debug() ); + + setting_reg #(.my_addr(SR_RX_CTRL1+3)) sr_clear_rx1 + (.clk(dsp_clk),.rst(dsp_rst), + .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), + .out(),.changed(clear_rx1)); + + vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1 + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), .overrun(overrun1), + .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), + .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o), + .debug() ); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [35:0] tx_data; + wire tx_src_rdy, tx_dst_rdy; + wire [31:0] debug_vt; + wire clear_tx; + + setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_tx)); + + ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(19)) + ext_fifo_i1 + (.int_clk(dsp_clk), + .ext_clk(clk_to_mac), + .rst(dsp_rst | clear_tx), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .datain(rd1_dat), + .src_rdy_i(rd1_ready_o), + .dst_rdy_o(rd1_ready_i), + .dataout(tx_data), + .src_rdy_o(tx_src_rdy), + .dst_rdy_i(tx_dst_rdy), + .debug(debug_extfifo), + .debug2(debug_extfifo2) ); + + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), + .DSP_NUMBER(0)) + vita_tx_chain + (.clk(dsp_clk), .reset(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), + .dac_a(dac_a),.dac_b(dac_b), + .underrun(underrun), .run(run_tx), + .debug(debug_vt)); + + // /////////////////////////////////////////////////////////////////////////////////// + // SERDES + + serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes + (.clk(dsp_clk),.rst(dsp_rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .rd_dat_i(rd0_dat[31:0]),.rd_flags_i(rd0_dat[35:32]),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .wr_dat_o(wr0_dat[31:0]),.wr_flags_o(wr0_dat[35:32]),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), + .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), + .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), + .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); + + assign RAM_CLK = clk_to_mac; + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing + + wire [31:0] debug_sync; + + time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit + (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), + .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), + .debug(debug_sync)); + + // ///////////////////////////////////////////////////////////////////////////////////////// + // Debug Pins + + assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; + assign debug = 32'd0; + assign debug_gpio_0 = 32'd0; + assign debug_gpio_1 = 32'd0; + +endmodule // u2_core diff --git a/usrp2/top/USRP2/u2_rev3.ucf b/usrp2/top/USRP2/u2_rev3.ucf new file mode 100644 index 000000000..8017f61ff --- /dev/null +++ b/usrp2/top/USRP2/u2_rev3.ucf @@ -0,0 +1,336 @@ +NET "leds[0]" LOC = "E8" ; +NET "leds[1]" LOC = "F7" ; +NET "leds[2]" LOC = "E5" ; +NET "leds[3]" LOC = "B7" ; +NET "leds[4]" LOC = "C11" ; +NET "leds[5]" LOC = "AB19" ; +NET "debug[0]" LOC = "N5" ; +NET "debug[1]" LOC = "N6" ; +NET "debug[2]" LOC = "P1" ; +NET "debug[3]" LOC = "P2" ; +NET "debug[4]" LOC = "P4" ; +NET "debug[5]" LOC = "P5" ; +NET "debug[6]" LOC = "R1" ; +NET "debug[7]" LOC = "R2" ; +NET "debug[8]" LOC = "P6" ; +NET "debug[9]" LOC = "R5" ; +NET "debug[10]" LOC = "R4" ; +NET "debug[11]" LOC = "T3" ; +NET "debug[12]" LOC = "U3" ; +NET "debug[13]" LOC = "M2" ; +NET "debug[14]" LOC = "M3" ; +NET "debug[15]" LOC = "M4" ; +NET "debug[16]" LOC = "M5" ; +NET "debug[17]" LOC = "M6" ; +NET "debug[18]" LOC = "N1" ; +NET "debug[19]" LOC = "N2" ; +NET "debug[20]" LOC = "N3" ; +NET "debug[21]" LOC = "T1" ; +NET "debug[22]" LOC = "T2" ; +NET "debug[23]" LOC = "U2" ; +NET "debug[24]" LOC = "T4" ; +NET "debug[25]" LOC = "U4" ; +NET "debug[26]" LOC = "T5" ; +NET "debug[27]" LOC = "T6" ; +NET "debug[28]" LOC = "U5" ; +NET "debug[29]" LOC = "V5" ; +NET "debug[30]" LOC = "W2" ; +NET "debug[31]" LOC = "W3" ; +NET "debug_clk[0]" LOC = "N4" ; +NET "debug_clk[1]" LOC = "M1" ; +NET "uart_tx_o" LOC = "C7" ; +NET "uart_rx_i" LOC = "A3" ; +NET "exp_time_in_p" LOC = "V3" ; +NET "exp_time_in_n" LOC = "V4" ; +NET "exp_time_out_p" LOC = "V1" ; +NET "exp_time_out_n" LOC = "V2" ; +NET "GMII_COL" LOC = "U16" ; +NET "GMII_CRS" LOC = "U17" ; +NET "GMII_TXD[0]" LOC = "W14" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[1]" LOC = "AA20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[2]" LOC = "AB20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[3]" LOC = "Y18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[4]" LOC = "AA18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[5]" LOC = "AB18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[6]" LOC = "V17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[7]" LOC = "W17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TX_EN" LOC = "Y17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TX_ER" LOC = "V16" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_GTX_CLK" LOC = "AA17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TX_CLK" LOC = "W13" ; +NET "GMII_RXD[0]" LOC = "AA15" ; +NET "GMII_RXD[1]" LOC = "AB15" ; +NET "GMII_RXD[2]" LOC = "U14" ; +NET "GMII_RXD[3]" LOC = "V14" ; +NET "GMII_RXD[4]" LOC = "U13" ; +NET "GMII_RXD[5]" LOC = "V13" ; +NET "GMII_RXD[6]" LOC = "Y13" ; +NET "GMII_RXD[7]" LOC = "AA13" ; +NET "GMII_RX_CLK" LOC = "AA12" ; +NET "GMII_RX_DV" LOC = "AB16" ; +NET "GMII_RX_ER" LOC = "AA16" ; +NET "MDIO" LOC = "Y16" |PULLUP ; +NET "MDC" LOC = "V18" ; +NET "PHY_INTn" LOC = "AB13" ; +NET "PHY_RESETn" LOC = "AA19" ; +NET "PHY_CLK" LOC = "V15" ; +NET "RAM_D[0]" LOC = "N20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[1]" LOC = "N21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[2]" LOC = "N22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[3]" LOC = "M17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[4]" LOC = "M18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[5]" LOC = "M19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[6]" LOC = "M20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[7]" LOC = "M21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[8]" LOC = "M22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[9]" LOC = "Y22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[10]" LOC = "Y21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[11]" LOC = "Y20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[12]" LOC = "Y19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[13]" LOC = "W22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[14]" LOC = "W21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[15]" LOC = "W20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[16]" LOC = "W19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[17]" LOC = "V22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[0]" LOC = "U21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[1]" LOC = "T19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[2]" LOC = "V21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[3]" LOC = "V20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[4]" LOC = "T20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[5]" LOC = "T21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[6]" LOC = "T22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[7]" LOC = "T18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[8]" LOC = "R18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[9]" LOC = "P19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[10]" LOC = "P21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[11]" LOC = "P22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[12]" LOC = "N19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[13]" LOC = "N17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[14]" LOC = "N18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[15]" LOC = "T17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[16]" LOC = "U19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[17]" LOC = "U18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[18]" LOC = "V19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_CE1n" LOC = "U20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_CENn" LOC = "P18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_CLK" LOC = "P17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_WEn" LOC = "R22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_OEn" LOC = "R21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_LDn" LOC = "R19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_enable" LOC = "W11" ; +NET "ser_prbsen" LOC = "AA3" ; +NET "ser_loopen" LOC = "Y4" ; +NET "ser_rx_en" LOC = "AB9" ; +NET "ser_tx_clk" LOC = "U7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[0]" LOC = "V7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[1]" LOC = "V10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[2]" LOC = "AB4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[3]" LOC = "AA4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[4]" LOC = "Y5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[5]" LOC = "W5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[6]" LOC = "AB5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[7]" LOC = "AA5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[8]" LOC = "W6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[9]" LOC = "V6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[10]" LOC = "AA6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[11]" LOC = "Y6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[12]" LOC = "W8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[13]" LOC = "V8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[14]" LOC = "AB8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[15]" LOC = "AA8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_tklsb" LOC = "U10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_tkmsb" LOC = "U11" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_rx_clk" LOC = "AA11" ; +NET "ser_r[0]" LOC = "AB10" ; +NET "ser_r[1]" LOC = "AA10" ; +NET "ser_r[2]" LOC = "U9" ; +NET "ser_r[3]" LOC = "U6" ; +NET "ser_r[4]" LOC = "AB11" ; +NET "ser_r[5]" LOC = "Y7" ; +NET "ser_r[6]" LOC = "W7" ; +NET "ser_r[7]" LOC = "AB7" ; +NET "ser_r[8]" LOC = "AA7" ; +NET "ser_r[9]" LOC = "W9" ; +NET "ser_r[10]" LOC = "W10" ; +NET "ser_r[11]" LOC = "Y1" ; +NET "ser_r[12]" LOC = "Y3" ; +NET "ser_r[13]" LOC = "Y2" ; +NET "ser_r[14]" LOC = "W4" ; +NET "ser_r[15]" LOC = "W1" ; +NET "ser_rklsb" LOC = "V9" ; +NET "ser_rkmsb" LOC = "Y10" ; +NET "cpld_start" LOC = "AA9" ; +NET "cpld_mode" LOC = "U12" ; +NET "cpld_done" LOC = "V12" ; +NET "cpld_din" LOC = "AA14" ; +NET "cpld_clk" LOC = "AB14" ; +NET "cpld_detached" LOC = "V11" ; +NET "cpld_init_b" LOC = "W12" ; +NET "cpld_misc" LOC = "Y12" ; +NET "POR" LOC = "W18" ; +NET "WDI" LOC = "W15" ; +NET "adc_a[0]" LOC = "A14" | IOBDELAY= "NONE" ; +NET "adc_a[1]" LOC = "B14" | IOBDELAY= "NONE" ; +NET "adc_a[2]" LOC = "C13" | IOBDELAY= "NONE" ; +NET "adc_a[3]" LOC = "D13" | IOBDELAY= "NONE" ; +NET "adc_a[4]" LOC = "A13" | IOBDELAY= "NONE" ; +NET "adc_a[5]" LOC = "B13" | IOBDELAY= "NONE" ; +NET "adc_a[6]" LOC = "E12" | IOBDELAY= "NONE" ; +NET "adc_a[7]" LOC = "C22" | IOBDELAY= "NONE" ; +NET "adc_a[8]" LOC = "C20" | IOBDELAY= "NONE" ; +NET "adc_a[9]" LOC = "C21" | IOBDELAY= "NONE" ; +NET "adc_a[10]" LOC = "D20" | IOBDELAY= "NONE" ; +NET "adc_a[11]" LOC = "D19" | IOBDELAY= "NONE" ; +NET "adc_a[12]" LOC = "D21" | IOBDELAY= "NONE" ; +NET "adc_a[13]" LOC = "E18" | IOBDELAY= "NONE" ; +NET "adc_ovf_a" LOC = "F18" ; +NET "adc_oen_a" LOC = "E19" ; +NET "adc_pdn_a" LOC = "E20" ; +NET "adc_b[0]" LOC = "A12" | IOBDELAY= "NONE"; +NET "adc_b[1]" LOC = "E16" | IOBDELAY= "NONE" ; +NET "adc_b[2]" LOC = "F12" | IOBDELAY= "NONE" ; +NET "adc_b[3]" LOC = "F13" | IOBDELAY= "NONE" ; +NET "adc_b[4]" LOC = "F16" | IOBDELAY= "NONE" ; +NET "adc_b[5]" LOC = "F17" | IOBDELAY= "NONE" ; +NET "adc_b[6]" LOC = "C19" | IOBDELAY= "NONE" ; +NET "adc_b[7]" LOC = "B20" | IOBDELAY= "NONE" ; +NET "adc_b[8]" LOC = "B19" | IOBDELAY= "NONE" ; +NET "adc_b[9]" LOC = "C18" | IOBDELAY= "NONE" ; +NET "adc_b[10]" LOC = "D18" | IOBDELAY= "NONE" ; +NET "adc_b[11]" LOC = "B18" | IOBDELAY= "NONE" ; +NET "adc_b[12]" LOC = "D17" | IOBDELAY= "NONE" ; +NET "adc_b[13]" LOC = "E17" | IOBDELAY= "NONE" ; +NET "adc_ovf_b" LOC = "B17" ; +NET "adc_oen_b" LOC = "C17" ; +NET "adc_pdn_b" LOC = "D15" ; +NET "dac_a[0]" LOC = "A5" ; +NET "dac_a[1]" LOC = "B5" ; +NET "dac_a[2]" LOC = "C5" ; +NET "dac_a[3]" LOC = "D5" ; +NET "dac_a[4]" LOC = "A4" ; +NET "dac_a[5]" LOC = "B4" ; +NET "dac_a[6]" LOC = "F6" ; +NET "dac_a[7]" LOC = "D10" ; +NET "dac_a[8]" LOC = "D9" ; +NET "dac_a[9]" LOC = "A10" ; +NET "dac_a[10]" LOC = "L2" ; +NET "dac_a[11]" LOC = "L4" ; +NET "dac_a[12]" LOC = "L3" ; +NET "dac_a[13]" LOC = "L6" ; +NET "dac_a[14]" LOC = "L5" ; +NET "dac_a[15]" LOC = "K2" ; +NET "dac_b[0]" LOC = "D11" ; +NET "dac_b[1]" LOC = "E11" ; +NET "dac_b[2]" LOC = "F11" ; +NET "dac_b[3]" LOC = "B10" ; +NET "dac_b[4]" LOC = "C10" ; +NET "dac_b[5]" LOC = "E10" ; +NET "dac_b[6]" LOC = "F10" ; +NET "dac_b[7]" LOC = "A9" ; +NET "dac_b[8]" LOC = "B9" ; +NET "dac_b[9]" LOC = "E9" ; +NET "dac_b[10]" LOC = "F9" ; +NET "dac_b[11]" LOC = "A8" ; +NET "dac_b[12]" LOC = "B8" ; +NET "dac_b[13]" LOC = "D7" ; +NET "dac_b[14]" LOC = "E7" ; +NET "dac_b[15]" LOC = "B6" ; +NET "dac_lock" LOC = "D6" ; +NET "SCL" LOC = "A7" ; +NET "SDA" LOC = "D8" ; +NET "clk_en[0]" LOC = "C4" ; +NET "clk_en[1]" LOC = "D1" ; +NET "clk_sel[0]" LOC = "C3" ; +NET "clk_sel[1]" LOC = "C2" ; +NET "clk_func" LOC = "C12" ; +NET "clk_status" LOC = "B12" ; +NET "clk_fpga_p" LOC = "A11" ; +NET "clk_fpga_n" LOC = "B11" ; +NET "clk_to_mac" LOC = "AB12" ; +NET "pps_in" LOC = "K1" ; +NET "sclk" LOC = "K5" ; +NET "sen_clk" LOC = "K6" ; +NET "sen_dac" LOC = "L1" ; +NET "sdi" LOC = "J1" ; +NET "sdo" LOC = "J2" ; +NET "sen_tx_db" LOC = "C1" ; +NET "sclk_tx_db" LOC = "D3" ; +NET "sdo_tx_db" LOC = "G3" ; +NET "sdi_tx_db" LOC = "G4" ; +NET "sen_tx_adc" LOC = "G2" ; +NET "sclk_tx_adc" LOC = "H1" ; +NET "sdo_tx_adc" LOC = "H2" ; +NET "sdi_tx_adc" LOC = "J4" ; +NET "sen_tx_dac" LOC = "H4" ; +NET "sclk_tx_dac" LOC = "J5" ; +NET "sdi_tx_dac" LOC = "J6" ; +NET "io_tx[0]" LOC = "K4" ; +NET "io_tx[1]" LOC = "K3" ; +NET "io_tx[2]" LOC = "G1" ; +NET "io_tx[3]" LOC = "G5" ; +NET "io_tx[4]" LOC = "H5" ; +NET "io_tx[5]" LOC = "F3" ; +NET "io_tx[6]" LOC = "F2" ; +NET "io_tx[7]" LOC = "F5" ; +NET "io_tx[8]" LOC = "G6" ; +NET "io_tx[9]" LOC = "E2" ; +NET "io_tx[10]" LOC = "E1" ; +NET "io_tx[11]" LOC = "E3" ; +NET "io_tx[12]" LOC = "F4" ; +NET "io_tx[13]" LOC = "D2" ; +NET "io_tx[14]" LOC = "D4" ; +NET "io_tx[15]" LOC = "E4" ; +NET "sen_rx_db" LOC = "D22" ; +NET "sclk_rx_db" LOC = "F19" ; +NET "sdo_rx_db" LOC = "G20" ; +NET "sdi_rx_db" LOC = "H19" ; +NET "sen_rx_adc" LOC = "H18" ; +NET "sclk_rx_adc" LOC = "J17" ; +NET "sdo_rx_adc" LOC = "H21" ; +NET "sdi_rx_adc" LOC = "H22" ; +NET "sen_rx_dac" LOC = "J18" ; +NET "sclk_rx_dac" LOC = "J19" ; +NET "sdi_rx_dac" LOC = "J21" ; +NET "io_rx[0]" LOC = "L21" ; +NET "io_rx[1]" LOC = "L20" ; +NET "io_rx[2]" LOC = "L19" ; +NET "io_rx[3]" LOC = "L18" ; +NET "io_rx[4]" LOC = "L17" ; +NET "io_rx[5]" LOC = "K22" ; +NET "io_rx[6]" LOC = "K21" ; +NET "io_rx[7]" LOC = "K20" ; +NET "io_rx[8]" LOC = "G22" ; +NET "io_rx[9]" LOC = "G21" ; +NET "io_rx[10]" LOC = "F21" ; +NET "io_rx[11]" LOC = "F20" ; +NET "io_rx[12]" LOC = "G19" ; +NET "io_rx[13]" LOC = "G18" ; +NET "io_rx[14]" LOC = "G17" ; +NET "io_rx[15]" LOC = "E22" ; + +NET "clk_to_mac" TNM_NET = "clk_to_mac"; +TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; + +NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; + +NET "cpld_clk" TNM_NET = "cpld_clk"; +TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %; + +NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; +TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; + +NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; +TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; + +NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE; +NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; + +#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; +#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; +#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; + +#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; +#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; + +TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns; diff --git a/usrp2/top/USRP2/u2_rev3.v b/usrp2/top/USRP2/u2_rev3.v new file mode 100644 index 000000000..bc7ae5f16 --- /dev/null +++ b/usrp2/top/USRP2/u2_rev3.v @@ -0,0 +1,572 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u2_rev3 + ( + // Misc, debug + output [5:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + output uart_tx_o, + input uart_rx_i, + + // Expansion + input exp_time_in_p, // Diff + input exp_time_in_n, // Diff + output exp_time_out_p, // Diff + output exp_time_out_n, // Diff + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output reg [7:0] GMII_TXD, + output reg GMII_TX_EN, + output reg GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + input PHY_CLK, // possibly use on-board osc + + // RAM + inout [17:0] RAM_D, + output [18:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_CLK, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output reg [15:0] ser_t, + output reg ser_tklsb, + output reg ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // CPLD interface + output cpld_start, // AA9 + output cpld_mode, // U12 + output cpld_done, // V12 + input cpld_din, // AA14 Now shared with CFG_Din + input cpld_clk, // AB14 serial clock + input cpld_detached,// V11 unused + output cpld_init_b, // W12 unused dual purpose + output cpld_misc, // Y12 + + // Watchdog interface + input POR, + output WDI, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_oen_a, + output adc_pdn_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_oen_b, + output adc_pdn_b, + + // DAC + output reg [15:0] dac_a, + output reg [15:0] dac_b, + input dac_lock, // unused for now + + // I2C + inout SCL, + inout SDA, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Clocks + input clk_fpga_p, // Diff + input clk_fpga_n, // Diff + input clk_to_mac, + input pps_in, + + // Generic SPI + output sclk, + output sen_clk, + output sen_dac, + output sdi, + input sdo, + + // TX DBoard + output sen_tx_db, + output sclk_tx_db, + input sdo_tx_db, + output sdi_tx_db, + + output sen_tx_adc, + output sclk_tx_adc, + input sdo_tx_adc, + output sdi_tx_adc, + + output sen_tx_dac, + output sclk_tx_dac, + output sdi_tx_dac, + + inout [15:0] io_tx, + + // RX DBoard + output sen_rx_db, + output sclk_rx_db, + input sdo_rx_db, + output sdi_rx_db, + + output sen_rx_adc, + output sclk_rx_adc, + input sdo_rx_adc, + output sdi_rx_adc, + + output sen_rx_dac, + output sclk_rx_dac, + output sdi_rx_dac, + + inout [15:0] io_rx + ); + + assign cpld_init_b = 0; + // FPGA-specific pins connections + wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; + wire clk90, clk180, clk270; + + // reset the watchdog continuously + reg [15:0] wd; + wire config_success; + + always @(posedge wb_clk) + if(~config_success) + wd <= 0; + else + wd <= wd + 1; + assign WDI = wd[15]; + + wire clk_fpga_unbuf; + + IBUFGDS clk_fpga_pin (.O(clk_fpga_unbuf),.I(clk_fpga_p),.IB(clk_fpga_n)); + BUFG clk_fpga_BUF (.O(clk_fpga),.I(clk_fpga_unbuf)); + + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + wire cpld_clock_buf; + BUFG cpld_clock_BUF (.O(cpld_clock_buf),.I(cpld_clock)); + + wire exp_time_in; + IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); + defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_time_out; + OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); + defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; + + reg [5:0] clock_ready_d; + always @(posedge clk_fpga) + clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; + wire dcm_rst = ~&clock_ready_d & |clock_ready_d; + + wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b; + assign adc_oen_a = ~adc_oe_a; + assign adc_oen_b = ~adc_oe_b; + assign adc_pdn_a = ~adc_on_a; + assign adc_pdn_b = ~adc_on_b; + + reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2; + reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2; + + // ADC A and B are swapped in schematic to facilitate clean layout + always @(posedge dsp_clk) + begin + adc_a_reg1 <= adc_b; + adc_b_reg1 <= adc_a; + adc_ovf_a_reg1 <= adc_ovf_b; + adc_ovf_b_reg1 <= adc_ovf_a; + end + + always @(posedge dsp_clk) + begin + adc_a_reg2 <= adc_a_reg1; + adc_b_reg2 <= adc_b_reg1; + adc_ovf_a_reg2 <= adc_ovf_a_reg1; + adc_ovf_b_reg2 <= adc_ovf_b_reg1; + end // always @ (posedge dsp_clk) + + // Handle Clocks + DCM DCM_INST (.CLKFB(dsp_clk), + .CLKIN(clk_fpga), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(clk90), + .CLK180(clk180), + .CLK270(clk270), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 10.000; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // LEDs are active low outputs + wire [5:0] leds_int; + assign leds = 6'b011111 ^ leds_int; // all except eth are active-low + + // SPI + wire miso, mosi, sclk_int; + assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0; + + assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) | + (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) | + (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc); + + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; + wire [7:0] GMII_TXD_unreg; + wire GMII_GTX_CLK_int; + + always @(posedge GMII_GTX_CLK_int) + begin + GMII_TX_EN <= GMII_TX_EN_unreg; + GMII_TX_ER <= GMII_TX_ER_unreg; + GMII_TXD <= GMII_TXD_unreg; + end + + OFDDRRSE OFDDRRSE_gmii_inst + (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) + .C0(GMII_GTX_CLK_int), // 0 degree clock input + .C1(~GMII_GTX_CLK_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + + wire ser_tklsb_unreg, ser_tkmsb_unreg; + wire [15:0] ser_t_unreg; + wire ser_tx_clk_int; + + always @(posedge ser_tx_clk_int) + begin + ser_tklsb <= ser_tklsb_unreg; + ser_tkmsb <= ser_tkmsb_unreg; + ser_t <= ser_t_unreg; + end + + assign ser_tx_clk = clk_fpga; + + reg [15:0] ser_r_int; + reg ser_rklsb_int, ser_rkmsb_int; + + wire ser_rx_clk_buf; + BUFG ser_rx_clk_BUF (.O(ser_rx_clk_buf),.I(ser_rx_clk)); + always @(posedge ser_rx_clk_buf) + begin + ser_r_int <= ser_r; + ser_rklsb_int <= ser_rklsb; + ser_rkmsb_int <= ser_rkmsb; + end + + wire [15:0] dac_a_int, dac_b_int; + // DAC A and B are swapped in schematic to facilitate clean layout + // DAC A is also inverted in schematic to facilitate clean layout + always @(posedge dsp_clk) dac_a <= ~dac_b_int; + always @(posedge dsp_clk) dac_b <= dac_a_int; + + /* + OFDDRRSE OFDDRRSE_serdes_inst + (.Q(ser_tx_clk), // Data output (connect directly to top-level port) + .C0(ser_tx_clk_int), // 0 degree clock input + .C1(~ser_tx_clk_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + */ + + wire [17:0] RAM_D_pi; + wire [17:0] RAM_D_po; + wire RAM_D_poe; + + genvar i; + + // + // Instantiate IO for Bidirectional bus to SRAM + // + + generate + for (i=0;i<18;i=i+1) + begin : gen_RAM_D_IO + + IOBUF #( + .DRIVE(12), + .IOSTANDARD("LVCMOS25"), + .SLEW("FAST") + ) + RAM_D_i ( + .O(RAM_D_pi[i]), + .I(RAM_D_po[i]), + .IO(RAM_D[i]), + .T(RAM_D_poe) + ); + end // block: gen_RAM_D_IO + endgenerate + + // + // DCM edits start here + // + + + wire RAM_CLK_buf; + wire clk_to_mac_buf; + wire clk125_ext_clk0; + wire clk125_ext_clk180; + wire clk125_ext_clk0_buf; + wire clk125_ext_clk180_buf; + wire clk125_int_buf; + wire clk125_int; + + IBUFG clk_to_mac_buf_i1 (.I(clk_to_mac), + .O(clk_to_mac_buf)); + + DCM DCM_INST1 (.CLKFB(RAM_CLK_buf), + .CLKIN(clk_to_mac_buf), + .DSSEN(1'b0), + .PSCLK(1'b0), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .RST(1'b0), + .CLK0(clk125_ext_clk0), + .CLK180(clk125_ext_clk180) ); + defparam DCM_INST1.CLK_FEEDBACK = "1X"; + defparam DCM_INST1.CLKDV_DIVIDE = 2.0; + defparam DCM_INST1.CLKFX_DIVIDE = 1; + defparam DCM_INST1.CLKFX_MULTIPLY = 4; + defparam DCM_INST1.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST1.CLKIN_PERIOD = 8.000; + defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "FIXED"; + defparam DCM_INST1.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST1.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST1.FACTORY_JF = 16'h8080; + defparam DCM_INST1.PHASE_SHIFT = -64; + defparam DCM_INST1.STARTUP_WAIT = "FALSE"; + + IBUFG RAM_CLK_buf_i1 (.I(RAM_CLK), + .O(RAM_CLK_buf)); + BUFG clk125_ext_clk0_buf_i1 (.I(clk125_ext_clk0), + .O(clk125_ext_clk0_buf)); + BUFG clk125_ext_clk180_buf_i1 (.I(clk125_ext_clk180), + .O(clk125_ext_clk180_buf)); + + OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK), + .C0(clk125_ext_clk0_buf), + .C1(clk125_ext_clk180_buf), + .CE(1'b1), + .D0(1'b1), + .D1(1'b0), + .R(1'b0), + .S(1'b0)); + +// SRL16 dcm2_rst_i1 (.D(1'b0), +// .CLK(clk_to_mac_buf), +// .Q(dcm2_rst), +// .A0(1'b1), +// .A1(1'b1), +// .A2(1'b1), +// .A3(1'b1)); + // synthesis attribute init of dcm2_rst_i1 is "000F"; + + DCM DCM_INST2 (.CLKFB(clk125_int_buf), + .CLKIN(clk_to_mac_buf), + .DSSEN(1'b0), + .PSCLK(1'b0), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .RST(1'b0), + .CLK0(clk125_int)); + defparam DCM_INST2.CLK_FEEDBACK = "1X"; + defparam DCM_INST2.CLKDV_DIVIDE = 2.0; + defparam DCM_INST2.CLKFX_DIVIDE = 1; + defparam DCM_INST2.CLKFX_MULTIPLY = 4; + defparam DCM_INST2.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST2.CLKIN_PERIOD = 8.000; + defparam DCM_INST2.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST2.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST2.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST2.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST2.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST2.FACTORY_JF = 16'h8080; + defparam DCM_INST2.PHASE_SHIFT = 0; + defparam DCM_INST2.STARTUP_WAIT = "FALSE"; + + BUFG clk125_int_buf_i1 (.I(clk125_int), + .O(clk125_int_buf)); + + // + // DCM edits end here + // + + + u2_core + u2_core(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk125_int_buf), + .pps_in (pps_in), + .leds (leds_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_time_in (exp_time_in), + .exp_time_out (exp_time_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk_buf), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .cpld_misc (cpld_misc), + .cpld_init_b (cpld_init_b), + .por (~POR), + .config_success (config_success), + .adc_a (adc_a_reg2), + .adc_ovf_a (adc_ovf_a_reg2), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b_reg2), + .adc_ovf_b (adc_ovf_b_reg2), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (dac_a_int), + .dac_b (dac_b_int), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk_int), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D_pi (RAM_D_pi), + .RAM_D_po (RAM_D_po), + .RAM_D_poe (RAM_D_poe), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + // .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (uart_tx_o), + .uart_rx_i (uart_rx_i), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2) + ); + +endmodule // u2_rev2 diff --git a/usrp2/top/safe_u1plus/.gitignore b/usrp2/top/safe_u1plus/.gitignore deleted file mode 100644 index 1b2211df0..000000000 --- a/usrp2/top/safe_u1plus/.gitignore +++ /dev/null @@ -1 +0,0 @@ -build* diff --git a/usrp2/top/safe_u1plus/Makefile b/usrp2/top/safe_u1plus/Makefile deleted file mode 100644 index 33a2a51c7..000000000 --- a/usrp2/top/safe_u1plus/Makefile +++ /dev/null @@ -1,122 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -################################################## -# xtclsh Shell and tcl Script Path -################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl - -################################################## -# Project Setup -################################################## -BUILD_DIR := build/ -export TOP_MODULE := safe_u1plus -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan3A" \ -device XC3S1400A \ -package ft256 \ -speed -4 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -top/safe_u1plus/safe_u1plus.ucf \ -top/safe_u1plus/safe_u1plus.v - -################################################## -# Process Properties -################################################## -export SYNTHESIZE_PROPERTIES := \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -export TRANSLATE_PROPERTIES := \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -export MAP_PROPERTIES := \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -export PLACE_ROUTE_PROPERTIES := \ -"Place & Route Effort Level (Overall)" High - -export STATIC_TIMING_PROPERTIES := \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -export GEN_PROG_FILE_PROPERTIES := \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -clean: - rm -rf $(BUILD_DIR) - - diff --git a/usrp2/top/safe_u1plus/safe_u1plus.ucf b/usrp2/top/safe_u1plus/safe_u1plus.ucf deleted file mode 100644 index a0c743525..000000000 --- a/usrp2/top/safe_u1plus/safe_u1plus.ucf +++ /dev/null @@ -1,171 +0,0 @@ -NET "debug_led<2>" LOC = "R2" ; -NET "debug_led<1>" LOC = "N4" ; -NET "debug_led<0>" LOC = "P4" ; -NET "reset_n" LOC = "D5" ; -NET "CLK_FPGA_P" LOC = "R7" ; -NET "CLK_FPGA_N" LOC = "T7" ; - -#NET "fpga_cfg_prog_b" LOC = "A2" ; -#NET "fpga_cfg_done" LOC = "T15" ; -#NET "fpga_cfg_din" LOC = "T14" ; -#NET "fpga_cfg_cclk" LOC = "R14" ; -NET "fpga_cfg_init_b" LOC = "T12" ; - - -#NET "TMS" LOC = "B2" ; -#NET "TDO" LOC = "B16" ; -#NET "TDI" LOC = "B1" ; -#NET "TCK" LOC = "A15" ; -#NET "GPIF_D07" LOC = "N12" ; -#NET "GPIF_D06" LOC = "P13" ; -#NET "GPIF_D05" LOC = "P11" ; -#NET "GPIF_RDY3" LOC = "N11" ; -#NET "GPIF_RDY2" LOC = "T10" ; -#NET "GPIF_RDY1" LOC = "T4" ; -#NET "GPIF_RDY0" LOC = "R5" ; -#NET "cgen_st_status" LOC = "P6" ; -#NET "GPIF_CTL3" LOC = "N5" ; -#NET "GPIF_CTL2" LOC = "M11" ; -#NET "GPIF_CTL1" LOC = "M9" ; -#NET "GPIF_CTL0" LOC = "M7" ; -#NET "SDA_FPGA" LOC = "T13" ; -#NET "SCL_FPGA" LOC = "R13" ; -#NET "FX2_PA7_FLAGD" LOC = "P12" ; -#NET "mystery_bus_2" LOC = "T11" ; -#NET "FX2_PA6_PKTEND" LOC = "R11" ; -#NET "FX2_PA2_SLOE" LOC = "P10" ; -#NET "GPIF_D15" LOC = "P7" ; -#NET "GPIF_D14" LOC = "N8" ; -#NET "GPIF_D13" LOC = "T5" ; -#NET "GPIF_D12" LOC = "T6" ; -#NET "GPIF_D11" LOC = "N6" ; -#NET "GPIF_D10" LOC = "P5" ; -#NET "GPIF_D09" LOC = "R3" ; -#NET "GPIF_D08" LOC = "T3" ; -#NET "cgen_ref_sel" LOC = "T2" ; -#NET "GPIF_D04" LOC = "R9" ; -#NET "GPIF_D03" LOC = "T9" ; -#NET "GPIF_D02" LOC = "N9" ; -#NET "GPIF_D01" LOC = "P9" ; -#NET "GPIF_D00" LOC = "P8" ; -#NET "IFCLK" LOC = "T8" ; -#NET "cgen_sync_b" LOC = "H15" ; -#NET "FPGA_TXD" LOC = "H16" ; -#NET "debug_00" LOC = "K16" ; -#NET "debug_01" LOC = "J16" ; -#NET "debug_clk0" LOC = "K15" ; -#NET "debug_clk1" LOC = "K14" ; -#NET "debug_02" LOC = "C16" ; -#NET "debug_03" LOC = "C15" ; -#NET "debug_04" LOC = "E13" ; -#NET "debug_05" LOC = "D14" ; -#NET "debug_06" LOC = "D16" ; -#NET "debug_07" LOC = "D15" ; -#NET "debug_08" LOC = "E14" ; -#NET "debug_09" LOC = "F13" ; -#NET "debug_10" LOC = "G13" ; -#NET "debug_11" LOC = "F14" ; -#NET "debug_12" LOC = "E16" ; -#NET "debug_13" LOC = "F15" ; -#NET "debug_14" LOC = "H13" ; -#NET "debug_15" LOC = "G14" ; -#NET "debug_16" LOC = "G16" ; -#NET "debug_17" LOC = "F16" ; -#NET "debug_18" LOC = "J12" ; -#NET "debug_19" LOC = "J13" ; -#NET "debug_20" LOC = "L14" ; -#NET "debug_21" LOC = "L16" ; -#NET "debug_22" LOC = "M15" ; -#NET "debug_23" LOC = "M16" ; -#NET "debug_24" LOC = "L13" ; -#NET "debug_25" LOC = "K13" ; -#NET "debug_26" LOC = "P16" ; -#NET "debug_27" LOC = "N16" ; -#NET "debug_28" LOC = "R15" ; -#NET "debug_29" LOC = "P15" ; -#NET "debug_30" LOC = "N13" ; -#NET "debug_31" LOC = "N14" ; -#NET "PPS_IN" LOC = "M14" ; -#NET "cgen_st_ld" LOC = "M13" ; -#NET "cgen_st_refmon" LOC = "J14" ; -#NET "FPGA_RXD" LOC = "H12" ; -#NET "DA10" LOC = "A8" ; -#NET "DA09" LOC = "B8" ; -#NET "DA08" LOC = "C8" ; -#NET "DA07" LOC = "D8" ; -#NET "DA06" LOC = "C9" ; -#NET "DA05" LOC = "A9" ; -#NET "DA04" LOC = "C10" ; -#NET "DA03" LOC = "D9" ; -#NET "SCLK_CODEC" LOC = "K3" ; -#NET "TXBLANK" LOC = "K1" ; -#NET "TXSYNC" LOC = "J2" ; -#NET "TX00" LOC = "J1" ; -#NET "TX01" LOC = "H3" ; -#NET "TX02" LOC = "J3" ; -#NET "TX03" LOC = "G2" ; -#NET "TX04" LOC = "H1" ; -#NET "TX05" LOC = "N3" ; -#NET "TX06" LOC = "M4" ; -#NET "TX07" LOC = "R1" ; -#NET "TX08" LOC = "P2" ; -#NET "TX09" LOC = "P1" ; -#NET "TX10" LOC = "M1" ; -#NET "TX11" LOC = "N1" ; -#NET "TX12" LOC = "M3" ; -#NET "TX13" LOC = "L4" ; -#NET "io_tx_00" LOC = "K4" ; -#NET "io_tx_01" LOC = "L3" ; -#NET "io_tx_02" LOC = "L2" ; -#NET "io_tx_03" LOC = "F1" ; -#NET "io_tx_04" LOC = "F3" ; -#NET "io_tx_05" LOC = "G3" ; -#NET "io_tx_06" LOC = "E3" ; -#NET "io_tx_07" LOC = "E2" ; -#NET "io_tx_08" LOC = "E4" ; -#NET "io_tx_09" LOC = "F4" ; -#NET "io_tx_10" LOC = "D1" ; -#NET "io_tx_11" LOC = "E1" ; -#NET "io_tx_12" LOC = "D4" ; -#NET "io_tx_13" LOC = "D3" ; -#NET "io_tx_14" LOC = "C2" ; -#NET "io_tx_15" LOC = "C1" ; -#NET "MISO_AUX" LOC = "J5" ; -#NET "MISO_CODEC" LOC = "G4" ; -#NET "MISO_TX_DB" LOC = "J4" ; -#NET "SEN_TX_DB" LOC = "N2" ; -#NET "MOSI_TX_DB" LOC = "L1" ; -#NET "SCLK_TX_DB" LOC = "G1" ; -#NET "DA02" LOC = "A3" ; -#NET "DA01" LOC = "B3" ; -#NET "DA00" LOC = "A4" ; -#NET "SEN_RX_DB" LOC = "B4" ; -#NET "MOSI_RX_DB" LOC = "A5" ; -#NET "SCLK_RX_DB" LOC = "C5" ; -#NET "io_rx_00" LOC = "D7" ; -#NET "io_rx_01" LOC = "C6" ; -#NET "io_rx_02" LOC = "A6" ; -#NET "io_rx_03" LOC = "B6" ; -#NET "io_rx_04" LOC = "E9" ; -#NET "io_rx_05" LOC = "A7" ; -#NET "io_rx_06" LOC = "C7" ; -#NET "io_rx_07" LOC = "B10" ; -#NET "io_rx_08" LOC = "A10" ; -#NET "io_rx_09" LOC = "C11" ; -#NET "io_rx_10" LOC = "A11" ; -#NET "io_rx_11" LOC = "D11" ; -#NET "io_rx_12" LOC = "B12" ; -#NET "io_rx_13" LOC = "A12" ; -#NET "io_rx_14" LOC = "A14" ; -#NET "io_rx_15" LOC = "A13" ; -#NET "SEN_AUX" LOC = "C12" ; -#NET "SCLK_AUX" LOC = "D12" ; -#NET "reset_codec" LOC = "B14" ; -#NET "SEN_CODEC" LOC = "D13" ; -#NET "MOSI_CODEC" LOC = "C13" ; -#NET "MISO_RX_DB" LOC = "E6" ; -#NET "mystery_bus_1" LOC = "C4" ; -#NET "mystery_bus_0" LOC = "E7" ; -#NET "RXSYNC" LOC = "D10" ; -#NET "DA11" LOC = "B15" ; - diff --git a/usrp2/top/safe_u1plus/safe_u1plus.v b/usrp2/top/safe_u1plus/safe_u1plus.v deleted file mode 100644 index e55c7f0be..000000000 --- a/usrp2/top/safe_u1plus/safe_u1plus.v +++ /dev/null @@ -1,28 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module safe_u1plus - (input CLK_FPGA_P, input CLK_FPGA_N, - input reset_n, - output [2:0] debug_led, // LED4 is shared w/INIT_B - output fpga_cfg_init_b - ); - - assign fpga_cfg_init_b = 1; - - // FPGA-specific pins connections - wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; - - IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; - - reg [31:0] ctr; - - always @(posedge clk_fpga) - ctr <= ctr + 1; - - assign debug_led[1:0] = ~ctr[26:25]; - - assign debug_led[2] = ~reset_n; - -endmodule // safe_u1plus diff --git a/usrp2/top/safe_u2plus/.gitignore b/usrp2/top/safe_u2plus/.gitignore deleted file mode 100644 index a96f0be92..000000000 --- a/usrp2/top/safe_u2plus/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -build* -*impact* diff --git a/usrp2/top/safe_u2plus/Makefile b/usrp2/top/safe_u2plus/Makefile deleted file mode 100644 index b72241050..000000000 --- a/usrp2/top/safe_u2plus/Makefile +++ /dev/null @@ -1,245 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -################################################## -# xtclsh Shell and tcl Script Path -################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl - -################################################## -# Project Setup -################################################## -BUILD_DIR := build/ -export TOP_MODULE := safe_u2plus -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd3400a \ -package fg676 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ -control_lib/bin2gray.v \ -control_lib/dcache.v \ -control_lib/decoder_3_8.v \ -control_lib/dpram32.v \ -control_lib/gray2bin.v \ -control_lib/gray_send.v \ -control_lib/icache.v \ -control_lib/mux4.v \ -control_lib/mux8.v \ -control_lib/nsgpio.v \ -control_lib/ram_2port.v \ -control_lib/ram_harv_cache.v \ -control_lib/ram_loader.v \ -control_lib/setting_reg.v \ -control_lib/settings_bus.v \ -control_lib/srl.v \ -control_lib/system_control.v \ -control_lib/wb_1master.v \ -control_lib/wb_readback_mux.v \ -control_lib/simple_uart.v \ -control_lib/simple_uart_tx.v \ -control_lib/simple_uart_rx.v \ -control_lib/oneshot_2clk.v \ -control_lib/sd_spi.v \ -control_lib/sd_spi_wb.v \ -control_lib/wb_bridge_16_32.v \ -control_lib/reset_sync.v \ -simple_gemac/simple_gemac_wrapper.v \ -simple_gemac/simple_gemac.v \ -simple_gemac/simple_gemac_wb.v \ -simple_gemac/simple_gemac_tx.v \ -simple_gemac/simple_gemac_rx.v \ -simple_gemac/crc.v \ -simple_gemac/delay_line.v \ -simple_gemac/flow_ctrl_tx.v \ -simple_gemac/flow_ctrl_rx.v \ -simple_gemac/address_filter.v \ -simple_gemac/ll8_to_txmac.v \ -simple_gemac/rxmac_to_ll8.v \ -simple_gemac/miim/eth_miim.v \ -simple_gemac/miim/eth_clockgen.v \ -simple_gemac/miim/eth_outputcontrol.v \ -simple_gemac/miim/eth_shiftreg.v \ -control_lib/newfifo/buffer_int.v \ -control_lib/newfifo/buffer_pool.v \ -control_lib/newfifo/fifo_2clock.v \ -control_lib/newfifo/fifo_2clock_cascade.v \ -control_lib/newfifo/ll8_shortfifo.v \ -control_lib/newfifo/ll8_to_fifo36.v \ -control_lib/newfifo/fifo_short.v \ -control_lib/newfifo/fifo_long.v \ -control_lib/newfifo/fifo_cascade.v \ -control_lib/newfifo/fifo36_to_ll8.v \ -control_lib/longfifo.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ -coregen/fifo_xlnx_2Kx36_2clk.v \ -coregen/fifo_xlnx_2Kx36_2clk.xco \ -coregen/fifo_xlnx_512x36_2clk.v \ -coregen/fifo_xlnx_512x36_2clk.xco \ -coregen/fifo_xlnx_64x36_2clk.v \ -coregen/fifo_xlnx_64x36_2clk.xco \ -opencores/8b10b/decode_8b10b.v \ -opencores/8b10b/encode_8b10b.v \ -opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -opencores/aemb/rtl/verilog/aeMB_core_BE.v \ -opencores/aemb/rtl/verilog/aeMB_ctrl.v \ -opencores/aemb/rtl/verilog/aeMB_edk32.v \ -opencores/aemb/rtl/verilog/aeMB_ibuf.v \ -opencores/aemb/rtl/verilog/aeMB_regf.v \ -opencores/aemb/rtl/verilog/aeMB_xecu.v \ -opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_defines.v \ -opencores/i2c/rtl/verilog/i2c_master_top.v \ -opencores/i2c/rtl/verilog/timescale.v \ -opencores/simple_pic/rtl/simple_pic.v \ -opencores/spi/rtl/verilog/spi_clgen.v \ -opencores/spi/rtl/verilog/spi_defines.v \ -opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ -sdr_lib/acc.v \ -sdr_lib/add2.v \ -sdr_lib/add2_and_round.v \ -sdr_lib/add2_and_round_reg.v \ -sdr_lib/add2_reg.v \ -sdr_lib/cic_dec_shifter.v \ -sdr_lib/cic_decim.v \ -sdr_lib/cic_int_shifter.v \ -sdr_lib/cic_interp.v \ -sdr_lib/cic_strober.v \ -sdr_lib/clip.v \ -sdr_lib/clip_reg.v \ -sdr_lib/cordic.v \ -sdr_lib/cordic_z24.v \ -sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_rx.v \ -sdr_lib/dsp_core_tx.v \ -sdr_lib/hb_dec.v \ -sdr_lib/hb_interp.v \ -sdr_lib/round.v \ -sdr_lib/round_reg.v \ -sdr_lib/rx_control.v \ -sdr_lib/rx_dcoffset.v \ -sdr_lib/sign_extend.v \ -sdr_lib/small_hb_dec.v \ -sdr_lib/small_hb_int.v \ -sdr_lib/tx_control.v \ -serdes/serdes.v \ -serdes/serdes_fc_rx.v \ -serdes/serdes_fc_tx.v \ -serdes/serdes_rx.v \ -serdes/serdes_tx.v \ -timing/time_receiver.v \ -timing/time_sender.v \ -timing/time_sync.v \ -timing/timer.v \ -top/u2_core/u2_core.v \ -top/u2plus/capture_ddrlvds.v \ -top/safe_u2plus/u2plus.ucf \ -top/safe_u2plus/safe_u2plus.v - -################################################## -# Process Properties -################################################## -export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -export TRANSLATE_PROPERTIES := \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -export MAP_PROPERTIES := \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -export PLACE_ROUTE_PROPERTIES := \ -"Place & Route Effort Level (Overall)" High - -export STATIC_TIMING_PROPERTIES := \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -export GEN_PROG_FILE_PROPERTIES := \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -clean: - rm -rf $(BUILD_DIR) - - diff --git a/usrp2/top/safe_u2plus/safe_u2plus.v b/usrp2/top/safe_u2plus/safe_u2plus.v deleted file mode 100644 index dca9688c5..000000000 --- a/usrp2/top/safe_u2plus/safe_u2plus.v +++ /dev/null @@ -1,23 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module safe_u2plus - ( - input CLK_FPGA_P, input CLK_FPGA_N, // Diff - output [5:1] leds, // LED4 is shared w/INIT_B - output ETH_LED - ); - - wire clk_fpga; - - IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; - - reg [31:0] ctr; - - always @(posedge clk_fpga) - ctr <= ctr + 1; - - assign {leds,ETH_LED} = ~ctr[29:24]; - -endmodule // safe_u2plus diff --git a/usrp2/top/safe_u2plus/u2plus.ucf b/usrp2/top/safe_u2plus/u2plus.ucf deleted file mode 100755 index 0a9460d86..000000000 --- a/usrp2/top/safe_u2plus/u2plus.ucf +++ /dev/null @@ -1,401 +0,0 @@ -## Main 100 MHz Clock -NET "CLK_FPGA_P" LOC = "AA13" ; -NET "CLK_FPGA_N" LOC = "Y13" ; - -## ADC -#NET "ADC_clkout_p" LOC = "P1" ; -#NET "ADC_clkout_n" LOC = "P2" ; -#NET "ADCA_12_p" LOC = "Y1" ; -#NET "ADCA_12_n" LOC = "Y2" ; -#NET "ADCA_10_p" LOC = "W3" ; -#NET "ADCA_10_n" LOC = "W4" ; -#NET "ADCA_8_p" LOC = "T7" ; -#NET "ADCA_8_n" LOC = "U6" ; -#NET "ADCA_6_p" LOC = "U5" ; -#NET "ADCA_6_n" LOC = "V5" ; -#NET "ADCA_4_p" LOC = "T10" ; -#NET "ADCA_4_n" LOC = "T9" ; -#NET "ADCA_2_p" LOC = "V1" ; -#NET "ADCA_2_n" LOC = "V2" ; -#NET "ADCA_0_p" LOC = "R8" ; -#NET "ADCA_0_n" LOC = "R7" ; -#NET "ADCB_2_p" LOC = "U7" ; -#NET "ADCB_2_n" LOC = "U8" ; -#NET "ADCB_0_p" LOC = "AA2" ; -#NET "ADCB_0_n" LOC = "AA3" ; -#NET "ADCB_4_p" LOC = "AE1" ; -#NET "ADCB_4_n" LOC = "AE2" ; -#NET "ADCB_6_p" LOC = "W1" ; -#NET "ADCB_6_n" LOC = "W2" ; -#NET "ADCB_8_p" LOC = "U3" ; -#NET "ADCB_8_n" LOC = "V4" ; -#NET "ADCB_10_p" LOC = "J1" ; -#NET "ADCB_10_n" LOC = "K1" ; -#NET "ADCB_12_p" LOC = "J3" ; -#NET "ADCB_12_n" LOC = "J2" ; - -## DAC -#NET "DAC_LOCK" LOC = "P4" ; -#NET "DACA<0>" LOC = "P8" ; -#NET "DACA<1>" LOC = "P9" ; -#NET "DACA<2>" LOC = "R5" ; -#NET "DACA<3>" LOC = "R6" ; -#NET "DACA<4>" LOC = "P7" ; -#NET "DACA<5>" LOC = "P6" ; -#NET "DACA<6>" LOC = "T3" ; -#NET "DACA<7>" LOC = "T4" ; -#NET "DACA<8>" LOC = "R3" ; -#NET "DACA<9>" LOC = "R4" ; -#NET "DACA<10>" LOC = "R2" ; -#NET "DACA<11>" LOC = "N1" ; -#NET "DACA<12>" LOC = "N2" ; -#NET "DACA<13>" LOC = "N5" ; -#NET "DACA<14>" LOC = "N4" ; -#NET "DACA<15>" LOC = "M2" ; -#NET "DACB<0>" LOC = "M5" ; -#NET "DACB<1>" LOC = "M6" ; -#NET "DACB<2>" LOC = "M4" ; -#NET "DACB<3>" LOC = "M3" ; -#NET "DACB<4>" LOC = "M8" ; -#NET "DACB<5>" LOC = "M7" ; -#NET "DACB<6>" LOC = "L4" ; -#NET "DACB<7>" LOC = "L3" ; -#NET "DACB<8>" LOC = "K3" ; -#NET "DACB<9>" LOC = "K2" ; -#NET "DACB<10>" LOC = "K5" ; -#NET "DACB<11>" LOC = "K4" ; -#NET "DACB<12>" LOC = "M10" ; -#NET "DACB<13>" LOC = "M9" ; -#NET "DACB<14>" LOC = "J5" ; -#NET "DACB<15>" LOC = "J4" ; - -## TX DB GPIO -#NET "io_tx<15>" LOC = "K6" ; -#NET "io_tx<14>" LOC = "L7" ; -#NET "io_tx<13>" LOC = "H2" ; -#NET "io_tx<12>" LOC = "H1" ; -#NET "io_tx<11>" LOC = "L10" ; -#NET "io_tx<10>" LOC = "L9" ; -#NET "io_tx<9>" LOC = "G3" ; -#NET "io_tx<8>" LOC = "F3" ; -#NET "io_tx<7>" LOC = "K7" ; -#NET "io_tx<6>" LOC = "J6" ; -#NET "io_tx<5>" LOC = "E1" ; -#NET "io_tx<4>" LOC = "F2" ; -#NET "io_tx<3>" LOC = "J7" ; -#NET "io_tx<2>" LOC = "H6" ; -#NET "io_tx<1>" LOC = "F5" ; -#NET "io_tx<0>" LOC = "G4" ; - -## RX DB GPIO -#NET "io_rx<15>" LOC = "AD1" ; -#NET "io_rx<14>" LOC = "AD2" ; -#NET "io_rx<13>" LOC = "AC2" ; -#NET "io_rx<12>" LOC = "AC3" ; -#NET "io_rx<11>" LOC = "W7" ; -#NET "io_rx<10>" LOC = "W6" ; -#NET "io_rx<9>" LOC = "U9" ; -#NET "io_rx<8>" LOC = "V8" ; -#NET "io_rx<7>" LOC = "AB1" ; -#NET "io_rx<6>" LOC = "AC1" ; -#NET "io_rx<5>" LOC = "V7" ; -#NET "io_rx<4>" LOC = "V6" ; -#NET "io_rx<3>" LOC = "Y5" ; -#NET "io_rx<2>" LOC = "R10" ; -#NET "io_rx<1>" LOC = "R1" ; -#NET "io_rx<0>" LOC = "M1" ; - -## MISC -NET "leds<5>" LOC = "AF25" ; -NET "leds<4>" LOC = "AE25" ; -NET "leds<3>" LOC = "AF23" ; -NET "leds<2>" LOC = "AE23" ; -NET "leds<1>" LOC = "AB18" ; -#NET "FPGA_RESET" LOC = "K24" ; - -## Debug -#NET "debug_clk<0>" LOC = "AA10" ; -#NET "debug_clk<1>" LOC = "AD11" ; -#NET "debug<0>" LOC = "AC19" ; -#NET "debug<1>" LOC = "AF20" ; -#NET "debug<2>" LOC = "AE20" ; -#NET "debug<3>" LOC = "AC16" ; -#NET "debug<4>" LOC = "AB16" ; -#NET "debug<5>" LOC = "AF19" ; -#NET "debug<6>" LOC = "AE19" ; -#NET "debug<7>" LOC = "V15" ; -#NET "debug<8>" LOC = "U15" ; -#NET "debug<9>" LOC = "AE17" ; -#NET "debug<10>" LOC = "AD17" ; -#NET "debug<11>" LOC = "V14" ; -#NET "debug<12>" LOC = "W15" ; -#NET "debug<13>" LOC = "AC15" ; -#NET "debug<14>" LOC = "AD14" ; -#NET "debug<15>" LOC = "AC14" ; -#NET "debug<16>" LOC = "AC11" ; -#NET "debug<17>" LOC = "AB12" ; -#NET "debug<18>" LOC = "AC12" ; -#NET "debug<19>" LOC = "V13" ; -#NET "debug<20>" LOC = "W13" ; -#NET "debug<21>" LOC = "AE8" ; -#NET "debug<22>" LOC = "AF8" ; -#NET "debug<23>" LOC = "V12" ; -#NET "debug<24>" LOC = "W12" ; -#NET "debug<25>" LOC = "AB9" ; -#NET "debug<26>" LOC = "AC9" ; -#NET "debug<27>" LOC = "AC8" ; -#NET "debug<28>" LOC = "AB7" ; -#NET "debug<29>" LOC = "V11" ; -#NET "debug<30>" LOC = "U11" ; -#NET "debug<31>" LOC = "Y10" ; - -## UARTS -#NET "TXD<3>" LOC = "AD20" ; -#NET "TXD<2>" LOC = "AC20" ; -#NET "TXD<1>" LOC = "AD19" ; -#NET "RXD<3>" LOC = "AF17" ; -#NET "RXD<2>" LOC = "AF15" ; -#NET "RXD<1>" LOC = "AD12" ; - -## AD9510 -#NET "CLK_STATUS" LOC = "AD22" ; -#NET "CLK_FUNC" LOC = "AC21" ; -#NET "clk_sel<0>" LOC = "AE21" ; -#NET "clk_sel<1>" LOC = "AD21" ; -#NET "clk_en<1>" LOC = "AA17" ; -#NET "clk_en<0>" LOC = "Y17" ; - -## I2C -#NET "SDA" LOC = "V16" ; -#NET "SCL" LOC = "U16" ; - -## Timing -#NET "PPS_IN" LOC = "AB6" ; -#NET "PPS2_IN" LOC = "AA20" ; - -## SPI -#NET "SEN_CLK" LOC = "AA18" ; -#NET "MOSI_CLK" LOC = "W17" ; -#NET "SCLK_CLK" LOC = "V17" ; -#NET "MISO_CLK" LOC = "AC10" ; - -#NET "SEN_DAC" LOC = "AE7" ; -#NET "SCLK_DAC" LOC = "AF5" ; -#NET "MOSI_DAC" LOC = "AE6" ; -#NET "MISO_DAC" LOC = "Y3" ; - -#NET "SCLK_ADC" LOC = "B1" ; -#NET "MOSI_ADC" LOC = "J8" ; -#NET "SEN_ADC" LOC = "J9" ; - -#NET "MOSI_TX_ADC" LOC = "V10" ; -#NET "SEN_TX_ADC" LOC = "W10" ; -#NET "SCLK_TX_ADC" LOC = "AC6" ; -#NET "MISO_TX_ADC" LOC = "G1" ; - -#NET "MOSI_TX_DAC" LOC = "AD6" ; -#NET "SEN_TX_DAC" LOC = "AE4" ; -#NET "SCLK_TX_DAC" LOC = "AF4" ; - -#NET "SCLK_TX_DB" LOC = "AE3" ; -#NET "MOSI_TX_DB" LOC = "AF3" ; -#NET "SEN_TX_DB" LOC = "W9" ; -#NET "MISO_TX_DB" LOC = "AA5" ; - -#NET "MOSI_RX_ADC" LOC = "E3" ; -#NET "SCLK_RX_ADC" LOC = "F4" ; -#NET "SEN_RX_ADC" LOC = "D3" ; -#NET "MISO_RX_ADC" LOC = "C1" ; - -#NET "SCLK_RX_DAC" LOC = "E4" ; -#NET "SEN_RX_DAC" LOC = "K9" ; -#NET "MOSI_RX_DAC" LOC = "K8" ; - -#NET "SCLK_RX_DB" LOC = "G6" ; -#NET "MOSI_RX_DB" LOC = "H7" ; -#NET "SEN_RX_DB" LOC = "B2" ; -#NET "MISO_RX_DB" LOC = "H4" ; - -## ETH PHY -#NET "CLK_TO_MAC" LOC = "P26" ; - -#NET "GMII_TXD<7>" LOC = "G21" ; -#NET "GMII_TXD<6>" LOC = "C26" ; -#NET "GMII_TXD<5>" LOC = "C25" ; -#NET "GMII_TXD<4>" LOC = "J21" ; -#NET "GMII_TXD<3>" LOC = "H21" ; -#NET "GMII_TXD<2>" LOC = "D25" ; -#NET "GMII_TXD<1>" LOC = "D24" ; -#NET "GMII_TXD<0>" LOC = "E26" ; -#NET "GMII_TX_EN" LOC = "D26" ; -#NET "GMII_TX_ER" LOC = "J19" ; -#NET "GMII_GTX_CLK" LOC = "J20" ; -#NET "GMII_TX_CLK" LOC = "P25" ; - -#NET "GMII_RX_CLK" LOC = "P21" ; -#NET "GMII_RXD<7>" LOC = "G22" ; -#NET "GMII_RXD<6>" LOC = "K19" ; -#NET "GMII_RXD<5>" LOC = "K18" ; -#NET "GMII_RXD<4>" LOC = "E24" ; -#NET "GMII_RXD<3>" LOC = "F23" ; -#NET "GMII_RXD<2>" LOC = "L18" ; -#NET "GMII_RXD<1>" LOC = "L17" ; -#NET "GMII_RXD<0>" LOC = "F25" ; -#NET "GMII_RX_DV" LOC = "F24" ; -#NET "GMII_RX_ER" LOC = "L20" ; -#NET "GMII_CRS" LOC = "K20" ; -#NET "GMII_COL" LOC = "G23" ; - -#NET "PHY_INTn" LOC = "L22" ; -#NET "MDIO" LOC = "K21" ; -#NET "MDC" LOC = "J23" ; -#NET "PHY_RESETn" LOC = "J22" ; -NET "ETH_LED" LOC = "H20" ; - -## MIMO Interface -#NET "exp_time_out_p" LOC = "Y14" ; -#NET "exp_time_out_n" LOC = "AA14" ; -#NET "exp_time_in_p" LOC = "N18" ; -#NET "exp_time_in_n" LOC = "N17" ; -#NET "exp_user_out_p" LOC = "AF14" ; -#NET "exp_user_out_n" LOC = "AE14" ; -#NET "exp_user_in_p" LOC = "L24" ; -#NET "exp_user_in_n" LOC = "M23" ; - -## SERDES -#NET "ser_enable" LOC = "R20" ; -#NET "ser_prbsen" LOC = "U23" ; -#NET "ser_loopen" LOC = "R19" ; -#NET "ser_rx_en" LOC = "Y21" ; -#NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK -#NET "ser_t<15>" LOC = "V23" ; -#NET "ser_t<14>" LOC = "U22" ; -#NET "ser_t<13>" LOC = "V24" ; -#NET "ser_t<12>" LOC = "V25" ; -#NET "ser_t<11>" LOC = "W23" ; -#NET "ser_t<10>" LOC = "V22" ; -#NET "ser_t<9>" LOC = "T18" ; -#NET "ser_t<8>" LOC = "T17" ; -#NET "ser_t<7>" LOC = "Y24" ; -#NET "ser_t<6>" LOC = "Y25" ; -#NET "ser_t<5>" LOC = "U21" ; -#NET "ser_t<4>" LOC = "T20" ; -#NET "ser_t<3>" LOC = "Y22" ; -#NET "ser_t<2>" LOC = "Y23" ; -#NET "ser_t<1>" LOC = "U19" ; -#NET "ser_t<0>" LOC = "U18" ; -#NET "ser_tkmsb" LOC = "AA24" ; -#NET "ser_tklsb" LOC = "AA25" ; -#NET "ser_rx_clk" LOC = "P18" ; -#NET "ser_r<15>" LOC = "V21" ; -#NET "ser_r<14>" LOC = "U20" ; -#NET "ser_r<13>" LOC = "AA22" ; -#NET "ser_r<12>" LOC = "AA23" ; -#NET "ser_r<11>" LOC = "V18" ; -#NET "ser_r<10>" LOC = "V19" ; -#NET "ser_r<9>" LOC = "AB23" ; -#NET "ser_r<8>" LOC = "AC26" ; -#NET "ser_r<7>" LOC = "AB26" ; -#NET "ser_r<6>" LOC = "AD26" ; -#NET "ser_r<5>" LOC = "AC25" ; -#NET "ser_r<4>" LOC = "W20" ; -#NET "ser_r<3>" LOC = "W21" ; -#NET "ser_r<2>" LOC = "AC23" ; -#NET "ser_r<1>" LOC = "AC24" ; -#NET "ser_r<0>" LOC = "AE26" ; -#NET "ser_rkmsb" LOC = "AD25" ; -#NET "ser_rklsb" LOC = "Y20" ; - -## SRAM -#NET "RAM_D<35>" LOC = "K16" ; -#NET "RAM_D<34>" LOC = "D20" ; -#NET "RAM_D<33>" LOC = "C20" ; -#NET "RAM_D<32>" LOC = "E21" ; -#NET "RAM_D<31>" LOC = "D21" ; -#NET "RAM_D<30>" LOC = "C21" ; -#NET "RAM_D<29>" LOC = "B21" ; -#NET "RAM_D<28>" LOC = "H17" ; -#NET "RAM_D<27>" LOC = "G17" ; -#NET "RAM_D<26>" LOC = "B23" ; -#NET "RAM_D<25>" LOC = "A22" ; -#NET "RAM_D<24>" LOC = "D23" ; -#NET "RAM_D<23>" LOC = "C23" ; -#NET "RAM_D<22>" LOC = "D22" ; -#NET "RAM_D<21>" LOC = "C22" ; -#NET "RAM_D<20>" LOC = "F19" ; -#NET "RAM_D<19>" LOC = "G20" ; -#NET "RAM_D<18>" LOC = "F20" ; -#NET "RAM_D<17>" LOC = "F7" ; -#NET "RAM_D<16>" LOC = "E7" ; -#NET "RAM_D<15>" LOC = "G9" ; -#NET "RAM_D<14>" LOC = "H9" ; -#NET "RAM_D<13>" LOC = "G10" ; -#NET "RAM_D<12>" LOC = "H10" ; -#NET "RAM_D<11>" LOC = "A4" ; -#NET "RAM_D<10>" LOC = "B4" ; -#NET "RAM_D<9>" LOC = "C5" ; -#NET "RAM_D<8>" LOC = "D6" ; -#NET "RAM_D<7>" LOC = "J11" ; -#NET "RAM_D<6>" LOC = "K11" ; -#NET "RAM_D<5>" LOC = "B7" ; -#NET "RAM_D<4>" LOC = "C7" ; -#NET "RAM_D<3>" LOC = "B6" ; -#NET "RAM_D<2>" LOC = "C6" ; -#NET "RAM_D<1>" LOC = "C8" ; -#NET "RAM_D<0>" LOC = "D8" ; -#NET "RAM_A<0>" LOC = "C11" ; -#NET "RAM_A<1>" LOC = "E12" ; -#NET "RAM_A<2>" LOC = "F12" ; -#NET "RAM_A<3>" LOC = "D13" ; -#NET "RAM_A<4>" LOC = "C12" ; -#NET "RAM_A<5>" LOC = "A12" ; -#NET "RAM_A<6>" LOC = "B12" ; -#NET "RAM_A<7>" LOC = "E14" ; -#NET "RAM_A<8>" LOC = "F14" ; -#NET "RAM_A<9>" LOC = "B15" ; -#NET "RAM_A<10>" LOC = "A15" ; -#NET "RAM_A<11>" LOC = "D16" ; -#NET "RAM_A<12>" LOC = "C15" ; -#NET "RAM_A<13>" LOC = "D17" ; -#NET "RAM_A<14>" LOC = "C16" ; -#NET "RAM_A<15>" LOC = "F15" ; -#NET "RAM_A<16>" LOC = "C17" ; -#NET "RAM_A<17>" LOC = "B17" ; -#NET "RAM_A<18>" LOC = "B18" ; -#NET "RAM_A<19>" LOC = "A18" ; -#NET "RAM_A<20>" LOC = "D18" ; -#NET "RAM_BWn<3>" LOC = "D9" ; -#NET "RAM_BWn<2>" LOC = "A9" ; -#NET "RAM_BWn<1>" LOC = "B9" ; -#NET "RAM_BWn<0>" LOC = "G12" ; -#NET "RAM_ZZ" LOC = "J12" ; -#NET "RAM_LDn" LOC = "H12" ; -#NET "RAM_OEn" LOC = "C10" ; -#NET "RAM_WEn" LOC = "D10" ; -#NET "RAM_CENn" LOC = "B10" ; -#NET "RAM_CLK" LOC = "A10" ; - -## SPI Flash -#NET "flash_miso" LOC = "AF24" ; -#NET "flash_clk" LOC = "AE24" ; -#NET "flash_mosi" LOC = "AB15" ; -#NET "flash_cs" LOC = "AA7" ; - -## MISC FPGA, unused for now -##NET "PROG_B" LOC = "A2" ; -##NET "PUDC_B" LOC = "G8" ; -##NET "DONE" LOC = "AB21" ; -##NET "INIT_B" LOC = "AA15" ; - - -##NET "unnamed_net19" LOC = "AE9" ; # VS1 -##NET "unnamed_net18" LOC = "AF9" ; # VS0 -##NET "unnamed_net17" LOC = "AA12" ; # VS2 -##NET "unnamed_net16" LOC = "Y7" ; # M2 -##NET "unnamed_net15" LOC = "AC4" ; # M1 -##NET "unnamed_net14" LOC = "AD4" ; # M0 -##NET "unnamed_net13" LOC = "D4" ; # TMS -##NET "unnamed_net12" LOC = "E23" ; # TDO -##NET "unnamed_net11" LOC = "G7" ; # TDI -##NET "unnamed_net10" LOC = "A25" ; # TCK -##NET "unnamed_net20" LOC = "V20" ; # SUSPEND diff --git a/usrp2/top/single_u2_sim/single_u2_sim.v b/usrp2/top/single_u2_sim/single_u2_sim.v deleted file mode 100644 index 2a7b24849..000000000 --- a/usrp2/top/single_u2_sim/single_u2_sim.v +++ /dev/null @@ -1,324 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module single_u2_sim(); - // Misc, debug - wire [7:0] leds; - wire [31:0] debug; - wire [1:0] debug_clk; - - // Expansion - wire exp_pps_in; - wire exp_pps_out; - - // GMII - // GMII-CTRL - wire GMII_COL; - wire GMII_CRS; - - // GMII-TX - wire [7:0] GMII_TXD; - wire GMII_TX_EN; - wire GMII_TX_ER; - wire GMII_GTX_CLK; - wire GMII_TX_CLK; // 100mbps clk - - // GMII-RX - wire [7:0] GMII_RXD; - wire GMII_RX_CLK; - wire GMII_RX_DV; - wire GMII_RX_ER; - - // GMII-Management - wire MDIO; - wire MDC; - wire PHY_INTn; // open drain - wire PHY_RESETn; - wire PHY_CLK; // possibly use on-board osc - - // RAM - wire [17:0] RAM_D; - wire [18:0] RAM_A; - wire RAM_CE1n; - wire RAM_CENn; - wire RAM_CLK; - wire RAM_WEn; - wire RAM_OEn; - wire RAM_LDn; - - // SERDES - wire ser_enable; - wire ser_prbsen; - wire ser_loopen; - wire ser_rx_en; - - wire ser_tx_clk; - wire [15:0] ser_t; - wire ser_tklsb; - wire ser_tkmsb; - - wire ser_rx_clk; - wire [15:0] ser_r; - wire ser_rklsb; - wire ser_rkmsb; - - // CPLD interface - wire cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done; - - // ADC - wire [13:0] adc_a; - wire adc_ovf_a; - wire adc_on_a, adc_oe_a; - - wire [13:0] adc_b; - wire adc_ovf_b; - wire adc_on_b, adc_oe_b; - - // DAC - wire [15:0] dac_a; - wire [15:0] dac_b; - - // I2C - wire SCL; - wire SDA; - - // Clock Gen Control - wire [1:0] clk_en; - wire [1:0] clk_sel; - wire clk_func; // FIXME is an input to control the 9510 - wire clk_status; - - // Clocks - reg clk_fpga; - reg clk_to_mac; - wire pps_in; - - // Generic SPI - wire sclk, mosi, miso; - wire sen_clk; - wire sen_dac; - wire sen_tx_db; - wire sen_tx_adc; - wire sen_tx_dac; - wire sen_rx_db; - wire sen_rx_adc; - wire sen_rx_dac; - - // GPIO to DBoards - wire [15:0] io_tx; - wire [15:0] io_rx; - - wire wb_clk; - wire start, clock_ready; - - reg aux_clk; - - initial aux_clk= 1'b0; - always #6 aux_clk = ~aux_clk; - - initial clk_fpga = 1'bx; - initial #3007 clk_fpga = 1'b0; - always #5 clk_fpga = ~clk_fpga; - - initial clk_to_mac = 0; - always #4 clk_to_mac = ~clk_to_mac; - - wire div_clk, dsp_clk; - reg [7:0] div_ctr = 0; - - assign dsp_clk = clock_ready ? clk_fpga : aux_clk; - assign wb_clk = div_clk; - -`define CLK_DIV_2 1 -//`define CLK_DIV_3 - -`ifdef CLK_DIV_2 - localparam clock_divider = 4'd2; - always @(posedge dsp_clk) - div_ctr <= div_ctr + 1; - assign div_clk = div_ctr[0]; -`endif - -`ifdef CLK_DIV_3 - localparam clock_divider = 2; - always @(posedge dsp_clk or negedge dsp_clk) - if(div_ctr == 5) - div_ctr <= 0; - else - div_ctr <= div_ctr + 1; - assign div_clk = ((div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2)); -`endif - - initial - $monitor($time, ,clock_ready); - - always #1000000 $monitor("Time in ns ",$time); - - initial begin - @(negedge cpld_done); - @(posedge cpld_done); - $dumpfile("single_u2_sim.lxt"); - $dumpvars(0,single_u2_sim); - end - - initial #10000000 $finish; - - cpld_model - cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done), - .dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached)); - - serdes_model serdes_model - (.ser_tx_clk(ser_tx_clk), .ser_tkmsb(ser_tkmsb), .ser_tklsb(ser_tklsb), .ser_t(ser_t), - .ser_rx_clk(ser_rx_clk), .ser_rkmsb(ser_rkmsb), .ser_rklsb(ser_rklsb), .ser_r(ser_r), - .even(0),.error(0) ); - - adc_model adc_model - (.clk(dsp_clk),.rst(0), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_on_a(adc_on_a),.adc_oe_a(adc_oe_a), - .adc_b(adc_b),.adc_ovf_b(adc_ovf_b),.adc_on_b(adc_on_b),.adc_oe_b(adc_oe_b) ); - - wire [2:0] speed; - phy_sim phy_model - (.Gtx_clk(GMII_GTX_CLK), . Rx_clk(GMII_RX_CLK), .Tx_clk(GMII_TX_CLK), - .Tx_er(GMII_TX_ER), .Tx_en(GMII_TX_EN), .Txd(GMII_TXD), - .Rx_er(GMII_RX_ER), .Rx_dv(GMII_RX_DV), .Rxd(GMII_RXD), - .Crs(GMII_CRS), .Col(GMII_COL), - .Speed(speed), .Done(0) ); - pullup p3(MDIO); - - miim_model miim_model - (.mdc_i(MDC),.mdio(MDIO),.phy_resetn_i(PHY_RESETn),.phy_clk_i(PHY_CLK), - .phy_intn_o(PHY_INTn),.speed_o(speed) ); - - xlnx_glbl glbl (.GSR(),.GTS()); - - wire RAM_MODE = 1'b0; - cy1356 ram_model(.d(RAM_D),.clk(RAM_CLK),.a(RAM_A), - .bws(2'b00),.we_b(RAM_WEn),.adv_lb(RAM_LDn), - .ce1b(RAM_CE1n),.ce2(1'b1),.ce3b(1'b0), - .oeb(RAM_OEn),.cenb(RAM_CENn),.mode(RAM_MODE) ); - - M24LC024B eeprom_model(.A0(0),.A1(0),.A2(0),.WP(0), - .SDA(SDA),.SCL(SCL),.RESET(0)); - - wire scl_pad_i, scl_pad_o, scl_pad_oen_o; - wire sda_pad_i, sda_pad_o, sda_pad_oen_o; - - pullup p1(SCL); - pullup p2(SDA); - - assign scl_pad_i = SCL; - assign sda_pad_i = SDA; - - assign SCL = scl_pad_oen_o ? 1'bz : scl_pad_o; - assign SDA = sda_pad_oen_o ? 1'bz : sda_pad_o; - - // printf output - wire uart_baud_o, uart_tx_o, uart_rx_i; - assign uart_rx_i = 1'b1; - - uart_rx uart_rx(.baudclk(uart_baud_o),.rxd(uart_tx_o)); - - // End the simulation - always @(posedge wb_clk) - if((u2_core.m0_we == 1'd1)&&(u2_core.m0_adr == 16'hC2F0)) - begin - $display($time, "Finish called.",); - $finish; - end - - u2_core #(.RAM_SIZE(32768)) - u2_core(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), - .leds (leds), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_pps_in), - .exp_pps_out (exp_pps_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD[7:0]), - .GMII_TX_EN (GMII_TX_EN), - .GMII_TX_ER (GMII_TX_ER), - .GMII_GTX_CLK (GMII_GTX_CLK), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk), - .ser_t (ser_t[15:0]), - .ser_tklsb (ser_tklsb), - .ser_tkmsb (ser_tkmsb), - .ser_rx_clk (ser_rx_clk), - .ser_r (ser_r[15:0]), - .ser_rklsb (ser_rklsb), - .ser_rkmsb (ser_rkmsb), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .cpld_init_b (1), - .por (0), - .adc_a (adc_a[13:0]), - .adc_ovf_a (adc_ovf_a), - .adc_on_a (adc_on_a), - .adc_oe_a (adc_oe_a), - .adc_b (adc_b[13:0]), - .adc_ovf_b (adc_ovf_b), - .adc_on_b (adc_on_b), - .adc_oe_b (adc_oe_b), - .dac_a (dac_a[15:0]), - .dac_b (dac_b[15:0]), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D (RAM_D), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - .RAM_CLK (RAM_CLK), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (uart_tx_o), - .uart_rx_i (uart_rx_i), - .uart_baud_o (uart_baud_o), - .sim_mode (1'b1), - .clock_divider (clock_divider) - ); - -endmodule // single_u2_sim diff --git a/usrp2/top/u1e/.gitignore b/usrp2/top/u1e/.gitignore deleted file mode 100644 index 8d872713e..000000000 --- a/usrp2/top/u1e/.gitignore +++ /dev/null @@ -1,6 +0,0 @@ -*~ -build -*.log -*.cmd -tb_u1e -*.lxt diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile deleted file mode 100644 index 5d721979b..000000000 --- a/usrp2/top/u1e/Makefile +++ /dev/null @@ -1,100 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = u1e -BUILD_DIR = $(abspath build$(ISE)) - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../gpmc/Makefile.srcs - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd1800a \ -package cs484 \ -speed -4 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -u1e_core.v \ -u1e.v \ -u1e.ucf \ -timing.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ -$(GPMC_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 \ -"Unused IOB Pins" "Pull Up" - -SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/u1e/README b/usrp2/top/u1e/README deleted file mode 100644 index 14c7a4955..000000000 --- a/usrp2/top/u1e/README +++ /dev/null @@ -1,4 +0,0 @@ - -make clean -make sim -./tb_u1e -lxt2 diff --git a/usrp2/top/u1e/cmdfile b/usrp2/top/u1e/cmdfile deleted file mode 100644 index 291c723b8..000000000 --- a/usrp2/top/u1e/cmdfile +++ /dev/null @@ -1,20 +0,0 @@ - -# My stuff --y . --y ../../control_lib --y ../../control_lib/newfifo --y ../../sdr_lib --y ../../timing --y ../../coregen --y ../../gpmc - -# Models --y ../../models --y /opt/Xilinx/10.1/ISE/verilog/src/unisims - -# Open Cores --y ../../opencores/spi/rtl/verilog -+incdir+../../opencores/spi/rtl/verilog --y ../../opencores/i2c/rtl/verilog -+incdir+../../opencores/i2c/rtl/verilog - diff --git a/usrp2/top/u1e/core_compile b/usrp2/top/u1e/core_compile deleted file mode 100755 index dc0cd081e..000000000 --- a/usrp2/top/u1e/core_compile +++ /dev/null @@ -1,3 +0,0 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models - - diff --git a/usrp2/top/u1e/make.sim b/usrp2/top/u1e/make.sim deleted file mode 100644 index 1c163884c..000000000 --- a/usrp2/top/u1e/make.sim +++ /dev/null @@ -1,7 +0,0 @@ -all: sim - -sim: - iverilog -Wimplicit -Wportbind -c cmdfile tb_u1e.v -o tb_u1e - -clean: - rm -f tb_u1e *.vcd *.lxt a.out diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v deleted file mode 100644 index 5fc8134fb..000000000 --- a/usrp2/top/u1e/tb_u1e.v +++ /dev/null @@ -1,41 +0,0 @@ -`timescale 1ps / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module tb_u1e(); - - wire [2:0] debug_led; - wire [31:0] debug; - wire [1:0] debug_clk; - - xlnx_glbl glbl (.GSR(),.GTS()); - - initial begin - $dumpfile("tb_u1e.lxt"); - $dumpvars(0,tb_u1e); - end - - // GPMC - wire EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE; - wire [15:0] EM_D; - wire [10:1] EM_A; - wire [1:0] EM_NBE; - - reg clk_fpga = 0, rst_fpga = 1; - always #15625 clk_fpga = ~clk_fpga; - - initial #200000 - @(posedge clk_fpga) - rst_fpga <= 0; - - u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(rst_fpga), - .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), - .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), - .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); - - gpmc_model_async gpmc_model_async - (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), - .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); - -endmodule // tb_u1e diff --git a/usrp2/top/u1e/timing.ucf b/usrp2/top/u1e/timing.ucf deleted file mode 100644 index 8df28c9d3..000000000 --- a/usrp2/top/u1e/timing.ucf +++ /dev/null @@ -1,13 +0,0 @@ - -NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; -TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; - - - - -#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; -#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; -#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; - -#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; -#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf deleted file mode 100644 index 0c487a601..000000000 --- a/usrp2/top/u1e/u1e.ucf +++ /dev/null @@ -1,259 +0,0 @@ - -NET "CLK_FPGA_P" LOC = "Y11" ; -NET "CLK_FPGA_N" LOC = "Y10" ; - -## GPMC -NET "EM_D<15>" LOC = "D13" ; -NET "EM_D<14>" LOC = "D15" ; -NET "EM_D<13>" LOC = "C16" ; -NET "EM_D<12>" LOC = "B20" ; -NET "EM_D<11>" LOC = "A19" ; -NET "EM_D<10>" LOC = "A17" ; -NET "EM_D<9>" LOC = "E15" ; -NET "EM_D<8>" LOC = "F15" ; -NET "EM_D<7>" LOC = "E16" ; -NET "EM_D<6>" LOC = "F16" ; -NET "EM_D<5>" LOC = "B17" ; -NET "EM_D<4>" LOC = "C17" ; -NET "EM_D<3>" LOC = "B19" ; -NET "EM_D<2>" LOC = "D19" ; -NET "EM_D<1>" LOC = "C19" ; -NET "EM_D<0>" LOC = "A20" ; - -NET "EM_A<10>" LOC = "C14" ; -NET "EM_A<9>" LOC = "C10" ; -NET "EM_A<8>" LOC = "C5" ; -NET "EM_A<7>" LOC = "A18" ; -NET "EM_A<6>" LOC = "A15" ; -NET "EM_A<5>" LOC = "A12" ; -NET "EM_A<4>" LOC = "A10" ; -NET "EM_A<3>" LOC = "E7" ; -NET "EM_A<2>" LOC = "A7" ; -NET "EM_A<1>" LOC = "C15" ; - -NET "EM_NCS6" LOC = "E17" ; -NET "EM_NCS5" LOC = "E10" ; -NET "EM_NCS4" LOC = "E6" ; -#NET "EM_NCS1" LOC = "D18" ; -#NET "EM_NCS0" LOC = "D17" ; - -NET "EM_CLK" LOC = "F11" ; -NET "EM_WAIT0" LOC = "F14" ; -NET "EM_NBE<1>" LOC = "D14" ; -NET "EM_NBE<0>" LOC = "A13" ; -NET "EM_NWE" LOC = "B13" ; -NET "EM_NOE" LOC = "A14" ; -#NET "EM_NADV_ALE" LOC = "B15" ; -#NET "EM_NWP" LOC = "F13" ; - -## Overo GPIO -NET "overo_gpio0" LOC = "F9" ; # MISC GPIO for debug -NET "overo_gpio14" LOC = "C4" ; # MISC GPIO for debug -NET "overo_gpio21" LOC = "D5" ; # MISC GPIO for debug -NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug -NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug -NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug -NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug - -NET "overo_gpio127" LOC = "C8" ; # Changed name to gpio10 -NET "overo_gpio128" LOC = "G8" ; # Changed name to gpio186 - -NET "overo_gpio144" LOC = "A5" ; # tx_have_space -NET "overo_gpio145" LOC = "C7" ; # tx_underrun -NET "overo_gpio146" LOC = "A6" ; # rx_have_data -NET "overo_gpio147" LOC = "B6" ; # rx_overrun -NET "overo_gpio163" LOC = "D7" ; # MISC GPIO for debug -NET "overo_gpio170" LOC = "E8" ; # MISC GPIO for debug -NET "overo_gpio176" LOC = "B4" ; # MISC GPIO for debug - -## Overo UART -#NET "overo_txd1" LOC = "C6" ; -#NET "overo_rxd1" LOC = "D6" ; - -## FTDI UART to USB converter -NET "FPGA_TXD" LOC = "G19" ; -NET "FPGA_RXD" LOC = "F20" ; - -#NET "SYSEN" LOC = "C11" ; - -## I2C -NET "db_scl" LOC = "F19" ; -NET "db_sda" LOC = "F18" ; - -## SPI -### DBoard SPI -NET "db_sclk_rx" LOC = "D21" ; -NET "db_miso_rx" LOC = "D22" ; -NET "db_mosi_rx" LOC = "D20" ; -NET "db_sen_rx" LOC = "E19" ; -NET "db_sclk_tx" LOC = "F21" ; -NET "db_miso_tx" LOC = "E20" ; -NET "db_mosi_tx" LOC = "G17" ; -NET "db_sen_tx" LOC = "G18" ; - -### AD9862 SPI and aux SPI Interfaces -#NET "aux_sdi_codec" LOC = "G3" ; -#NET "aux_sdo_codec" LOC = "F3" ; -#NET "aux_sclk_codec" LOC = "C1" ; -NET "sen_codec" LOC = "F5" |IOSTANDARD = LVCMOS33; -NET "mosi_codec" LOC = "F4" |IOSTANDARD = LVCMOS33; -NET "miso_codec" LOC = "H4" ; -NET "sclk_codec" LOC = "H3" |IOSTANDARD = LVCMOS33; - -### Clock Gen SPI -NET "cgen_miso" LOC = "F22" ; -NET "cgen_mosi" LOC = "E22" ; -NET "cgen_sclk" LOC = "J19" ; -NET "cgen_sen_b" LOC = "H20" ; - -## Clock gen control -NET "cgen_st_status" LOC = "P20" ; -NET "cgen_st_ld" LOC = "R17" ; -NET "cgen_st_refmon" LOC = "P17" ; -NET "cgen_sync_b" LOC = "U18" ; -NET "cgen_ref_sel" LOC = "U19" ; - -## Debug pins -NET "debug_led<3>" LOC = "Y15" ; -NET "debug_led<2>" LOC = "K16" ; -NET "debug_led<1>" LOC = "J17" ; -NET "debug_led<0>" LOC = "H22" ; -NET "debug<0>" LOC = "G22" ; -NET "debug<1>" LOC = "H17" ; -NET "debug<2>" LOC = "H18" ; -NET "debug<3>" LOC = "K20" ; -NET "debug<4>" LOC = "J20" ; -NET "debug<5>" LOC = "K19" ; -NET "debug<6>" LOC = "K18" ; -NET "debug<7>" LOC = "L22" ; -NET "debug<8>" LOC = "K22" ; -NET "debug<9>" LOC = "N22" ; -NET "debug<10>" LOC = "M22" ; -NET "debug<11>" LOC = "N20" ; -NET "debug<12>" LOC = "N19" ; -NET "debug<13>" LOC = "R22" ; -NET "debug<14>" LOC = "P22" ; -NET "debug<15>" LOC = "N17" ; -NET "debug<16>" LOC = "P16" ; -NET "debug<17>" LOC = "U22" ; -NET "debug<18>" LOC = "P19" ; -NET "debug<19>" LOC = "R18" ; -NET "debug<20>" LOC = "U20" ; -NET "debug<21>" LOC = "T20" ; -NET "debug<22>" LOC = "R19" ; -NET "debug<23>" LOC = "R20" ; -NET "debug<24>" LOC = "W22" ; -NET "debug<25>" LOC = "Y22" ; -NET "debug<26>" LOC = "T18" ; -NET "debug<27>" LOC = "T17" ; -NET "debug<28>" LOC = "W19" ; -NET "debug<29>" LOC = "V20" ; -NET "debug<30>" LOC = "Y21" ; -NET "debug<31>" LOC = "AA22" ; -NET "debug_clk<0>" LOC = "N18" ; -NET "debug_clk<1>" LOC = "M17" ; - -NET "debug_pb" LOC = "C22" ; - -#NET "reset_codec" LOC = "C2" ; - -NET "RXSYNC" LOC = "F2" ; -NET "DB<11>" LOC = "G6" ; -NET "DB<10>" LOC = "G5" ; -NET "DB<9>" LOC = "E4" ; -NET "DB<8>" LOC = "E3" ; -NET "DB<7>" LOC = "H6" ; -NET "DB<6>" LOC = "H5" ; -NET "DB<5>" LOC = "H1" ; -NET "DB<4>" LOC = "G1" ; -NET "DB<3>" LOC = "K5" ; -NET "DB<2>" LOC = "K4" ; -NET "DB<1>" LOC = "H2" ; -NET "DB<0>" LOC = "L5" ; - -NET "DA<11>" LOC = "K6" ; -NET "DA<10>" LOC = "K3" ; -NET "DA<9>" LOC = "K2" ; -NET "DA<8>" LOC = "N1" ; -NET "DA<7>" LOC = "N5" ; -NET "DA<6>" LOC = "N6" ; -NET "DA<5>" LOC = "P2" ; -NET "DA<4>" LOC = "P1" ; -NET "DA<3>" LOC = "R6" ; -NET "DA<2>" LOC = "P6" ; -NET "DA<1>" LOC = "R1" ; -NET "DA<0>" LOC = "R2" ; - -NET "TX<13>" LOC = "T6" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<12>" LOC = "U1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<11>" LOC = "T1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<10>" LOC = "R5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<9>" LOC = "V1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<8>" LOC = "U2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<7>" LOC = "T4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<6>" LOC = "R3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<5>" LOC = "W1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<4>" LOC = "Y1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<3>" LOC = "V3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<2>" LOC = "V4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<1>" LOC = "W2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TX<0>" LOC = "W3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TXSYNC" LOC = "U5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; -NET "TXBLANK" LOC = "U4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; - -NET "PPS_IN" LOC = "M5" ; - -NET "io_tx<0>" LOC = "AB20" ; -NET "io_tx<1>" LOC = "Y17" ; -NET "io_tx<2>" LOC = "Y16" ; -NET "io_tx<3>" LOC = "U16" ; -NET "io_tx<4>" LOC = "V16" ; -NET "io_tx<5>" LOC = "AB19" ; -NET "io_tx<6>" LOC = "AA19" ; -NET "io_tx<7>" LOC = "U14" ; -NET "io_tx<8>" LOC = "U15" ; -NET "io_tx<9>" LOC = "AB17" ; -NET "io_tx<10>" LOC = "AB18" ; -NET "io_tx<11>" LOC = "Y13" ; -NET "io_tx<12>" LOC = "W14" ; -NET "io_tx<13>" LOC = "U13" ; -NET "io_tx<14>" LOC = "AA15" ; -NET "io_tx<15>" LOC = "AB14" ; - -NET "io_rx<0>" LOC = "Y8" ; -NET "io_rx<1>" LOC = "Y9" ; -NET "io_rx<2>" LOC = "V7" ; -NET "io_rx<3>" LOC = "U8" ; -NET "io_rx<4>" LOC = "V10" ; -NET "io_rx<5>" LOC = "U9" ; -NET "io_rx<6>" LOC = "AB7" ; -NET "io_rx<7>" LOC = "AA8" ; -NET "io_rx<8>" LOC = "W8" ; -NET "io_rx<9>" LOC = "V8" ; -NET "io_rx<10>" LOC = "AB5" ; -NET "io_rx<11>" LOC = "AB6" ; -NET "io_rx<12>" LOC = "AB4" ; -NET "io_rx<13>" LOC = "AA4" ; -NET "io_rx<14>" LOC = "W5" ; -NET "io_rx<15>" LOC = "Y4" ; - -#NET "CLKOUT2_CODEC" LOC = "U12" ; -#NET "CLKOUT1_CODEC" LOC = "V12" ; - -## FPGA Config Pins -#NET "fpga_cfg_prog_b" LOC = "A2" ; -#NET "fpga_cfg_done" LOC = "AB21" ; -#NET "fpga_cfg_din" LOC = "W17" ; -#NET "fpga_cfg_cclk" LOC = "V17" ; -#NET "fpga_cfg_init_b" LOC = "W15" ; - -## Unused -#NET "unnamed_net53" LOC = "B1" ; # TMS -#NET "unnamed_net52" LOC = "B22" ; # TDO -#NET "unnamed_net51" LOC = "D2" ; # TDI -#NET "unnamed_net50" LOC = "A21" ; # TCK -#NET "unnamed_net59" LOC = "F7" ; # PUDC_B -#NET "unnamed_net58" LOC = "V6" ; # M2 -#NET "unnamed_net57" LOC = "AA3" ; # M1 -#NET "unnamed_net56" LOC = "AB3" ; # M0 -#NET "GND" LOC = "V19" ; # Suspend, unused diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v deleted file mode 100644 index 445b14a03..000000000 --- a/usrp2/top/u1e/u1e.v +++ /dev/null @@ -1,141 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module u1e - (input CLK_FPGA_P, input CLK_FPGA_N, // Diff - output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - input debug_pb, output FPGA_TXD, input FPGA_RXD, - - // GPMC - input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, - input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, - input EM_NWE, input EM_NOE, - - inout db_sda, inout db_scl, // I2C - - output db_sclk_tx, output db_sen_tx, output db_mosi_tx, input db_miso_tx, // DB TX SPI - output db_sclk_rx, output db_sen_rx, output db_mosi_rx, input db_miso_rx, // DB TX SPI - output sclk_codec, output sen_codec, output mosi_codec, input miso_codec, // AD9862 main SPI - output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso, // Clock gen SPI - - input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, - - output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls - input overo_gpio0, input overo_gpio14, input overo_gpio21, input overo_gpio22, // Misc GPIO - input overo_gpio23, input overo_gpio64, input overo_gpio65, input overo_gpio127, // Misc GPIO - input overo_gpio128, input overo_gpio163, input overo_gpio170, input overo_gpio176, // Misc GPIO - - inout [15:0] io_tx, inout [15:0] io_rx, - - output [13:0] TX, output TXSYNC, output TXBLANK, - input [11:0] DA, input [11:0] DB, input RXSYNC, - - input PPS_IN - ); - - // ///////////////////////////////////////////////////////////////////////// - // Clocking - wire clk_fpga, clk_fpga_in; - - IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) - clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - - wire clk_2x, dcm_rst, dcm_locked, clk_fb; - DCM #(.CLK_FEEDBACK ( "1X" ), - .CLKDV_DIVIDE ( 2 ), - .CLKFX_DIVIDE ( 2 ), - .CLKFX_MULTIPLY ( 2 ), - .CLKIN_DIVIDE_BY_2 ( "FALSE" ), - .CLKIN_PERIOD ( 15.625 ), - .CLKOUT_PHASE_SHIFT ( "NONE" ), - .DESKEW_ADJUST ( "SYSTEM_SYNCHRONOUS" ), - .DFS_FREQUENCY_MODE ( "LOW" ), - .DLL_FREQUENCY_MODE ( "LOW" ), - .DUTY_CYCLE_CORRECTION ( "TRUE" ), - .FACTORY_JF ( 16'h8080 ), - .PHASE_SHIFT ( 0 ), - .STARTUP_WAIT ( "FALSE" )) - clk_doubler (.CLKFB(clk_fb), .CLKIN(clk_fpga_in), .RST(dcm_rst), - .DSSEN(0), .PSCLK(0), .PSEN(0), .PSINCDEC(0), .PSDONE(), - .CLKDV(), .CLKFX(), .CLKFX180(), - .CLK2X(), .CLK2X180(), - .CLK0(clk_fb), .CLK90(clk_fpga), .CLK180(), .CLK270(), - .LOCKED(dcm_locked), .STATUS()); - - // ///////////////////////////////////////////////////////////////////////// - // SPI - wire mosi, sclk, miso; - assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0; - assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0; - assign { sclk_codec, mosi_codec } = ~sen_codec ? {sclk,mosi} : 2'b0; - assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0; - assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) | - (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso); - - // ///////////////////////////////////////////////////////////////////////// - // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL - - assign TXBLANK = 0; - wire [13:0] tx_i, tx_q; - - reg[13:0] delay_q; - always @(posedge clk_fpga) - delay_q <= tx_q; - - genvar i; - generate - for(i=0;i<14;i=i+1) - begin : gen_dacout - ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" - .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 - .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset - ODDR2_inst (.Q(TX[i]), // 1-bit DDR output data - .C0(clk_fpga), // 1-bit clock input - .C1(~clk_fpga), // 1-bit clock input - .CE(1'b1), // 1-bit clock enable input - .D0(tx_i[i]), // 1-bit data input (associated with C0) - .D1(delay_q[i]), // 1-bit data input (associated with C1) - .R(1'b0), // 1-bit reset input - .S(1'b0)); // 1-bit set input - end // block: gen_dacout - endgenerate - ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" - .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 - .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset - ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data - .C0(clk_fpga), // 1-bit clock input - .C1(~clk_fpga), // 1-bit clock input - .CE(1'b1), // 1-bit clock enable input - .D0(1'b0), // 1-bit data input (associated with C0) - .D1(1'b1), // 1-bit data input (associated with C1) - .R(1'b0), // 1-bit reset input - .S(1'b0)); // 1-bit set input - - // ///////////////////////////////////////////////////////////////////////// - // Main U1E Core - u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb), - .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), - .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), - .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS5(EM_NCS5), - .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), - .db_sda(db_sda), .db_scl(db_scl), - .sclk(sclk), .sen({cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso), - .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), - .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel), - .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), - .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), - .io_tx(io_tx), .io_rx(io_rx), - .tx_i(tx_i), .tx_q(tx_q), - .rx_i(DA), .rx_q(DB), - .misc_gpio( {{overo_gpio128,overo_gpio163,overo_gpio170,overo_gpio176}, - {overo_gpio0,overo_gpio14,overo_gpio21,overo_gpio22}, - {overo_gpio23,overo_gpio64,overo_gpio65,overo_gpio127}}), - .pps_in(PPS_IN) ); - - // ///////////////////////////////////////////////////////////////////////// - // Local Debug - // assign debug_clk = {clk_fpga, clk_2x }; - // assign debug = { TXSYNC, TXBLANK, TX }; - -endmodule // u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v deleted file mode 100644 index d10a3ab30..000000000 --- a/usrp2/top/u1e/u1e_core.v +++ /dev/null @@ -1,421 +0,0 @@ - - -module u1e_core - (input clk_fpga, input rst_fpga, - output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - output debug_txd, input debug_rxd, - - // GPMC - input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, - input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, - input EM_NWE, input EM_NOE, - - inout db_sda, inout db_scl, - output sclk, output [15:0] sen, output mosi, input miso, - - input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, - output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, - inout [15:0] io_tx, inout [15:0] io_rx, - output [13:0] tx_i, output [13:0] tx_q, - input [11:0] rx_i, input [11:0] rx_q, - - input [11:0] misc_gpio, input pps_in - ); - - localparam TXFIFOSIZE = 13; - localparam RXFIFOSIZE = 13; - - // 64 total regs in address space - localparam SR_RX_CTRL = 0; // 9 regs (+0 to +8) - localparam SR_RX_DSP = 16; // 7 regs (+0 to +6) - localparam SR_TX_CTRL = 24; // 6 regs (+0 to +5) - localparam SR_TX_DSP = 32; // 5 regs (+0 to +4) - localparam SR_TIME64 = 40; // 6 regs (+0 to +5) - localparam SR_CLEAR_RX_FIFO = 48; // 1 reg - localparam SR_CLEAR_TX_FIFO = 49; // 1 reg - localparam SR_GLOBAL_RESET = 50; // 1 reg - localparam SR_REG_TEST32 = 52; // 1 reg - - wire [7:0] COMPAT_NUM = 8'd4; - - wire wb_clk = clk_fpga; - wire wb_rst, global_reset; - - wire pps_int; - wire [63:0] vita_time, vita_time_pps; - reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; - wire [7:0] test_rate; - wire [3:0] test_ctrl; - - wire [7:0] set_addr; - wire [31:0] set_data; - wire set_stb; - - wire [31:0] debug_vt; - wire rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc; - assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp; - assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp; - - setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset - (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(global_reset)); - - reset_sync reset_sync(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(wb_rst)); - - // ///////////////////////////////////////////////////////////////////////////////////// - // GPMC Slave to Wishbone Master - localparam dw = 16; - localparam aw = 11; - localparam sw = 2; - - wire [dw-1:0] m0_dat_mosi, m0_dat_miso; - wire [aw-1:0] m0_adr; - wire [sw-1:0] m0_sel; - wire m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty; - - wire [31:0] debug_gpmc; - - wire [35:0] tx_data, rx_data, tx_err_data; - wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, - tx_err_src_rdy, tx_err_dst_rdy; - reg [15:0] tx_frame_len; - wire [15:0] rx_frame_len; - - wire bus_error; - wire clear_tx, clear_rx; - - setting_reg #(.my_addr(SR_CLEAR_RX_FIFO), .width(1)) sr_clear_rx - (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_rx)); - - setting_reg #(.my_addr(SR_CLEAR_TX_FIFO), .width(1)) sr_clear_tx - (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_tx)); - - gpmc_async #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE)) - gpmc (.arst(wb_rst), - .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), - .EM_NOE(EM_NOE), - - .rx_have_data(rx_have_data), .tx_have_space(tx_have_space), - .bus_error(bus_error), .bus_reset(0), - - .wb_clk(wb_clk), .wb_rst(wb_rst), - .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), - .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), - .wb_ack_i(m0_ack), - - .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx), - .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), - .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), - - .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), - .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc), - - .test_rate(test_rate), .test_ctrl(test_ctrl), - .debug(debug_gpmc)); - - wire rx_sof = rx_data[32]; - wire rx_eof = rx_data[33]; - wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int; - - wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug, vr_debug; - - // ///////////////////////////////////////////////////////////////////////// - // DSP RX - wire [31:0] sample_rx; - wire strobe_rx, run_rx; - wire [35:0] vita_rx_data; - wire vita_rx_src_rdy, vita_rx_dst_rdy; - - dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx - (.clk(wb_clk),.rst(wb_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a({rx_i,2'b0}),.adc_ovf_a(0),.adc_b({rx_q,2'b0}),.adc_ovf_b(0), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .debug(debug_rx_dsp) ); - - vita_rx_chain #(.BASE(SR_RX_CTRL), .UNIT(0), .FIFOSIZE(9), .PROT_ENG_FLAGS(0)) vita_rx_chain - (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time), .overrun(rx_overrun_dsp), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .rx_data_o(vita_rx_data), .rx_dst_rdy_i(vita_rx_dst_rdy), .rx_src_rdy_o(vita_rx_src_rdy), - .debug(vr_debug) ); - - fifo36_mux #(.prio(0)) mux_err_stream - (.clk(wb_clk), .reset(wb_rst), .clear(0), - .data0_i(vita_rx_data), .src0_rdy_i(vita_rx_src_rdy), .dst0_rdy_o(vita_rx_dst_rdy), - .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), - .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); - - // /////////////////////////////////////////////////////////////////////////////////// - // DSP TX - - wire [15:0] tx_i_int, tx_q_int; - wire run_tx; - - vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), - .REPORT_ERROR(1), .DO_FLOW_CONTROL(0), - .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0), - .DSP_NUMBER(0)) - vita_tx_chain - (.clk(wb_clk), .reset(wb_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time), - .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), - .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), - .dac_a(tx_i_int),.dac_b(tx_q_int), - .underrun(tx_underrun_dsp), .run(run_tx), - .debug(debug_vt)); - - assign tx_i = tx_i_int[15:2]; - assign tx_q = tx_q_int[15:2]; - - // ///////////////////////////////////////////////////////////////////////////////////// - // Wishbone Intercon, single master - wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, - s4_dat_mosi, s5_dat_mosi, s4_dat_miso, s5_dat_miso, s6_dat_mosi, s7_dat_mosi, s6_dat_miso, s7_dat_miso, - s8_dat_mosi, s9_dat_mosi, s8_dat_miso, s9_dat_miso, sa_dat_mosi, sb_dat_mosi, sa_dat_miso, sb_dat_miso, - sc_dat_mosi, sd_dat_mosi, sc_dat_miso, sd_dat_miso, se_dat_mosi, sf_dat_mosi, se_dat_miso, sf_dat_miso; - wire [aw-1:0] s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr; - wire [aw-1:0] s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; - wire [sw-1:0] s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel; - wire [sw-1:0] s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; - wire s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack; - wire s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; - wire s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb; - wire s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; - wire s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc; - wire s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; - wire s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we; - wire s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we, sf_we; - - wb_1master #(.dw(dw), .aw(aw), .sw(sw), .decode_w(4), - .s0_addr(4'h0), .s0_mask(4'hF), .s1_addr(4'h1), .s1_mask(4'hF), - .s2_addr(4'h2), .s2_mask(4'hF), .s3_addr(4'h3), .s3_mask(4'hF), - .s4_addr(4'h4), .s4_mask(4'hF), .s5_addr(4'h5), .s5_mask(4'hF), - .s6_addr(4'h6), .s6_mask(4'hF), .s7_addr(4'h7), .s7_mask(4'hF), - .s8_addr(4'h8), .s8_mask(4'hE), .s9_addr(4'hf), .s9_mask(4'hF), // slave 8 is double wide - .sa_addr(4'ha), .sa_mask(4'hF), .sb_addr(4'hb), .sb_mask(4'hF), - .sc_addr(4'hc), .sc_mask(4'hF), .sd_addr(4'hd), .sd_mask(4'hF), - .se_addr(4'he), .se_mask(4'hF), .sf_addr(4'hf), .sf_mask(4'hF)) - wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - .m0_dat_o(m0_dat_miso),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_mosi), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_mosi),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_miso),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), - .s1_dat_o(s1_dat_mosi),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_miso),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), - .s2_dat_o(s2_dat_mosi),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_miso),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), - .s3_dat_o(s3_dat_mosi),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_miso),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), - .s4_dat_o(s4_dat_mosi),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_miso),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), - .s5_dat_o(s5_dat_mosi),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_miso),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), - .s6_dat_o(s6_dat_mosi),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_miso),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), - .s7_dat_o(s7_dat_mosi),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_miso),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), - .s8_dat_o(s8_dat_mosi),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), - .s8_dat_i(s8_dat_miso),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), - .s9_dat_o(s9_dat_mosi),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), - .s9_dat_i(s9_dat_miso),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), - .sa_dat_o(sa_dat_mosi),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), - .sa_dat_i(sa_dat_miso),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), - .sb_dat_o(sb_dat_mosi),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), - .sb_dat_i(sb_dat_miso),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), - .sc_dat_o(sc_dat_mosi),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), - .sc_dat_i(sc_dat_miso),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), - .sd_dat_o(sd_dat_mosi),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), - .sd_dat_i(sd_dat_miso),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), - .se_dat_o(se_dat_mosi),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), - .se_dat_i(se_dat_miso),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), - .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), - .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); - - assign s5_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; - assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; - - // ///////////////////////////////////////////////////////////////////////////////////// - // Slave 0, Misc LEDs, Switches, controls - - localparam REG_LEDS = 7'd0; // out - localparam REG_CGEN_CTRL = 7'd4; // out - localparam REG_CGEN_ST = 7'd6; // in - localparam REG_TEST = 7'd8; // out - localparam REG_RX_FRAMELEN = 7'd10; // in - localparam REG_TX_FRAMELEN = 7'd12; // out - localparam REG_XFER_RATE = 7'd14; // out - localparam REG_COMPAT = 7'd16; // in - - always @(posedge wb_clk) - if(wb_rst) - begin - reg_leds <= 0; - reg_cgen_ctrl <= 2'b11; - reg_test <= 0; - tx_frame_len <= 0; - xfer_rate <= 0; - end - else - if(s0_cyc & s0_stb & s0_we) - case(s0_adr[6:0]) - REG_LEDS : - reg_leds <= s0_dat_mosi; - REG_CGEN_CTRL : - reg_cgen_ctrl <= s0_dat_mosi; - REG_TEST : - reg_test <= s0_dat_mosi; - REG_TX_FRAMELEN : - tx_frame_len <= s0_dat_mosi; - REG_XFER_RATE : - xfer_rate <= s0_dat_mosi; - endcase // case (s0_adr[6:0]) - - assign test_ctrl = xfer_rate[11:8]; - assign test_rate = xfer_rate[7:0]; - - assign { debug_led[3:0] } = ~{run_rx,run_tx,reg_leds[1:0]}; - assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; - - assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : - (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : - (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : - (s0_adr[6:0] == REG_TEST) ? reg_test : - (s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len : - (s0_adr[6:0] == REG_COMPAT) ? { 8'd0, COMPAT_NUM } : - 16'hBEEF; - - assign s0_ack = s0_stb & s0_cyc; - - // ///////////////////////////////////////////////////////////////////////////////////// - // Slave 1, UART - // depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock - - simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart - (.clk_i(wb_clk),.rst_i(wb_rst), - .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack), - .adr_i(s1_adr[3:1]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso), - .rx_int_o(),.tx_int_o(), - .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o()); - - // ///////////////////////////////////////////////////////////////////////////////////// - // Slave 2, SPI - - spi_top16 shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_mosi), - .wb_dat_o(s2_dat_miso),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), - .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(), - .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) ); - - // ///////////////////////////////////////////////////////////////////////// - // Slave 3, I2C - - wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o; - i2c_master_top #(.ARST_LVL(1)) i2c - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_dat_miso[15:8] = 8'd0; - - // I2C -- Don't use external transistors for open drain, the FPGA implements this - IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o)); - IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o)); - - // ///////////////////////////////////////////////////////////////////////// - // GPIOs -- Slave #4 - - wire [31:0] atr_lines; - wire [31:0] debug_gpio_0, debug_gpio_1; - - nsgpio16LE - nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), - .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), - .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( {io_tx,io_rx} ) ); - - // ///////////////////////////////////////////////////////////////////////// - // Settings Bus -- Slave #8 + 9 - - // only have 64 regs, 32 bits each with current setup... - settings_bus_16LE #(.AWIDTH(11),.RWIDTH(6)) settings_bus_16LE - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr),.wb_dat_i(s8_dat_mosi), - .wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack), - .strobe(set_stb),.addr(set_addr),.data(set_data) ); - - // ///////////////////////////////////////////////////////////////////////// - // ATR Controller -- Slave #6 - - atr_controller16 atr_controller16 - (.clk_i(wb_clk), .rst_i(wb_rst), - .adr_i(s6_adr[5:0]), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), - .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), - .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines)); - - // ///////////////////////////////////////////////////////////////////////// - // Readback mux 32 -- Slave #7 - - wire [31:0] reg_test32; - - setting_reg #(.my_addr(SR_REG_TEST32)) sr_reg_test32 - (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(reg_test32),.changed()); - - wb_readback_mux_16LE readback_mux_32 - (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s7_stb), - .wb_adr_i({5'b0,s7_adr}), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack), - - .word00(vita_time[63:32]), .word01(vita_time[31:0]), - .word02(vita_time_pps[63:32]), .word03(vita_time_pps[31:0]), - .word04(reg_test32), .word05(32'b0), - .word06(32'b0), .word07(32'b0), - .word08(32'b0), .word09(32'b0), - .word10(32'b0), .word11(32'b0), - .word12(32'b0), .word13(32'b0), - .word14(32'b0), .word15(32'b0) - ); - - // ///////////////////////////////////////////////////////////////////////// - // VITA Timing - - time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit - (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), - .exp_time_in(0)); - - // ///////////////////////////////////////////////////////////////////////////////////// - // Debug circuitry - - assign debug_clk = { EM_CLK, clk_fpga }; - -/* - assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun }, - { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int }, - { EM_D } }; - -*/ - assign debug = debug_gpmc; - - assign debug_gpio_0 = { {run_tx, 1'b0, run_rx, strobe_rx, tx_i[11:0]}, - {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; - - assign debug_gpio_1 = debug_vt; - -/* - assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy}, - {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy}, - {rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0}, - {2'b0, bus_error, debug_gpmc[4:0] }, - {misc_gpio[7:0]} }; - */ -endmodule // u1e_core diff --git a/usrp2/top/u1e_passthru/.gitignore b/usrp2/top/u1e_passthru/.gitignore deleted file mode 100644 index 1b2211df0..000000000 --- a/usrp2/top/u1e_passthru/.gitignore +++ /dev/null @@ -1 +0,0 @@ -build* diff --git a/usrp2/top/u1e_passthru/Makefile b/usrp2/top/u1e_passthru/Makefile deleted file mode 100644 index f2d835608..000000000 --- a/usrp2/top/u1e_passthru/Makefile +++ /dev/null @@ -1,98 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = passthru -BUILD_DIR = $(abspath build$(ISE)) - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../gpmc/Makefile.srcs - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd1800a \ -package cs484 \ -speed -4 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -passthru.v \ -passthru.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) \ -$(GPMC_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 \ -"Unused IOB Pins" "Pull Up" - -SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/u1e_passthru/passthru.ucf b/usrp2/top/u1e_passthru/passthru.ucf deleted file mode 100644 index 64e6f0440..000000000 --- a/usrp2/top/u1e_passthru/passthru.ucf +++ /dev/null @@ -1,6 +0,0 @@ -NET "overo_gpio145" LOC = "C7" ; -NET "cgen_mosi" LOC = "E22" ; -NET "cgen_sclk" LOC = "J19" ; -NET "cgen_sen_b" LOC = "H20" ; -NET "fpga_cfg_din" LOC = "W17" ; -NET "fpga_cfg_cclk" LOC = "V17" ; diff --git a/usrp2/top/u1e_passthru/passthru.v b/usrp2/top/u1e_passthru/passthru.v deleted file mode 100644 index 12e4db017..000000000 --- a/usrp2/top/u1e_passthru/passthru.v +++ /dev/null @@ -1,18 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module passthru - (input overo_gpio145, - output cgen_sclk, - output cgen_sen_b, - output cgen_mosi, - input fpga_cfg_din, - input fpga_cfg_cclk - ); - - assign cgen_sclk = fpga_cfg_cclk; - assign cgen_sen_b = overo_gpio145; - assign cgen_mosi = fpga_cfg_din; - - -endmodule // passthru diff --git a/usrp2/top/u1plus/.gitignore b/usrp2/top/u1plus/.gitignore deleted file mode 100644 index 1b2211df0..000000000 --- a/usrp2/top/u1plus/.gitignore +++ /dev/null @@ -1 +0,0 @@ -build* diff --git a/usrp2/top/u1plus/Makefile b/usrp2/top/u1plus/Makefile deleted file mode 100644 index ca6ec9320..000000000 --- a/usrp2/top/u1plus/Makefile +++ /dev/null @@ -1,97 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -BUILD_DIR := build/ -export TOP_MODULE := u1plus -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../gpif/Makefile.srcs - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan3A" \ -device XC3S1400A \ -package ft256 \ -speed -4 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -u1plus.v \ -u1plus_core.v \ -u1plus.ucf \ -timing.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ -$(GPIF_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 \ -"Unused IOB Pins" "Pull Up" - -SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/u1plus/core_compile b/usrp2/top/u1plus/core_compile deleted file mode 100755 index b2ccc8b49..000000000 --- a/usrp2/top/u1plus/core_compile +++ /dev/null @@ -1 +0,0 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models diff --git a/usrp2/top/u1plus/timing.ucf b/usrp2/top/u1plus/timing.ucf deleted file mode 100644 index b2a455f6d..000000000 --- a/usrp2/top/u1plus/timing.ucf +++ /dev/null @@ -1,5 +0,0 @@ -NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; -TIMESPEC "TS_CLK_FPGA_P" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; - -NET "IFCLK" TNM_NET = "IFCLK"; -TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20833 ps HIGH 50 %; diff --git a/usrp2/top/u1plus/u1plus.ucf b/usrp2/top/u1plus/u1plus.ucf deleted file mode 100644 index cd89878e3..000000000 --- a/usrp2/top/u1plus/u1plus.ucf +++ /dev/null @@ -1,203 +0,0 @@ -## Main Clock -NET "CLK_FPGA_P" LOC = "R7" ; -NET "CLK_FPGA_N" LOC = "T7" ; - -## UART -NET "FPGA_TXD" LOC = "H16" ; -NET "FPGA_RXD" LOC = "H12" ; - -## I2C -NET "SDA_FPGA" LOC = "T13" ; -NET "SCL_FPGA" LOC = "R13" ; - -## CGEN -NET "cgen_st_ld" LOC = "M13" ; -NET "cgen_st_refmon" LOC = "J14" ; -NET "cgen_st_status" LOC = "P6" ; -NET "cgen_ref_sel" LOC = "T2" ; -NET "cgen_sync_b" LOC = "H15" ; - -## FPGA Config -#NET "fpga_cfg_din" LOC = "T14" ; -#NET "fpga_cfg_cclk" LOC = "R14" ; -#NET "fpga_cfg_init_b" LOC = "T12" ; - -## MISC -#NET "mystery_bus<2>" LOC = "T11" ; -#NET "mystery_bus<1>" LOC = "C4" ; -#NET "mystery_bus<0>" LOC = "E7" ; -NET "reset_n" LOC = "D5" ; -NET "PPS_IN" LOC = "M14" ; -NET "reset_codec" LOC = "B14" ; - -## GPIF -NET "GPIF_D<15>" LOC = "P7" ; -NET "GPIF_D<14>" LOC = "N8" ; -NET "GPIF_D<13>" LOC = "T5" ; -NET "GPIF_D<12>" LOC = "T6" ; -NET "GPIF_D<11>" LOC = "N6" ; -NET "GPIF_D<10>" LOC = "P5" ; -NET "GPIF_D<9>" LOC = "R3" ; -NET "GPIF_D<8>" LOC = "T3" ; -NET "GPIF_D<7>" LOC = "N12" ; -NET "GPIF_D<6>" LOC = "P13" ; -NET "GPIF_D<5>" LOC = "P11" ; -NET "GPIF_D<4>" LOC = "R9" ; -NET "GPIF_D<3>" LOC = "T9" ; -NET "GPIF_D<2>" LOC = "N9" ; -NET "GPIF_D<1>" LOC = "P9" ; -NET "GPIF_D<0>" LOC = "P8" ; - -NET "GPIF_CTL<3>" LOC = "N5" ; -NET "GPIF_CTL<2>" LOC = "M11" ; -NET "GPIF_CTL<1>" LOC = "M9" ; -NET "GPIF_CTL<0>" LOC = "M7" ; - -NET "GPIF_RDY<3>" LOC = "N11" ; -NET "GPIF_RDY<2>" LOC = "T10" ; -NET "GPIF_RDY<1>" LOC = "T4" ; -NET "GPIF_RDY<0>" LOC = "R5" ; - -NET "FX2_PA7_FLAGD" LOC = "P12" ; -NET "FX2_PA6_PKTEND" LOC = "R11" ; -NET "FX2_PA2_SLOE" LOC = "P10" ; - -NET "IFCLK" LOC = "T8" ; - -## LEDs -NET "debug_led<2>" LOC = "R2" ; -NET "debug_led<1>" LOC = "N4" ; -NET "debug_led<0>" LOC = "P4" ; - -## Debug bus -NET "debug_clk<0>" LOC = "K15" ; -NET "debug_clk<1>" LOC = "K14" ; -NET "debug<0>" LOC = "K16" ; -NET "debug<1>" LOC = "J16" ; -NET "debug<2>" LOC = "C16" ; -NET "debug<3>" LOC = "C15" ; -NET "debug<4>" LOC = "E13" ; -NET "debug<5>" LOC = "D14" ; -NET "debug<6>" LOC = "D16" ; -NET "debug<7>" LOC = "D15" ; -NET "debug<8>" LOC = "E14" ; -NET "debug<9>" LOC = "F13" ; -NET "debug<10>" LOC = "G13" ; -NET "debug<11>" LOC = "F14" ; -NET "debug<12>" LOC = "E16" ; -NET "debug<13>" LOC = "F15" ; -NET "debug<14>" LOC = "H13" ; -NET "debug<15>" LOC = "G14" ; -NET "debug<16>" LOC = "G16" ; -NET "debug<17>" LOC = "F16" ; -NET "debug<18>" LOC = "J12" ; -NET "debug<19>" LOC = "J13" ; -NET "debug<20>" LOC = "L14" ; -NET "debug<21>" LOC = "L16" ; -NET "debug<22>" LOC = "M15" ; -NET "debug<23>" LOC = "M16" ; -NET "debug<24>" LOC = "L13" ; -NET "debug<25>" LOC = "K13" ; -NET "debug<26>" LOC = "P16" ; -NET "debug<27>" LOC = "N16" ; -NET "debug<28>" LOC = "R15" ; -NET "debug<29>" LOC = "P15" ; -NET "debug<30>" LOC = "N13" ; -NET "debug<31>" LOC = "N14" ; - -## ADC -NET "adc<11>" LOC = "B15" ; -NET "adc<10>" LOC = "A8" ; -NET "adc<9>" LOC = "B8" ; -NET "adc<8>" LOC = "C8" ; -NET "adc<7>" LOC = "D8" ; -NET "adc<6>" LOC = "C9" ; -NET "adc<5>" LOC = "A9" ; -NET "adc<4>" LOC = "C10" ; -NET "adc<3>" LOC = "D9" ; -NET "adc<2>" LOC = "A3" ; -NET "adc<1>" LOC = "B3" ; -NET "adc<0>" LOC = "A4" ; -NET "RXSYNC" LOC = "D10" ; - -## DAC -NET "TXBLANK" LOC = "K1" ; -NET "TXSYNC" LOC = "J2" ; -NET "dac<0>" LOC = "J1" ; -NET "dac<1>" LOC = "H3" ; -NET "dac<2>" LOC = "J3" ; -NET "dac<3>" LOC = "G2" ; -NET "dac<4>" LOC = "H1" ; -NET "dac<5>" LOC = "N3" ; -NET "dac<6>" LOC = "M4" ; -NET "dac<7>" LOC = "R1" ; -NET "dac<8>" LOC = "P2" ; -NET "dac<9>" LOC = "P1" ; -NET "dac<10>" LOC = "M1" ; -NET "dac<11>" LOC = "N1" ; -NET "dac<12>" LOC = "M3" ; -NET "dac<13>" LOC = "L4" ; - -## TX DB -NET "io_tx<0>" LOC = "K4" ; -NET "io_tx<1>" LOC = "L3" ; -NET "io_tx<2>" LOC = "L2" ; -NET "io_tx<3>" LOC = "F1" ; -NET "io_tx<4>" LOC = "F3" ; -NET "io_tx<5>" LOC = "G3" ; -NET "io_tx<6>" LOC = "E3" ; -NET "io_tx<7>" LOC = "E2" ; -NET "io_tx<8>" LOC = "E4" ; -NET "io_tx<9>" LOC = "F4" ; -NET "io_tx<10>" LOC = "D1" ; -NET "io_tx<11>" LOC = "E1" ; -NET "io_tx<12>" LOC = "D4" ; -NET "io_tx<13>" LOC = "D3" ; -NET "io_tx<14>" LOC = "C2" ; -NET "io_tx<15>" LOC = "C1" ; - -## RX DB -NET "io_rx<0>" LOC = "D7" ; -NET "io_rx<1>" LOC = "C6" ; -NET "io_rx<2>" LOC = "A6" ; -NET "io_rx<3>" LOC = "B6" ; -NET "io_rx<4>" LOC = "E9" ; -NET "io_rx<5>" LOC = "A7" ; -NET "io_rx<6>" LOC = "C7" ; -NET "io_rx<7>" LOC = "B10" ; -NET "io_rx<8>" LOC = "A10" ; -NET "io_rx<9>" LOC = "C11" ; -NET "io_rx<10>" LOC = "A11" ; -NET "io_rx<11>" LOC = "D11" ; -NET "io_rx<12>" LOC = "B12" ; -NET "io_rx<13>" LOC = "A12" ; -NET "io_rx<14>" LOC = "A14" ; -NET "io_rx<15>" LOC = "A13" ; - -## SPI -#NET "SEN_AUX" LOC = "C12" ; -#NET "SCLK_AUX" LOC = "D12" ; -#NET "MISO_AUX" LOC = "J5" ; -NET "SCLK_CODEC" LOC = "K3" ; -NET "SEN_CODEC" LOC = "D13" ; -NET "MOSI_CODEC" LOC = "C13" ; -NET "MISO_CODEC" LOC = "G4" ; - -NET "MISO_RX_DB" LOC = "E6" ; -NET "SEN_RX_DB" LOC = "B4" ; -NET "MOSI_RX_DB" LOC = "A5" ; -NET "SCLK_RX_DB" LOC = "C5" ; - -NET "MISO_TX_DB" LOC = "J4" ; -NET "SEN_TX_DB" LOC = "N2" ; -NET "MOSI_TX_DB" LOC = "L1" ; -NET "SCLK_TX_DB" LOC = "G1" ; - -## Dedicated pins -#NET "TMS" LOC = "B2" ; -#NET "TDO" LOC = "B16" ; -#NET "TDI" LOC = "B1" ; -#NET "TCK" LOC = "A15" ; - -##NET "fpga_cfg_prog_b" LOC = "A2" ; -##NET "fpga_cfg_done" LOC = "T15" ; diff --git a/usrp2/top/u1plus/u1plus.v b/usrp2/top/u1plus/u1plus.v deleted file mode 100644 index 9aafef3ce..000000000 --- a/usrp2/top/u1plus/u1plus.v +++ /dev/null @@ -1,156 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module u1plus - (input CLK_FPGA_P, input CLK_FPGA_N, // Diff - output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - output FPGA_TXD, input FPGA_RXD, - - // GPIF - inout [15:0] GPIF_D, input [3:0] GPIF_CTL, output [3:0] GPIF_RDY, - output FX2_PA7_FLAGD, output FX2_PA6_PKTEND, output FX2_PA2_SLOE, - input IFCLK, - - inout SDA_FPGA, inout SCL_FPGA, // I2C - - output SCLK_TX_DB, output SEN_TX_DB, output MOSI_TX_DB, input MISO_TX_DB, // DB TX SPI - output SCLK_RX_DB, output SEN_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, // DB TX SPI - output SCLK_CODEC, output SEN_CODEC, output MOSI_CODEC, input MISO_CODEC, // AD9862 main SPI - - input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, - - inout [15:0] io_tx, inout [15:0] io_rx, - - output [13:0] dac, output TXSYNC, output TXBLANK, - input [11:0] adc, input RXSYNC, - - input PPS_IN, - input reset_n, output reset_codec - ); - - assign reset_codec = 1; // Believed to be active low - - // ///////////////////////////////////////////////////////////////////////// - // Clocking - wire clk_fpga, clk_fpga_in, reset; - - IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) - clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - - BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga)); - - reset_sync reset_sync(.clk(clk_fpga), .reset_in(~reset_n), .reset_out(reset)); - - // ///////////////////////////////////////////////////////////////////////// - // SPI - wire mosi, sclk, miso; - assign { SCLK_TX_DB, MOSI_TX_DB } = ~SEN_TX_DB ? {sclk,mosi} : 2'b0; - assign { SCLK_RX_DB, MOSI_RX_DB } = ~SEN_RX_DB ? {sclk,mosi} : 2'b0; - assign { SCLK_CODEC, MOSI_CODEC } = ~SEN_CODEC ? {sclk,mosi} : 2'b0; - assign miso = (~SEN_TX_DB & MISO_TX_DB) | (~SEN_RX_DB & MISO_RX_DB) | - (~SEN_CODEC & MISO_CODEC); - - // ///////////////////////////////////////////////////////////////////////// - // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL - - assign TXBLANK = 0; - wire [13:0] tx_i, tx_q; - - genvar i; - generate - for(i=0;i<14;i=i+1) - begin : gen_dacout - ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" - .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 - .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset - ODDR2_inst (.Q(dac[i]), // 1-bit DDR output data - .C0(clk_fpga), // 1-bit clock input - .C1(~clk_fpga), // 1-bit clock input - .CE(1'b1), // 1-bit clock enable input - .D0(tx_i[i]), // 1-bit data input (associated with C0) - .D1(tx_q[i]), // 1-bit data input (associated with C1) - .R(1'b0), // 1-bit reset input - .S(1'b0)); // 1-bit set input - end // block: gen_dacout - endgenerate - ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" - .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 - .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset - ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data - .C0(clk_fpga), // 1-bit clock input - .C1(~clk_fpga), // 1-bit clock input - .CE(1'b1), // 1-bit clock enable input - .D0(1'b0), // 1-bit data input (associated with C0) - .D1(1'b1), // 1-bit data input (associated with C1) - .R(1'b0), // 1-bit reset input - .S(1'b0)); // 1-bit set input - - // ///////////////////////////////////////////////////////////////////////// - // RX ADC -- handles deinterleaving - - reg [11:0] rx_i, rx_q; - wire [11:0] rx_a, rx_b; - - genvar j; - generate - for(j=0;j<12;j=j+1) - begin : gen_adcin - IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" - .INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1 - .INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1 - .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset - IDDR2_inst (.Q0(rx_a[j]), // 1-bit output captured with C0 clock - .Q1(rx_b[j]), // 1-bit output captured with C1 clock - .C0(clk_fpga), // 1-bit clock input - .C1(~clk_fpga), // 1-bit clock input - .CE(1'b1), // 1-bit clock enable input - .D(adc[j]), // 1-bit DDR data input - .R(1'b0), // 1-bit reset input - .S(1'b0)); // 1-bit set input - end // block: gen_adcin - endgenerate - - IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" - .INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1 - .INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1 - .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset - IDDR2_sync (.Q0(rxsync_0), // 1-bit output captured with C0 clock - .Q1(rxsync_1), // 1-bit output captured with C1 clock - .C0(clk_fpga), // 1-bit clock input - .C1(~clk_fpga), // 1-bit clock input - .CE(1'b1), // 1-bit clock enable input - .D(RXSYNC), // 1-bit DDR data input - .R(1'b0), // 1-bit reset input - .S(1'b0)); // 1-bit set input - - always @(posedge clk_fpga) - if(rxsync_0) - begin - rx_i <= rx_b; - rx_q <= rx_a; - end - else - begin - rx_i <= rx_a; - rx_q <= rx_b; - end - - // ///////////////////////////////////////////////////////////////////////// - // Main U1E Core - u1plus_core u1p_c(.clk_fpga(clk_fpga), .rst_fpga(reset), - .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), - .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), - .gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_rdy(GPIF_RDY), - .gpif_misc({FX2_PA7_FLAGD,FX2_PA6_PKTEND,FX2_PA2_SLOE}), - .gpif_clk(IFCLK), - - .db_sda(SDA_FPGA), .db_scl(SCL_FPGA), - .sclk(sclk), .sen({SEN_CODEC,SEN_TX_DB,SEN_RX_DB}), .mosi(mosi), .miso(miso), - .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), - .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel), - .io_tx(io_tx), .io_rx(io_rx), - .tx_i(tx_i), .tx_q(tx_q), - .rx_i(rx_i), .rx_q(rx_q), - .pps_in(PPS_IN) ); - -endmodule // u1plus diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v deleted file mode 100644 index 898f5950c..000000000 --- a/usrp2/top/u1plus/u1plus_core.v +++ /dev/null @@ -1,392 +0,0 @@ - - -module u1plus_core - (input clk_fpga, input rst_fpga, - output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - output debug_txd, input debug_rxd, - - // GPIF - inout [15:0] gpif_d, input [3:0] gpif_ctl, output [3:0] gpif_rdy, - output [2:0] gpif_misc, input gpif_clk, - - inout db_sda, inout db_scl, - output sclk, output [15:0] sen, output mosi, input miso, - - input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, - output tx_underrun, output rx_overrun, - inout [15:0] io_tx, inout [15:0] io_rx, - output [13:0] tx_i, output [13:0] tx_q, - input [11:0] rx_i, input [11:0] rx_q, - input pps_in - ); - - localparam TXFIFOSIZE = 11; - localparam RXFIFOSIZE = 11; - - // 64 total regs in address space - localparam SR_RX_CTRL = 0; // 9 regs (+0 to +8) - localparam SR_RX_DSP = 16; // 7 regs (+0 to +6) - localparam SR_TX_CTRL = 24; // 6 regs (+0 to +5) - localparam SR_TX_DSP = 32; // 5 regs (+0 to +4) - localparam SR_TIME64 = 40; // 6 regs (+0 to +5) - localparam SR_CLEAR_RX_FIFO = 48; // 1 reg - localparam SR_CLEAR_TX_FIFO = 49; // 1 reg - localparam SR_GLOBAL_RESET = 50; // 1 reg - localparam SR_REG_TEST32 = 52; // 1 reg - - wire [7:0] COMPAT_NUM = 8'd3; - - wire wb_clk = clk_fpga; - wire wb_rst, global_reset; - - wire pps_int; - wire [63:0] vita_time, vita_time_pps; - reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; - wire [7:0] test_rate; - wire [3:0] test_ctrl; - - wire [7:0] set_addr; - wire [31:0] set_data; - wire set_stb; - - wire [31:0] debug0; - wire [31:0] debug1; - - wire [31:0] debug_vt; - wire gpif_rst; - - wire rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc; - reg [7:0] frames_per_packet; - - assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp; - assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp; - - setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset - (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(global_reset)); - - reset_sync reset_sync_wb(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(wb_rst)); - reset_sync reset_sync_gp(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(gpif_rst)); - wire [15:0] test_len; - - // ///////////////////////////////////////////////////////////////////////////////////// - // GPIF Slave to Wishbone Master - localparam dw = 16; - localparam aw = 11; - localparam sw = 2; - - wire [dw-1:0] m0_dat_mosi, m0_dat_miso; - wire [aw-1:0] m0_adr; - wire [sw-1:0] m0_sel; - wire m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty; - - wire [31:0] debug_gpmc; - - wire [35:0] tx_data, rx_data, tx_err_data; - wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, - tx_err_src_rdy, tx_err_dst_rdy; - - wire bus_error; - wire clear_tx, clear_rx; - - setting_reg #(.my_addr(SR_CLEAR_RX_FIFO), .width(1)) sr_clear_rx - (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_rx)); - - setting_reg #(.my_addr(SR_CLEAR_TX_FIFO), .width(1)) sr_clear_tx - (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_tx)); - - gpif #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE)) - gpif (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_d(gpif_d), - .gpif_ctl(gpif_ctl), .gpif_rdy(gpif_rdy), .gpif_misc(gpif_misc), - - .wb_clk(wb_clk), .wb_rst(wb_rst), - .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), - .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), - .wb_ack_i(m0_ack), .triggers(8'd0), - - .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx), - .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), - .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), - .tx_err_data_i(tx_err_data), .tx_err_src_rdy_i(tx_err_src_rdy), .tx_err_dst_rdy_o(tx_err_dst_rdy), - - .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc), - - .frames_per_packet(frames_per_packet), .test_len(test_len), .test_rate(test_rate), .test_ctrl(test_ctrl), - .debug0(debug0), .debug1(debug1)); - - // ///////////////////////////////////////////////////////////////////////// - // DSP RX - wire [31:0] sample_rx; - wire strobe_rx, run_rx; - wire [31:0] debug_rx_dsp, vr_debug; - - dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx - (.clk(wb_clk),.rst(wb_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a({rx_i,2'b0}),.adc_ovf_a(0),.adc_b({rx_q,2'b0}),.adc_ovf_b(0), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .debug(debug_rx_dsp) ); - - vita_rx_chain #(.BASE(SR_RX_CTRL), .UNIT(0), .FIFOSIZE(9), .PROT_ENG_FLAGS(0)) vita_rx_chain - (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time), .overrun(rx_overrun_dsp), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .rx_data_o(rx_data), .rx_dst_rdy_i(rx_dst_rdy), .rx_src_rdy_o(rx_src_rdy), - .debug(vr_debug) ); - - // /////////////////////////////////////////////////////////////////////////////////// - // DSP TX - - wire [15:0] tx_i_int, tx_q_int; - wire run_tx; - - vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), - .REPORT_ERROR(1), .DO_FLOW_CONTROL(0), - .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0), - .DSP_NUMBER(0)) - vita_tx_chain - (.clk(wb_clk), .reset(wb_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time), - .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), - .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), - .dac_a(tx_i_int),.dac_b(tx_q_int), - .underrun(tx_underrun_dsp), .run(run_tx), - .debug(debug_vt)); - - assign tx_i = tx_i_int[15:2]; - assign tx_q = tx_q_int[15:2]; - - // ///////////////////////////////////////////////////////////////////////////////////// - // Wishbone Intercon, single master - wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, - s4_dat_mosi, s5_dat_mosi, s4_dat_miso, s5_dat_miso, s6_dat_mosi, s7_dat_mosi, s6_dat_miso, s7_dat_miso, - s8_dat_mosi, s9_dat_mosi, s8_dat_miso, s9_dat_miso, sa_dat_mosi, sb_dat_mosi, sa_dat_miso, sb_dat_miso, - sc_dat_mosi, sd_dat_mosi, sc_dat_miso, sd_dat_miso, se_dat_mosi, sf_dat_mosi, se_dat_miso, sf_dat_miso; - wire [aw-1:0] s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr; - wire [aw-1:0] s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; - wire [sw-1:0] s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel; - wire [sw-1:0] s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; - wire s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack; - wire s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; - wire s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb; - wire s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; - wire s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc; - wire s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; - wire s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we; - wire s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we, sf_we; - - wb_1master #(.dw(dw), .aw(aw), .sw(sw), .decode_w(4), - .s0_addr(4'h0), .s0_mask(4'hF), .s1_addr(4'h1), .s1_mask(4'hF), - .s2_addr(4'h2), .s2_mask(4'hF), .s3_addr(4'h3), .s3_mask(4'hF), - .s4_addr(4'h4), .s4_mask(4'hF), .s5_addr(4'h5), .s5_mask(4'hF), - .s6_addr(4'h6), .s6_mask(4'hF), .s7_addr(4'h7), .s7_mask(4'hF), - .s8_addr(4'h8), .s8_mask(4'hE), .s9_addr(4'hf), .s9_mask(4'hF), // slave 8 is double wide - .sa_addr(4'ha), .sa_mask(4'hF), .sb_addr(4'hb), .sb_mask(4'hF), - .sc_addr(4'hc), .sc_mask(4'hF), .sd_addr(4'hd), .sd_mask(4'hF), - .se_addr(4'he), .se_mask(4'hF), .sf_addr(4'hf), .sf_mask(4'hF)) - wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - .m0_dat_o(m0_dat_miso),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_mosi), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_mosi),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_miso),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), - .s1_dat_o(s1_dat_mosi),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_miso),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), - .s2_dat_o(s2_dat_mosi),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_miso),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), - .s3_dat_o(s3_dat_mosi),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_miso),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), - .s4_dat_o(s4_dat_mosi),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_miso),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), - .s5_dat_o(s5_dat_mosi),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_miso),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), - .s6_dat_o(s6_dat_mosi),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_miso),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), - .s7_dat_o(s7_dat_mosi),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_miso),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), - .s8_dat_o(s8_dat_mosi),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), - .s8_dat_i(s8_dat_miso),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), - .s9_dat_o(s9_dat_mosi),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), - .s9_dat_i(s9_dat_miso),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), - .sa_dat_o(sa_dat_mosi),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), - .sa_dat_i(sa_dat_miso),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), - .sb_dat_o(sb_dat_mosi),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), - .sb_dat_i(sb_dat_miso),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), - .sc_dat_o(sc_dat_mosi),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), - .sc_dat_i(sc_dat_miso),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), - .sd_dat_o(sd_dat_mosi),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), - .sd_dat_i(sd_dat_miso),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), - .se_dat_o(se_dat_mosi),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), - .se_dat_i(se_dat_miso),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), - .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), - .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); - - assign s5_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; - assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; - - // ///////////////////////////////////////////////////////////////////////////////////// - // Slave 0, Misc LEDs, Switches, controls - - localparam REG_LEDS = 7'd0; // out - localparam REG_CGEN_CTRL = 7'd4; // out - localparam REG_CGEN_ST = 7'd6; // in - localparam REG_TEST = 7'd8; // out - localparam REG_RX_FRAMELEN = 7'd10; // in - localparam REG_TX_FRAMELEN = 7'd12; // out - localparam REG_XFER_RATE = 7'd14; // out - localparam REG_COMPAT = 7'd16; // in - - always @(posedge wb_clk) - if(wb_rst) - begin - reg_leds <= 0; - reg_cgen_ctrl <= 2'b11; - reg_test <= 0; - xfer_rate <= 0; - frames_per_packet <= 0; - end - else - if(s0_cyc & s0_stb & s0_we) - case(s0_adr[6:0]) - REG_LEDS : - reg_leds <= s0_dat_mosi; - REG_CGEN_CTRL : - reg_cgen_ctrl <= s0_dat_mosi; - REG_TEST : - reg_test <= s0_dat_mosi; - REG_RX_FRAMELEN : - frames_per_packet <= s0_dat_mosi[7:0]; - REG_XFER_RATE : - xfer_rate <= s0_dat_mosi; - endcase // case (s0_adr[6:0]) - - assign test_ctrl = xfer_rate[11:8]; - assign test_rate = xfer_rate[7:0]; - assign test_len = reg_test[15:0]; - - assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board - assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; - - assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : - (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : - (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : - (s0_adr[6:0] == REG_TEST) ? reg_test : - (s0_adr[6:0] == REG_COMPAT) ? { 8'd0, COMPAT_NUM } : - 16'hBEEF; - - assign s0_ack = s0_stb & s0_cyc; - - // ///////////////////////////////////////////////////////////////////////////////////// - // Slave 1, UART - // depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock - - simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart - (.clk_i(wb_clk),.rst_i(wb_rst), - .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack), - .adr_i(s1_adr[3:1]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso), - .rx_int_o(),.tx_int_o(), - .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o()); - - // ///////////////////////////////////////////////////////////////////////////////////// - // Slave 2, SPI - - spi_top16 shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_mosi), - .wb_dat_o(s2_dat_miso),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), - .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(), - .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) ); - - // ///////////////////////////////////////////////////////////////////////// - // Slave 3, I2C - - wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o; - i2c_master_top #(.ARST_LVL(1)) i2c - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr[3:1]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_dat_miso[15:8] = 8'd0; - - // I2C -- Don't use external transistors for open drain, the FPGA implements this - IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o)); - IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o)); - - // ///////////////////////////////////////////////////////////////////////// - // GPIOs -- Slave #4 - - wire [31:0] atr_lines; - wire [31:0] debug_gpio_0, debug_gpio_1; - - nsgpio16LE - nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), - .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), - .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( {io_tx,io_rx} ) ); - - // ///////////////////////////////////////////////////////////////////////// - // Settings Bus -- Slave #8 + 9 - - // only have 64 regs, 32 bits each with current setup... - settings_bus_16LE #(.AWIDTH(11),.RWIDTH(6)) settings_bus_16LE - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr[10:0]),.wb_dat_i(s8_dat_mosi), - .wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack), - .strobe(set_stb),.addr(set_addr),.data(set_data) ); - - // ///////////////////////////////////////////////////////////////////////// - // ATR Controller -- Slave #6 - - atr_controller16 atr_controller16 - (.clk_i(wb_clk), .rst_i(wb_rst), - .adr_i(s6_adr[5:0]), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), - .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), - .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines)); - - // ///////////////////////////////////////////////////////////////////////// - // Readback mux 32 -- Slave #7 - - wire [31:0] reg_test32; - - setting_reg #(.my_addr(SR_REG_TEST32)) sr_reg_test32 - (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(reg_test32),.changed()); - - wb_readback_mux_16LE readback_mux_32 - (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s7_stb), - .wb_adr_i({5'b0,s7_adr}), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack), - - .word00(vita_time[63:32]), .word01(vita_time[31:0]), - .word02(vita_time_pps[63:32]), .word03(vita_time_pps[31:0]), - .word04(reg_test32), .word05(32'b0), - .word06(32'b0), .word07(32'b0), - .word08(32'b0), .word09(32'b0), - .word10(32'b0), .word11(32'b0), - .word12(32'b0), .word13(32'b0), - .word14(32'b0), .word15(32'b0) - ); - - // ///////////////////////////////////////////////////////////////////////// - // VITA Timing - - time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit - (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), - .exp_time_in(0)); - - // ///////////////////////////////////////////////////////////////////////////////////// - // Debug circuitry - - assign debug_clk = { gpif_clk, clk_fpga }; - assign debug = debug0; - assign debug_gpio_0 = 0; - assign debug_gpio_1 = 0; - //assign {io_tx,io_rx} = {debug1}; - -endmodule // u1plus_core diff --git a/usrp2/top/u2_rev3/.gitignore b/usrp2/top/u2_rev3/.gitignore deleted file mode 100644 index f50a2b7e5..000000000 --- a/usrp2/top/u2_rev3/.gitignore +++ /dev/null @@ -1,57 +0,0 @@ -/*.ptwx -/*.xrpt -/*.zip -/*_xdb -/templates -/netgen -/_ngo -/_xmsgs -/_pace.ucf -/*.cmd -/*.ibs -/*.lfp -/*.mfp -/*.bit -/*.bin -/*.stx -/*.par -/*.unroutes -/*.ntrc_log -/*.ngr -/*.mrp -/*.html -/*.lso -/*.twr -/*.bld -/*.ncd -/*.txt -/*.cmd_log -/*.drc -/*.map -/*.twr -/*.xml -/*.syr -/*.ngm -/*.xst -/*.csv -/*.html -/*.lock -/*.ncd -/*.twx -/*.ise_ISE_Backup -/*.xml -/*.ut -/*.xpi -/*.ngd -/*.ncd -/*.pad -/*.bgn -/*.ngc -/*.pcf -/*.ngd -/xst -/*.log -/*.rpt -/*.cel -/*.restore -/build* diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile deleted file mode 100644 index e9b43491a..000000000 --- a/usrp2/top/u2_rev3/Makefile +++ /dev/null @@ -1,98 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = u2_rev3 -BUILD_DIR = $(abspath build) - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../extramfifo/Makefile.srcs - - -################################################## -# Project Properties -################################################## -PROJECT_PROPERTIES = \ -family Spartan3 \ -device xc3s2000 \ -package fg456 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -u2_core.v \ -u2_rev3.v \ -u2_rev3.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v deleted file mode 100644 index 0e6120ec6..000000000 --- a/usrp2/top/u2_rev3/u2_core.v +++ /dev/null @@ -1,707 +0,0 @@ -// //////////////////////////////////////////////////////////////////////////////// -// Module Name: u2_core -// //////////////////////////////////////////////////////////////////////////////// - -module u2_core - (// Clocks - input dsp_clk, - input wb_clk, - output clock_ready, - input clk_to_mac, - input pps_in, - - // Misc, debug - output [7:0] leds, - output [31:0] debug, - output [1:0] debug_clk, - - // Expansion - input exp_time_in, - output exp_time_out, - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output [7:0] GMII_TXD, - output GMII_TX_EN, - output GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - output PHY_RESETn, - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output [15:0] ser_t, - output ser_tklsb, - output ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // CPLD interface - output cpld_start, - output cpld_mode, - output cpld_done, - input cpld_din, - input cpld_clk, - input cpld_detached, - output cpld_misc, - input cpld_init_b, - input por, - output config_success, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_on_a, - output adc_oe_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_on_b, - output adc_oe_b, - - // DAC - output [15:0] dac_a, - output [15:0] dac_b, - - // I2C - input scl_pad_i, - output scl_pad_o, - output scl_pad_oen_o, - input sda_pad_i, - output sda_pad_o, - output sda_pad_oen_o, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Generic SPI - output sclk, - output mosi, - input miso, - output sen_clk, - output sen_dac, - output sen_tx_db, - output sen_tx_adc, - output sen_tx_dac, - output sen_rx_db, - output sen_rx_adc, - output sen_rx_dac, - - // GPIO to DBoards - inout [15:0] io_tx, - inout [15:0] io_rx, - - // External RAM - input [17:0] RAM_D_pi, - output [17:0] RAM_D_po, - output RAM_D_poe, - output [18:0] RAM_A, - output RAM_CE1n, - output RAM_CENn, - output RAM_WEn, - output RAM_OEn, - output RAM_LDn, - - // Debug stuff - output uart_tx_o, - input uart_rx_i, - output uart_baud_o, - input sim_mode, - input [3:0] clock_divider - ); - - localparam SR_MISC = 0; // 7 regs - localparam SR_SIMTIMER = 8; // 2 - localparam SR_TIME64 = 10; // 6 - localparam SR_BUF_POOL = 16; // 4 - - localparam SR_RX_FRONT = 24; // 5 - localparam SR_RX_CTRL0 = 32; // 9 - localparam SR_RX_DSP0 = 48; // 7 - localparam SR_RX_CTRL1 = 80; // 9 - localparam SR_RX_DSP1 = 96; // 7 - - localparam SR_TX_FRONT = 128; // ? - localparam SR_TX_CTRL = 144; // 6 - localparam SR_TX_DSP = 160; // 5 - - localparam SR_UDP_SM = 192; // 64 - - // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 - // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs - // localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo - localparam DSP_RX_FIFOSIZE = 10; - localparam ETH_TX_FIFOSIZE = 9; - localparam ETH_RX_FIFOSIZE = 11; - localparam SERDES_TX_FIFOSIZE = 9; - localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? - - wire [7:0] set_addr, set_addr_dsp; - wire [31:0] set_data, set_data_dsp; - wire set_stb, set_stb_dsp; - - wire ram_loader_done, ram_loader_rst; - wire wb_rst; - wire dsp_rst = wb_rst; - - wire [31:0] status; - wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; - wire proc_int, overrun0, overrun1, underrun; - wire uart_tx_int, uart_rx_int; - - wire [31:0] debug_gpio_0, debug_gpio_1; - wire [31:0] atr_lines; - - wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2; - - wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; - wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; - wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; - - wire serdes_link_up; - wire epoch; - wire [31:0] irq; - wire [63:0] vita_time, vita_time_pps; - - wire run_rx0, run_rx1, run_tx; - reg run_rx0_d1, run_rx1_d1; - - // /////////////////////////////////////////////////////////////////////////////////////////////// - // Wishbone Single Master INTERCON - localparam dw = 32; // Data bus width - localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space - localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. - - wire [dw-1:0] m0_dat_o, m0_dat_i; - wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, - s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, - s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, - sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o, sf_dat_i, sf_dat_o; - wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; - wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; - wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; - wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; - wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; - wire m0_err, m0_rty; - wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we; - - wb_1master #(.decode_w(8), - .s0_addr(8'b0000_0000),.s0_mask(8'b1100_0000), // Main RAM (0-16K) - .s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000), // Packet Router (16-20K) - .s2_addr(8'b0101_0000),.s2_mask(8'b1111_1100), // SPI - .s3_addr(8'b0101_0100),.s3_mask(8'b1111_1100), // I2C - .s4_addr(8'b0101_1000),.s4_mask(8'b1111_1100), // GPIO - .s5_addr(8'b0101_1100),.s5_mask(8'b1111_1100), // Readback - .s6_addr(8'b0110_0000),.s6_mask(8'b1111_0000), // Ethernet MAC - .s7_addr(8'b0111_0000),.s7_mask(8'b1111_0000), // 20K-24K, Settings Bus (only uses 1K) - .s8_addr(8'b1000_0000),.s8_mask(8'b1111_1100), // PIC - .s9_addr(8'b1000_0100),.s9_mask(8'b1111_1100), // Unused - .sa_addr(8'b1000_1000),.sa_mask(8'b1111_1100), // UART - .sb_addr(8'b1000_1100),.sb_mask(8'b1111_1100), // ATR - .sc_addr(8'b1001_0000),.sc_mask(8'b1111_0000), // Unused - .sd_addr(8'b1010_0000),.sd_mask(8'b1111_0000), // SD Card access - .se_addr(8'b1011_0000),.se_mask(8'b1111_0000), // Unused - .sf_addr(8'b1100_0000),.sf_mask(8'b1100_0000), // Unused - .dw(dw),.aw(aw),.sw(sw)) wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), - .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), - .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), - .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), - .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), - .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), - .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), - .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), - .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), - .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), - .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), - .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), - .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), - .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), - .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), - .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), - .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), - .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), - .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), - .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), - .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), - .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), - .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), - .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0)); - - ////////////////////////////////////////////////////////////////////////////////////////// - // Reset Controller - system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), - .ram_loader_rst_o(ram_loader_rst), - .wb_rst_o(wb_rst), - .ram_loader_done_i(ram_loader_done)); - - assign config_success = ram_loader_done; - reg takeover = 0; - - wire cpld_start_int, cpld_mode_int, cpld_done_int; - - always @(posedge wb_clk) - if(ram_loader_done) - takeover = 1; - assign cpld_misc = ~takeover; - - wire sd_clk, sd_csn, sd_mosi, sd_miso; - - assign sd_miso = cpld_din; - assign cpld_start = takeover ? sd_clk : cpld_start_int; - assign cpld_mode = takeover ? sd_csn : cpld_mode_int; - assign cpld_done = takeover ? sd_mosi : cpld_done_int; - - // /////////////////////////////////////////////////////////////////// - // RAM Loader - - wire [31:0] ram_loader_dat; - wire [15:0] ram_loader_adr; - wire [3:0] ram_loader_sel; - wire ram_loader_stb, ram_loader_we; - ram_loader #(.AWIDTH(aw),.RAM_SIZE(16384)) - ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst), - .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr), - .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel), - .wb_we(ram_loader_we), - .ram_loader_done(ram_loader_done), - // CPLD Interface - .cpld_clk(cpld_clk), - .cpld_din(cpld_din), - .cpld_start(cpld_start_int), - .cpld_mode(cpld_mode_int), - .cpld_done(cpld_done_int), - .cpld_detached(cpld_detached)); - - // ///////////////////////////////////////////////////////////////////////// - // Processor - - assign bus_error = m0_err | m0_rty; - - wire [63:0] zpu_status; - zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) - zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(ram_loader_done), - // Data Wishbone bus to system bus fabric - .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr), - .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), - // Interrupts and exceptions - .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); - - // ///////////////////////////////////////////////////////////////////////// - // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone - // I-port connects directly to processor and ram loader - - ram_harvard #(.AWIDTH(14),.RAM_SIZE(16384),.ICWIDTH(7),.DCWIDTH(6)) - sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - - .ram_loader_adr_i(ram_loader_adr[13:0]), .ram_loader_dat_i(ram_loader_dat), - .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), - .ram_loader_we_i(ram_loader_we), - .ram_loader_done_i(ram_loader_done), - - .if_adr(16'b0), .if_data(), - - .dwb_adr_i(s0_adr[13:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool, slave #1 - wire rd0_ready_i, rd0_ready_o; - wire rd1_ready_i, rd1_ready_o; - wire rd2_ready_i, rd2_ready_o; - wire rd3_ready_i, rd3_ready_o; - wire [35:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; - - wire wr0_ready_i, wr0_ready_o; - wire wr1_ready_i, wr1_ready_o; - wire wr2_ready_i, wr2_ready_o; - wire wr3_ready_i, wr3_ready_o; - wire [35:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - wire [35:0] tx_err_data; - wire tx_err_src_rdy, tx_err_dst_rdy; - - wire [31:0] router_debug; - - packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), - .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), - - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0), - - .status(status), .sys_int_o(buffer_int), .debug(router_debug), - - .ser_inp_data(wr0_dat), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), - .dsp0_inp_data(wr1_dat), .dsp0_inp_valid(wr1_ready_i), .dsp0_inp_ready(wr1_ready_o), - .dsp1_inp_data(wr3_dat), .dsp1_inp_valid(wr3_ready_i), .dsp1_inp_ready(wr3_ready_o), - .eth_inp_data(wr2_dat), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), - .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy), - - .ser_out_data(rd0_dat), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), - .dsp_out_data(rd1_dat), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), - .eth_out_data(rd2_dat), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) - ); - - // ///////////////////////////////////////////////////////////////////////// - // SPI -- Slave #2 - spi_top shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), - .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), - .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), - .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), - .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); - - // ///////////////////////////////////////////////////////////////////////// - // I2C -- Slave #3 - i2c_master_top #(.ARST_LVL(1)) - i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_dat_i[31:8] = 24'd0; - - // ///////////////////////////////////////////////////////////////////////// - // GPIOs -- Slave #4 - nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), - .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), - .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio({io_tx,io_rx}) ); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool Status -- Slave #5 - - //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd6; - - wb_readback_mux buff_pool_status - (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), - .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - - .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), - .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), - .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(compat_num),.word13(irq), - .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]) - ); - - // ///////////////////////////////////////////////////////////////////////// - // Ethernet MAC Slave #6 - - simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE), - .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper - (.clk125(clk_to_mac), .reset(wb_rst), - .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), - .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), - .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), - .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .sys_clk(dsp_clk), - .rx_f36_data(wr2_dat), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), - .tx_f36_data(rd2_dat), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), - .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), - .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), - .mdio(MDIO), .mdc(MDC), - .debug(debug_mac)); - - // ///////////////////////////////////////////////////////////////////////// - // Settings Bus -- Slave #7 - settings_bus settings_bus - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), - .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), - .strobe(set_stb),.addr(set_addr),.data(set_data)); - - assign s7_dat_i = 32'd0; - - settings_bus_crossclock settings_bus_crossclock - (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), - .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); - - // Output control lines - wire [7:0] clock_outs, serdes_outs, adc_outs; - assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; - assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; - assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; - - wire phy_reset; - assign PHY_RESETn = ~phy_reset; - - setting_reg #(.my_addr(SR_MISC+0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), - .in(set_data),.out(clock_outs),.changed()); - setting_reg #(.my_addr(SR_MISC+1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(serdes_outs),.changed()); - setting_reg #(.my_addr(SR_MISC+2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(adc_outs),.changed()); - setting_reg #(.my_addr(SR_MISC+4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phy_reset),.changed()); - - // ///////////////////////////////////////////////////////////////////////// - // LEDS - // register 8 determines whether leds are controlled by SW or not - // 1 = controlled by HW, 0 = by SW - // In Rev3 there are only 6 leds, and the highest one is on the ETH connector - - wire [7:0] led_src, led_sw; - wire [7:0] led_hw = {run_tx, (run_rx0_d1 | run_rx1_d1), clk_status, serdes_link_up, 1'b0}; - - setting_reg #(.my_addr(SR_MISC+3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_sw),.changed()); - - setting_reg #(.my_addr(SR_MISC+6),.width(8), .at_reset(8'b0001_1110)) - sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed()); - - assign leds = (led_src & led_hw) | (~led_src & led_sw); - - // ///////////////////////////////////////////////////////////////////////// - // Interrupt Controller, Slave #8 - - // Pass interrupts on dsp_clk to wb_clk. These need edge triggering in the pic - wire underrun_wb, overrun_wb, pps_wb; - - oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb)); - oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun0 | overrun1), .clk_out(wb_clk), .out(overrun_wb)); - oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb)); - - assign irq= {{8'b0}, - {8'b0}, - {3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, - {pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; - - pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), - .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), - .irq(irq) ); - - // ///////////////////////////////////////////////////////////////////////// - // Master Timer, Slave #9 - - // No longer used, replaced with simple_timer below - assign s9_ack = 0; - - // ///////////////////////////////////////////////////////////////////////// - // Simple Timer interrupts - - simple_timer #(.BASE(SR_SIMTIMER)) simple_timer - (.clk(wb_clk), .reset(wb_rst), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .onetime_int(onetime_int), .periodic_int(periodic_int)); - - // ///////////////////////////////////////////////////////////////////////// - // UART, Slave #10 - - simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries - (.clk_i(wb_clk),.rst_i(wb_rst), - .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), - .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), - .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), - .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); - - // ///////////////////////////////////////////////////////////////////////// - // ATR Controller, Slave #11 - - atr_controller atr_controller - (.clk_i(wb_clk),.rst_i(wb_rst), - .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), - .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), - .run_rx(run_rx0_d1 | run_rx1_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); - - // ////////////////////////////////////////////////////////////////////////// - // Time Sync, Slave #12 - - // No longer used, see time_64bit. Still need to handle mimo time, though - assign sc_ack = 0; - - // ///////////////////////////////////////////////////////////////////////// - // SD Card Reader / Writer, Slave #13 - - sd_spi_wb sd_spi_wb - (.clk(wb_clk),.rst(wb_rst), - .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), - .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we), - .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o[7:0]),.wb_dat_o(sd_dat_i[7:0]), - .wb_ack_o(sd_ack) ); - - assign sd_dat_i[31:8] = 0; - - // ///////////////////////////////////////////////////////////////////////// - // DSP RX 0 - wire [31:0] sample_rx0; - wire clear_rx0, strobe_rx0; - - always @(posedge dsp_clk) - run_rx0_d1 <= run_rx0; - - dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0 - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0), - .debug() ); - - setting_reg #(.my_addr(SR_RX_CTRL0+3)) sr_clear_rx0 - (.clk(dsp_clk),.rst(dsp_rst), - .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), - .out(),.changed(clear_rx0)); - - vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0 - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .vita_time(vita_time), .overrun(overrun0), - .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), - .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o), - .debug() ); - - // ///////////////////////////////////////////////////////////////////////// - // DSP RX 1 - wire [31:0] sample_rx1; - wire clear_rx1, strobe_rx1; - - always @(posedge dsp_clk) - run_rx1_d1 <= run_rx1; - - dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1), - .debug() ); - - setting_reg #(.my_addr(SR_RX_CTRL1+3)) sr_clear_rx1 - (.clk(dsp_clk),.rst(dsp_rst), - .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), - .out(),.changed(clear_rx1)); - - vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1 - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .vita_time(vita_time), .overrun(overrun1), - .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), - .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o), - .debug() ); - - // /////////////////////////////////////////////////////////////////////////////////// - // DSP TX - - wire [35:0] tx_data; - wire tx_src_rdy, tx_dst_rdy; - wire [31:0] debug_vt; - wire clear_tx; - - setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_tx)); - - ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(19)) - ext_fifo_i1 - (.int_clk(dsp_clk), - .ext_clk(clk_to_mac), - .rst(dsp_rst | clear_tx), - .RAM_D_pi(RAM_D_pi), - .RAM_D_po(RAM_D_po), - .RAM_D_poe(RAM_D_poe), - .RAM_A(RAM_A), - .RAM_WEn(RAM_WEn), - .RAM_CENn(RAM_CENn), - .RAM_LDn(RAM_LDn), - .RAM_OEn(RAM_OEn), - .RAM_CE1n(RAM_CE1n), - .datain(rd1_dat), - .src_rdy_i(rd1_ready_o), - .dst_rdy_o(rd1_ready_i), - .dataout(tx_data), - .src_rdy_o(tx_src_rdy), - .dst_rdy_i(tx_dst_rdy), - .debug(debug_extfifo), - .debug2(debug_extfifo2) ); - - vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), - .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), - .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), - .DSP_NUMBER(0)) - vita_tx_chain - (.clk(dsp_clk), .reset(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .vita_time(vita_time), - .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), - .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), - .dac_a(dac_a),.dac_b(dac_b), - .underrun(underrun), .run(run_tx), - .debug(debug_vt)); - - // /////////////////////////////////////////////////////////////////////////////////// - // SERDES - - serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes - (.clk(dsp_clk),.rst(dsp_rst), - .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .rd_dat_i(rd0_dat[31:0]),.rd_flags_i(rd0_dat[35:32]),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), - .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .wr_dat_o(wr0_dat[31:0]),.wr_flags_o(wr0_dat[35:32]),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), - .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), - .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), - .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); - - assign RAM_CLK = clk_to_mac; - - // ///////////////////////////////////////////////////////////////////////// - // VITA Timing - - wire [31:0] debug_sync; - - time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit - (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), - .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), - .debug(debug_sync)); - - // ///////////////////////////////////////////////////////////////////////////////////////// - // Debug Pins - - assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; - assign debug = 32'd0; - assign debug_gpio_0 = 32'd0; - assign debug_gpio_1 = 32'd0; - -endmodule // u2_core diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf deleted file mode 100644 index 8017f61ff..000000000 --- a/usrp2/top/u2_rev3/u2_rev3.ucf +++ /dev/null @@ -1,336 +0,0 @@ -NET "leds[0]" LOC = "E8" ; -NET "leds[1]" LOC = "F7" ; -NET "leds[2]" LOC = "E5" ; -NET "leds[3]" LOC = "B7" ; -NET "leds[4]" LOC = "C11" ; -NET "leds[5]" LOC = "AB19" ; -NET "debug[0]" LOC = "N5" ; -NET "debug[1]" LOC = "N6" ; -NET "debug[2]" LOC = "P1" ; -NET "debug[3]" LOC = "P2" ; -NET "debug[4]" LOC = "P4" ; -NET "debug[5]" LOC = "P5" ; -NET "debug[6]" LOC = "R1" ; -NET "debug[7]" LOC = "R2" ; -NET "debug[8]" LOC = "P6" ; -NET "debug[9]" LOC = "R5" ; -NET "debug[10]" LOC = "R4" ; -NET "debug[11]" LOC = "T3" ; -NET "debug[12]" LOC = "U3" ; -NET "debug[13]" LOC = "M2" ; -NET "debug[14]" LOC = "M3" ; -NET "debug[15]" LOC = "M4" ; -NET "debug[16]" LOC = "M5" ; -NET "debug[17]" LOC = "M6" ; -NET "debug[18]" LOC = "N1" ; -NET "debug[19]" LOC = "N2" ; -NET "debug[20]" LOC = "N3" ; -NET "debug[21]" LOC = "T1" ; -NET "debug[22]" LOC = "T2" ; -NET "debug[23]" LOC = "U2" ; -NET "debug[24]" LOC = "T4" ; -NET "debug[25]" LOC = "U4" ; -NET "debug[26]" LOC = "T5" ; -NET "debug[27]" LOC = "T6" ; -NET "debug[28]" LOC = "U5" ; -NET "debug[29]" LOC = "V5" ; -NET "debug[30]" LOC = "W2" ; -NET "debug[31]" LOC = "W3" ; -NET "debug_clk[0]" LOC = "N4" ; -NET "debug_clk[1]" LOC = "M1" ; -NET "uart_tx_o" LOC = "C7" ; -NET "uart_rx_i" LOC = "A3" ; -NET "exp_time_in_p" LOC = "V3" ; -NET "exp_time_in_n" LOC = "V4" ; -NET "exp_time_out_p" LOC = "V1" ; -NET "exp_time_out_n" LOC = "V2" ; -NET "GMII_COL" LOC = "U16" ; -NET "GMII_CRS" LOC = "U17" ; -NET "GMII_TXD[0]" LOC = "W14" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[1]" LOC = "AA20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[2]" LOC = "AB20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[3]" LOC = "Y18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[4]" LOC = "AA18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[5]" LOC = "AB18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[6]" LOC = "V17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TXD[7]" LOC = "W17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TX_EN" LOC = "Y17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TX_ER" LOC = "V16" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_GTX_CLK" LOC = "AA17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "GMII_TX_CLK" LOC = "W13" ; -NET "GMII_RXD[0]" LOC = "AA15" ; -NET "GMII_RXD[1]" LOC = "AB15" ; -NET "GMII_RXD[2]" LOC = "U14" ; -NET "GMII_RXD[3]" LOC = "V14" ; -NET "GMII_RXD[4]" LOC = "U13" ; -NET "GMII_RXD[5]" LOC = "V13" ; -NET "GMII_RXD[6]" LOC = "Y13" ; -NET "GMII_RXD[7]" LOC = "AA13" ; -NET "GMII_RX_CLK" LOC = "AA12" ; -NET "GMII_RX_DV" LOC = "AB16" ; -NET "GMII_RX_ER" LOC = "AA16" ; -NET "MDIO" LOC = "Y16" |PULLUP ; -NET "MDC" LOC = "V18" ; -NET "PHY_INTn" LOC = "AB13" ; -NET "PHY_RESETn" LOC = "AA19" ; -NET "PHY_CLK" LOC = "V15" ; -NET "RAM_D[0]" LOC = "N20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[1]" LOC = "N21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[2]" LOC = "N22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[3]" LOC = "M17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[4]" LOC = "M18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[5]" LOC = "M19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[6]" LOC = "M20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[7]" LOC = "M21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[8]" LOC = "M22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[9]" LOC = "Y22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[10]" LOC = "Y21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[11]" LOC = "Y20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[12]" LOC = "Y19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[13]" LOC = "W22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[14]" LOC = "W21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[15]" LOC = "W20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[16]" LOC = "W19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_D[17]" LOC = "V22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[0]" LOC = "U21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[1]" LOC = "T19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[2]" LOC = "V21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[3]" LOC = "V20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[4]" LOC = "T20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[5]" LOC = "T21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[6]" LOC = "T22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[7]" LOC = "T18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[8]" LOC = "R18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[9]" LOC = "P19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[10]" LOC = "P21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[11]" LOC = "P22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[12]" LOC = "N19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[13]" LOC = "N17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[14]" LOC = "N18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[15]" LOC = "T17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[16]" LOC = "U19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[17]" LOC = "U18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_A[18]" LOC = "V19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_CE1n" LOC = "U20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_CENn" LOC = "P18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_CLK" LOC = "P17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_WEn" LOC = "R22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_OEn" LOC = "R21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "RAM_LDn" LOC = "R19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_enable" LOC = "W11" ; -NET "ser_prbsen" LOC = "AA3" ; -NET "ser_loopen" LOC = "Y4" ; -NET "ser_rx_en" LOC = "AB9" ; -NET "ser_tx_clk" LOC = "U7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[0]" LOC = "V7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[1]" LOC = "V10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[2]" LOC = "AB4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[3]" LOC = "AA4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[4]" LOC = "Y5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[5]" LOC = "W5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[6]" LOC = "AB5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[7]" LOC = "AA5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[8]" LOC = "W6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[9]" LOC = "V6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[10]" LOC = "AA6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[11]" LOC = "Y6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[12]" LOC = "W8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[13]" LOC = "V8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[14]" LOC = "AB8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_t[15]" LOC = "AA8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_tklsb" LOC = "U10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_tkmsb" LOC = "U11" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; -NET "ser_rx_clk" LOC = "AA11" ; -NET "ser_r[0]" LOC = "AB10" ; -NET "ser_r[1]" LOC = "AA10" ; -NET "ser_r[2]" LOC = "U9" ; -NET "ser_r[3]" LOC = "U6" ; -NET "ser_r[4]" LOC = "AB11" ; -NET "ser_r[5]" LOC = "Y7" ; -NET "ser_r[6]" LOC = "W7" ; -NET "ser_r[7]" LOC = "AB7" ; -NET "ser_r[8]" LOC = "AA7" ; -NET "ser_r[9]" LOC = "W9" ; -NET "ser_r[10]" LOC = "W10" ; -NET "ser_r[11]" LOC = "Y1" ; -NET "ser_r[12]" LOC = "Y3" ; -NET "ser_r[13]" LOC = "Y2" ; -NET "ser_r[14]" LOC = "W4" ; -NET "ser_r[15]" LOC = "W1" ; -NET "ser_rklsb" LOC = "V9" ; -NET "ser_rkmsb" LOC = "Y10" ; -NET "cpld_start" LOC = "AA9" ; -NET "cpld_mode" LOC = "U12" ; -NET "cpld_done" LOC = "V12" ; -NET "cpld_din" LOC = "AA14" ; -NET "cpld_clk" LOC = "AB14" ; -NET "cpld_detached" LOC = "V11" ; -NET "cpld_init_b" LOC = "W12" ; -NET "cpld_misc" LOC = "Y12" ; -NET "POR" LOC = "W18" ; -NET "WDI" LOC = "W15" ; -NET "adc_a[0]" LOC = "A14" | IOBDELAY= "NONE" ; -NET "adc_a[1]" LOC = "B14" | IOBDELAY= "NONE" ; -NET "adc_a[2]" LOC = "C13" | IOBDELAY= "NONE" ; -NET "adc_a[3]" LOC = "D13" | IOBDELAY= "NONE" ; -NET "adc_a[4]" LOC = "A13" | IOBDELAY= "NONE" ; -NET "adc_a[5]" LOC = "B13" | IOBDELAY= "NONE" ; -NET "adc_a[6]" LOC = "E12" | IOBDELAY= "NONE" ; -NET "adc_a[7]" LOC = "C22" | IOBDELAY= "NONE" ; -NET "adc_a[8]" LOC = "C20" | IOBDELAY= "NONE" ; -NET "adc_a[9]" LOC = "C21" | IOBDELAY= "NONE" ; -NET "adc_a[10]" LOC = "D20" | IOBDELAY= "NONE" ; -NET "adc_a[11]" LOC = "D19" | IOBDELAY= "NONE" ; -NET "adc_a[12]" LOC = "D21" | IOBDELAY= "NONE" ; -NET "adc_a[13]" LOC = "E18" | IOBDELAY= "NONE" ; -NET "adc_ovf_a" LOC = "F18" ; -NET "adc_oen_a" LOC = "E19" ; -NET "adc_pdn_a" LOC = "E20" ; -NET "adc_b[0]" LOC = "A12" | IOBDELAY= "NONE"; -NET "adc_b[1]" LOC = "E16" | IOBDELAY= "NONE" ; -NET "adc_b[2]" LOC = "F12" | IOBDELAY= "NONE" ; -NET "adc_b[3]" LOC = "F13" | IOBDELAY= "NONE" ; -NET "adc_b[4]" LOC = "F16" | IOBDELAY= "NONE" ; -NET "adc_b[5]" LOC = "F17" | IOBDELAY= "NONE" ; -NET "adc_b[6]" LOC = "C19" | IOBDELAY= "NONE" ; -NET "adc_b[7]" LOC = "B20" | IOBDELAY= "NONE" ; -NET "adc_b[8]" LOC = "B19" | IOBDELAY= "NONE" ; -NET "adc_b[9]" LOC = "C18" | IOBDELAY= "NONE" ; -NET "adc_b[10]" LOC = "D18" | IOBDELAY= "NONE" ; -NET "adc_b[11]" LOC = "B18" | IOBDELAY= "NONE" ; -NET "adc_b[12]" LOC = "D17" | IOBDELAY= "NONE" ; -NET "adc_b[13]" LOC = "E17" | IOBDELAY= "NONE" ; -NET "adc_ovf_b" LOC = "B17" ; -NET "adc_oen_b" LOC = "C17" ; -NET "adc_pdn_b" LOC = "D15" ; -NET "dac_a[0]" LOC = "A5" ; -NET "dac_a[1]" LOC = "B5" ; -NET "dac_a[2]" LOC = "C5" ; -NET "dac_a[3]" LOC = "D5" ; -NET "dac_a[4]" LOC = "A4" ; -NET "dac_a[5]" LOC = "B4" ; -NET "dac_a[6]" LOC = "F6" ; -NET "dac_a[7]" LOC = "D10" ; -NET "dac_a[8]" LOC = "D9" ; -NET "dac_a[9]" LOC = "A10" ; -NET "dac_a[10]" LOC = "L2" ; -NET "dac_a[11]" LOC = "L4" ; -NET "dac_a[12]" LOC = "L3" ; -NET "dac_a[13]" LOC = "L6" ; -NET "dac_a[14]" LOC = "L5" ; -NET "dac_a[15]" LOC = "K2" ; -NET "dac_b[0]" LOC = "D11" ; -NET "dac_b[1]" LOC = "E11" ; -NET "dac_b[2]" LOC = "F11" ; -NET "dac_b[3]" LOC = "B10" ; -NET "dac_b[4]" LOC = "C10" ; -NET "dac_b[5]" LOC = "E10" ; -NET "dac_b[6]" LOC = "F10" ; -NET "dac_b[7]" LOC = "A9" ; -NET "dac_b[8]" LOC = "B9" ; -NET "dac_b[9]" LOC = "E9" ; -NET "dac_b[10]" LOC = "F9" ; -NET "dac_b[11]" LOC = "A8" ; -NET "dac_b[12]" LOC = "B8" ; -NET "dac_b[13]" LOC = "D7" ; -NET "dac_b[14]" LOC = "E7" ; -NET "dac_b[15]" LOC = "B6" ; -NET "dac_lock" LOC = "D6" ; -NET "SCL" LOC = "A7" ; -NET "SDA" LOC = "D8" ; -NET "clk_en[0]" LOC = "C4" ; -NET "clk_en[1]" LOC = "D1" ; -NET "clk_sel[0]" LOC = "C3" ; -NET "clk_sel[1]" LOC = "C2" ; -NET "clk_func" LOC = "C12" ; -NET "clk_status" LOC = "B12" ; -NET "clk_fpga_p" LOC = "A11" ; -NET "clk_fpga_n" LOC = "B11" ; -NET "clk_to_mac" LOC = "AB12" ; -NET "pps_in" LOC = "K1" ; -NET "sclk" LOC = "K5" ; -NET "sen_clk" LOC = "K6" ; -NET "sen_dac" LOC = "L1" ; -NET "sdi" LOC = "J1" ; -NET "sdo" LOC = "J2" ; -NET "sen_tx_db" LOC = "C1" ; -NET "sclk_tx_db" LOC = "D3" ; -NET "sdo_tx_db" LOC = "G3" ; -NET "sdi_tx_db" LOC = "G4" ; -NET "sen_tx_adc" LOC = "G2" ; -NET "sclk_tx_adc" LOC = "H1" ; -NET "sdo_tx_adc" LOC = "H2" ; -NET "sdi_tx_adc" LOC = "J4" ; -NET "sen_tx_dac" LOC = "H4" ; -NET "sclk_tx_dac" LOC = "J5" ; -NET "sdi_tx_dac" LOC = "J6" ; -NET "io_tx[0]" LOC = "K4" ; -NET "io_tx[1]" LOC = "K3" ; -NET "io_tx[2]" LOC = "G1" ; -NET "io_tx[3]" LOC = "G5" ; -NET "io_tx[4]" LOC = "H5" ; -NET "io_tx[5]" LOC = "F3" ; -NET "io_tx[6]" LOC = "F2" ; -NET "io_tx[7]" LOC = "F5" ; -NET "io_tx[8]" LOC = "G6" ; -NET "io_tx[9]" LOC = "E2" ; -NET "io_tx[10]" LOC = "E1" ; -NET "io_tx[11]" LOC = "E3" ; -NET "io_tx[12]" LOC = "F4" ; -NET "io_tx[13]" LOC = "D2" ; -NET "io_tx[14]" LOC = "D4" ; -NET "io_tx[15]" LOC = "E4" ; -NET "sen_rx_db" LOC = "D22" ; -NET "sclk_rx_db" LOC = "F19" ; -NET "sdo_rx_db" LOC = "G20" ; -NET "sdi_rx_db" LOC = "H19" ; -NET "sen_rx_adc" LOC = "H18" ; -NET "sclk_rx_adc" LOC = "J17" ; -NET "sdo_rx_adc" LOC = "H21" ; -NET "sdi_rx_adc" LOC = "H22" ; -NET "sen_rx_dac" LOC = "J18" ; -NET "sclk_rx_dac" LOC = "J19" ; -NET "sdi_rx_dac" LOC = "J21" ; -NET "io_rx[0]" LOC = "L21" ; -NET "io_rx[1]" LOC = "L20" ; -NET "io_rx[2]" LOC = "L19" ; -NET "io_rx[3]" LOC = "L18" ; -NET "io_rx[4]" LOC = "L17" ; -NET "io_rx[5]" LOC = "K22" ; -NET "io_rx[6]" LOC = "K21" ; -NET "io_rx[7]" LOC = "K20" ; -NET "io_rx[8]" LOC = "G22" ; -NET "io_rx[9]" LOC = "G21" ; -NET "io_rx[10]" LOC = "F21" ; -NET "io_rx[11]" LOC = "F20" ; -NET "io_rx[12]" LOC = "G19" ; -NET "io_rx[13]" LOC = "G18" ; -NET "io_rx[14]" LOC = "G17" ; -NET "io_rx[15]" LOC = "E22" ; - -NET "clk_to_mac" TNM_NET = "clk_to_mac"; -TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; - -NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; -TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; - -NET "cpld_clk" TNM_NET = "cpld_clk"; -TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %; - -NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; -TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; - -NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; -TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; - -NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE; -NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; - -#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; -#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; -#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; - -#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; -#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; - -TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns; diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v deleted file mode 100644 index bc7ae5f16..000000000 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ /dev/null @@ -1,572 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module u2_rev3 - ( - // Misc, debug - output [5:0] leds, - output [31:0] debug, - output [1:0] debug_clk, - output uart_tx_o, - input uart_rx_i, - - // Expansion - input exp_time_in_p, // Diff - input exp_time_in_n, // Diff - output exp_time_out_p, // Diff - output exp_time_out_n, // Diff - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output reg [7:0] GMII_TXD, - output reg GMII_TX_EN, - output reg GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - output PHY_RESETn, - input PHY_CLK, // possibly use on-board osc - - // RAM - inout [17:0] RAM_D, - output [18:0] RAM_A, - output RAM_CE1n, - output RAM_CENn, - output RAM_CLK, - output RAM_WEn, - output RAM_OEn, - output RAM_LDn, - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output reg [15:0] ser_t, - output reg ser_tklsb, - output reg ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // CPLD interface - output cpld_start, // AA9 - output cpld_mode, // U12 - output cpld_done, // V12 - input cpld_din, // AA14 Now shared with CFG_Din - input cpld_clk, // AB14 serial clock - input cpld_detached,// V11 unused - output cpld_init_b, // W12 unused dual purpose - output cpld_misc, // Y12 - - // Watchdog interface - input POR, - output WDI, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_oen_a, - output adc_pdn_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_oen_b, - output adc_pdn_b, - - // DAC - output reg [15:0] dac_a, - output reg [15:0] dac_b, - input dac_lock, // unused for now - - // I2C - inout SCL, - inout SDA, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Clocks - input clk_fpga_p, // Diff - input clk_fpga_n, // Diff - input clk_to_mac, - input pps_in, - - // Generic SPI - output sclk, - output sen_clk, - output sen_dac, - output sdi, - input sdo, - - // TX DBoard - output sen_tx_db, - output sclk_tx_db, - input sdo_tx_db, - output sdi_tx_db, - - output sen_tx_adc, - output sclk_tx_adc, - input sdo_tx_adc, - output sdi_tx_adc, - - output sen_tx_dac, - output sclk_tx_dac, - output sdi_tx_dac, - - inout [15:0] io_tx, - - // RX DBoard - output sen_rx_db, - output sclk_rx_db, - input sdo_rx_db, - output sdi_rx_db, - - output sen_rx_adc, - output sclk_rx_adc, - input sdo_rx_adc, - output sdi_rx_adc, - - output sen_rx_dac, - output sclk_rx_dac, - output sdi_rx_dac, - - inout [15:0] io_rx - ); - - assign cpld_init_b = 0; - // FPGA-specific pins connections - wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; - wire clk90, clk180, clk270; - - // reset the watchdog continuously - reg [15:0] wd; - wire config_success; - - always @(posedge wb_clk) - if(~config_success) - wd <= 0; - else - wd <= wd + 1; - assign WDI = wd[15]; - - wire clk_fpga_unbuf; - - IBUFGDS clk_fpga_pin (.O(clk_fpga_unbuf),.I(clk_fpga_p),.IB(clk_fpga_n)); - BUFG clk_fpga_BUF (.O(clk_fpga),.I(clk_fpga_unbuf)); - - defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; - - wire cpld_clock_buf; - BUFG cpld_clock_BUF (.O(cpld_clock_buf),.I(cpld_clock)); - - wire exp_time_in; - IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); - defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; - - wire exp_time_out; - OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); - defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; - - reg [5:0] clock_ready_d; - always @(posedge clk_fpga) - clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; - wire dcm_rst = ~&clock_ready_d & |clock_ready_d; - - wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b; - assign adc_oen_a = ~adc_oe_a; - assign adc_oen_b = ~adc_oe_b; - assign adc_pdn_a = ~adc_on_a; - assign adc_pdn_b = ~adc_on_b; - - reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2; - reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2; - - // ADC A and B are swapped in schematic to facilitate clean layout - always @(posedge dsp_clk) - begin - adc_a_reg1 <= adc_b; - adc_b_reg1 <= adc_a; - adc_ovf_a_reg1 <= adc_ovf_b; - adc_ovf_b_reg1 <= adc_ovf_a; - end - - always @(posedge dsp_clk) - begin - adc_a_reg2 <= adc_a_reg1; - adc_b_reg2 <= adc_b_reg1; - adc_ovf_a_reg2 <= adc_ovf_a_reg1; - adc_ovf_b_reg2 <= adc_ovf_b_reg1; - end // always @ (posedge dsp_clk) - - // Handle Clocks - DCM DCM_INST (.CLKFB(dsp_clk), - .CLKIN(clk_fpga), - .DSSEN(0), - .PSCLK(0), - .PSEN(0), - .PSINCDEC(0), - .RST(dcm_rst), - .CLKDV(clk_div), - .CLKFX(), - .CLKFX180(), - .CLK0(dcm_out), - .CLK2X(), - .CLK2X180(), - .CLK90(clk90), - .CLK180(clk180), - .CLK270(clk270), - .LOCKED(LOCKED_OUT), - .PSDONE(), - .STATUS()); - defparam DCM_INST.CLK_FEEDBACK = "1X"; - defparam DCM_INST.CLKDV_DIVIDE = 2.0; - defparam DCM_INST.CLKFX_DIVIDE = 1; - defparam DCM_INST.CLKFX_MULTIPLY = 4; - defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; - defparam DCM_INST.CLKIN_PERIOD = 10.000; - defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; - defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; - defparam DCM_INST.FACTORY_JF = 16'h8080; - defparam DCM_INST.PHASE_SHIFT = 0; - defparam DCM_INST.STARTUP_WAIT = "FALSE"; - - BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); - BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); - - // I2C -- Don't use external transistors for open drain, the FPGA implements this - IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); - IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); - - // LEDs are active low outputs - wire [5:0] leds_int; - assign leds = 6'b011111 ^ leds_int; // all except eth are active-low - - // SPI - wire miso, mosi, sclk_int; - assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0; - - assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) | - (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) | - (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc); - - wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; - wire [7:0] GMII_TXD_unreg; - wire GMII_GTX_CLK_int; - - always @(posedge GMII_GTX_CLK_int) - begin - GMII_TX_EN <= GMII_TX_EN_unreg; - GMII_TX_ER <= GMII_TX_ER_unreg; - GMII_TXD <= GMII_TXD_unreg; - end - - OFDDRRSE OFDDRRSE_gmii_inst - (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) - .C0(GMII_GTX_CLK_int), // 0 degree clock input - .C1(~GMII_GTX_CLK_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - - wire ser_tklsb_unreg, ser_tkmsb_unreg; - wire [15:0] ser_t_unreg; - wire ser_tx_clk_int; - - always @(posedge ser_tx_clk_int) - begin - ser_tklsb <= ser_tklsb_unreg; - ser_tkmsb <= ser_tkmsb_unreg; - ser_t <= ser_t_unreg; - end - - assign ser_tx_clk = clk_fpga; - - reg [15:0] ser_r_int; - reg ser_rklsb_int, ser_rkmsb_int; - - wire ser_rx_clk_buf; - BUFG ser_rx_clk_BUF (.O(ser_rx_clk_buf),.I(ser_rx_clk)); - always @(posedge ser_rx_clk_buf) - begin - ser_r_int <= ser_r; - ser_rklsb_int <= ser_rklsb; - ser_rkmsb_int <= ser_rkmsb; - end - - wire [15:0] dac_a_int, dac_b_int; - // DAC A and B are swapped in schematic to facilitate clean layout - // DAC A is also inverted in schematic to facilitate clean layout - always @(posedge dsp_clk) dac_a <= ~dac_b_int; - always @(posedge dsp_clk) dac_b <= dac_a_int; - - /* - OFDDRRSE OFDDRRSE_serdes_inst - (.Q(ser_tx_clk), // Data output (connect directly to top-level port) - .C0(ser_tx_clk_int), // 0 degree clock input - .C1(~ser_tx_clk_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - */ - - wire [17:0] RAM_D_pi; - wire [17:0] RAM_D_po; - wire RAM_D_poe; - - genvar i; - - // - // Instantiate IO for Bidirectional bus to SRAM - // - - generate - for (i=0;i<18;i=i+1) - begin : gen_RAM_D_IO - - IOBUF #( - .DRIVE(12), - .IOSTANDARD("LVCMOS25"), - .SLEW("FAST") - ) - RAM_D_i ( - .O(RAM_D_pi[i]), - .I(RAM_D_po[i]), - .IO(RAM_D[i]), - .T(RAM_D_poe) - ); - end // block: gen_RAM_D_IO - endgenerate - - // - // DCM edits start here - // - - - wire RAM_CLK_buf; - wire clk_to_mac_buf; - wire clk125_ext_clk0; - wire clk125_ext_clk180; - wire clk125_ext_clk0_buf; - wire clk125_ext_clk180_buf; - wire clk125_int_buf; - wire clk125_int; - - IBUFG clk_to_mac_buf_i1 (.I(clk_to_mac), - .O(clk_to_mac_buf)); - - DCM DCM_INST1 (.CLKFB(RAM_CLK_buf), - .CLKIN(clk_to_mac_buf), - .DSSEN(1'b0), - .PSCLK(1'b0), - .PSEN(1'b0), - .PSINCDEC(1'b0), - .RST(1'b0), - .CLK0(clk125_ext_clk0), - .CLK180(clk125_ext_clk180) ); - defparam DCM_INST1.CLK_FEEDBACK = "1X"; - defparam DCM_INST1.CLKDV_DIVIDE = 2.0; - defparam DCM_INST1.CLKFX_DIVIDE = 1; - defparam DCM_INST1.CLKFX_MULTIPLY = 4; - defparam DCM_INST1.CLKIN_DIVIDE_BY_2 = "FALSE"; - defparam DCM_INST1.CLKIN_PERIOD = 8.000; - defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "FIXED"; - defparam DCM_INST1.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - defparam DCM_INST1.DFS_FREQUENCY_MODE = "LOW"; - defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW"; - defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE"; - defparam DCM_INST1.FACTORY_JF = 16'h8080; - defparam DCM_INST1.PHASE_SHIFT = -64; - defparam DCM_INST1.STARTUP_WAIT = "FALSE"; - - IBUFG RAM_CLK_buf_i1 (.I(RAM_CLK), - .O(RAM_CLK_buf)); - BUFG clk125_ext_clk0_buf_i1 (.I(clk125_ext_clk0), - .O(clk125_ext_clk0_buf)); - BUFG clk125_ext_clk180_buf_i1 (.I(clk125_ext_clk180), - .O(clk125_ext_clk180_buf)); - - OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK), - .C0(clk125_ext_clk0_buf), - .C1(clk125_ext_clk180_buf), - .CE(1'b1), - .D0(1'b1), - .D1(1'b0), - .R(1'b0), - .S(1'b0)); - -// SRL16 dcm2_rst_i1 (.D(1'b0), -// .CLK(clk_to_mac_buf), -// .Q(dcm2_rst), -// .A0(1'b1), -// .A1(1'b1), -// .A2(1'b1), -// .A3(1'b1)); - // synthesis attribute init of dcm2_rst_i1 is "000F"; - - DCM DCM_INST2 (.CLKFB(clk125_int_buf), - .CLKIN(clk_to_mac_buf), - .DSSEN(1'b0), - .PSCLK(1'b0), - .PSEN(1'b0), - .PSINCDEC(1'b0), - .RST(1'b0), - .CLK0(clk125_int)); - defparam DCM_INST2.CLK_FEEDBACK = "1X"; - defparam DCM_INST2.CLKDV_DIVIDE = 2.0; - defparam DCM_INST2.CLKFX_DIVIDE = 1; - defparam DCM_INST2.CLKFX_MULTIPLY = 4; - defparam DCM_INST2.CLKIN_DIVIDE_BY_2 = "FALSE"; - defparam DCM_INST2.CLKIN_PERIOD = 8.000; - defparam DCM_INST2.CLKOUT_PHASE_SHIFT = "NONE"; - defparam DCM_INST2.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - defparam DCM_INST2.DFS_FREQUENCY_MODE = "LOW"; - defparam DCM_INST2.DLL_FREQUENCY_MODE = "LOW"; - defparam DCM_INST2.DUTY_CYCLE_CORRECTION = "TRUE"; - defparam DCM_INST2.FACTORY_JF = 16'h8080; - defparam DCM_INST2.PHASE_SHIFT = 0; - defparam DCM_INST2.STARTUP_WAIT = "FALSE"; - - BUFG clk125_int_buf_i1 (.I(clk125_int), - .O(clk125_int_buf)); - - // - // DCM edits end here - // - - - u2_core - u2_core(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk125_int_buf), - .pps_in (pps_in), - .leds (leds_int), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_time_in (exp_time_in), - .exp_time_out (exp_time_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD_unreg[7:0]), - .GMII_TX_EN (GMII_TX_EN_unreg), - .GMII_TX_ER (GMII_TX_ER_unreg), - .GMII_GTX_CLK (GMII_GTX_CLK_int), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk_int), - .ser_t (ser_t_unreg[15:0]), - .ser_tklsb (ser_tklsb_unreg), - .ser_tkmsb (ser_tkmsb_unreg), - .ser_rx_clk (ser_rx_clk_buf), - .ser_r (ser_r_int[15:0]), - .ser_rklsb (ser_rklsb_int), - .ser_rkmsb (ser_rkmsb_int), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .cpld_misc (cpld_misc), - .cpld_init_b (cpld_init_b), - .por (~POR), - .config_success (config_success), - .adc_a (adc_a_reg2), - .adc_ovf_a (adc_ovf_a_reg2), - .adc_on_a (adc_on_a), - .adc_oe_a (adc_oe_a), - .adc_b (adc_b_reg2), - .adc_ovf_b (adc_ovf_b_reg2), - .adc_on_b (adc_on_b), - .adc_oe_b (adc_oe_b), - .dac_a (dac_a_int), - .dac_b (dac_b_int), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk_int), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D_pi (RAM_D_pi), - .RAM_D_po (RAM_D_po), - .RAM_D_poe (RAM_D_poe), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - // .RAM_CLK (RAM_CLK), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (uart_tx_o), - .uart_rx_i (uart_rx_i), - .uart_baud_o (), - .sim_mode (1'b0), - .clock_divider (2) - ); - -endmodule // u2_rev2 diff --git a/usrp2/top/u2plus/.gitignore b/usrp2/top/u2plus/.gitignore deleted file mode 100644 index 1b2211df0..000000000 --- a/usrp2/top/u2plus/.gitignore +++ /dev/null @@ -1 +0,0 @@ -build* diff --git a/usrp2/top/u2plus/Makefile.N200R3 b/usrp2/top/u2plus/Makefile.N200R3 deleted file mode 100644 index a525836ed..000000000 --- a/usrp2/top/u2plus/Makefile.N200R3 +++ /dev/null @@ -1,98 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = u2plus -BUILD_DIR = $(abspath build$(ISE)-N200R3) - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../extramfifo/Makefile.srcs - - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd1800a \ -package fg676 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -u2plus_core.v \ -u2plus.v \ -u2plus.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/u2plus/Makefile.N200R4 b/usrp2/top/u2plus/Makefile.N200R4 deleted file mode 100644 index 955aadc59..000000000 --- a/usrp2/top/u2plus/Makefile.N200R4 +++ /dev/null @@ -1,100 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = u2plus -BUILD_DIR = $(abspath build$(ISE)-N200R4) - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../extramfifo/Makefile.srcs - - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd1800a \ -package fg676 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -rev4_defs.v \ -capture_ddrlvds.v \ -u2plus_core.v \ -u2plus.v \ -u2plus.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/u2plus/Makefile.N210R3 b/usrp2/top/u2plus/Makefile.N210R3 deleted file mode 100644 index e29251e1c..000000000 --- a/usrp2/top/u2plus/Makefile.N210R3 +++ /dev/null @@ -1,98 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = u2plus -BUILD_DIR = $(abspath build$(ISE)-N210R3) - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../extramfifo/Makefile.srcs - - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd3400a \ -package fg676 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -u2plus_core.v \ -u2plus.v \ -u2plus.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/u2plus/Makefile.N210R4 b/usrp2/top/u2plus/Makefile.N210R4 deleted file mode 100644 index 73747e544..000000000 --- a/usrp2/top/u2plus/Makefile.N210R4 +++ /dev/null @@ -1,100 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = u2plus -BUILD_DIR = $(abspath build$(ISE)-N210R4) - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../extramfifo/Makefile.srcs - - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd3400a \ -package fg676 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -rev4_defs.v \ -capture_ddrlvds.v \ -u2plus_core.v \ -u2plus.v \ -u2plus.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/u2plus/bootloader.rmi b/usrp2/top/u2plus/bootloader.rmi deleted file mode 100644 index e5be670fb..000000000 --- a/usrp2/top/u2plus/bootloader.rmi +++ /dev/null @@ -1,512 +0,0 @@ -defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_d6cd0400_3a0b0b80_80e29c0c_82700b0b_0b0b0b0b; -defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_80d7972d_88080b0b_80088408; -defparam bootram.RAM0.INIT_02=256'h00000000_00000000_04000000_ffff0652_832b2a83_81058205_72830609_71fd0608; -defparam bootram.RAM0.INIT_03=256'h83a70400_0b0b0b0b_7383ffff_2b2b0906_05820583_83060981_83ffff73_71fd0608; -defparam bootram.RAM0.INIT_04=256'h00000000_00000000_53510400_070a8106_73097306_09060906_72057373_72098105; -defparam bootram.RAM0.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722473; -defparam bootram.RAM0.INIT_06=256'h00000000_53510400_81065151_0a31050a_0a720a10_30720a10_71068106_71737109; -defparam bootram.RAM0.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722673; -defparam bootram.RAM0.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM0.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_c4040000_0b0b0b88; -defparam bootram.RAM0.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_0a535104_720a722b; -defparam bootram.RAM0.INIT_0B=256'h00000000_00000000_00000000_00000000_05040000_0b0b88a7_0981050b_72729f06; -defparam bootram.RAM0.INIT_0C=256'h00000000_00000000_04000000_06075351_8106ff05_0974090a_739f062a_72722aff; -defparam bootram.RAM0.INIT_0D=256'h00000000_0c515104_0772fc06_832b0b2b_81058205_73830609_020d0406_71715351; -defparam bootram.RAM0.INIT_0E=256'h00000000_00000000_00000000_51040000_0a810653_81050906_72050970_72098105; -defparam bootram.RAM0.INIT_0F=256'h00000000_00000000_00000000_53510400_0a098106_81050906_72050970_72098105; -defparam bootram.RAM0.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_52040000_71098105; -defparam bootram.RAM0.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_04000000_05055351_72720981; -defparam bootram.RAM0.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_07535104_73730906_72097206; -defparam bootram.RAM0.INIT_13=256'h00000000_00000000_04000000_81ff0652_1010102a_81058305_72830609_71fc0608; -defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88aa0400_060b0b0b_10100508_88738306_0b0b80e2_71fc0608; -defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_ee2d5050_0b0b80cd_88087575_80088408; -defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_a02d5050_0b0b80cf_88087575_80088408; -defparam bootram.RAM0.INIT_17=256'h04000000_07515151_05ff0506_73097274_70547106_8106ff05_0509060a_72097081; -defparam bootram.RAM0.INIT_18=256'h51040000_06075151_7405ff05_06730972_05705471_098106ff_0509060a_72097081; -defparam bootram.RAM0.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_05ff0504; -defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_80e2980c_810b0b0b; -defparam bootram.RAM0.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_04000000_71810552; -defparam bootram.RAM0.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM0.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_04000000_10100552_02840572; -defparam bootram.RAM0.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM0.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_020d0400_05715351_717105ff; -defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_cf943f04_82813f80; -defparam bootram.RAM0.INIT_21=256'hfc060c51_102b0772_83051010_06098105_ff067383_51047381_10101053_10101010; -defparam bootram.RAM0.INIT_22=256'h51535104_72ed3851_0a100a53_71105272_09720605_8106ff05_72728072_51043c04; -defparam bootram.RAM0.INIT_23=256'h800b80e2_f40c82a0_0b0b80e2_8380800b_822ebd38_80e29c08_802ea438_80e29808; -defparam bootram.RAM0.INIT_24=256'h0b80e2f8_80808280_e2f40cf8_0b0b0b80_808080a4_fc0c04f8_800b80e2_f80c8290; -defparam bootram.RAM0.INIT_25=256'h940b80e2_80c0a880_80e2f40c_8c0b0b0b_80c0a880_e2fc0c04_84800b80_0cf88080; -defparam bootram.RAM0.INIT_26=256'h70085252_80e2a408_5170a738_80e38033_04ff3d0d_80e2fc0c_80d7c80b_f80c0b0b; -defparam bootram.RAM0.INIT_27=256'h8034833d_810b80e3_5270ee38_08700852_2d80e2a4_e2a40c70_38841280_70802e94; -defparam bootram.RAM0.INIT_28=256'h38823d0d_09810685_800b802e_0b0b0b0b_802e8e38_80e2f008_3d0d0b0b_0d040480; -defparam bootram.RAM0.INIT_29=256'h852eb238_5a798380_0d973d22_0404ee3d_3f823d0d_0b0bf5d4_e2f0510b_040b0b80; -defparam bootram.RAM0.INIT_2A=256'h5a953d22_819d3980_862e8f38_39798380_8e3881a7_8380842e_248b3879_79838085; -defparam bootram.RAM0.INIT_2B=256'h7053963d_f423923d_3d2280e4_39815a95_e4f8238a_953d2280_9539825a_80e4fc23; -defparam bootram.RAM0.INIT_2C=256'h7b1d7f1d_3d415e5c_0b883d99_5b5f4080_0284057b_ae3f8008_abdc3f8b_84055241; -defparam bootram.RAM0.INIT_2D=256'h79337b34_7d055b5b_7b1d963d_901f5e5c_ef38800b_5c887c26_7b34811c_5b5b7933; -defparam bootram.RAM0.INIT_2E=256'h7c26ef38_811c5c86_79337b34_601d5b5b_5e5c7b1d_800b881f_7c26ed38_811c5c88; -defparam bootram.RAM0.INIT_2F=256'h3d0d686a_3d0d04ee_9d903f94_7c26ef38_811c5c86_79337b34_611d5b5b_805c7b1e; -defparam bootram.RAM0.INIT_30=256'ha23f80e1_d7cc5198_538a5280_2e8f3875_0856758a_27973876_5a578379_8412085a; -defparam bootram.RAM0.INIT_31=256'h9f185675_17085dff_5ba05c88_3fa0588a_9c51988f_a45280d8_8e387853_5878a326; -defparam bootram.RAM0.INIT_32=256'h39951733_085e82f2_cc3f8008_80c15c8a_56750804_80da8c05_38758429_95268388; -defparam bootram.RAM0.INIT_33=256'h55961733_5a515677_2a848006_70307096_3380f232_92389417_7580f22e_56888058; -defparam bootram.RAM0.INIT_34=256'h80085f80_5199b83f_38815877_75782e83_18335758_52800b97_538c1708_54901708; -defparam bootram.RAM0.INIT_35=256'h398d1733_c95c81dd_8fdb3f80_18335256_ea05538c_7054953d_398d1733_d35c82aa; -defparam bootram.RAM0.INIT_36=256'h75822488_822ea038_17335675_81c7399c_3f80c85c_525690e7_538c1833_70548e18; -defparam bootram.RAM0.INIT_37=256'h17085692_5695398c_1808710c_8c170890_8106a038_75842e09_a138a839_3875812e; -defparam bootram.RAM0.INIT_38=256'h9e387582_5675822e_399c1733_d05c81ba_33763480_08569317_8a398c17_17227623; -defparam bootram.RAM0.INIT_39=256'h17087022_5691398c_08700840_9a388c17_2e098106_a2397584_812e9d38_24883875; -defparam bootram.RAM0.INIT_3A=256'h7553943d_83389456_56947625_398d1733_d25c80fe_33405680_8c170870_40568839; -defparam bootram.RAM0.INIT_3B=256'h94762583_8d173356_3480d739_8405b505_5c800802_bc3f80d6_1733518b_ea05528c; -defparam bootram.RAM0.INIT_3C=256'h05b50534_5c750284_9d3f80d5_1733518a_8e17528c_993f7553_1733518d_3894568c; -defparam bootram.RAM0.INIT_3D=256'h57577533_963d7905_5a587719_800b833d_3ddc0554_17085594_80cc5c8c_ad39785e; -defparam bootram.RAM0.INIT_3E=256'h19963d79_3d5a5877_54800b83_943ddc05_a05ca455_ed38a439_58887826_77348118; -defparam bootram.RAM0.INIT_3F=256'h0d747053_0d04fe3d_a63f943d_8080519d_26ed3883_18588878_33773481_05575775; -defparam bootram.RAM1.INIT_00=256'h8d39a052_3f9db93f_815191ea_5188953f_38a052a0_72802e92_5394b83f_80d8e852; -defparam bootram.RAM1.INIT_01=256'h5280d9a4_89b53f86_80d98851_0d82b53f_0d04fa3d_d93f843d_3f725191_72518884; -defparam bootram.RAM1.INIT_02=256'h92b43f88_3f800851_bd3f85df_85cb3f86_3fa7f13f_c45193f3_8a5280d9_5193fc3f; -defparam bootram.RAM1.INIT_03=256'h96db3f86_52800851_85c13f73_3f800854_8c3f86b1_92ce3f88_3f800851_983f86bd; -defparam bootram.RAM1.INIT_04=256'h83808451_3f8ab252_805197a1_fb528380_96e53f8b_5190bf3f_84528008_a03f8380; -defparam bootram.RAM1.INIT_05=256'h825196f9_dd528380_97833fbe_83808651_3f8ab252_8551978d_b2528380_97973f8a; -defparam bootram.RAM1.INIT_06=256'h802e80c9_08568008_90b43f80_3dfc0551_aabb3f88_51a8a93f_bd3f8ffa_3f805190; -defparam bootram.RAM1.INIT_07=256'h055180c3_52800890_5380d9e8_06ad3884_ee2e0981_557382fd_8e052255_38768008; -defparam bootram.RAM1.INIT_08=256'h3f883974_735185dd_3f86e23f_525491a4_3f941670_f05192b3_9a3880d9_853f8008; -defparam bootram.RAM1.INIT_09=256'h8d38a00b_5573802e_81065155_70852a70_82808c08_3f8eae3f_b43f8fb9_5275519c; -defparam bootram.RAM1.INIT_0A=256'h808c0c80_80c00b82_2efef838_51547380_2a708106_9d3f7486_80d55186_82808c0c; -defparam bootram.RAM1.INIT_0B=256'h3f9f5280_aa3f89d8_889f3f8d_3f82b73f_f53f93c5_fe3d0d85_3ffee839_cf518682; -defparam bootram.RAM1.INIT_0C=256'hcf3f8852_82ac518c_5185913f_3f845284_ac518cdc_859e3f82_9f528051_5185c23f; -defparam bootram.RAM1.INIT_0D=256'h805184e8_82539f52_518cb53f_f73f82ac_52905184_8cc23f90_3f82ac51_88518584; -defparam bootram.RAM1.INIT_0E=256'h9f529e51_8025df38_ff135372_518c993f_db3f80e4_529c5184_8ca63f9f_3f80e451; -defparam bootram.RAM1.INIT_0F=256'h808c0870_803d0d82_843d0d04_810b800c_81e0840c_bf3f890b_52815184_84e33f9f; -defparam bootram.RAM1.INIT_10=256'h82055a57_30708025_a7053370_7f028c05_3d0d7a7d_3d0d04f9_800c5182_8b2a8106; -defparam bootram.RAM1.INIT_11=256'h30709f2a_388a5573_88557383_832e8838_88055575_38728025_75822e93_57585957; -defparam bootram.RAM1.INIT_12=256'h842b0751_fe057072_05777131_76812cff_802e9738_38725472_8177259e_51538054; -defparam bootram.RAM1.INIT_13=256'h73528118_51ac9a3f_ff065277_a43f7281_527b51ac_81805474_86397353_54548054; -defparam bootram.RAM1.INIT_14=256'h54bd5378_815580ca_9f053356_fb3d0d02_893d0d04_51ac8a3f_815280da_51ac923f; -defparam bootram.RAM1.INIT_15=256'hff3ffeb8_51d63f90_3f815281_c551abe1_0d815280_0d04fe3d_e63f873d_527551fe; -defparam bootram.RAM1.INIT_16=256'hfa3d0d78_843d0d04_e0800c53_70900781_81e08008_802ef338_ff065372_3f800881; -defparam bootram.RAM1.INIT_17=256'h33527181_38805471_70802e83_70335252_9e387217_53727627_70565480_7a575781; -defparam bootram.RAM1.INIT_18=256'h04fe3d0d_0c883d0d_81517080_802e8338_74075170_53df3974_80558113_ff2e8338; -defparam bootram.RAM1.INIT_19=256'h88335574_3d0d80e3_3d0d04f9_bcac3f84_80e2ac51_80dae852_88348653_810b80e3; -defparam bootram.RAM1.INIT_1A=256'h80d051ab_54568252_54873d70_24b63886_08558075_3481b8a4_0b80e388_80c63881; -defparam bootram.RAM1.INIT_1B=256'h38865375_0655748c_800881ff_51fee93f_38865275_74802e9c_81ff0655_d53f8008; -defparam bootram.RAM1.INIT_1C=256'h80e2a80c_80dae408_80e38434_0d04810b_800c893d_80e2ac0b_51bbd73f_5280e2ac; -defparam bootram.RAM1.INIT_1D=256'h38845487_807524b3_b8a40855_e3843481_38810b80_557480c3_80e38433_04fb3d0d; -defparam bootram.RAM1.INIT_1E=256'h0551fdfc_52873dfc_2e993884_06557480_800881ff_51aaeb3f_8c5280d0_3dfc0553; -defparam bootram.RAM1.INIT_1F=256'h77568454_04fb3d0d_0c873d0d_e2a80b80_e2a80c80_86387580_ff065574_3f800881; -defparam bootram.RAM1.INIT_20=256'h0b80e384_e2a80c81_38750880_74802e8d_81ff0655_b13f8008_80d051a9_75538c52; -defparam bootram.RAM1.INIT_21=256'h81e08c0c_80e38c0c_08060770_7180e38c_09737506_803d0d73_873d0d04_3474800c; -defparam bootram.RAM1.INIT_22=256'h0c51823d_0c81e098_7080e390_90080607_067180e3_73097375_04803d0d_51823d0d; -defparam bootram.RAM1.INIT_23=256'h8a528051_04ff3d0d_0c843d0d_c93f7280_53805182_0d747053_3f04fe3d_0d0482b1; -defparam bootram.RAM1.INIT_24=256'h157481ff_2e903881_54547280_7081ff06_56567433_3d0d7779_3d0d04fb_82b83f83; -defparam bootram.RAM1.INIT_25=256'h75335556_59565880_0d797b7d_0d04f93d_800c873d_e539800b_5582933f_06537652; -defparam bootram.RAM1.INIT_26=256'h8b387581_5473802e_e53f7433_78525581_81157453_77259d38_38815680_73762ea4; -defparam bootram.RAM1.INIT_27=256'h04fe3d0d_3f833d0d_8051ff8f_3d0d7352_3d0d04ff_75800c89_7324e538_17575376; -defparam bootram.RAM1.INIT_28=256'h528051dd_ff3d0d73_843d0d04_800b800c_5181ab3f_3f8a5272_5253feff_74765370; -defparam bootram.RAM1.INIT_29=256'h73348008_c23f8008_53755181_84398113_56575556_77797b71_04fb3d0d_3f833d0d; -defparam bootram.RAM1.INIT_2A=256'h7431800c_80733472_7224db38_74315274_2e8a3872_387181ff_718a2e90_81ff0652; -defparam bootram.RAM1.INIT_2B=256'h14708429_0d738429_0d04ff3d_1234823d_3380e2b4_51028f05_803d0d72_873d0d04; -defparam bootram.RAM1.INIT_2C=256'hb4133352_805380e2_04fe3d0d_51833d0d_720c5451_f0057022_761080da_82908005; -defparam bootram.RAM1.INIT_2D=256'h0d767856_0d04fc3d_e538843d_53827325_c93f8113_33527251_80e2b813_7251c13f; -defparam bootram.RAM1.INIT_2E=256'h3f738429_527351de_0687388d_812e0981_14335372_3880e2b4_09810695_54748a2e; -defparam bootram.RAM1.INIT_2F=256'h3d0d7484_3d0d04fe_8c150c86_2ef83874_08537280_55538414_82908005_14708429; -defparam bootram.RAM1.INIT_30=256'h800c843d_12085372_2e853890_ff537080_52535181_05881108_29829080_29157084; -defparam bootram.RAM1.INIT_31=256'h38901208_70732e91_52545253_05881108_29829080_29167084_0d807584_0d04fe3d; -defparam bootram.RAM1.INIT_32=256'h0c81b8a4_0b81a888_ff3d0d80_843d0d04_3872800c_545170f1_88140852_7081ff06; -defparam bootram.RAM1.INIT_33=256'h0c70882a_0681a880_227081ff_e2bc0570_51701080_25833884_51518471_08708f06; -defparam bootram.RAM1.INIT_34=256'h55535481_05970533_76780288_04fd3d0d_0c833d0d_0b81a888_51518180_81a8840c; -defparam bootram.RAM1.INIT_35=256'ha88c0c81_10810781_70f13872_06515151_862a7081_a8900870_81863881_5171802e; -defparam bootram.RAM1.INIT_36=256'h2a708106_90087087_f13881a8_51515170_2a708106_90087081_900c81a8_900b81a8; -defparam bootram.RAM1.INIT_37=256'h81a8900c_38a05170_71812e83_3880e851_71802eb1_802eba38_51515170_70813251; -defparam bootram.RAM1.INIT_38=256'hff1252cc_81055634_51707470_81a88c08_5170f138_81065151_70812a70_81a89008; -defparam bootram.RAM1.INIT_39=256'h05335553_02880597_3d0d7678_3d0d04fd_70800c85_81a8900c_3980c00b_39815188; -defparam bootram.RAM1.INIT_3A=256'h2e843881_d0517180_a88c0c81_38721081_515170f1_70810651_0870862a_5481a890; -defparam bootram.RAM1.INIT_3B=256'h872a7081_a8900870_70f13881_06515151_812a7081_a8900870_a8900c81_90517081; -defparam bootram.RAM1.INIT_3C=256'h5171812e_8c0c80d0_733381a8_2e80c538_cf387180_70802e80_51515151_06708132; -defparam bootram.RAM1.INIT_3D=256'h0870872a_3881a890_515170f1_70810651_0870812a_0c81a890_7081a890_83389051; -defparam bootram.RAM1.INIT_3E=256'h80c00b81_81518a39_54ffb739_14ff1353_2e8e3881_51517080_81325151_70810670; -defparam bootram.RAM1.INIT_3F=256'ha2387052_51525470_70810a06_81b8a408_fd3d0d75_853d0d04_5170800c_a8900c80; -defparam bootram.RAM2.INIT_00=256'h52e23985_f1388112_8d9f7127_31515186_ac087074_085381b8_3881b8ac_7174259b; -defparam bootram.RAM2.INIT_01=256'h808c0c80_0cff0b82_0b828084_80800cef_81e20b82_8280880c_3d0dff0b_3d0d04ff; -defparam bootram.RAM2.INIT_02=256'h82808808_04fb3d0d_38833d0d_708025f1_0cff1151_70840554_51a1c972_e4d45287; -defparam bootram.RAM2.INIT_03=256'h38725173_71802e8f_74760652_e4d45555_53810b80_58515280_8c087106_70098280; -defparam bootram.RAM2.INIT_04=256'h04ff3d0d_38873d0d_877325dc_10575553_13841576_0c8f3981_7482808c_0852712d; -defparam bootram.RAM2.INIT_05=256'h72068280_80880870_2b700982_0c518172_d4057571_842980e4_269f3871_73527187; -defparam bootram.RAM2.INIT_06=256'h0c833d0d_5281e0c8_81e0c40c_22747008_0d029205_0404ff3d_52833d0d_880c5351; -defparam bootram.RAM2.INIT_07=256'hcc0c823d_820b81e0_802ef338_06515170_a0087084_cc0c81b8_810b81e0_04803d0d; -defparam bootram.RAM2.INIT_08=256'hb8a00875_2e933881_54527280_08708106_0d81b8a0_0c04fe3d_7181e0c0_0d04de3f; -defparam bootram.RAM2.INIT_09=256'hfc51f7af_8b3880da_5271802e_70810651_3971812a_8080529a_0c535381_71902a71; -defparam bootram.RAM2.INIT_0A=256'h2ef23881_51517080_7080c006_81b8a008_04803d0d_0c843d0d_72527180_3fff9e3f; -defparam bootram.RAM2.INIT_0B=256'ha0087090_0c5281b8_0781e0cc_70902b88_028e0522_04ff3d0d_0c823d0d_80800b80; -defparam bootram.RAM2.INIT_0C=256'h8638ba51_5372802e_0d755480_0d04fd3d_cc0c833d_840b81e0_802ef338_06515170; -defparam bootram.RAM2.INIT_0D=256'h83113356_fb3d0d77_853d0d04_7327e638_81135385_52a1ca3f_14703352_f5c43f72; -defparam bootram.RAM2.INIT_0E=256'h61630290_3d0d7c7e_3d0d04f6_80ed3f87_80db8051_70335356_81113354_82113355; -defparam bootram.RAM2.INIT_0F=256'had51782d_8a387952_3875802e_7680258f_5d5b5957_2a515b5f_7030709f_05bb0533; -defparam bootram.RAM2.INIT_10=256'h527651a9_ffbd3f77_3f800851_7651a990_80537752_79557854_77269438_76305777; -defparam bootram.RAM2.INIT_11=256'h3d0d04f7_f4ac3f82_8b053351_803d0d02_8c3d0d04_3351782d_80db8c05_a83f8008; -defparam bootram.RAM2.INIT_12=256'h387681ff_802e81d1_06575775_337081ff_5c5a5878_5208a4b0_70708405_3d0d8c3d; -defparam bootram.RAM2.INIT_13=256'ha0387580_7580f024_2e80fb38_597580f0_19703357_80db3881_2e098106_065675a5; -defparam bootram.RAM2.INIT_14=256'h397580f5_c638818b_80e42e80_81953975_2e819e38_8a387580_7580e324_e32eb938; -defparam bootram.RAM2.INIT_15=256'h77841983_3880ec39_80f82eba_80f53975_2e80db38_387580f3_80f5248b_2eac3875; -defparam bootram.RAM2.INIT_16=256'h53903977_a4b05480_59568055_19710852_da397784_51792d80_56805275_12335259; -defparam bootram.RAM2.INIT_17=256'ha4b05480_59568055_19710852_92397784_81538a52_55a4b054_52595680_84197108; -defparam bootram.RAM2.INIT_18=256'h76708105_8e388052_5675802e_59567633_19710859_9e397784_51fdd03f_53905275; -defparam bootram.RAM2.INIT_19=256'h803d0d81_a0940c04_04810b81_0c8b3d0d_39800b80_1959fea3_2dec3981_58335179; -defparam bootram.RAM2.INIT_1A=256'hff067b8c_05337980_3d0d0297_3d0d04fd_70f13882_06515151_882a7081_a0900870; -defparam bootram.RAM2.INIT_1B=256'h81a0900c_a0800c72_980c7781_ff0681a0_3f7683ff_555354d0_80c08007_80060770; -defparam bootram.RAM2.INIT_1C=256'h3d0d04fc_70800c85_a0800851_ffaa3f81_802e8938_0c735173_0781a090_7180c280; -defparam bootram.RAM2.INIT_1D=256'h3971902a_555351ee_73058115_10157022_278f3872_80537274_7a545555_3d0d7678; -defparam bootram.RAM2.INIT_1E=256'h86537552_04fd3d0d_0c863d0d_ec397180_902a0552_ffff0672_8d387183_5170802e; -defparam bootram.RAM2.INIT_1F=256'h80720c88_a8528551_3d0d80e3_3d0d04ff_a00c5485_700880e3_aaf83f76_80e39851; -defparam bootram.RAM2.INIT_20=256'h52702254_80e3a452_2253800b_0d029605_0d04fd3d_f338833d_52708025_12ff1252; -defparam bootram.RAM2.INIT_21=256'h787a7183_04fa3d0d_0c853d0d_80517080_7225ee38_12525285_38811288_72742e8e; -defparam bootram.RAM2.INIT_22=256'h80e3a455_80e3a80b_ad398008_0884050c_89387680_8008802e_5856c73f_ffff0653; -defparam bootram.RAM2.INIT_23=256'h73237684_988c3f75_7525eb38_14545585_38811588_71802e8f_88155552_55557308; -defparam bootram.RAM2.INIT_24=256'h88055291_7353923d_54a9c73f_3dd60552_933d5392_0d867054_0d04f13d_140c883d; -defparam bootram.RAM2.INIT_25=256'h23800b8c_8405a605_3d238002_8a800b8b_a2052381_80028405_a9b83f90_3ddc0551; -defparam bootram.RAM2.INIT_26=256'h5e80538a_23685d66_8405ae05_3d238002_c0910b8d_aa052380_80028405_3d238180; -defparam bootram.RAM2.INIT_27=256'h05ba0523_3d220284_903d2396_23983d22_8405ae05_3f800802_0551fdb7_52913de4; -defparam bootram.RAM2.INIT_28=256'h9a903f91_e6840551_80c02981_d4055269_ac53913d_05be0523_23800284_800b913d; -defparam bootram.RAM2.INIT_29=256'h80e39852_a53f8653_f20551a8_3d529a3d_2386539b_800b973d_3d0d805b_3d0d04e8; -defparam bootram.RAM2.INIT_2A=256'h5a800b9b_08800858_f7f73f80_80e20523_22028405_0280f205_51a8973f_9a3df805; -defparam bootram.RAM2.INIT_2B=256'ha33d0840_a13d085f_905d6e5e_4659845c_45a33d08_44a13d08_f005436e_3dc41143; -defparam bootram.RAM2.INIT_2C=256'h75085473_3873760c_73752784_51565a55_90807131_1a787c31_58750870_8c3d5684; -defparam bootram.RAM2.INIT_2D=256'h3f750853_a851eedc_883880db_5473802e_16088306_738c3894_73830654_802e9a38; -defparam bootram.RAM2.INIT_2E=256'h26843880_ac3878bf_778025ff_ff195957_05570817_3f757084_765198e6_94160852; -defparam bootram.RAM2.INIT_2F=256'h1f94055a_943d237f_818a800b_6b6e4040_04ea3d0d_3f9a3d0d_2a51f781_c0597882; -defparam bootram.RAM2.INIT_30=256'h5a79963d_80c08007_ce052369_02840580_23818080_800b953d_80ca0523_79028405; -defparam bootram.RAM2.INIT_31=256'h8008095a_5cfae43f_933d7052_80538a52_08466847_2380e3a0_0580d205_23800284; -defparam bootram.RAM2.INIT_32=256'h923880db_ff065a79_3f800881_5c5e8a8e_983d7053_913d7053_80d20523_79028405; -defparam bootram.RAM2.INIT_33=256'h54908053_5d94557b_60586b57_7f5a6d59_3fa93902_cf3fec8d_3f7a51f6_d451f7db; -defparam bootram.RAM2.INIT_34=256'h3d0d7f58_3d0d04f7_fd8d3f98_7c26ef38_811c5c86_79337b34_7c1f5b5b_805c7b1d; -defparam bootram.RAM2.INIT_35=256'h05237756_028405a6_8b3d2380_88185776_05a20523_3d220284_8a3d238d_02ae0522; -defparam bootram.RAM2.INIT_36=256'h90800284_0b8e3d23_ee3d0d81_8b3d0d04_51fe9e3f_5391527d_8b3df805_7e558854; -defparam bootram.RAM2.INIT_37=256'h80085294_be3f8653_b60523e8_81028405_05b50534_34840284_860b8f3d_05b20523; -defparam bootram.RAM2.INIT_38=256'h3df60551_53805294_a4c83f86_3df20551_80085294_983f8453_a4d83fe9_3dec0551; -defparam bootram.RAM2.INIT_39=256'h8653805b_e4055490_9c55943d_80578056_80598058_0843025c_fc3f8008_a5d53fe8; -defparam bootram.RAM2.INIT_3A=256'haa3d088e_04d93d0d_3f943d0d_ef38fbcf_5b867b26_7a34811b_dba01b33_7a1c5a80; -defparam bootram.RAM2.INIT_3B=256'h8d387952_5b799b26_29f2055b_ac3d0884_9d38901d_09810682_7d90862e_11225f5d; -defparam bootram.RAM2.INIT_3C=256'h802e0981_225a7990_a838821b_09810686_5a79812e_b4397a22_f5b93f86_80dc8451; -defparam bootram.RAM2.INIT_3D=256'h85ff389e_2e098106_225a7981_8c38861b_09810686_798c842e_841b225a_06869a38; -defparam bootram.RAM2.INIT_3E=256'h0551a28a_a93dffa8_80e3a052_08438453_87c33f80_1d70525f_87cb3fa8_1d705240; -defparam bootram.RAM2.INIT_3F=256'h821b2202_22a13d23_a2e83f7a_98527951_865380e3_38a73d5a_800885d5_3f80085c; -defparam bootram.RAM3.INIT_00=256'h05238653_84058182_05348202_84058181_851b3302_33a23d34_0523841b_840580fe; -defparam bootram.RAM3.INIT_01=256'h5b865398_02818e05_5aa2a73f_3dea0552_547f53aa_b53f8470_e40551a2_7952a93d; -defparam bootram.RAM3.INIT_02=256'ha2803f02_7a527e51_3d5f8653_a28c3f9e_3df40551_537f52a9_a2983f79_1d527a51; -defparam bootram.RAM3.INIT_03=256'h811c5c86_79337b34_7f1d5b5b_7d537b1d_3ddc0554_5d9c55a9_7c587c57_7c5a7c59; -defparam bootram.RAM3.INIT_04=256'h5b5b6084_708c2a43_901d7022_0684aa38_802e0981_b4397d90_f99d3f84_7c26ef38; -defparam bootram.RAM3.INIT_05=256'hffff065e_861b2280_06848638_852e0981_06515a79_882a708f_84973879_2e098106; -defparam bootram.RAM3.INIT_06=256'h5580e3a0_7d901c62_8338815f_993f8008_821d51a0_80dba052_7d5f8653_7d83fa38; -defparam bootram.RAM3.INIT_07=256'h5183fe3f_1d529c1d_83c73888_387b802e_815c7e87_80088338_5ca0833f_5470535b; -defparam bootram.RAM3.INIT_08=256'h087a08a4_a4388c1b_09810683_387f912e_812e81bb_415d407f_1c22ec11_891b3382; -defparam bootram.RAM3.INIT_09=256'h1de41d82_838339ac_51f2883f_5280dca4_3879537e_7e7a2e8f_5d5d4240_1f841122; -defparam bootram.RAM3.INIT_0A=256'h3d405a88_499a3d99_993d237f_ec387a22_08802e82_80084280_5df5c73f_1d22535d; -defparam bootram.RAM3.INIT_0B=256'h8853a93d_3d236047_821b2297_519feb3f_5379527f_9c3d4088_519ff73f_537e5279; -defparam bootram.RAM3.INIT_0C=256'h1d7f1d5b_3d5e5c7b_7c557d84_cd3f7b56_527e519f_3f885379_79519fd6_ffb40552; -defparam bootram.RAM3.INIT_0D=256'h887b26ef_34811b5b_0284051c_1b5a7933_38805b7f_887c26ef_34811c5c_5b79337b; -defparam bootram.RAM3.INIT_0E=256'h2e818138_8a387e88_427e832e_7033415b_1b08a41e_81f3398c_085a792d_38618405; -defparam bootram.RAM3.INIT_0F=256'h810681bd_79912e09_1e335b5b_80c01db5_0680e838_832e0981_1a335a79_81db3981; -defparam bootram.RAM3.INIT_10=256'h840c7d81_0c7d81e1_0b81e180_9438810a_2e098106_5c5a797b_80e4fc22_38821b22; -defparam bootram.RAM3.INIT_11=256'hc40c7d81_0c7d81e2_0b81e2c0_9438810a_2e098106_225b797b_3980e4f8_e1880cb3; -defparam bootram.RAM3.INIT_12=256'h3f80de39_e951e48a_e4d00c80_86387d81_2e098106_225b797b_3980e4f4_e2c80c93; -defparam bootram.RAM3.INIT_13=256'h22963d23_0523841a_840580ce_05347d02_840580cd_3d347d02_5d5d7d95_ac1de41d; -defparam bootram.RAM3.INIT_14=256'h527c51f1_537b812a_8a3f8008_70525bf2_6052943d_05237d53_840580d2_861a2202; -defparam bootram.RAM3.INIT_15=256'h3fa93d0d_6151f6b1_7a537f52_7c557e54_05237b56_840580ce_095a7902_fe3f8008; -defparam bootram.RAM3.INIT_16=256'h8c135351_56517108_80e3dc54_38767008_727427a4_d4085553_800b80e3_04fc3d0d; -defparam bootram.RAM3.INIT_17=256'h04fb3d0d_0c863d0d_ff517080_7326e738_81135373_72518b39_81068538_70752e09; -defparam bootram.RAM3.INIT_18=256'he3d40c8e_38811480_73872689_e3d40854_25ba3880_3f800880_5755ffb9_77797153; -defparam bootram.RAM3.INIT_19=256'h54865375_dc120c51_760880e3_1470822b_0c547310_0680e3d8_08811187_3980e3d8; -defparam bootram.RAM3.INIT_1A=256'h813f873d_e005519c_842980e3_53755273_08055486_80081080_14519439_5280e3e0; -defparam bootram.RAM3.INIT_1B=256'h842980e3_54865373_10800805_99388008_73800824_d83f8054_0d7551fe_0d04fd3d; -defparam bootram.RAM3.INIT_1C=256'h2b71902b_12337198_75703381_04fd3d0d_0c853d0d_81547380_519bd73f_e0055276; -defparam bootram.RAM3.INIT_1D=256'h0d883d70_0d04ea3d_5452853d_52535456_7107800c_07831633_70882b72_07821433; -defparam bootram.RAM3.INIT_1E=256'h9d387381_7381ff2e_70335154_57557417_84059d05_b43f8002_52685194_545780c0; -defparam bootram.RAM3.INIT_1F=256'h55be7527_8b398115_85388154_2e098106_54738199_16703351_06943874_aa2e0981; -defparam bootram.RAM3.INIT_20=256'h845380dc_e43f8055_52795193_70545484_3d0d863d_3d0d04f9_73800c98_d1388054; -defparam bootram.RAM3.INIT_21=256'he0940c04_04810b81_0c893d0d_81557480_81068338_08752e09_99c43f80_c8527351; -defparam bootram.RAM3.INIT_22=256'h81065151_708d2a70_81b8b408_5189bb3f_ff065580_3f800881_d13f8abc_fc3d0d8d; -defparam bootram.RAM3.INIT_23=256'h8008802e_51febf3f_3fb0800a_8451e1a4_b53880dd_81833974_80dccc51_54738838; -defparam bootram.RAM3.INIT_24=256'hdde85180_84b53f80_b0800a51_51e6d93f_813f82ac_3f815189_b051e190_9a3880dd; -defparam bootram.RAM3.INIT_25=256'hff529880_805380ff_e33f8380_deb451e0_2ebb3880_3f800880_0a51fee3_cc399880; -defparam bootram.RAM3.INIT_26=256'h82ac51e6_51e0bd3f_3f80df84_9b3ffee5_82ac51e6_51e0cd3f_3f80dee0_0a5192b9; -defparam bootram.RAM3.INIT_27=256'h0d757053_0c04fd3d_7180e4bc_863d0d04_51e0a93f_3980dfc0_83e93f88_8b3f8051; -defparam bootram.RAM3.INIT_28=256'h2d853d0d_38735172_72802e85_e4bc0853_de9a3f80_a052a051_54eab83f_80e08c52; -defparam bootram.RAM3.INIT_29=256'h04fc3d0d_2d843d0d_38805172_72802e85_e4bc0853_ddfe3f80_a0528051_04fe3d0d; -defparam bootram.RAM3.INIT_2A=256'h08868006_38820b80_802e80ec_54815571_81065153_08862a70_3fff0b80_9a518987; -defparam bootram.RAM3.INIT_2B=256'h54718480_8a3987e8_802e8e38_388a5471_8280248a_2e9b3871_54718280_535580e4; -defparam bootram.RAM3.INIT_2C=256'h83067207_088a2c70_2a8c0680_ba3f7188_52855188_c23f8008_54845188_2e8338ff; -defparam bootram.RAM3.INIT_2D=256'hc8110852_8c0680e2_3f71822b_5452debb_c4555351_c80c80e0_337080e4_80e18411; -defparam bootram.RAM3.INIT_2E=256'ha338fec1_2e098106_a6387481_0c74822e_7480e4c0_082e9838_7480e4c0_52ded53f; -defparam bootram.RAM3.INIT_2F=256'h51fdfb3f_fea73f73_80e4c40c_2e8e3873_80e4c408_06963873_822e0981_3f9e3974; -defparam bootram.RAM3.INIT_30=256'h0b80e4c4_e4c00cff_3f800b80_0851879c_daa93f80_04fd3d0d_3f863d0d_995187c7; -defparam bootram.RAM3.INIT_31=256'he03f8451_528451e4_c73fbabd_529c5187_3f81ae80_985187d0_a63f8d52_0c995187; -defparam bootram.RAM3.INIT_32=256'h8d388008_7380082e_5186f43f_87aa3f84_53548451_f49f0670_08908007_87893f80; -defparam bootram.RAM3.INIT_33=256'h0d04fd3d_833f853d_52805187_08848007_86dd3f80_d63f8051_e0dc51e7_53735280; -defparam bootram.RAM3.INIT_34=256'h73109006_71730707_812a8806_2a840672_2a077183_82067187_3370852a_0d029705; -defparam bootram.RAM3.INIT_35=256'hff0682c0_2b077081_72077887_80c00670_0676852b_077081ff_06717307_74832ba0; -defparam bootram.RAM3.INIT_36=256'hff51ff9e_0a075381_0a0681d0_3d0d74d0_3d0d04fe_55555285_53515552_800c5152; -defparam bootram.RAM3.INIT_37=256'h813f7288_80e151ff_51ff873f_ff8c3fb2_3f819951_aa51ff92_ff983f81_3f81ff51; -defparam bootram.RAM3.INIT_38=256'h3f72982a_8151fee2_fee83f81_ed3fb251_ff0651fe_f53f7281_065252fe_2a7081ff; -defparam bootram.RAM3.INIT_39=256'h51febf3f_fec43f80_3f81a151_b051feca_53fecf3f_81ff0652_72902a70_51fedb3f; -defparam bootram.RAM3.INIT_3A=256'h04ffaf3d_3f843d0d_8051fea6_51feab3f_feb03fa0_b53f8051_3fa051fe_8e51feba; -defparam bootram.RAM3.INIT_3B=256'h9451e5bf_945280e1_38775382_82932690_58595777_08841208_0880da3d_0d80d83d; -defparam bootram.RAM3.INIT_3C=256'h80ca3875_7580e426_2e80e938_387580e4_80e62698_80cc3875_7580e62e_3f81d039; -defparam bootram.RAM3.INIT_3D=256'h81953975_2e80f738_387580f2_80f3268b_819b3875_7580f32e_3881ac39_80e12ea5; -defparam bootram.RAM3.INIT_3E=256'h8c943f80_3f800841_80398c90_08084181_d7d33f80_3980c15f_da38818b_80f72e80; -defparam bootram.RAM3.INIT_3F=256'h5f80d639_f93f80c5_e0055189_80d33dfd_8c170852_90170853_5f80ee39_084280c6; -defparam bootram.RAM4.INIT_00=256'h5fb73994_bc3980c2_3880c45f_75802e86_81ff0656_bb3f8008_e005518a_80d33dfd; -defparam bootram.RAM4.INIT_01=256'h528c1708_53901708_3dfe8005_a43980d3_3f80d75f_085188dd_08528c17_17539017; -defparam bootram.RAM4.INIT_02=256'hec055480_80d33dfd_5f829455_3f8339a0_8051fcff_3980d35f_80d25f8d_518bba3f; -defparam bootram.RAM4.INIT_03=256'h8251ec9b_ec388380_58887826_77348118_57577533_d53d7905_58771980_0b833d5a; -defparam bootram.RAM4.INIT_04=256'h028405ab_02a70533_3ff93d0d_ff518398_51d8e03f_0d80e1e0_0d04803d_3f80d33d; -defparam bootram.RAM4.INIT_05=256'h0d7a7c7f_0d04f83d_9e3f893d_528051e5_54755381_88805598_2b075757_05337188; -defparam bootram.RAM4.INIT_06=256'h58330284_76708105_738a3d34_81175754_25b73875_56548074_5874ff16_7f5a5757; -defparam bootram.RAM4.INIT_07=256'hef3f7380_548a51dd_0881ff06_dcc13f80_81ff0651_fc055277_82538a3d_05a10534; -defparam bootram.RAM4.INIT_08=256'hdc567588_56748338_335580de_0d02a305_0d04fa3d_800c8a3d_39815473_2e8538c1; -defparam bootram.RAM4.INIT_09=256'hab053389_0d7c5702_0d04f93d_893f883d_80d051ff_5381f752_883dfc05_3d348154; -defparam bootram.RAM4.INIT_0A=256'h802e9e38_70565473_0881ff06_dbe13f80_33705256_5202a705_893dfc05_3d348153; -defparam bootram.RAM4.INIT_0B=256'h5574800c_2e833881_56547380_81ff0670_a43f8008_527551da_3876537b_80772597; -defparam bootram.RAM4.INIT_0C=256'h56567480_0b883d33_ffa03f80_5280d051_055381f7_54883dfc_fa3d0d81_893d0d04; -defparam bootram.RAM4.INIT_0D=256'h0ca60b81_0b81c080_940c80eb_990b81c0_883d0d04_5675800c_06833881_de2e0981; -defparam bootram.RAM4.INIT_0E=256'h820b81c0_c0980c51_70810781_2bbe8006_3d0d7288_b00c0480_b00b81c0_c0ac0c89; -defparam bootram.RAM4.INIT_0F=256'h803d0d72_823d0d04_a808800c_f13881c0_51515170_2a708106_a4087081_a00c81c0; -defparam bootram.RAM4.INIT_10=256'h70812a70_81c0a408_81c0a00c_9c0c840b_517381c0_81c0980c_06708107_882bbe80; -defparam bootram.RAM4.INIT_11=256'h91387583_55575771_72830655_0d787a7c_ff39fa3d_823d0d04_5170f138_81065151; -defparam bootram.RAM4.INIT_12=256'h94387382_55737527_822a7255_88ca3f72_86388151_5271802e_38728306_0652718a; -defparam bootram.RAM4.INIT_13=256'h708f0680_7470842a_04fe3d0d_39883d0d_811454e9_0c525452_12700872_2b771177; -defparam bootram.RAM4.INIT_14=256'h803d0d82_843d0d04_53d3cf3f_ec113352_8f0680e1_d3dc3f72_54515353_e1ec1133; -defparam bootram.RAM4.INIT_15=256'hff067a8c_05337880_3d0d0293_3d0d04fe_70f13882_06515151_882a7081_e0900870; -defparam bootram.RAM4.INIT_16=256'h800c7182_387682e0_515170f1_70810651_0870882a_5382e090_c0800753_80060780; -defparam bootram.RAM4.INIT_17=256'h90087088_963882e0_5172802e_e0900c72_82800782_e0980c71_81ff0682_e0900c75; -defparam bootram.RAM4.INIT_18=256'he0940c88_0d810b82_0d04fc3d_800c843d_80085170_f13882e0_51515170_2a708106; -defparam bootram.RAM4.INIT_19=256'h81528151_548a8053_88805590_04fc3d0d_3f863d0d_8051ff87_80538052_80558854; -defparam bootram.RAM4.INIT_1A=256'hfed53f86_81528051_88548653_0d888055_0d04fc3d_800c863d_0881ff06_fef13f80; -defparam bootram.RAM4.INIT_1B=256'hff065170_3f800881_803d0deb_823d0d04_8106800c_80088132_3d0dca3f_3d0d0480; -defparam bootram.RAM4.INIT_1C=256'h8055a054_ffb43f88_9b38dd3f_75800826_5684e33f_fb3d0d77_823d0d04_802ef438; -defparam bootram.RAM4.INIT_1D=256'h80cb3d08_80c93d08_ffba3d0d_873d0d04_51fe843f_53815280_069b0a07_75fe9b0a; -defparam bootram.RAM4.INIT_1E=256'h805381ff_81a73882_73800826_54849f3f_b4387517_81ff2681_57805573_ff115657; -defparam bootram.RAM4.INIT_1F=256'h9f3f7482_fed43ffd_3ffefd3f_73518aea_cb3d0852_3f755380_52548c8f_52883d70; -defparam bootram.RAM4.INIT_20=256'h0c88a00b_0b82e098_e0800c81_c00a0782_c00a0680_900c76fe_800b82e0_e0980c88; -defparam bootram.RAM4.INIT_21=256'h0c54fe84_0882e08c_fe801570_3d558f56_ef3f80c8_e0900cfc_8aa00b82_82e0900c; -defparam bootram.RAM4.INIT_22=256'h88800b82_e0800c54_15700882_0c54fe8c_0882e084_fe881570_e0880c54_15700882; -defparam bootram.RAM4.INIT_23=256'he0980c81_38800b82_8025ffbc_16565675_3fff1690_900cfcb0_800b82e0_e0900c8a; -defparam bootram.RAM4.INIT_24=256'h082680cb_80577380_5682db3f_12575a56_797b7d72_04f93d0d_80c83d0d_5574800c; -defparam bootram.RAM4.INIT_25=256'h27833876_55577675_80743175_2ea23882_06547380_387581ff_802e80c3_38815774; -defparam bootram.RAM4.INIT_26=256'h807527e1_38745482_74802e8e_31575956_74197676_eb3f7316_527551fd_54775373; -defparam bootram.RAM4.INIT_27=256'h802e8d38_56545573_0d76787a_0d04fc3d_800c893d_3f815776_dc39fd8c_38828054; -defparam bootram.RAM4.INIT_28=256'hcb3f8008_0ca63981_160c8075_0c800b84_800b8816_74279038_ed3f8008_73135481; -defparam bootram.RAM4.INIT_29=256'h51fcc93f_88160c71_84160c71_760c7406_80083072_5281bd3f_ff165651_30707406; -defparam bootram.RAM4.INIT_2A=256'h14088415_38815388_71802e9f_06705452_800881ff_54fc983f_fd3d0d75_863d0d04; -defparam bootram.RAM4.INIT_2B=256'h0d04fc3d_800c853d_3f805372_0c51fc94_05708816_14088008_81823f88_082e9438; -defparam bootram.RAM4.INIT_2C=256'h04ff3d0d_0c863d0d_800a0680_3f8008fe_8151faa3_0a538152_a05481f9_0d888055; -defparam bootram.RAM4.INIT_2D=256'h81069338_70a02e09_06545151_800881ff_7081ff06_8008882a_a038d73f_80e4cc08; -defparam bootram.RAM4.INIT_2E=256'hc03f8008_833d0d04_3f71800c_8438f5b2_52827127_08ea1152_0c80e4cc_7180e4cc; -defparam bootram.RAM4.INIT_2F=256'h04f63d0d_082b800c_3f810b80_0c04ffa9_80082b80_f33f810b_33800c04_80e2c205; -defparam bootram.RAM4.INIT_30=256'he0800c81_7c882b82_82e0840c_900c8b0b_800b82e0_e0980c88_3f800b82_7d56f998; -defparam bootram.RAM4.INIT_31=256'h2780d338_80547376_e73f7e55_e0900cf8_8aa80b82_82e0900c_0c88a80b_0b82e098; -defparam bootram.RAM4.INIT_32=256'he084085a_88085982_085882e0_3f82e08c_900cf8cc_800b82e0_e0900c8a_88800b82; -defparam bootram.RAM4.INIT_33=256'h71175170_73279138_53805271_27833870_90537073_75315257_5b883d76_82e08008; -defparam bootram.RAM4.INIT_34=256'h803d0d72_8c3d0d04_82e0980c_a939800b_721454ff_1252ec39_05573481_33757081; -defparam bootram.RAM4.INIT_35=256'h3f800870_085182de_8c088805_8c050852_80538c08_0cfd3d0d_8c08028c_51f7893f; -defparam bootram.RAM4.INIT_36=256'h05085182_528c0888_088c0508_0d81538c_8c0cfd3d_048c0802_3d0d8c0c_800c5485; -defparam bootram.RAM4.INIT_37=256'h0c8c0888_8c08fc05_3d0d800b_028c0cf9_0c048c08_853d0d8c_70800c54_b93f8008; -defparam bootram.RAM4.INIT_38=256'h08883881_8c08fc05_08f4050c_0c800b8c_8c088805_88050830_ab388c08_05088025; -defparam bootram.RAM4.INIT_39=256'h0508308c_388c088c_088025ab_8c088c05_08fc050c_f405088c_050c8c08_0b8c08f4; -defparam bootram.RAM4.INIT_3A=256'h05088c08_0c8c08f0_8c08f005_8838810b_08fc0508_f0050c8c_800b8c08_088c050c; -defparam bootram.RAM4.INIT_3B=256'h548c08fc_08f8050c_8008708c_5181a73f_08880508_0508528c_538c088c_fc050c80; -defparam bootram.RAM4.INIT_3C=256'h0d8c0c04_0c54893d_05087080_0c8c08f8_8c08f805_f8050830_8c388c08_0508802e; -defparam bootram.RAM4.INIT_3D=256'h08308c08_8c088805_80259338_08880508_fc050c8c_800b8c08_0cfb3d0d_8c08028c; -defparam bootram.RAM4.INIT_3E=256'h050c8153_308c088c_088c0508_258c388c_8c050880_050c8c08_0b8c08fc_88050c81; -defparam bootram.RAM4.INIT_3F=256'h802e8c38_08fc0508_050c548c_708c08f8_ad3f8008_88050851_08528c08_8c088c05; -defparam bootram.RAM5.INIT_00=256'h028c0cfd_0c048c08_873d0d8c_70800c54_08f80508_f8050c8c_08308c08_8c08f805; -defparam bootram.RAM5.INIT_01=256'h388c08fc_050827ac_088c0888_8c088c05_08f8050c_0c800b8c_8c08fc05_3d0d810b; -defparam bootram.RAM5.INIT_02=256'h08fc0508_8c050c8c_08108c08_8c088c05_08249938_8c088c05_a338800b_0508802e; -defparam bootram.RAM5.INIT_03=256'h26a1388c_08880508_8c05088c_c9388c08_08802e80_8c08fc05_050cc939_108c08fc; -defparam bootram.RAM5.INIT_04=256'hf8050c8c_08078c08_8c08fc05_08f80508_88050c8c_08318c08_8c088c05_08880508; -defparam bootram.RAM5.INIT_05=256'h90050880_af398c08_8c050cff_812a8c08_088c0508_fc050c8c_812a8c08_08fc0508; -defparam bootram.RAM5.INIT_06=256'h518c08f4_08f4050c_0508708c_398c08f8_050c518d_708c08f4_08880508_2e8f388c; -defparam bootram.RAM5.INIT_07=256'h06517080_74740783_72278c38_56565283_0d787779_0c04fc3d_853d0d8c_0508800c; -defparam bootram.RAM5.INIT_08=256'h15ff1454_38811581_098106bd_5372712e_33743352_2ea03874_125271ff_2eb038ff; -defparam bootram.RAM5.INIT_09=256'h81068f38_73082e09_54517008_0d047474_800c863d_e238800b_2e098106_555571ff; -defparam bootram.RAM5.INIT_0A=256'h0d04fc3d_800c863d_39727131_5555ffaf_e9387073_51718326_fc145454_84118414; -defparam bootram.RAM5.INIT_0B=256'h71ff2e98_38ff1252_70802ea7_07830651_8c387275_558f7227_7b555555_0d767079; -defparam bootram.RAM5.INIT_0C=256'h3d0d0474_74800c86_8106ea38_71ff2e09_34ff1252_70810556_05543374_38727081; -defparam bootram.RAM5.INIT_0D=256'h05540871_0c727084_70840553_05540871_0c727084_70840553_05540871_51727084; -defparam bootram.RAM5.INIT_0E=256'h95387270_38837227_718f26c9_0cf01252_70840553_05540871_0c727084_70840553; -defparam bootram.RAM5.INIT_0F=256'h71028c05_3d0d7679_ff8339fc_ed387054_52718326_530cfc12_71708405_84055408; -defparam bootram.RAM5.INIT_10=256'h38737370_71ff2e93_38ff1252_70802ea2_74830651_72278a38_55535583_9f053357; -defparam bootram.RAM5.INIT_11=256'h7071902b_882b7507_0d047474_800c863d_06ef3874_ff2e0981_ff125271_81055534; -defparam bootram.RAM5.INIT_12=256'h530c7271_71708405_05530c72_72717084_8405530c_38727170_8f7227a5_07515451; -defparam bootram.RAM5.INIT_13=256'h718326f2_0cfc1252_70840553_90387271_38837227_718f26dd_0cf01252_70840553; -defparam bootram.RAM5.INIT_14=256'h5170802e_74078306_80d93871_5272802e_70545555_0d787a7c_9039fa3d_387053ff; -defparam bootram.RAM5.INIT_15=256'h81873870_3872802e_098106a9_5174712e_33743356_2eb13871_135372ff_80d438ff; -defparam bootram.RAM5.INIT_16=256'h33743356_06d13871_ff2e0981_55555272_8115ff15_fc388112_70802e80_81ff0651; -defparam bootram.RAM5.INIT_17=256'h27883871_57558373_0d047174_800c883d_51525270_06717131_067581ff_517081ff; -defparam bootram.RAM5.INIT_18=256'hff120670_09f7fbfd_38740870_72802eb1_39fc1353_5552ff97_88387476_0874082e; -defparam bootram.RAM5.INIT_19=256'hd0387476_0876082e_27d03874_57558373_84158417_51709a38_80065151_f8848281; -defparam bootram.RAM5.INIT_1A=256'h387380e4_72812e9e_9c085454_800b80e2_04fd3d0d_0c883d0d_39800b80_5552fedf; -defparam bootram.RAM5.INIT_1B=256'he4d00cff_a33f7280_800851f6_ffb9bb3f_dc528151_973f80e2_fb3fffb1_d00cffb1; -defparam bootram.RAM5.INIT_1C=256'h0d80e2e4_ff39ff3d_f6863f00_3f800851_51ffb99e_e2dc5281_b0fa3f80_b1de3fff; -defparam bootram.RAM5.INIT_1D=256'h833d0d04_8106f138_70ff2e09_70085252_702dfc12_ff2e9138_08525270_0bfc0570; -defparam bootram.RAM5.INIT_1E=256'h6c207061_6e74726f_6e20636f_6f722069_21457272_00000040_3f040000_04ffb289; -defparam bootram.RAM5.INIT_1F=256'h74696269_6f6d7061_65642063_70656374_3a204578_646c6572_2068616e_636b6574; -defparam bootram.RAM5.INIT_20=256'h21457272_25640a00_676f7420_62757420_25642c20_62657220_206e756d_6c697479; -defparam bootram.RAM5.INIT_21=256'h3a204578_646c6572_2068616e_636b6574_6c207061_6e74726f_6e20636f_6f722069; -defparam bootram.RAM5.INIT_22=256'h7420676f_2c206275_68202564_656e6774_6164206c_61796c6f_65642070_70656374; -defparam bootram.RAM5.INIT_23=256'h70656564_643a2073_616e6765_6b206368_206c696e_0a657468_0a000000_74202564; -defparam bootram.RAM5.INIT_24=256'h6f616465_6f6f746c_44502062_31302055_50204e32_0a555352_640a0000_203d2025; -defparam bootram.RAM5.INIT_25=256'h723a2025_756d6265_7479206e_62696c69_70617469_20636f6d_46504741_720a0000; -defparam bootram.RAM5.INIT_26=256'h756d6265_7479206e_62696c69_70617469_20636f6d_77617265_4669726d_640a0000; -defparam bootram.RAM5.INIT_27=256'h65727920_65636f76_69702072_476f7420_00000000_61646472_640a0000_723a2025; -defparam bootram.RAM5.INIT_28=256'h000007cc_000007cc_000007cc_000007cc_00000650_00000000_65743a20_7061636b; -defparam bootram.RAM5.INIT_29=256'h000007cc_000007a2_000007cc_000007cc_000006a5_000006bd_000007cc_000007cc; -defparam bootram.RAM5.INIT_2A=256'h00000778_000007cc_0000065d_00000715_000007cc_000006d3_000007cc_000007cc; -defparam bootram.RAM5.INIT_2B=256'h45000000_01b200d9_05160364_14580a2c_3fff0000_0050c285_c0a80a02_00000751; -defparam bootram.RAM5.INIT_2C=256'h00000000_43444546_38394142_34353637_30313233_2e256400_642e2564_25642e25; -defparam bootram.RAM5.INIT_2D=256'h656e7420_69676e6d_6420616c_3a206261_5f706b74_73656e64_ffff0000_ffffffff; -defparam bootram.RAM5.INIT_2E=256'h6f6e3a20_636f6d6d_6e65745f_66000000_72206275_6e642f6f_656e2061_6f66206c; -defparam bootram.RAM5.INIT_2F=256'h666f7220_696e6720_6c6f6f6b_63686520_74206361_6f206869_65642074_6661696c; -defparam bootram.RAM5.INIT_30=256'h3d202564_697a6520_72642073_20776569_6172703a_646c655f_0a68616e_00000000; -defparam bootram.RAM5.INIT_31=256'h3a202564_67746873_206c656e_74656e74_6e736973_696e636f_55445020_0a000000; -defparam bootram.RAM5.INIT_32=256'h696e2073_50322b20_20555352_74696e67_53746172_0b0b0b0b_00000000_2025640a; -defparam bootram.RAM5.INIT_33=256'h6172652e_69726d77_66652066_67207361_6164696e_2e204c6f_6d6f6465_61666520; -defparam bootram.RAM5.INIT_34=256'h6374696f_726f6475_69642070_2076616c_20666f72_6b696e67_43686563_00000000; -defparam bootram.RAM5.INIT_35=256'h74696f6e_6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650; -defparam bootram.RAM5.INIT_36=256'h6720746f_7074696e_7474656d_642e2041_666f756e_61676520_4120696d_20465047; -defparam bootram.RAM5.INIT_37=256'h46504741_696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f; -defparam bootram.RAM5.INIT_38=256'h6820746f_726f7567_67207468_6c6c696e_2e0a4661_6f756e64_67652066_20696d61; -defparam bootram.RAM5.INIT_39=256'h6f647563_64207072_56616c69_72652e00_726d7761_6e206669_6c742d69_20627569; -defparam bootram.RAM5.INIT_3A=256'h2e2e2e00_64696e67_204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e; -defparam bootram.RAM5.INIT_3B=256'h6d616765_6e672069_61727469_2e205374_64696e67_206c6f61_73686564_46696e69; -defparam bootram.RAM5.INIT_3C=256'h70726f67_61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f_2e000000; -defparam bootram.RAM5.INIT_3D=256'h6e210000_61707065_65722068_206e6576_6f756c64_73207368_20546869_72616d21; -defparam bootram.RAM5.INIT_3E=256'h20666f75_77617265_6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076; -defparam bootram.RAM5.INIT_3F=256'h2d696e20_75696c74_746f2062_75676820_7468726f_696e6720_46616c6c_6e642e20; -defparam bootram.RAM6.INIT_00=256'h00000000_2025640a_7420746f_64207365_53706565_2e000000_77617265_6669726d; -defparam bootram.RAM6.INIT_01=256'h45545249_53594d4d_58000000_57455f52_58000000_57455f54_00000000_4e4f4e45; -defparam bootram.RAM6.INIT_02=256'h5048595f_6c3a2000_6e74726f_7720636f_20666c6f_726e6574_65746865_43000000; -defparam bootram.RAM6.INIT_03=256'h20307825_20676f74_7825782c_74652030_2077726f_4144563a_4e45475f_4155544f; -defparam bootram.RAM6.INIT_04=256'h6e207570_6f722069_21457272_00030203_00000001_00030003_00000000_780a0000; -defparam bootram.RAM6.INIT_05=256'h64207061_65637465_20457870_6c65723a_68616e64_6b657420_20706163_64617465; -defparam bootram.RAM6.INIT_06=256'h00000000_2025640a_20676f74_20627574_2025642c_6e677468_64206c65_796c6f61; -defparam bootram.RAM6.INIT_07=256'h64756d6d_43444546_38394142_34353637_30313233_00000000_6f72740a_0a0a6162; -defparam bootram.RAM6.INIT_08=256'h00000000_00000000_ffffff00_ffff00ff_ff00ffff_00ffffff_65000000_792e6578; -defparam bootram.RAM6.INIT_09=256'hffff0031_05050400_01010100_3fff0000_0050c285_c0a80a02_0000316c_00000000; -defparam bootram.RAM6.INIT_0A=256'h000030fc_10101200_00003038_00003030_00003028_00003020_000b0000_0018000f; -defparam bootram.RAM6.INIT_0B=256'h00000000_00000000_00000000_00000000_00000000_ffffffff_00000000_ffffffff; -defparam bootram.RAM6.INIT_0C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_0F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_2B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_2C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_2D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_2E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_2F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_37=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_38=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM6.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_00=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_02=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_03=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_04=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_06=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_0B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_0C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_0F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_2B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_2C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_2D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_2E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_2F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_37=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_38=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM7.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; diff --git a/usrp2/top/u2plus/capture_ddrlvds.v b/usrp2/top/u2plus/capture_ddrlvds.v deleted file mode 100644 index d263e0cfa..000000000 --- a/usrp2/top/u2plus/capture_ddrlvds.v +++ /dev/null @@ -1,38 +0,0 @@ - - -module capture_ddrlvds - #(parameter WIDTH=7) - (input clk, - input ssclk_p, - input ssclk_n, - input [WIDTH-1:0] in_p, - input [WIDTH-1:0] in_n, - output reg [(2*WIDTH)-1:0] out); - - wire [WIDTH-1:0] ddr_dat; - wire ssclk; - wire [(2*WIDTH)-1:0] out_pre1; - reg [(2*WIDTH)-1:0] out_pre2; - - IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) - clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); - - genvar i; - generate - for(i = 0; i < WIDTH; i = i + 1) - begin : gen_lvds_pins - IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("FALSE")) ibufds - (.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) ); - IDDR2 #(.DDR_ALIGNMENT("C1")) iddr2 - (.Q0(out_pre1[2*i]), .Q1(out_pre1[(2*i)+1]), .C0(ssclk), .C1(~ssclk), - .CE(1'b1), .D(ddr_dat[i]), .R(1'b0), .S(1'b0)); - end - endgenerate - - always @(posedge clk) - out_pre2 <= out_pre1; - - always @(posedge clk) - out <= out_pre2; - -endmodule // capture_ddrlvds diff --git a/usrp2/top/u2plus/rev4_defs.v b/usrp2/top/u2plus/rev4_defs.v deleted file mode 100644 index e37f34851..000000000 --- a/usrp2/top/u2plus/rev4_defs.v +++ /dev/null @@ -1 +0,0 @@ -`define LVDS 1 diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf deleted file mode 100755 index 5fbe55c26..000000000 --- a/usrp2/top/u2plus/u2plus.ucf +++ /dev/null @@ -1,424 +0,0 @@ -## Main 100 MHz Clock -NET "CLK_FPGA_P" LOC = "AA13" ; -NET "CLK_FPGA_N" LOC = "Y13" ; - -## ADC -NET "ADC_clkout_p" LOC = "P1" ; -NET "ADC_clkout_n" LOC = "P2" ; -NET "ADCA_12_p" LOC = "Y1" ; -NET "ADCA_12_n" LOC = "Y2" ; -NET "ADCA_10_p" LOC = "W3" ; -NET "ADCA_10_n" LOC = "W4" ; -NET "ADCA_8_p" LOC = "T7" ; -NET "ADCA_8_n" LOC = "U6" ; -NET "ADCA_6_p" LOC = "U5" ; -NET "ADCA_6_n" LOC = "V5" ; -NET "ADCA_4_p" LOC = "T10" ; -NET "ADCA_4_n" LOC = "T9" ; -NET "ADCA_2_p" LOC = "V1" ; -NET "ADCA_2_n" LOC = "V2" ; -NET "ADCA_0_p" LOC = "R8" ; -NET "ADCA_0_n" LOC = "R7" ; -NET "ADCB_2_p" LOC = "U7" ; -NET "ADCB_2_n" LOC = "U8" ; -NET "ADCB_0_p" LOC = "AA2" ; -NET "ADCB_0_n" LOC = "AA3" ; -NET "ADCB_4_p" LOC = "AE1" ; -NET "ADCB_4_n" LOC = "AE2" ; -NET "ADCB_6_p" LOC = "W1" ; -NET "ADCB_6_n" LOC = "W2" ; -NET "ADCB_8_p" LOC = "U3" ; -NET "ADCB_8_n" LOC = "V4" ; -NET "ADCB_10_p" LOC = "J1" ; -NET "ADCB_10_n" LOC = "K1" ; -NET "ADCB_12_p" LOC = "J3" ; -NET "ADCB_12_n" LOC = "J2" ; - -## DAC -NET "DAC_LOCK" LOC = "P4" ; -NET "DACA<0>" LOC = "P8" ; -NET "DACA<1>" LOC = "P9" ; -NET "DACA<2>" LOC = "R5" ; -NET "DACA<3>" LOC = "R6" ; -NET "DACA<4>" LOC = "P7" ; -NET "DACA<5>" LOC = "P6" ; -NET "DACA<6>" LOC = "T3" ; -NET "DACA<7>" LOC = "T4" ; -NET "DACA<8>" LOC = "R3" ; -NET "DACA<9>" LOC = "R4" ; -NET "DACA<10>" LOC = "R2" ; -NET "DACA<11>" LOC = "N1" ; -NET "DACA<12>" LOC = "N2" ; -NET "DACA<13>" LOC = "N5" ; -NET "DACA<14>" LOC = "N4" ; -NET "DACA<15>" LOC = "M2" ; -NET "DACB<0>" LOC = "M5" ; -NET "DACB<1>" LOC = "M6" ; -NET "DACB<2>" LOC = "M4" ; -NET "DACB<3>" LOC = "M3" ; -NET "DACB<4>" LOC = "M8" ; -NET "DACB<5>" LOC = "M7" ; -NET "DACB<6>" LOC = "L4" ; -NET "DACB<7>" LOC = "L3" ; -NET "DACB<8>" LOC = "K3" ; -NET "DACB<9>" LOC = "K2" ; -NET "DACB<10>" LOC = "K5" ; -NET "DACB<11>" LOC = "K4" ; -NET "DACB<12>" LOC = "M10" ; -NET "DACB<13>" LOC = "M9" ; -NET "DACB<14>" LOC = "J5" ; -NET "DACB<15>" LOC = "J4" ; - -## TX DB GPIO -NET "io_tx<15>" LOC = "K6" ; -NET "io_tx<14>" LOC = "L7" ; -NET "io_tx<13>" LOC = "H2" ; -NET "io_tx<12>" LOC = "H1" ; -NET "io_tx<11>" LOC = "L10" ; -NET "io_tx<10>" LOC = "L9" ; -NET "io_tx<9>" LOC = "G3" ; -NET "io_tx<8>" LOC = "F3" ; -NET "io_tx<7>" LOC = "K7" ; -NET "io_tx<6>" LOC = "J6" ; -NET "io_tx<5>" LOC = "E1" ; -NET "io_tx<4>" LOC = "F2" ; -NET "io_tx<3>" LOC = "J7" ; -NET "io_tx<2>" LOC = "H6" ; -NET "io_tx<1>" LOC = "F5" ; -NET "io_tx<0>" LOC = "G4" ; - -## RX DB GPIO -NET "io_rx<15>" LOC = "AD1" ; -NET "io_rx<14>" LOC = "AD2" ; -NET "io_rx<13>" LOC = "AC2" ; -NET "io_rx<12>" LOC = "AC3" ; -NET "io_rx<11>" LOC = "W7" ; -NET "io_rx<10>" LOC = "W6" ; -NET "io_rx<9>" LOC = "U9" ; -NET "io_rx<8>" LOC = "V8" ; -NET "io_rx<7>" LOC = "AB1" ; -NET "io_rx<6>" LOC = "AC1" ; -NET "io_rx<5>" LOC = "V7" ; -NET "io_rx<4>" LOC = "V6" ; -NET "io_rx<3>" LOC = "Y5" ; -NET "io_rx<2>" LOC = "R10" ; -NET "io_rx<1>" LOC = "R1" ; -NET "io_rx<0>" LOC = "M1" ; - -## MISC -NET "leds<5>" LOC = "AF25" ; -NET "leds<4>" LOC = "AE25" ; -NET "leds<3>" LOC = "AF23" ; -NET "leds<2>" LOC = "AE23" ; -NET "leds<1>" LOC = "AB18" ; -NET "FPGA_RESET" LOC = "K24" ; - -## Debug -NET "debug_clk<0>" LOC = "AA10" ; -NET "debug_clk<1>" LOC = "AD11" ; -NET "debug<0>" LOC = "AC19" ; -NET "debug<1>" LOC = "AF20" ; -NET "debug<2>" LOC = "AE20" ; -NET "debug<3>" LOC = "AC16" ; -NET "debug<4>" LOC = "AB16" ; -NET "debug<5>" LOC = "AF19" ; -NET "debug<6>" LOC = "AE19" ; -NET "debug<7>" LOC = "V15" ; -NET "debug<8>" LOC = "U15" ; -NET "debug<9>" LOC = "AE17" ; -NET "debug<10>" LOC = "AD17" ; -NET "debug<11>" LOC = "V14" ; -NET "debug<12>" LOC = "W15" ; -NET "debug<13>" LOC = "AC15" ; -NET "debug<14>" LOC = "AD14" ; -NET "debug<15>" LOC = "AC14" ; -NET "debug<16>" LOC = "AC11" ; -NET "debug<17>" LOC = "AB12" ; -NET "debug<18>" LOC = "AC12" ; -NET "debug<19>" LOC = "V13" ; -NET "debug<20>" LOC = "W13" ; -NET "debug<21>" LOC = "AE8" ; -NET "debug<22>" LOC = "AF8" ; -NET "debug<23>" LOC = "V12" ; -NET "debug<24>" LOC = "W12" ; -NET "debug<25>" LOC = "AB9" ; -NET "debug<26>" LOC = "AC9" ; -NET "debug<27>" LOC = "AC8" ; -NET "debug<28>" LOC = "AB7" ; -NET "debug<29>" LOC = "V11" ; -NET "debug<30>" LOC = "U11" ; -NET "debug<31>" LOC = "Y10" ; - -## UARTS -NET "TXD<3>" LOC = "AD20" ; -NET "TXD<2>" LOC = "AC20" ; -NET "TXD<1>" LOC = "AD19" ; -NET "RXD<3>" LOC = "AF17" ; -NET "RXD<2>" LOC = "AF15" ; -NET "RXD<1>" LOC = "AD12" ; - -## AD9510 -NET "clk_status" LOC = "AD22" ; -NET "CLK_FUNC" LOC = "AC21" ; -NET "clk_sel<0>" LOC = "AE21" ; -NET "clk_sel<1>" LOC = "AD21" ; -NET "clk_en<1>" LOC = "AA17" ; -NET "clk_en<0>" LOC = "Y17" ; - -## I2C -NET "SDA" LOC = "V16" ; -NET "SCL" LOC = "U16" ; - -## Timing -NET "PPS_IN" LOC = "AB6" ; -NET "PPS2_IN" LOC = "AA20" ; - -## SPI -NET "SEN_CLK" LOC = "AA18" ; -NET "MOSI_CLK" LOC = "W17" ; -NET "SCLK_CLK" LOC = "V17" ; -NET "MISO_CLK" LOC = "AC10" ; - -NET "SEN_DAC" LOC = "AE7" ; -NET "SCLK_DAC" LOC = "AF5" ; -NET "MOSI_DAC" LOC = "AE6" ; -NET "MISO_DAC" LOC = "Y3" ; - -NET "SCLK_ADC" LOC = "B1" ; -NET "MOSI_ADC" LOC = "J8" ; -NET "SEN_ADC" LOC = "J9" ; - -NET "MOSI_TX_ADC" LOC = "V10" ; -NET "SEN_TX_ADC" LOC = "W10" ; -NET "SCLK_TX_ADC" LOC = "AC6" ; -NET "MISO_TX_ADC" LOC = "G1" ; - -NET "MOSI_TX_DAC" LOC = "AD6" ; -NET "SEN_TX_DAC" LOC = "AE4" ; -NET "SCLK_TX_DAC" LOC = "AF4" ; - -NET "SCLK_TX_DB" LOC = "AE3" ; -NET "MOSI_TX_DB" LOC = "AF3" ; -NET "SEN_TX_DB" LOC = "W9" ; -NET "MISO_TX_DB" LOC = "AA5" ; - -NET "MOSI_RX_ADC" LOC = "E3" ; -NET "SCLK_RX_ADC" LOC = "F4" ; -NET "SEN_RX_ADC" LOC = "D3" ; -NET "MISO_RX_ADC" LOC = "C1" ; - -NET "SCLK_RX_DAC" LOC = "E4" ; -NET "SEN_RX_DAC" LOC = "K9" ; -NET "MOSI_RX_DAC" LOC = "K8" ; - -NET "SCLK_RX_DB" LOC = "G6" ; -NET "MOSI_RX_DB" LOC = "H7" ; -NET "SEN_RX_DB" LOC = "B2" ; -NET "MISO_RX_DB" LOC = "H4" ; - -## ETH PHY -NET "CLK_TO_MAC" LOC = "P26" ; - -NET "GMII_TXD<7>" LOC = "G21" ; -NET "GMII_TXD<6>" LOC = "C26" ; -NET "GMII_TXD<5>" LOC = "C25" ; -NET "GMII_TXD<4>" LOC = "J21" ; -NET "GMII_TXD<3>" LOC = "H21" ; -NET "GMII_TXD<2>" LOC = "D25" ; -NET "GMII_TXD<1>" LOC = "D24" ; -NET "GMII_TXD<0>" LOC = "E26" ; -NET "GMII_TX_EN" LOC = "D26" ; -NET "GMII_TX_ER" LOC = "J19" ; -NET "GMII_GTX_CLK" LOC = "J20" ; -NET "GMII_TX_CLK" LOC = "P25" ; - -NET "GMII_RX_CLK" LOC = "P21" ; -NET "GMII_RXD<7>" LOC = "G22" ; -NET "GMII_RXD<6>" LOC = "K19" ; -NET "GMII_RXD<5>" LOC = "K18" ; -NET "GMII_RXD<4>" LOC = "E24" ; -NET "GMII_RXD<3>" LOC = "F23" ; -NET "GMII_RXD<2>" LOC = "L18" ; -NET "GMII_RXD<1>" LOC = "L17" ; -NET "GMII_RXD<0>" LOC = "F25" ; -NET "GMII_RX_DV" LOC = "F24" ; -NET "GMII_RX_ER" LOC = "L20" ; -NET "GMII_CRS" LOC = "K20" ; -NET "GMII_COL" LOC = "G23" ; - -NET "PHY_INTn" LOC = "L22" ; -NET "MDIO" LOC = "K21" ; -NET "MDC" LOC = "J23" ; -NET "PHY_RESETn" LOC = "J22" ; -NET "ETH_LED" LOC = "H20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; - -## MIMO Interface -NET "exp_time_out_p" LOC = "Y14" ; -NET "exp_time_out_n" LOC = "AA14" ; -NET "exp_time_in_p" LOC = "N18" ; -NET "exp_time_in_n" LOC = "N17" ; -NET "exp_user_out_p" LOC = "AF14" ; -NET "exp_user_out_n" LOC = "AE14" ; -NET "exp_user_in_p" LOC = "L24" ; -NET "exp_user_in_n" LOC = "M23" ; - -## SERDES -NET "ser_enable" LOC = "R20" ; -NET "ser_prbsen" LOC = "U23" ; -NET "ser_loopen" LOC = "R19" ; -NET "ser_rx_en" LOC = "Y21" ; -NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK -NET "ser_t<15>" LOC = "V23" ; -NET "ser_t<14>" LOC = "U22" ; -NET "ser_t<13>" LOC = "V24" ; -NET "ser_t<12>" LOC = "V25" ; -NET "ser_t<11>" LOC = "W23" ; -NET "ser_t<10>" LOC = "V22" ; -NET "ser_t<9>" LOC = "T18" ; -NET "ser_t<8>" LOC = "T17" ; -NET "ser_t<7>" LOC = "Y24" ; -NET "ser_t<6>" LOC = "Y25" ; -NET "ser_t<5>" LOC = "U21" ; -NET "ser_t<4>" LOC = "T20" ; -NET "ser_t<3>" LOC = "Y22" ; -NET "ser_t<2>" LOC = "Y23" ; -NET "ser_t<1>" LOC = "U19" ; -NET "ser_t<0>" LOC = "U18" ; -NET "ser_tkmsb" LOC = "AA24" ; -NET "ser_tklsb" LOC = "AA25" ; -NET "ser_rx_clk" LOC = "P18" ; -NET "ser_r<15>" LOC = "V21" ; -NET "ser_r<14>" LOC = "U20" ; -NET "ser_r<13>" LOC = "AA22" ; -NET "ser_r<12>" LOC = "AA23" ; -NET "ser_r<11>" LOC = "V18" ; -NET "ser_r<10>" LOC = "V19" ; -NET "ser_r<9>" LOC = "AB23" ; -NET "ser_r<8>" LOC = "AC26" ; -NET "ser_r<7>" LOC = "AB26" ; -NET "ser_r<6>" LOC = "AD26" ; -NET "ser_r<5>" LOC = "AC25" ; -NET "ser_r<4>" LOC = "W20" ; -NET "ser_r<3>" LOC = "W21" ; -NET "ser_r<2>" LOC = "AC23" ; -NET "ser_r<1>" LOC = "AC24" ; -NET "ser_r<0>" LOC = "AE26" ; -NET "ser_rkmsb" LOC = "AD25" ; -NET "ser_rklsb" LOC = "Y20" ; - -## SRAM -NET "RAM_D<35>" LOC = "K16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<34>" LOC = "D20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<33>" LOC = "C20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<32>" LOC = "E21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<31>" LOC = "D21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<30>" LOC = "C21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<29>" LOC = "B21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<28>" LOC = "H17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<27>" LOC = "G17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<26>" LOC = "B23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<25>" LOC = "A22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<24>" LOC = "D23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<23>" LOC = "C23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<22>" LOC = "D22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<21>" LOC = "C22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<20>" LOC = "F19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<19>" LOC = "G20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<18>" LOC = "F20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<17>" LOC = "F7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<16>" LOC = "E7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<15>" LOC = "G9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<14>" LOC = "H9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<13>" LOC = "G10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<12>" LOC = "H10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<11>" LOC = "A4" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<10>" LOC = "B4" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<9>" LOC = "C5" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<8>" LOC = "D6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<7>" LOC = "J11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<6>" LOC = "K11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<5>" LOC = "B7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<4>" LOC = "C7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<3>" LOC = "B6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<2>" LOC = "C6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<1>" LOC = "C8" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_D<0>" LOC = "D8" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<0>" LOC = "C11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<1>" LOC = "E12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<2>" LOC = "F12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<3>" LOC = "D13" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<4>" LOC = "C12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<5>" LOC = "A12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<6>" LOC = "B12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<7>" LOC = "E14" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<8>" LOC = "F14" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<9>" LOC = "B15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<10>" LOC = "A15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<11>" LOC = "D16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<12>" LOC = "C15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<13>" LOC = "D17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<14>" LOC = "C16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<15>" LOC = "F15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<16>" LOC = "C17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<17>" LOC = "B17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<18>" LOC = "B18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<19>" LOC = "A18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_A<20>" LOC = "D18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_BWn<3>" LOC = "D9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_BWn<2>" LOC = "A9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_BWn<1>" LOC = "B9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_BWn<0>" LOC = "G12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_ZZ" LOC = "J12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_LDn" LOC = "H12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_OEn" LOC = "C10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_WEn" LOC = "D10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_CENn" LOC = "B10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; -NET "RAM_CLK" LOC = "A10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; - -## SPI Flash -NET "flash_miso" LOC = "AF24" ; -NET "flash_clk" LOC = "AE24" ; -NET "flash_mosi" LOC = "AB15" ; -NET "flash_cs" LOC = "AA7" ; - -## MISC FPGA, unused for now -#NET "PROG_B" LOC = "A2" ; -#NET "PUDC_B" LOC = "G8" ; -#NET "DONE" LOC = "AB21" ; -#NET "INIT_B" LOC = "AA15" ; - - -#NET "unnamed_net19" LOC = "AE9" ; # VS1 -#NET "unnamed_net18" LOC = "AF9" ; # VS0 -#NET "unnamed_net17" LOC = "AA12" ; # VS2 -#NET "unnamed_net16" LOC = "Y7" ; # M2 -#NET "unnamed_net15" LOC = "AC4" ; # M1 -#NET "unnamed_net14" LOC = "AD4" ; # M0 -#NET "unnamed_net13" LOC = "D4" ; # TMS -#NET "unnamed_net12" LOC = "E23" ; # TDO -#NET "unnamed_net11" LOC = "G7" ; # TDI -#NET "unnamed_net10" LOC = "A25" ; # TCK -#NET "unnamed_net20" LOC = "V20" ; # SUSPEND - - -NET "clk_to_mac" TNM_NET = "clk_to_mac"; -TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; - -NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; -TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; - -NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; -TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; - -NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; -TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; - -TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns; - -#NET "CLK_FPGA_P" CLOCK_DEDICATED_ROUTE = FALSE; -#PIN "DCM_INST/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; - -#NET "RAM_CLK" CLOCK_DEDICATED_ROUTE = FALSE; -#PIN "DCM_INST1/DCM_SP.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE; - - diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v deleted file mode 100644 index 7bf467fde..000000000 --- a/usrp2/top/u2plus/u2plus.v +++ /dev/null @@ -1,454 +0,0 @@ -`timescale 1ns / 1ps -//`define LVDS 1 -//`define DCM_FOR_RAMCLK -////////////////////////////////////////////////////////////////////////////////// - -module u2plus - ( - input CLK_FPGA_P, input CLK_FPGA_N, // Diff - - // ADC - input ADC_clkout_p, input ADC_clkout_n, - input ADCA_12_p, input ADCA_12_n, - input ADCA_10_p, input ADCA_10_n, - input ADCA_8_p, input ADCA_8_n, - input ADCA_6_p, input ADCA_6_n, - input ADCA_4_p, input ADCA_4_n, - input ADCA_2_p, input ADCA_2_n, - input ADCA_0_p, input ADCA_0_n, - input ADCB_12_p, input ADCB_12_n, - input ADCB_10_p, input ADCB_10_n, - input ADCB_8_p, input ADCB_8_n, - input ADCB_6_p, input ADCB_6_n, - input ADCB_4_p, input ADCB_4_n, - input ADCB_2_p, input ADCB_2_n, - input ADCB_0_p, input ADCB_0_n, - - // DAC - output reg [15:0] DACA, - output reg [15:0] DACB, - input DAC_LOCK, // unused for now - - // DB IO Pins - inout [15:0] io_tx, - inout [15:0] io_rx, - - // Misc, debug - output [5:1] leds, // LED4 is shared w/INIT_B - input FPGA_RESET, - output [1:0] debug_clk, - output [31:0] debug, - output [3:1] TXD, input [3:1] RXD, // UARTs - //input [3:0] dipsw, // Forgot DIP Switches... - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input CLK_FUNC, // FIXME is an input to control the 9510 - input clk_status, - - inout SCL, inout SDA, // I2C - - // PPS - input PPS_IN, input PPS2_IN, - - // SPI - output SEN_CLK, output SCLK_CLK, output MOSI_CLK, input MISO_CLK, - output SEN_DAC, output SCLK_DAC, output MOSI_DAC, input MISO_DAC, - output SEN_ADC, output SCLK_ADC, output MOSI_ADC, - output SEN_TX_DB, output SCLK_TX_DB, output MOSI_TX_DB, input MISO_TX_DB, - output SEN_TX_DAC, output SCLK_TX_DAC, output MOSI_TX_DAC, - output SEN_TX_ADC, output SCLK_TX_ADC, output MOSI_TX_ADC, input MISO_TX_ADC, - output SEN_RX_DB, output SCLK_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, - output SEN_RX_DAC, output SCLK_RX_DAC, output MOSI_RX_DAC, - output SEN_RX_ADC, output SCLK_RX_ADC, output MOSI_RX_ADC, input MISO_RX_ADC, - - // GigE PHY - input CLK_TO_MAC, - - output reg [7:0] GMII_TXD, - output reg GMII_TX_EN, - output reg GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - input GMII_RX_CLK, - input [7:0] GMII_RXD, - input GMII_RX_DV, - input GMII_RX_ER, - input GMII_COL, - input GMII_CRS, - - input PHY_INTn, // open drain - inout MDIO, - output MDC, - output PHY_RESETn, - output ETH_LED, - -// input POR, - - // Expansion - input exp_time_in_p, input exp_time_in_n, // Diff - output exp_time_out_p, output exp_time_out_n, // Diff - input exp_user_in_p, input exp_user_in_n, // Diff - output exp_user_out_p, output exp_user_out_n, // Diff - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output reg [15:0] ser_t, - output reg ser_tklsb, - output reg ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // SRAM - inout [35:0] RAM_D, - output [20:0] RAM_A, - output [3:0] RAM_BWn, - output RAM_ZZ, - output RAM_LDn, - output RAM_OEn, - output RAM_WEn, - output RAM_CENn, - output RAM_CLK, - - // SPI Flash - output flash_cs, - output flash_clk, - output flash_mosi, - input flash_miso - ); - - wire CLK_TO_MAC_int, CLK_TO_MAC_int2; - IBUFG phyclk (.O(CLK_TO_MAC_int), .I(CLK_TO_MAC)); - BUFG phyclk2 (.O(CLK_TO_MAC_int2), .I(CLK_TO_MAC_int)); - - // FPGA-specific pins connections - wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; - - IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; - - wire exp_time_in; - IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); - defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; - - wire exp_time_out; - OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); - defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; - - wire exp_user_in; - IBUFDS exp_user_in_pin (.O(exp_user_in),.I(exp_user_in_p),.IB(exp_user_in_n)); - defparam exp_user_in_pin.IOSTANDARD = "LVDS_25"; - - wire exp_user_out; - OBUFDS exp_user_out_pin (.O(exp_user_out_p),.OB(exp_user_out_n),.I(exp_user_out)); - defparam exp_user_out_pin.IOSTANDARD = "LVDS_25"; - - reg [5:0] clock_ready_d; - always @(posedge clk_fpga) - clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; - wire dcm_rst = ~&clock_ready_d & |clock_ready_d; - - // ADC A is inverted on the schematic to facilitate a clean layout - // We account for that here by inverting it -`ifdef LVDS - wire [13:0] adc_a, adc_a_inv, adc_b; - capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds - (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), - .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p}, - {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), - .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n}, - {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), - .out({adc_a_inv,adc_b})); - assign adc_a = ~adc_a_inv; -`else - reg [13:0] adc_a, adc_b; - always @(posedge dsp_clk) - begin - adc_a <= ~{ADCA_12_p,ADCA_12_n, ADCA_10_p,ADCA_10_n, ADCA_8_p,ADCA_8_n, ADCA_6_p,ADCA_6_n, - ADCA_4_p,ADCA_4_n, ADCA_2_p,ADCA_2_n, ADCA_0_p,ADCA_0_n }; - adc_b <= {ADCB_12_p,ADCB_12_n, ADCB_10_p,ADCB_10_n, ADCB_8_p,ADCB_8_n, ADCB_6_p,ADCB_6_n, - ADCB_4_p,ADCB_4_n, ADCB_2_p,ADCB_2_n, ADCB_0_p,ADCB_0_n }; - end -`endif // !`ifdef LVDS - - // Handle Clocks - DCM DCM_INST (.CLKFB(dsp_clk), - .CLKIN(clk_fpga), - .DSSEN(0), - .PSCLK(0), - .PSEN(0), - .PSINCDEC(0), - .RST(dcm_rst), - .CLKDV(clk_div), - .CLKFX(), - .CLKFX180(), - .CLK0(dcm_out), - .CLK2X(), - .CLK2X180(), - .CLK90(), - .CLK180(), - .CLK270(clk270_100), - .LOCKED(LOCKED_OUT), - .PSDONE(), - .STATUS()); - defparam DCM_INST.CLK_FEEDBACK = "1X"; - defparam DCM_INST.CLKDV_DIVIDE = 2.0; - defparam DCM_INST.CLKFX_DIVIDE = 1; - defparam DCM_INST.CLKFX_MULTIPLY = 4; - defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; - defparam DCM_INST.CLKIN_PERIOD = 10.000; - defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; - defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; - defparam DCM_INST.FACTORY_JF = 16'h8080; - defparam DCM_INST.PHASE_SHIFT = 0; - defparam DCM_INST.STARTUP_WAIT = "FALSE"; - - BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); - BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); - - // Create clock for external SRAM thats -90degree phase to DSPCLK (i.e) 2nS earlier at 100MHz. - BUFG clk270_100_buf_i1 (.I(clk270_100), - .O(clk270_100_buf)); - OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK), - .C0(clk270_100_buf), - .C1(~clk270_100_buf), - .CE(1'b1), - .D0(1'b1), - .D1(1'b0), - .R(1'b0), - .S(1'b0)); - - // I2C -- Don't use external transistors for open drain, the FPGA implements this - IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); - IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); - - // LEDs are active low outputs - wire [5:0] leds_int; - assign {ETH_LED,leds} = {6'b011111 ^ leds_int}; // drive low to turn on leds - - // SPI - wire miso, mosi, sclk; - - assign {SCLK_CLK,MOSI_CLK} = ~SEN_CLK ? {sclk,mosi} : 2'B0; - assign {SCLK_DAC,MOSI_DAC} = ~SEN_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_ADC,MOSI_ADC} = ~SEN_ADC ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_DAC,MOSI_TX_DAC} = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_ADC,MOSI_TX_ADC} = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_DAC,MOSI_RX_DAC} = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_ADC,MOSI_RX_ADC} = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0; - - assign miso = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) | - (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) | - (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC); - - wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; - wire [7:0] GMII_TXD_unreg; - wire GMII_GTX_CLK_int; - - always @(posedge GMII_GTX_CLK_int) - begin - GMII_TX_EN <= GMII_TX_EN_unreg; - GMII_TX_ER <= GMII_TX_ER_unreg; - GMII_TXD <= GMII_TXD_unreg; - end - - OFDDRRSE OFDDRRSE_gmii_inst - (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) - .C0(GMII_GTX_CLK_int), // 0 degree clock input - .C1(~GMII_GTX_CLK_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - - wire ser_tklsb_unreg, ser_tkmsb_unreg; - wire [15:0] ser_t_unreg; - wire ser_tx_clk_int; - - always @(posedge ser_tx_clk_int) - begin - ser_tklsb <= ser_tklsb_unreg; - ser_tkmsb <= ser_tkmsb_unreg; - ser_t <= ser_t_unreg; - end - - assign ser_tx_clk = clk_fpga; - - reg [15:0] ser_r_int; - reg ser_rklsb_int, ser_rkmsb_int; - - always @(posedge ser_rx_clk) - begin - ser_r_int <= ser_r; - ser_rklsb_int <= ser_rklsb; - ser_rkmsb_int <= ser_rkmsb; - end - - /* - OFDDRRSE OFDDRRSE_serdes_inst - (.Q(ser_tx_clk), // Data output (connect directly to top-level port) - .C0(ser_tx_clk_int), // 0 degree clock input - .C1(~ser_tx_clk_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - */ - - - // - // Instantiate IO for Bidirectional bus to SRAM - // - wire [35:0] RAM_D_pi; - wire [35:0] RAM_D_po; - wire RAM_D_poe; - - genvar i; - - generate - for (i=0;i<36;i=i+1) - begin : gen_RAM_D_IO - - IOBUF #( - .DRIVE(12), - .IOSTANDARD("LVCMOS25"), - .SLEW("FAST") - ) - RAM_D_i ( - .O(RAM_D_pi[i]), - .I(RAM_D_po[i]), - .IO(RAM_D[i]), - .T(RAM_D_poe) - ); - end // block: gen_RAM_D_IO - endgenerate - - - - wire [15:0] dac_a_int, dac_b_int; - // DAC A and B are swapped in schematic to facilitate clean layout - // DAC A is also inverted in schematic to facilitate clean layout - always @(negedge dsp_clk) DACA <= ~dac_b_int; - always @(negedge dsp_clk) DACB <= dac_a_int; - - wire pps; - assign pps = PPS_IN ^ PPS2_IN; - - u2plus_core u2p_c(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (CLK_TO_MAC_int2), - .pps_in (pps), - .leds (leds_int), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_time_in (exp_time_in), - .exp_time_out (exp_time_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD_unreg[7:0]), - .GMII_TX_EN (GMII_TX_EN_unreg), - .GMII_TX_ER (GMII_TX_ER_unreg), - .GMII_GTX_CLK (GMII_GTX_CLK_int), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk_int), - .ser_t (ser_t_unreg[15:0]), - .ser_tklsb (ser_tklsb_unreg), - .ser_tkmsb (ser_tkmsb_unreg), - .ser_rx_clk (ser_rx_clk), - .ser_r (ser_r_int[15:0]), - .ser_rklsb (ser_rklsb_int), - .ser_rkmsb (ser_rkmsb_int), - .adc_a (adc_a[13:0]), - .adc_ovf_a (1'b0), - .adc_on_a (), - .adc_oe_a (), - .adc_b (adc_b[13:0]), - .adc_ovf_b (1'b0), - .adc_on_b (), - .adc_oe_b (), - .dac_a (dac_a_int[15:0]), - .dac_b (dac_b_int[15:0]), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk), - .mosi (mosi), - .miso (miso), - .sen_clk (SEN_CLK), - .sen_dac (SEN_DAC), - .sen_adc (SEN_ADC), - .sen_tx_db (SEN_TX_DB), - .sen_tx_adc (SEN_TX_ADC), - .sen_tx_dac (SEN_TX_DAC), - .sen_rx_db (SEN_RX_DB), - .sen_rx_adc (SEN_RX_ADC), - .sen_rx_dac (SEN_RX_DAC), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D_po (RAM_D_po), - .RAM_D_pi (RAM_D_pi), - .RAM_D_poe (RAM_D_poe), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (TXD[3:1]), - .uart_rx_i ({1'b1,RXD[3:1]}), - .uart_baud_o (), - .sim_mode (1'b0), - .clock_divider (2), - .button (FPGA_RESET), - .spiflash_cs (flash_cs), - .spiflash_clk (flash_clk), - .spiflash_miso (flash_miso), - .spiflash_mosi (flash_mosi) - ); - - // Drive low so that RAM does not sleep. - assign RAM_ZZ = 0; - // Byte Writes are qualified by the global write enable - // Always do 36bit operations to extram. - assign RAM_BWn = 4'b0000; - -endmodule // u2plus diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v deleted file mode 100644 index ee5d7efcd..000000000 --- a/usrp2/top/u2plus/u2plus_core.v +++ /dev/null @@ -1,708 +0,0 @@ -// //////////////////////////////////////////////////////////////////////////////// -// Module Name: u2_core -// //////////////////////////////////////////////////////////////////////////////// - -module u2plus_core - (// Clocks - input dsp_clk, - input wb_clk, - output clock_ready, - input clk_to_mac, - input pps_in, - - // Misc, debug - output [7:0] leds, - output [31:0] debug, - output [1:0] debug_clk, - - // Expansion - input exp_time_in, - output exp_time_out, - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output [7:0] GMII_TXD, - output GMII_TX_EN, - output GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - output PHY_RESETn, - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output [15:0] ser_t, - output ser_tklsb, - output ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - input por, - output config_success, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_on_a, - output adc_oe_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_on_b, - output adc_oe_b, - - // DAC - output [15:0] dac_a, - output [15:0] dac_b, - - // I2C - input scl_pad_i, - output scl_pad_o, - output scl_pad_oen_o, - input sda_pad_i, - output sda_pad_o, - output sda_pad_oen_o, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Generic SPI - output sclk, - output mosi, - input miso, - output sen_clk, - output sen_dac, - output sen_adc, - output sen_tx_db, - output sen_tx_adc, - output sen_tx_dac, - output sen_rx_db, - output sen_rx_adc, - output sen_rx_dac, - - // GPIO to DBoards - inout [15:0] io_tx, - inout [15:0] io_rx, - - // External RAM - input [35:0] RAM_D_pi, - output [35:0] RAM_D_po, - output RAM_D_poe, - output [20:0] RAM_A, - output RAM_CE1n, - output RAM_CENn, - output RAM_WEn, - output RAM_OEn, - output RAM_LDn, - - // Debug stuff - output [3:0] uart_tx_o, - input [3:0] uart_rx_i, - output [3:0] uart_baud_o, - input sim_mode, - input [3:0] clock_divider, - input button, - - output spiflash_cs, output spiflash_clk, input spiflash_miso, output spiflash_mosi - ); - - localparam SR_MISC = 0; // 7 regs - localparam SR_SIMTIMER = 8; // 2 - localparam SR_TIME64 = 10; // 6 - localparam SR_BUF_POOL = 16; // 4 - - localparam SR_RX_FRONT = 24; // 5 - localparam SR_RX_CTRL0 = 32; // 9 - localparam SR_RX_DSP0 = 48; // 7 - localparam SR_RX_CTRL1 = 80; // 9 - localparam SR_RX_DSP1 = 96; // 7 - - localparam SR_TX_FRONT = 128; // ? - localparam SR_TX_CTRL = 144; // 6 - localparam SR_TX_DSP = 160; // 5 - - localparam SR_UDP_SM = 192; // 64 - - // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 - // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs - // localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo - localparam DSP_RX_FIFOSIZE = 10; - localparam ETH_TX_FIFOSIZE = 9; - localparam ETH_RX_FIFOSIZE = 11; - localparam SERDES_TX_FIFOSIZE = 9; - localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? - - wire [7:0] set_addr, set_addr_dsp; - wire [31:0] set_data, set_data_dsp; - wire set_stb, set_stb_dsp; - - reg wb_rst; - wire dsp_rst = wb_rst; - - wire [31:0] status; - wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; - wire proc_int, overrun0, overrun1, underrun; - wire [3:0] uart_tx_int, uart_rx_int; - - wire [31:0] debug_gpio_0, debug_gpio_1; - wire [31:0] atr_lines; - - wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2; - - wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; - wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; - wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; - - wire serdes_link_up; - wire epoch; - wire [31:0] irq; - wire [63:0] vita_time, vita_time_pps; - - wire run_rx0, run_rx1, run_tx; - reg run_rx0_d1, run_rx1_d1; - - // /////////////////////////////////////////////////////////////////////////////////////////////// - // Wishbone Single Master INTERCON - localparam dw = 32; // Data bus width - localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space - localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. - - wire [dw-1:0] m0_dat_o, m0_dat_i; - wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, - s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, - s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, - sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o, sf_dat_i, sf_dat_o; - wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; - wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; - wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; - wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; - wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; - wire m0_err, m0_rty; - wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we; - - wb_1master #(.decode_w(8), - .s0_addr(8'b0000_0000),.s0_mask(8'b1100_0000), // Main RAM (0-16K) - .s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000), // Packet Router (16-20K) - .s2_addr(8'b0101_0000),.s2_mask(8'b1111_1100), // SPI - .s3_addr(8'b0101_0100),.s3_mask(8'b1111_1100), // I2C - .s4_addr(8'b0101_1000),.s4_mask(8'b1111_1100), // GPIO - .s5_addr(8'b0101_1100),.s5_mask(8'b1111_1100), // Readback - .s6_addr(8'b0110_0000),.s6_mask(8'b1111_0000), // Ethernet MAC - .s7_addr(8'b0111_0000),.s7_mask(8'b1111_0000), // 20K-24K, Settings Bus (only uses 1K) - .s8_addr(8'b1000_0000),.s8_mask(8'b1111_1100), // PIC - .s9_addr(8'b1000_0100),.s9_mask(8'b1111_1100), // Unused - .sa_addr(8'b1000_1000),.sa_mask(8'b1111_1100), // UART - .sb_addr(8'b1000_1100),.sb_mask(8'b1111_1100), // ATR - .sc_addr(8'b1001_0000),.sc_mask(8'b1111_0000), // Unused - .sd_addr(8'b1010_0000),.sd_mask(8'b1111_0000), // ICAP - .se_addr(8'b1011_0000),.se_mask(8'b1111_0000), // SPI Flash - .sf_addr(8'b1100_0000),.sf_mask(8'b1100_0000), // 48K-64K, Boot RAM - .dw(dw),.aw(aw),.sw(sw)) wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), - .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), - .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), - .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), - .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), - .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), - .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), - .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), - .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), - .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), - .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), - .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), - .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), - .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), - .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), - .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), - .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), - .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), - .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), - .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), - .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), - .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), - .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), - .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0)); - - // //////////////////////////////////////////////////////////////////////////////////////// - // Reset Controller - - reg cpu_bldr_ctrl_state; - localparam CPU_BLDR_CTRL_WAIT = 0; - localparam CPU_BLDR_CTRL_DONE = 1; - - wire bldr_done; - wire por_rst; - wire [aw-1:0] cpu_adr; - - // Swap boot ram and main ram when in bootloader mode - assign m0_adr = (^cpu_adr[15:14] | (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_DONE)) ? cpu_adr : - cpu_adr ^ 16'hC000; - - system_control sysctrl - (.wb_clk_i(wb_clk), .wb_rst_o(por_rst), .ram_loader_done_i(1'b1) ); - - always @(posedge wb_clk) - if(por_rst) begin - cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_WAIT; - wb_rst <= 1'b1; - end - else begin - case(cpu_bldr_ctrl_state) - - CPU_BLDR_CTRL_WAIT: begin - wb_rst <= 1'b0; - if (bldr_done == 1'b1) begin //set by the bootloader - cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_DONE; - wb_rst <= 1'b1; - end - end - - CPU_BLDR_CTRL_DONE: begin //stay here forever - wb_rst <= 1'b0; - end - - endcase //cpu_bldr_ctrl_state - end - - // ///////////////////////////////////////////////////////////////////////// - // Processor - - assign bus_error = m0_err | m0_rty; - - wire [63:0] zpu_status; - zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) - zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(~wb_rst), - // Data Wishbone bus to system bus fabric - .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(cpu_adr), - .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), - // Interrupts and exceptions - .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); - - // ///////////////////////////////////////////////////////////////////////// - // Dual Ported Boot RAM -- D-Port is Slave #0 on main Wishbone - // Dual Ported Main RAM -- D-Port is Slave #F on main Wishbone - // I-port connects directly to processor - - bootram bootram(.clk(wb_clk), .reset(wb_rst), - .if_adr(14'b0), .if_data(), - .dwb_adr_i(sf_adr[13:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i), - .dwb_we_i(sf_we), .dwb_ack_o(sf_ack), .dwb_stb_i(sf_stb), .dwb_sel_i(sf_sel)); - -////blinkenlights v0.1 -//defparam bootram.RAM0.INIT_00=256'hbc32fff0_aa43502b_b00000fe_30630001_80000000_10600000_a48500ff_10a00000; -//defparam bootram.RAM0.INIT_01=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_308000ff_be23000c_a4640001; - -`include "bootloader.rmi" - - ram_harvard2 #(.AWIDTH(14),.RAM_SIZE(16384)) - sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .if_adr(14'b0), .if_data(), - .dwb_adr_i(s0_adr[13:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool, slave #1 - wire rd0_ready_i, rd0_ready_o; - wire rd1_ready_i, rd1_ready_o; - wire rd2_ready_i, rd2_ready_o; - wire rd3_ready_i, rd3_ready_o; - wire [35:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; - - wire wr0_ready_i, wr0_ready_o; - wire wr1_ready_i, wr1_ready_o; - wire wr2_ready_i, wr2_ready_o; - wire wr3_ready_i, wr3_ready_o; - wire [35:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - wire [35:0] tx_err_data; - wire tx_err_src_rdy, tx_err_dst_rdy; - - wire [31:0] router_debug; - - packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), - .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), - - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0), - - .status(status), .sys_int_o(buffer_int), .debug(router_debug), - - .ser_inp_data(wr0_dat), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), - .dsp0_inp_data(wr1_dat), .dsp0_inp_valid(wr1_ready_i), .dsp0_inp_ready(wr1_ready_o), - .dsp1_inp_data(wr3_dat), .dsp1_inp_valid(wr3_ready_i), .dsp1_inp_ready(wr3_ready_o), - .eth_inp_data(wr2_dat), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), - .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy), - - .ser_out_data(rd0_dat), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), - .dsp_out_data(rd1_dat), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), - .eth_out_data(rd2_dat), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) - ); - - // ///////////////////////////////////////////////////////////////////////// - // SPI -- Slave #2 - spi_top shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), - .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), - .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), - .ss_pad_o({sen_adc, sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), - .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); - - // ///////////////////////////////////////////////////////////////////////// - // I2C -- Slave #3 - i2c_master_top #(.ARST_LVL(1)) - i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_dat_i[31:8] = 24'd0; - - // ///////////////////////////////////////////////////////////////////////// - // GPIOs -- Slave #4 - nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), - .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), - .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio({io_tx,io_rx}) ); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool Status -- Slave #5 - - //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd6; - - wb_readback_mux buff_pool_status - (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), - .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - - .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), - .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), - .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(compat_num),.word13(irq), - .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]) - ); - - // ///////////////////////////////////////////////////////////////////////// - // Ethernet MAC Slave #6 - - simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE), - .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper - (.clk125(clk_to_mac), .reset(wb_rst), - .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), - .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), - .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), - .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .sys_clk(dsp_clk), - .rx_f36_data(wr2_dat), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), - .tx_f36_data(rd2_dat), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), - .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), - .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), - .mdio(MDIO), .mdc(MDC), - .debug(debug_mac)); - - // ///////////////////////////////////////////////////////////////////////// - // Settings Bus -- Slave #7 - settings_bus settings_bus - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), - .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), - .strobe(set_stb),.addr(set_addr),.data(set_data)); - - assign s7_dat_i = 32'd0; - - settings_bus_crossclock settings_bus_crossclock - (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), - .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); - - // Output control lines - wire [7:0] clock_outs, serdes_outs, adc_outs; - assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; - assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; - assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; - - wire phy_reset; - assign PHY_RESETn = ~phy_reset; - - setting_reg #(.my_addr(SR_MISC+0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), - .in(set_data),.out(clock_outs),.changed()); - setting_reg #(.my_addr(SR_MISC+1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(serdes_outs),.changed()); - setting_reg #(.my_addr(SR_MISC+2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(adc_outs),.changed()); - setting_reg #(.my_addr(SR_MISC+4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phy_reset),.changed()); - setting_reg #(.my_addr(SR_MISC+5),.width(1)) sr_bld (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(bldr_done),.changed()); - - // ///////////////////////////////////////////////////////////////////////// - // LEDS - // register 8 determines whether leds are controlled by SW or not - // 1 = controlled by HW, 0 = by SW - // In Rev3 there are only 6 leds, and the highest one is on the ETH connector - - wire [7:0] led_src, led_sw; - wire [7:0] led_hw = {run_tx, (run_rx0_d1 | run_rx1_d1), clk_status, serdes_link_up, 1'b0}; - - setting_reg #(.my_addr(SR_MISC+3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_sw),.changed()); - - setting_reg #(.my_addr(SR_MISC+6),.width(8), .at_reset(8'b0001_1110)) - sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed()); - - assign leds = (led_src & led_hw) | (~led_src & led_sw); - - // ///////////////////////////////////////////////////////////////////////// - // Interrupt Controller, Slave #8 - - // Pass interrupts on dsp_clk to wb_clk. These need edge triggering in the pic - wire underrun_wb, overrun_wb, pps_wb; - - oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb)); - oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun0 | overrun1), .clk_out(wb_clk), .out(overrun_wb)); - oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb)); - - assign irq= {{8'b0}, - {uart_tx_int[3:0], uart_rx_int[3:0]}, - {2'b0, button, periodic_int, clk_status, serdes_link_up, 2'b00}, - {pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; - - pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), - .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), - .irq(irq) ); - - // ///////////////////////////////////////////////////////////////////////// - // Master Timer, Slave #9 - - // No longer used, replaced with simple_timer below - assign s9_ack = 0; - - // ///////////////////////////////////////////////////////////////////////// - // Simple Timer interrupts - - simple_timer #(.BASE(SR_SIMTIMER)) simple_timer - (.clk(wb_clk), .reset(wb_rst), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .onetime_int(onetime_int), .periodic_int(periodic_int)); - - // ///////////////////////////////////////////////////////////////////////// - // UART, Slave #10 - - quad_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries - (.clk_i(wb_clk),.rst_i(wb_rst), - .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), - .adr_i(sa_adr[6:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), - .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), - .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); - - // ///////////////////////////////////////////////////////////////////////// - // ATR Controller, Slave #11 - - atr_controller atr_controller - (.clk_i(wb_clk),.rst_i(wb_rst), - .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), - .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), - .run_rx(run_rx0_d1 | run_rx1_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); - - // ////////////////////////////////////////////////////////////////////////// - // Time Sync, Slave #12 - - // No longer used, see time_64bit. Still need to handle mimo time, though - assign sc_ack = 0; - - // ///////////////////////////////////////////////////////////////////////// - // ICAP for reprogramming the FPGA, Slave #13 (D) - - s3a_icap_wb s3a_icap_wb - (.clk(wb_clk), .reset(wb_rst), .cyc_i(sd_cyc), .stb_i(sd_stb), - .we_i(sd_we), .ack_o(sd_ack), .dat_i(sd_dat_o), .dat_o(sd_dat_i)); - - // ///////////////////////////////////////////////////////////////////////// - // SPI for Flash -- Slave #14 (E) - spi_top flash_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(se_adr[4:0]),.wb_dat_i(se_dat_o), - .wb_dat_o(se_dat_i),.wb_sel_i(se_sel),.wb_we_i(se_we),.wb_stb_i(se_stb), - .wb_cyc_i(se_cyc),.wb_ack_o(se_ack),.wb_err_o(se_err),.wb_int_o(spiflash_int), - .ss_pad_o(spiflash_cs), - .sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) ); - - // ///////////////////////////////////////////////////////////////////////// - // DSP RX 0 - wire [31:0] sample_rx0; - wire clear_rx0, strobe_rx0; - - always @(posedge dsp_clk) - run_rx0_d1 <= run_rx0; - - dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0 - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0), - .debug() ); - - setting_reg #(.my_addr(SR_RX_CTRL0+3)) sr_clear_rx0 - (.clk(dsp_clk),.rst(dsp_rst), - .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), - .out(),.changed(clear_rx0)); - - vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0 - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .vita_time(vita_time), .overrun(overrun0), - .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), - .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o), - .debug() ); - - // ///////////////////////////////////////////////////////////////////////// - // DSP RX 1 - wire [31:0] sample_rx1; - wire clear_rx1, strobe_rx1; - - always @(posedge dsp_clk) - run_rx1_d1 <= run_rx1; - - dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1), - .debug() ); - - setting_reg #(.my_addr(SR_RX_CTRL1+3)) sr_clear_rx1 - (.clk(dsp_clk),.rst(dsp_rst), - .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), - .out(),.changed(clear_rx1)); - - vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1 - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .vita_time(vita_time), .overrun(overrun1), - .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), - .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o), - .debug() ); - - // /////////////////////////////////////////////////////////////////////////////////// - // DSP TX - - wire [35:0] tx_data; - wire tx_src_rdy, tx_dst_rdy; - wire [31:0] debug_vt; - wire clear_tx; - - setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_tx)); - - assign RAM_A[20:18] = 3'b0; - - ext_fifo #(.EXT_WIDTH(36),.INT_WIDTH(36),.RAM_DEPTH(18),.FIFO_DEPTH(18)) - ext_fifo_i1 - (.int_clk(dsp_clk), - .ext_clk(dsp_clk), - .rst(dsp_rst | clear_tx), - .RAM_D_pi(RAM_D_pi), - .RAM_D_po(RAM_D_po), - .RAM_D_poe(RAM_D_poe), - .RAM_A(RAM_A[17:0]), - .RAM_WEn(RAM_WEn), - .RAM_CENn(RAM_CENn), - .RAM_LDn(RAM_LDn), - .RAM_OEn(RAM_OEn), - .RAM_CE1n(RAM_CE1n), - .datain(rd1_dat), - .src_rdy_i(rd1_ready_o), - .dst_rdy_o(rd1_ready_i), - .dataout(tx_data), - .src_rdy_o(tx_src_rdy), - .dst_rdy_i(tx_dst_rdy), - .debug(debug_extfifo), - .debug2(debug_extfifo2) ); - - vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), - .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), - .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), - .DSP_NUMBER(0)) - vita_tx_chain - (.clk(dsp_clk), .reset(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .vita_time(vita_time), - .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), - .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), - .dac_a(dac_a),.dac_b(dac_b), - .underrun(underrun), .run(run_tx), - .debug(debug_vt)); - - // /////////////////////////////////////////////////////////////////////////////////// - // SERDES - - serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes - (.clk(dsp_clk),.rst(dsp_rst), - .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .rd_dat_i(rd0_dat[31:0]),.rd_flags_i(rd0_dat[35:32]),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), - .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .wr_dat_o(wr0_dat[31:0]),.wr_flags_o(wr0_dat[35:32]),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), - .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), - .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), - .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); - - // ///////////////////////////////////////////////////////////////////////// - // VITA Timing - - wire [31:0] debug_sync; - - time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit - (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), - .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), - .debug(debug_sync)); - - // ///////////////////////////////////////////////////////////////////////////////////////// - // Debug Pins - - assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; - assign debug = 32'd0; - assign debug_gpio_0 = 32'd0; - assign debug_gpio_1 = 32'd0; - -endmodule // u2_core -- cgit v1.2.3 From bfaa5d1489c428bc49ed0a84f6732ceac703ac92 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 7 Jun 2011 19:42:18 -0700 Subject: added copyrights --- usrp2/control_lib/atr_controller.v | 17 +++++++++++++++++ usrp2/control_lib/atr_controller16.v | 17 +++++++++++++++++ usrp2/control_lib/bin2gray.v | 17 +++++++++++++++++ usrp2/control_lib/bootram.v | 17 +++++++++++++++++ usrp2/control_lib/clock_bootstrap_rom.v | 17 +++++++++++++++++ usrp2/control_lib/clock_control.v | 17 +++++++++++++++++ usrp2/control_lib/clock_control_tb.v | 17 +++++++++++++++++ usrp2/control_lib/dcache.v | 17 +++++++++++++++++ usrp2/control_lib/decoder_3_8.v | 17 +++++++++++++++++ usrp2/control_lib/dpram32.v | 17 +++++++++++++++++ usrp2/control_lib/fifo_to_wb.v | 17 +++++++++++++++++ usrp2/control_lib/fifo_to_wb_tb.v | 17 +++++++++++++++++ usrp2/control_lib/gray2bin.v | 17 +++++++++++++++++ usrp2/control_lib/gray_send.v | 17 +++++++++++++++++ usrp2/control_lib/icache.v | 17 +++++++++++++++++ usrp2/control_lib/longfifo.v | 17 +++++++++++++++++ usrp2/control_lib/medfifo.v | 17 +++++++++++++++++ usrp2/control_lib/mux4.v | 17 +++++++++++++++++ usrp2/control_lib/mux8.v | 17 +++++++++++++++++ usrp2/control_lib/mux_32_4.v | 17 +++++++++++++++++ usrp2/control_lib/oneshot_2clk.v | 17 +++++++++++++++++ usrp2/control_lib/priority_enc.v | 17 +++++++++++++++++ usrp2/control_lib/quad_uart.v | 17 +++++++++++++++++ usrp2/control_lib/ram_2port.v | 17 +++++++++++++++++ usrp2/control_lib/ram_2port_mixed_width.v | 17 +++++++++++++++++ usrp2/control_lib/ram_harv_cache.v | 17 +++++++++++++++++ usrp2/control_lib/ram_harvard.v | 17 +++++++++++++++++ usrp2/control_lib/ram_harvard2.v | 17 +++++++++++++++++ usrp2/control_lib/ram_loader.v | 17 +++++++++++++++++ usrp2/control_lib/ram_wb_harvard.v | 17 +++++++++++++++++ usrp2/control_lib/reset_sync.v | 17 +++++++++++++++++ usrp2/control_lib/s3a_icap_wb.v | 17 +++++++++++++++++ usrp2/control_lib/sd_spi.v | 17 +++++++++++++++++ usrp2/control_lib/sd_spi_tb.v | 17 +++++++++++++++++ usrp2/control_lib/sd_spi_wb.v | 17 +++++++++++++++++ usrp2/control_lib/setting_reg.v | 17 +++++++++++++++++ usrp2/control_lib/settings_bus.v | 17 +++++++++++++++++ usrp2/control_lib/settings_bus_16LE.v | 17 +++++++++++++++++ usrp2/control_lib/settings_bus_crossclock.v | 17 +++++++++++++++++ usrp2/control_lib/shortfifo.v | 17 +++++++++++++++++ usrp2/control_lib/simple_uart.v | 17 +++++++++++++++++ usrp2/control_lib/simple_uart_rx.v | 17 +++++++++++++++++ usrp2/control_lib/simple_uart_tx.v | 17 +++++++++++++++++ usrp2/control_lib/spi.v | 17 +++++++++++++++++ usrp2/control_lib/srl.v | 17 +++++++++++++++++ usrp2/control_lib/ss_rcvr.v | 17 +++++++++++++++++ usrp2/control_lib/system_control.v | 17 +++++++++++++++++ usrp2/control_lib/system_control_tb.v | 17 +++++++++++++++++ usrp2/control_lib/traffic_cop.v | 17 +++++++++++++++++ usrp2/control_lib/v5icap_wb.v | 17 +++++++++++++++++ usrp2/control_lib/wb_bridge_16_32.v | 17 +++++++++++++++++ usrp2/control_lib/wb_bus_writer.v | 17 +++++++++++++++++ usrp2/control_lib/wb_output_pins32.v | 17 +++++++++++++++++ usrp2/control_lib/wb_ram_block.v | 17 +++++++++++++++++ usrp2/control_lib/wb_ram_dist.v | 17 +++++++++++++++++ usrp2/control_lib/wb_readback_mux.v | 17 +++++++++++++++++ usrp2/control_lib/wb_readback_mux_16LE.v | 17 +++++++++++++++++ usrp2/control_lib/wb_regfile_2clock.v | 17 +++++++++++++++++ usrp2/control_lib/wb_semaphore.v | 17 +++++++++++++++++ usrp2/control_lib/wb_sim.v | 17 +++++++++++++++++ usrp2/extramfifo/ext_fifo.v | 17 +++++++++++++++++ usrp2/extramfifo/ext_fifo_tb.v | 17 +++++++++++++++++ usrp2/extramfifo/nobl_fifo.v | 17 +++++++++++++++++ usrp2/extramfifo/nobl_if.v | 17 +++++++++++++++++ usrp2/extramfifo/refill_randomizer.v | 17 +++++++++++++++++ usrp2/extramfifo/test_sram_if.v | 17 +++++++++++++++++ usrp2/fifo/buffer_int.v | 17 +++++++++++++++++ usrp2/fifo/buffer_int2.v | 17 +++++++++++++++++ usrp2/fifo/buffer_int_tb.v | 17 +++++++++++++++++ usrp2/fifo/buffer_pool.v | 17 +++++++++++++++++ usrp2/fifo/buffer_pool_tb.v | 17 +++++++++++++++++ usrp2/fifo/crossbar36.v | 17 +++++++++++++++++ usrp2/fifo/dsp_framer36.v | 17 +++++++++++++++++ usrp2/fifo/fifo19_mux.v | 17 +++++++++++++++++ usrp2/fifo/fifo19_pad.v | 17 +++++++++++++++++ usrp2/fifo/fifo19_to_fifo36.v | 17 +++++++++++++++++ usrp2/fifo/fifo19_to_ll8.v | 17 +++++++++++++++++ usrp2/fifo/fifo36_demux.v | 17 +++++++++++++++++ usrp2/fifo/fifo36_mux.v | 17 +++++++++++++++++ usrp2/fifo/fifo36_to_fifo19.v | 17 +++++++++++++++++ usrp2/fifo/fifo36_to_fifo72.v | 17 +++++++++++++++++ usrp2/fifo/fifo36_to_ll8.v | 17 +++++++++++++++++ usrp2/fifo/fifo72_to_fifo36.v | 17 +++++++++++++++++ usrp2/fifo/fifo_19to36_tb.v | 17 +++++++++++++++++ usrp2/fifo/fifo_2clock.v | 17 +++++++++++++++++ usrp2/fifo/fifo_2clock_cascade.v | 17 +++++++++++++++++ usrp2/fifo/fifo_cascade.v | 17 +++++++++++++++++ usrp2/fifo/fifo_long.v | 17 +++++++++++++++++ usrp2/fifo/fifo_pacer.v | 17 +++++++++++++++++ usrp2/fifo/fifo_short.v | 17 +++++++++++++++++ usrp2/fifo/fifo_tb.v | 17 +++++++++++++++++ usrp2/fifo/ll8_shortfifo.v | 17 +++++++++++++++++ usrp2/fifo/ll8_to_fifo19.v | 17 +++++++++++++++++ usrp2/fifo/ll8_to_fifo36.v | 17 +++++++++++++++++ usrp2/fifo/packet32_tb.v | 17 +++++++++++++++++ usrp2/fifo/packet_generator.v | 17 +++++++++++++++++ usrp2/fifo/packet_generator32.v | 17 +++++++++++++++++ usrp2/fifo/packet_router.v | 17 +++++++++++++++++ usrp2/fifo/packet_tb.v | 17 +++++++++++++++++ usrp2/fifo/packet_verifier.v | 17 +++++++++++++++++ usrp2/fifo/packet_verifier32.v | 17 +++++++++++++++++ usrp2/fifo/splitter36.v | 17 +++++++++++++++++ usrp2/fifo/valve36.v | 17 +++++++++++++++++ usrp2/gpif/gpif.v | 17 +++++++++++++++++ usrp2/gpif/gpif_rd.v | 17 +++++++++++++++++ usrp2/gpif/gpif_tb.v | 17 +++++++++++++++++ usrp2/gpif/gpif_wr.v | 17 +++++++++++++++++ usrp2/gpif/gpif_wr_tb.v | 17 +++++++++++++++++ usrp2/gpif/packet_reframer.v | 17 +++++++++++++++++ usrp2/gpif/packet_splitter.v | 17 +++++++++++++++++ usrp2/gpif/packet_splitter_tb.v | 17 +++++++++++++++++ usrp2/gpmc/dbsm.v | 17 +++++++++++++++++ usrp2/gpmc/edge_sync.v | 17 +++++++++++++++++ usrp2/gpmc/fifo_to_gpmc_async.v | 17 +++++++++++++++++ usrp2/gpmc/fifo_to_gpmc_sync.v | 17 +++++++++++++++++ usrp2/gpmc/fifo_watcher.v | 17 +++++++++++++++++ usrp2/gpmc/gpmc_async.v | 17 +++++++++++++++++ usrp2/gpmc/gpmc_sync.v | 17 +++++++++++++++++ usrp2/gpmc/gpmc_to_fifo_async.v | 17 +++++++++++++++++ usrp2/gpmc/gpmc_to_fifo_sync.v | 17 +++++++++++++++++ usrp2/gpmc/gpmc_wb.v | 17 +++++++++++++++++ usrp2/gpmc/ram_to_fifo.v | 17 +++++++++++++++++ usrp2/models/CY7C1356C/cy1356.v | 17 +++++++++++++++++ usrp2/models/CY7C1356C/testbench.v | 17 +++++++++++++++++ usrp2/models/M24LC024B.v | 17 +++++++++++++++++ usrp2/models/M24LC02B.v | 17 +++++++++++++++++ usrp2/models/MULT18X18S.v | 17 +++++++++++++++++ usrp2/models/adc_model.v | 17 +++++++++++++++++ usrp2/models/cpld_model.v | 17 +++++++++++++++++ usrp2/models/gpmc_model_async.v | 17 +++++++++++++++++ usrp2/models/gpmc_model_sync.v | 17 +++++++++++++++++ usrp2/models/math_real.v | 17 +++++++++++++++++ usrp2/models/miim_model.v | 17 +++++++++++++++++ usrp2/models/serdes_model.v | 17 +++++++++++++++++ usrp2/models/uart_rx.v | 17 +++++++++++++++++ usrp2/models/xlnx_glbl.v | 17 +++++++++++++++++ usrp2/sdr_lib/acc.v | 17 +++++++++++++++++ usrp2/sdr_lib/add2.v | 17 +++++++++++++++++ usrp2/sdr_lib/add2_and_round.v | 17 +++++++++++++++++ usrp2/sdr_lib/add2_and_round_reg.v | 17 +++++++++++++++++ usrp2/sdr_lib/add2_reg.v | 17 +++++++++++++++++ usrp2/sdr_lib/dsp_core_rx.v | 17 +++++++++++++++++ usrp2/sdr_lib/dsp_core_rx_old.v | 17 +++++++++++++++++ usrp2/sdr_lib/dsp_core_rx_udp.v | 17 +++++++++++++++++ usrp2/sdr_lib/dsp_core_tx.v | 17 +++++++++++++++++ usrp2/sdr_lib/dummy_rx.v | 17 +++++++++++++++++ usrp2/sdr_lib/halfband_ideal.v | 17 +++++++++++++++++ usrp2/sdr_lib/halfband_tb.v | 17 +++++++++++++++++ usrp2/sdr_lib/hb/acc.v | 17 +++++++++++++++++ usrp2/sdr_lib/hb/coeff_ram.v | 17 +++++++++++++++++ usrp2/sdr_lib/hb/coeff_rom.v | 17 +++++++++++++++++ usrp2/sdr_lib/hb/halfband_interp.v | 17 +++++++++++++++++ usrp2/sdr_lib/hb/hbd_tb/test_hbd.v | 17 +++++++++++++++++ usrp2/sdr_lib/hb/mac.v | 17 +++++++++++++++++ usrp2/sdr_lib/hb/mult.v | 17 +++++++++++++++++ usrp2/sdr_lib/hb/ram16_2port.v | 17 +++++++++++++++++ usrp2/sdr_lib/hb/ram16_2sum.v | 17 +++++++++++++++++ usrp2/sdr_lib/hb/ram32_2sum.v | 17 +++++++++++++++++ usrp2/sdr_lib/hb_dec.v | 17 +++++++++++++++++ usrp2/sdr_lib/hb_dec_tb.v | 17 +++++++++++++++++ usrp2/sdr_lib/hb_interp.v | 17 +++++++++++++++++ usrp2/sdr_lib/hb_interp_tb.v | 17 +++++++++++++++++ usrp2/sdr_lib/hb_tb.v | 17 +++++++++++++++++ usrp2/sdr_lib/integrate.v | 17 +++++++++++++++++ usrp2/sdr_lib/med_hb_int.v | 17 +++++++++++++++++ usrp2/sdr_lib/rssi.v | 17 +++++++++++++++++ usrp2/sdr_lib/rx_control.v | 17 +++++++++++++++++ usrp2/sdr_lib/rx_dcoffset.v | 17 +++++++++++++++++ usrp2/sdr_lib/rx_dcoffset_tb.v | 17 +++++++++++++++++ usrp2/sdr_lib/small_hb_dec.v | 17 +++++++++++++++++ usrp2/sdr_lib/small_hb_dec_tb.v | 17 +++++++++++++++++ usrp2/sdr_lib/small_hb_int.v | 17 +++++++++++++++++ usrp2/sdr_lib/small_hb_int_tb.v | 17 +++++++++++++++++ usrp2/sdr_lib/tx_control.v | 17 +++++++++++++++++ usrp2/serdes/serdes.v | 17 +++++++++++++++++ usrp2/serdes/serdes_fc_rx.v | 17 +++++++++++++++++ usrp2/serdes/serdes_fc_tx.v | 17 +++++++++++++++++ usrp2/serdes/serdes_rx.v | 17 +++++++++++++++++ usrp2/serdes/serdes_tb.v | 17 +++++++++++++++++ usrp2/serdes/serdes_tx.v | 17 +++++++++++++++++ usrp2/simple_gemac/address_filter.v | 17 +++++++++++++++++ usrp2/simple_gemac/address_filter_promisc.v | 17 +++++++++++++++++ usrp2/simple_gemac/crc.v | 17 +++++++++++++++++ usrp2/simple_gemac/delay_line.v | 17 +++++++++++++++++ usrp2/simple_gemac/eth_tasks.v | 17 +++++++++++++++++ usrp2/simple_gemac/eth_tasks_f19.v | 17 +++++++++++++++++ usrp2/simple_gemac/eth_tasks_f36.v | 17 +++++++++++++++++ usrp2/simple_gemac/ethrx_realign.v | 17 +++++++++++++++++ usrp2/simple_gemac/ethtx_realign.v | 17 +++++++++++++++++ usrp2/simple_gemac/flow_ctrl_rx.v | 17 +++++++++++++++++ usrp2/simple_gemac/flow_ctrl_tx.v | 17 +++++++++++++++++ usrp2/simple_gemac/ll8_to_txmac.v | 17 +++++++++++++++++ usrp2/simple_gemac/rxmac_to_ll8.v | 17 +++++++++++++++++ usrp2/simple_gemac/simple_gemac.v | 17 +++++++++++++++++ usrp2/simple_gemac/simple_gemac_rx.v | 17 +++++++++++++++++ usrp2/simple_gemac/simple_gemac_tb.v | 17 +++++++++++++++++ usrp2/simple_gemac/simple_gemac_tx.v | 17 +++++++++++++++++ usrp2/simple_gemac/simple_gemac_wb.v | 17 +++++++++++++++++ usrp2/simple_gemac/simple_gemac_wrapper.v | 17 +++++++++++++++++ usrp2/simple_gemac/simple_gemac_wrapper19.v | 17 +++++++++++++++++ usrp2/simple_gemac/simple_gemac_wrapper19_tb.v | 17 +++++++++++++++++ usrp2/simple_gemac/simple_gemac_wrapper_f36_tb.v | 17 +++++++++++++++++ usrp2/simple_gemac/simple_gemac_wrapper_tb.v | 17 +++++++++++++++++ usrp2/testbench/single_u2_sim.v | 17 +++++++++++++++++ usrp2/timing/simple_timer.v | 17 +++++++++++++++++ usrp2/timing/time_64bit.v | 17 +++++++++++++++++ usrp2/timing/time_compare.v | 17 +++++++++++++++++ usrp2/timing/time_receiver.v | 17 +++++++++++++++++ usrp2/timing/time_sender.v | 17 +++++++++++++++++ usrp2/timing/time_sync.v | 17 +++++++++++++++++ usrp2/timing/time_transfer_tb.v | 17 +++++++++++++++++ usrp2/timing/timer.v | 17 +++++++++++++++++ usrp2/top/B100/u1plus.v | 17 +++++++++++++++++ usrp2/top/B100/u1plus_core.v | 17 +++++++++++++++++ usrp2/top/E1x0/passthru.v | 17 +++++++++++++++++ usrp2/top/E1x0/tb_u1e.v | 17 +++++++++++++++++ usrp2/top/E1x0/u1e.v | 17 +++++++++++++++++ usrp2/top/E1x0/u1e_core.v | 17 +++++++++++++++++ usrp2/top/N2x0/capture_ddrlvds.v | 17 +++++++++++++++++ usrp2/top/N2x0/rev4_defs.v | 17 +++++++++++++++++ usrp2/top/N2x0/u2plus.v | 17 +++++++++++++++++ usrp2/top/N2x0/u2plus_core.v | 17 +++++++++++++++++ usrp2/top/USRP2/u2_core.v | 17 +++++++++++++++++ usrp2/top/USRP2/u2_rev3.v | 17 +++++++++++++++++ usrp2/udp/add_onescomp.v | 17 +++++++++++++++++ usrp2/udp/fifo19_rxrealign.v | 17 +++++++++++++++++ usrp2/udp/prot_eng_rx.v | 17 +++++++++++++++++ usrp2/udp/prot_eng_tx.v | 17 +++++++++++++++++ usrp2/udp/prot_eng_tx_tb.v | 17 +++++++++++++++++ usrp2/udp/udp_wrapper.v | 17 +++++++++++++++++ usrp2/vrt/gen_context_pkt.v | 17 +++++++++++++++++ usrp2/vrt/trigger_context_pkt.v | 17 +++++++++++++++++ usrp2/vrt/vita_pkt_gen.v | 17 +++++++++++++++++ usrp2/vrt/vita_rx_chain.v | 17 +++++++++++++++++ usrp2/vrt/vita_rx_control.v | 17 +++++++++++++++++ usrp2/vrt/vita_rx_framer.v | 17 +++++++++++++++++ usrp2/vrt/vita_rx_tb.v | 17 +++++++++++++++++ usrp2/vrt/vita_tx_chain.v | 17 +++++++++++++++++ usrp2/vrt/vita_tx_control.v | 17 +++++++++++++++++ usrp2/vrt/vita_tx_deframer.v | 17 +++++++++++++++++ usrp2/vrt/vita_tx_tb.v | 17 +++++++++++++++++ 241 files changed, 4097 insertions(+) diff --git a/usrp2/control_lib/atr_controller.v b/usrp2/control_lib/atr_controller.v index a161b5e00..2cef8ba2b 100644 --- a/usrp2/control_lib/atr_controller.v +++ b/usrp2/control_lib/atr_controller.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Automatic transmit/receive switching of control pins to daughterboards // Store everything in registers for now, but could use a RAM for more diff --git a/usrp2/control_lib/atr_controller16.v b/usrp2/control_lib/atr_controller16.v index 74ce30a54..ff4f634c7 100644 --- a/usrp2/control_lib/atr_controller16.v +++ b/usrp2/control_lib/atr_controller16.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Automatic transmit/receive switching of control pins to daughterboards // Store everything in registers for now, but could use a RAM for more diff --git a/usrp2/control_lib/bin2gray.v b/usrp2/control_lib/bin2gray.v index 513402163..8336a5afc 100644 --- a/usrp2/control_lib/bin2gray.v +++ b/usrp2/control_lib/bin2gray.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module bin2gray diff --git a/usrp2/control_lib/bootram.v b/usrp2/control_lib/bootram.v index 29d21ab5a..249a09814 100644 --- a/usrp2/control_lib/bootram.v +++ b/usrp2/control_lib/bootram.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Boot RAM for S3A, 8KB, dual port diff --git a/usrp2/control_lib/clock_bootstrap_rom.v b/usrp2/control_lib/clock_bootstrap_rom.v index 46563db65..542f49380 100644 --- a/usrp2/control_lib/clock_bootstrap_rom.v +++ b/usrp2/control_lib/clock_bootstrap_rom.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module clock_bootstrap_rom(input [15:0] addr, output [47:0] data); diff --git a/usrp2/control_lib/clock_control.v b/usrp2/control_lib/clock_control.v index 1bbe6bd75..000eaf1fb 100644 --- a/usrp2/control_lib/clock_control.v +++ b/usrp2/control_lib/clock_control.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // AD9510 Register Map (from datasheet Rev. A) diff --git a/usrp2/control_lib/clock_control_tb.v b/usrp2/control_lib/clock_control_tb.v index 4e705cf23..9760efbe3 100644 --- a/usrp2/control_lib/clock_control_tb.v +++ b/usrp2/control_lib/clock_control_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module clock_control_tb(); diff --git a/usrp2/control_lib/dcache.v b/usrp2/control_lib/dcache.v index 9063bf02a..384c5a149 100644 --- a/usrp2/control_lib/dcache.v +++ b/usrp2/control_lib/dcache.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module dcache #(parameter AWIDTH=14, diff --git a/usrp2/control_lib/decoder_3_8.v b/usrp2/control_lib/decoder_3_8.v index 729b45d18..8f91d8263 100644 --- a/usrp2/control_lib/decoder_3_8.v +++ b/usrp2/control_lib/decoder_3_8.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module decoder_3_8 (input [2:0] sel, diff --git a/usrp2/control_lib/dpram32.v b/usrp2/control_lib/dpram32.v index 4da621823..386435e70 100644 --- a/usrp2/control_lib/dpram32.v +++ b/usrp2/control_lib/dpram32.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Dual ported RAM // Addresses are byte-oriented, so botton 2 address bits are ignored. diff --git a/usrp2/control_lib/fifo_to_wb.v b/usrp2/control_lib/fifo_to_wb.v index b2a2fd18b..9b6b5e804 100644 --- a/usrp2/control_lib/fifo_to_wb.v +++ b/usrp2/control_lib/fifo_to_wb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module fifo_to_wb #(parameter PKT_LEN = 16) diff --git a/usrp2/control_lib/fifo_to_wb_tb.v b/usrp2/control_lib/fifo_to_wb_tb.v index 96ef4647c..37459e2c2 100644 --- a/usrp2/control_lib/fifo_to_wb_tb.v +++ b/usrp2/control_lib/fifo_to_wb_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module fifo_to_wb_tb(); reg clk = 0; diff --git a/usrp2/control_lib/gray2bin.v b/usrp2/control_lib/gray2bin.v index 5df40bd52..399d5bba0 100644 --- a/usrp2/control_lib/gray2bin.v +++ b/usrp2/control_lib/gray2bin.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module gray2bin diff --git a/usrp2/control_lib/gray_send.v b/usrp2/control_lib/gray_send.v index 7fc07d40c..62402f8d3 100644 --- a/usrp2/control_lib/gray_send.v +++ b/usrp2/control_lib/gray_send.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + diff --git a/usrp2/control_lib/icache.v b/usrp2/control_lib/icache.v index bd21f47cc..810b5fa64 100644 --- a/usrp2/control_lib/icache.v +++ b/usrp2/control_lib/icache.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module icache #(parameter AWIDTH=14, diff --git a/usrp2/control_lib/longfifo.v b/usrp2/control_lib/longfifo.v index bf3338e0b..c77f2dcb1 100644 --- a/usrp2/control_lib/longfifo.v +++ b/usrp2/control_lib/longfifo.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // FIFO intended to be interchangeable with shortfifo, but // based on block ram instead of SRL16's diff --git a/usrp2/control_lib/medfifo.v b/usrp2/control_lib/medfifo.v index 5a77e8c16..0f66f6597 100644 --- a/usrp2/control_lib/medfifo.v +++ b/usrp2/control_lib/medfifo.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module medfifo #(parameter WIDTH=32, diff --git a/usrp2/control_lib/mux4.v b/usrp2/control_lib/mux4.v index 31c85c832..b1878f011 100644 --- a/usrp2/control_lib/mux4.v +++ b/usrp2/control_lib/mux4.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module mux4 diff --git a/usrp2/control_lib/mux8.v b/usrp2/control_lib/mux8.v index 9db96a60f..bdb015dc3 100644 --- a/usrp2/control_lib/mux8.v +++ b/usrp2/control_lib/mux8.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module mux8 diff --git a/usrp2/control_lib/mux_32_4.v b/usrp2/control_lib/mux_32_4.v index fef5812e9..4a1244933 100644 --- a/usrp2/control_lib/mux_32_4.v +++ b/usrp2/control_lib/mux_32_4.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module mux_32_4 diff --git a/usrp2/control_lib/oneshot_2clk.v b/usrp2/control_lib/oneshot_2clk.v index 72f16a4b3..7ed5bc8f6 100644 --- a/usrp2/control_lib/oneshot_2clk.v +++ b/usrp2/control_lib/oneshot_2clk.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Retime a single bit from one clock domain to another // Guarantees that no matter what the relative clock rates, if the in signal is high for at least diff --git a/usrp2/control_lib/priority_enc.v b/usrp2/control_lib/priority_enc.v index 916192445..d30870be9 100644 --- a/usrp2/control_lib/priority_enc.v +++ b/usrp2/control_lib/priority_enc.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module priority_enc (input [31:0] in, diff --git a/usrp2/control_lib/quad_uart.v b/usrp2/control_lib/quad_uart.v index afa6fae1d..39998150d 100644 --- a/usrp2/control_lib/quad_uart.v +++ b/usrp2/control_lib/quad_uart.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module quad_uart #(parameter TXDEPTH = 1, diff --git a/usrp2/control_lib/ram_2port.v b/usrp2/control_lib/ram_2port.v index 3716a7c8a..86d7e4703 100644 --- a/usrp2/control_lib/ram_2port.v +++ b/usrp2/control_lib/ram_2port.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module ram_2port diff --git a/usrp2/control_lib/ram_2port_mixed_width.v b/usrp2/control_lib/ram_2port_mixed_width.v index fae7d8de3..2910d4041 100644 --- a/usrp2/control_lib/ram_2port_mixed_width.v +++ b/usrp2/control_lib/ram_2port_mixed_width.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module ram_2port_mixed_width (input clk16, diff --git a/usrp2/control_lib/ram_harv_cache.v b/usrp2/control_lib/ram_harv_cache.v index 29fdebf7a..e68ed7f68 100644 --- a/usrp2/control_lib/ram_harv_cache.v +++ b/usrp2/control_lib/ram_harv_cache.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Dual ported, Harvard architecture, cached ram diff --git a/usrp2/control_lib/ram_harvard.v b/usrp2/control_lib/ram_harvard.v index a190e20fd..00ffb1984 100644 --- a/usrp2/control_lib/ram_harvard.v +++ b/usrp2/control_lib/ram_harvard.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Dual ported, Harvard architecture, cached ram diff --git a/usrp2/control_lib/ram_harvard2.v b/usrp2/control_lib/ram_harvard2.v index 67777af2a..d8fe472f5 100644 --- a/usrp2/control_lib/ram_harvard2.v +++ b/usrp2/control_lib/ram_harvard2.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Dual ported, Harvard architecture diff --git a/usrp2/control_lib/ram_loader.v b/usrp2/control_lib/ram_loader.v index c53ea7aa7..85ccf91b4 100644 --- a/usrp2/control_lib/ram_loader.v +++ b/usrp2/control_lib/ram_loader.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module ram_loader #(parameter AWIDTH=16, RAM_SIZE=16384) ( diff --git a/usrp2/control_lib/ram_wb_harvard.v b/usrp2/control_lib/ram_wb_harvard.v index c3efc12e0..8d5a45247 100644 --- a/usrp2/control_lib/ram_wb_harvard.v +++ b/usrp2/control_lib/ram_wb_harvard.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Dual ported RAM for Harvard architecture processors // Does no forwarding diff --git a/usrp2/control_lib/reset_sync.v b/usrp2/control_lib/reset_sync.v index 94d966840..304aba106 100644 --- a/usrp2/control_lib/reset_sync.v +++ b/usrp2/control_lib/reset_sync.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module reset_sync diff --git a/usrp2/control_lib/s3a_icap_wb.v b/usrp2/control_lib/s3a_icap_wb.v index 83d9f775e..e49b56cff 100644 --- a/usrp2/control_lib/s3a_icap_wb.v +++ b/usrp2/control_lib/s3a_icap_wb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module s3a_icap_wb diff --git a/usrp2/control_lib/sd_spi.v b/usrp2/control_lib/sd_spi.v index 3f4d7f46a..fa998d19a 100644 --- a/usrp2/control_lib/sd_spi.v +++ b/usrp2/control_lib/sd_spi.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module sd_spi (input clk, input rst, diff --git a/usrp2/control_lib/sd_spi_tb.v b/usrp2/control_lib/sd_spi_tb.v index e30a5bdf6..2b5ae083f 100644 --- a/usrp2/control_lib/sd_spi_tb.v +++ b/usrp2/control_lib/sd_spi_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module sd_spi_tb; diff --git a/usrp2/control_lib/sd_spi_wb.v b/usrp2/control_lib/sd_spi_wb.v index 7a6258b56..b09debd70 100644 --- a/usrp2/control_lib/sd_spi_wb.v +++ b/usrp2/control_lib/sd_spi_wb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Wishbone module for spi communications with an SD Card // The programming interface is simple -- diff --git a/usrp2/control_lib/setting_reg.v b/usrp2/control_lib/setting_reg.v index 3d3bb65e5..e4c84d910 100644 --- a/usrp2/control_lib/setting_reg.v +++ b/usrp2/control_lib/setting_reg.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module setting_reg diff --git a/usrp2/control_lib/settings_bus.v b/usrp2/control_lib/settings_bus.v index aec179516..e2ea7e44b 100644 --- a/usrp2/control_lib/settings_bus.v +++ b/usrp2/control_lib/settings_bus.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Grab settings off the wishbone bus, send them out to our simpler bus on the fast clock diff --git a/usrp2/control_lib/settings_bus_16LE.v b/usrp2/control_lib/settings_bus_16LE.v index 76061e9e0..7c42a0870 100644 --- a/usrp2/control_lib/settings_bus_16LE.v +++ b/usrp2/control_lib/settings_bus_16LE.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Grab settings off the wishbone bus, send them out to settings bus // 16 bits little endian, but all registers need to be written 32 bits at a time. diff --git a/usrp2/control_lib/settings_bus_crossclock.v b/usrp2/control_lib/settings_bus_crossclock.v index b043aa0ad..9c5912042 100644 --- a/usrp2/control_lib/settings_bus_crossclock.v +++ b/usrp2/control_lib/settings_bus_crossclock.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // This module takes the settings bus on one clock domain and crosses it over to another domain diff --git a/usrp2/control_lib/shortfifo.v b/usrp2/control_lib/shortfifo.v index d8ce1428e..c7c916375 100644 --- a/usrp2/control_lib/shortfifo.v +++ b/usrp2/control_lib/shortfifo.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module shortfifo #(parameter WIDTH=32) diff --git a/usrp2/control_lib/simple_uart.v b/usrp2/control_lib/simple_uart.v index 0dd58b5f5..f44a719f4 100644 --- a/usrp2/control_lib/simple_uart.v +++ b/usrp2/control_lib/simple_uart.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module simple_uart #(parameter TXDEPTH = 1, diff --git a/usrp2/control_lib/simple_uart_rx.v b/usrp2/control_lib/simple_uart_rx.v index debdd618b..5f7646e03 100644 --- a/usrp2/control_lib/simple_uart_rx.v +++ b/usrp2/control_lib/simple_uart_rx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module simple_uart_rx diff --git a/usrp2/control_lib/simple_uart_tx.v b/usrp2/control_lib/simple_uart_tx.v index e11a347ed..f38460bd4 100644 --- a/usrp2/control_lib/simple_uart_tx.v +++ b/usrp2/control_lib/simple_uart_tx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module simple_uart_tx #(parameter DEPTH=0) diff --git a/usrp2/control_lib/spi.v b/usrp2/control_lib/spi.v index a80c488e9..1abebee1c 100644 --- a/usrp2/control_lib/spi.v +++ b/usrp2/control_lib/spi.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // AD9510 Register Map (from datasheet Rev. A) diff --git a/usrp2/control_lib/srl.v b/usrp2/control_lib/srl.v index fa28c7669..bdef30058 100644 --- a/usrp2/control_lib/srl.v +++ b/usrp2/control_lib/srl.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module srl #(parameter WIDTH=18) diff --git a/usrp2/control_lib/ss_rcvr.v b/usrp2/control_lib/ss_rcvr.v index 8e650d21b..4fb732c23 100644 --- a/usrp2/control_lib/ss_rcvr.v +++ b/usrp2/control_lib/ss_rcvr.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Source-synchronous receiver diff --git a/usrp2/control_lib/system_control.v b/usrp2/control_lib/system_control.v index 5d89f13db..7e7b71f3c 100644 --- a/usrp2/control_lib/system_control.v +++ b/usrp2/control_lib/system_control.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // System bootup order: // 0 - Internal POR to reset this block. Maybe control it from CPLD in the future? // 1 - Everything in reset diff --git a/usrp2/control_lib/system_control_tb.v b/usrp2/control_lib/system_control_tb.v index a8eff4811..8fecfd1f0 100644 --- a/usrp2/control_lib/system_control_tb.v +++ b/usrp2/control_lib/system_control_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module system_control_tb(); diff --git a/usrp2/control_lib/traffic_cop.v b/usrp2/control_lib/traffic_cop.v index e7579656a..874e4c2d9 100644 --- a/usrp2/control_lib/traffic_cop.v +++ b/usrp2/control_lib/traffic_cop.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module traffic_cop(); diff --git a/usrp2/control_lib/v5icap_wb.v b/usrp2/control_lib/v5icap_wb.v index c8800285a..92a6769e5 100644 --- a/usrp2/control_lib/v5icap_wb.v +++ b/usrp2/control_lib/v5icap_wb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module v5icap_wb diff --git a/usrp2/control_lib/wb_bridge_16_32.v b/usrp2/control_lib/wb_bridge_16_32.v index 405e25c3c..7c62c9cbd 100644 --- a/usrp2/control_lib/wb_bridge_16_32.v +++ b/usrp2/control_lib/wb_bridge_16_32.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module wb_bridge_16_32 diff --git a/usrp2/control_lib/wb_bus_writer.v b/usrp2/control_lib/wb_bus_writer.v index fc148a0ff..08e641d37 100644 --- a/usrp2/control_lib/wb_bus_writer.v +++ b/usrp2/control_lib/wb_bus_writer.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // wb_bus_writer // diff --git a/usrp2/control_lib/wb_output_pins32.v b/usrp2/control_lib/wb_output_pins32.v index 1517f2066..43e239797 100644 --- a/usrp2/control_lib/wb_output_pins32.v +++ b/usrp2/control_lib/wb_output_pins32.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Simple 32-bit Wishbone compatible slave output port diff --git a/usrp2/control_lib/wb_ram_block.v b/usrp2/control_lib/wb_ram_block.v index 044d34ca4..da6c610d3 100644 --- a/usrp2/control_lib/wb_ram_block.v +++ b/usrp2/control_lib/wb_ram_block.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Since this is a block ram, there are no byte-selects and there is a 1-cycle read latency diff --git a/usrp2/control_lib/wb_ram_dist.v b/usrp2/control_lib/wb_ram_dist.v index cffc2f423..491a6ae11 100644 --- a/usrp2/control_lib/wb_ram_dist.v +++ b/usrp2/control_lib/wb_ram_dist.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module wb_ram_dist diff --git a/usrp2/control_lib/wb_readback_mux.v b/usrp2/control_lib/wb_readback_mux.v index 3922b03e3..a5bf224b8 100644 --- a/usrp2/control_lib/wb_readback_mux.v +++ b/usrp2/control_lib/wb_readback_mux.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Note -- clocks must be synchronous (derived from the same source) diff --git a/usrp2/control_lib/wb_readback_mux_16LE.v b/usrp2/control_lib/wb_readback_mux_16LE.v index 2b01898c1..aceec601b 100644 --- a/usrp2/control_lib/wb_readback_mux_16LE.v +++ b/usrp2/control_lib/wb_readback_mux_16LE.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Note -- clocks must be synchronous (derived from the same source) diff --git a/usrp2/control_lib/wb_regfile_2clock.v b/usrp2/control_lib/wb_regfile_2clock.v index e248e5161..ce93ab3f4 100644 --- a/usrp2/control_lib/wb_regfile_2clock.v +++ b/usrp2/control_lib/wb_regfile_2clock.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module wb_regfile_2clock (input wb_clk_i, diff --git a/usrp2/control_lib/wb_semaphore.v b/usrp2/control_lib/wb_semaphore.v index a9208e6a1..e90950509 100644 --- a/usrp2/control_lib/wb_semaphore.v +++ b/usrp2/control_lib/wb_semaphore.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // up to 8 semaphores diff --git a/usrp2/control_lib/wb_sim.v b/usrp2/control_lib/wb_sim.v index b324e1457..9f2fbea54 100644 --- a/usrp2/control_lib/wb_sim.v +++ b/usrp2/control_lib/wb_sim.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module wb_sim(); diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v index 80f82fc63..620f4dddd 100644 --- a/usrp2/extramfifo/ext_fifo.v +++ b/usrp2/extramfifo/ext_fifo.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // // FIFO backed by an off chip ZBT/NoBL SRAM. // diff --git a/usrp2/extramfifo/ext_fifo_tb.v b/usrp2/extramfifo/ext_fifo_tb.v index 395ad2884..f6fe47297 100644 --- a/usrp2/extramfifo/ext_fifo_tb.v +++ b/usrp2/extramfifo/ext_fifo_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + `timescale 1ns / 1ps `define USRP2 //`define USRP2PLUS diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v index 0b63768fc..469e3eab5 100644 --- a/usrp2/extramfifo/nobl_fifo.v +++ b/usrp2/extramfifo/nobl_fifo.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Since this FIFO uses a ZBT/NoBL SRAM for its storage which is a since port // device it can only sustain data throughput at half the RAM clock rate. // Fair arbitration to ensure this occurs is included in this logic and diff --git a/usrp2/extramfifo/nobl_if.v b/usrp2/extramfifo/nobl_if.v index b5ebe9c6b..0a64d3857 100644 --- a/usrp2/extramfifo/nobl_if.v +++ b/usrp2/extramfifo/nobl_if.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Tested against an IDT 71v65603s150 in simulation and a Cypress 7C1356C in the real world. module nobl_if diff --git a/usrp2/extramfifo/refill_randomizer.v b/usrp2/extramfifo/refill_randomizer.v index 0b30f4049..09728b8c0 100644 --- a/usrp2/extramfifo/refill_randomizer.v +++ b/usrp2/extramfifo/refill_randomizer.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // // EMI mitigation. // Process FULL flag from FIFO so that de-assertion diff --git a/usrp2/extramfifo/test_sram_if.v b/usrp2/extramfifo/test_sram_if.v index 0e74b49eb..dcb881a92 100644 --- a/usrp2/extramfifo/test_sram_if.v +++ b/usrp2/extramfifo/test_sram_if.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Instantiate this block at the core level to conduct closed // loop testing of the AC performance of the USRP2 SRAM interface diff --git a/usrp2/fifo/buffer_int.v b/usrp2/fifo/buffer_int.v index 49ded8c8d..c068226ec 100644 --- a/usrp2/fifo/buffer_int.v +++ b/usrp2/fifo/buffer_int.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // FIFO Interface to the 2K buffer RAMs // Read port is read-acknowledge diff --git a/usrp2/fifo/buffer_int2.v b/usrp2/fifo/buffer_int2.v index 532980aa2..7dd528dd5 100644 --- a/usrp2/fifo/buffer_int2.v +++ b/usrp2/fifo/buffer_int2.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // FIFO Interface to the 2K buffer RAMs // Read port is read-acknowledge diff --git a/usrp2/fifo/buffer_int_tb.v b/usrp2/fifo/buffer_int_tb.v index df54dcc0b..44f8be0a0 100644 --- a/usrp2/fifo/buffer_int_tb.v +++ b/usrp2/fifo/buffer_int_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module buffer_int_tb (); diff --git a/usrp2/fifo/buffer_pool.v b/usrp2/fifo/buffer_pool.v index 41ac1deb3..48f5bd69c 100644 --- a/usrp2/fifo/buffer_pool.v +++ b/usrp2/fifo/buffer_pool.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Buffer pool. Contains 8 buffers, each 2K (512 by 32). Each buffer // is a dual-ported RAM. Port A on each of them is indirectly connected diff --git a/usrp2/fifo/buffer_pool_tb.v b/usrp2/fifo/buffer_pool_tb.v index 91a01d268..0ee76689e 100644 --- a/usrp2/fifo/buffer_pool_tb.v +++ b/usrp2/fifo/buffer_pool_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module buffer_pool_tb(); diff --git a/usrp2/fifo/crossbar36.v b/usrp2/fifo/crossbar36.v index 2a046d8bf..4e2aed7ce 100644 --- a/usrp2/fifo/crossbar36.v +++ b/usrp2/fifo/crossbar36.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module crossbar36 diff --git a/usrp2/fifo/dsp_framer36.v b/usrp2/fifo/dsp_framer36.v index 58455cee1..ef7395551 100644 --- a/usrp2/fifo/dsp_framer36.v +++ b/usrp2/fifo/dsp_framer36.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // This has 3 functions: // Correct the VITA packet length diff --git a/usrp2/fifo/fifo19_mux.v b/usrp2/fifo/fifo19_mux.v index ebf961678..a23ac2bb4 100644 --- a/usrp2/fifo/fifo19_mux.v +++ b/usrp2/fifo/fifo19_mux.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Mux packets from multiple FIFO interfaces onto a single one. // Can alternate or give priority to one port (port 0) diff --git a/usrp2/fifo/fifo19_pad.v b/usrp2/fifo/fifo19_pad.v index 1a40c1631..bb6e1fa92 100644 --- a/usrp2/fifo/fifo19_pad.v +++ b/usrp2/fifo/fifo19_pad.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Pads a packet out to the minimum length // Packets already longer than min length are unchanged diff --git a/usrp2/fifo/fifo19_to_fifo36.v b/usrp2/fifo/fifo19_to_fifo36.v index 502821435..32734405a 100644 --- a/usrp2/fifo/fifo19_to_fifo36.v +++ b/usrp2/fifo/fifo19_to_fifo36.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Parameter LE tells us if we are little-endian. // Little-endian means send lower 16 bits first. diff --git a/usrp2/fifo/fifo19_to_ll8.v b/usrp2/fifo/fifo19_to_ll8.v index 4707f7523..1ebb140c2 100644 --- a/usrp2/fifo/fifo19_to_ll8.v +++ b/usrp2/fifo/fifo19_to_ll8.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module fifo19_to_ll8 (input clk, input reset, input clear, diff --git a/usrp2/fifo/fifo36_demux.v b/usrp2/fifo/fifo36_demux.v index a54759d4d..6f516691a 100644 --- a/usrp2/fifo/fifo36_demux.v +++ b/usrp2/fifo/fifo36_demux.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Demux packets from a fifo based on the contents of the first line // If first line matches the parameter and mask, send to data1, otherwise send to data0 diff --git a/usrp2/fifo/fifo36_mux.v b/usrp2/fifo/fifo36_mux.v index 7f0f803ff..cf7b2b4d1 100644 --- a/usrp2/fifo/fifo36_mux.v +++ b/usrp2/fifo/fifo36_mux.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Mux packets from multiple FIFO interfaces onto a single one. // Can alternate or give priority to one port (port 0) diff --git a/usrp2/fifo/fifo36_to_fifo19.v b/usrp2/fifo/fifo36_to_fifo19.v index 0e9b2d442..cb93e10ad 100644 --- a/usrp2/fifo/fifo36_to_fifo19.v +++ b/usrp2/fifo/fifo36_to_fifo19.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Parameter LE tells us if we are little-endian. // Little-endian means send lower 16 bits first. diff --git a/usrp2/fifo/fifo36_to_fifo72.v b/usrp2/fifo/fifo36_to_fifo72.v index 038eda9e9..237149cc2 100644 --- a/usrp2/fifo/fifo36_to_fifo72.v +++ b/usrp2/fifo/fifo36_to_fifo72.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Parameter LE tells us if we are little-endian. // Little-endian means send lower 16 bits first. diff --git a/usrp2/fifo/fifo36_to_ll8.v b/usrp2/fifo/fifo36_to_ll8.v index 390e49962..5c2da812f 100644 --- a/usrp2/fifo/fifo36_to_ll8.v +++ b/usrp2/fifo/fifo36_to_ll8.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module fifo36_to_ll8 (input clk, input reset, input clear, diff --git a/usrp2/fifo/fifo72_to_fifo36.v b/usrp2/fifo/fifo72_to_fifo36.v index 1b3bc3ab7..c365f0196 100644 --- a/usrp2/fifo/fifo72_to_fifo36.v +++ b/usrp2/fifo/fifo72_to_fifo36.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Parameter LE tells us if we are little-endian. // Little-endian means send lower 16 bits first. diff --git a/usrp2/fifo/fifo_19to36_tb.v b/usrp2/fifo/fifo_19to36_tb.v index c585392c3..143b92b1b 100644 --- a/usrp2/fifo/fifo_19to36_tb.v +++ b/usrp2/fifo/fifo_19to36_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module fifo_tb(); reg clk = 0; diff --git a/usrp2/fifo/fifo_2clock.v b/usrp2/fifo/fifo_2clock.v index f3ed5324f..756ad508f 100644 --- a/usrp2/fifo/fifo_2clock.v +++ b/usrp2/fifo/fifo_2clock.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // FIXME ignores the AWIDTH (fifo size) parameter diff --git a/usrp2/fifo/fifo_2clock_cascade.v b/usrp2/fifo/fifo_2clock_cascade.v index 4e8c244c2..49cac7097 100644 --- a/usrp2/fifo/fifo_2clock_cascade.v +++ b/usrp2/fifo/fifo_2clock_cascade.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module fifo_2clock_cascade #(parameter WIDTH=32, SIZE=9) diff --git a/usrp2/fifo/fifo_cascade.v b/usrp2/fifo/fifo_cascade.v index fdd8449bc..5a79c4090 100644 --- a/usrp2/fifo/fifo_cascade.v +++ b/usrp2/fifo/fifo_cascade.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // This FIFO exists to provide an intermediate point for the data on its diff --git a/usrp2/fifo/fifo_long.v b/usrp2/fifo/fifo_long.v index 0426779f6..e9739ad94 100644 --- a/usrp2/fifo/fifo_long.v +++ b/usrp2/fifo/fifo_long.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // FIFO intended to be interchangeable with shortfifo, but // based on block ram instead of SRL16's diff --git a/usrp2/fifo/fifo_pacer.v b/usrp2/fifo/fifo_pacer.v index 1bf03ab6e..3e3fbf8b8 100644 --- a/usrp2/fifo/fifo_pacer.v +++ b/usrp2/fifo/fifo_pacer.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module fifo_pacer diff --git a/usrp2/fifo/fifo_short.v b/usrp2/fifo/fifo_short.v index 53a7603c7..32f26beef 100644 --- a/usrp2/fifo/fifo_short.v +++ b/usrp2/fifo/fifo_short.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module fifo_short #(parameter WIDTH=32) diff --git a/usrp2/fifo/fifo_tb.v b/usrp2/fifo/fifo_tb.v index 3e2862a70..c63c201d0 100644 --- a/usrp2/fifo/fifo_tb.v +++ b/usrp2/fifo/fifo_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module fifo_tb(); reg clk = 0; diff --git a/usrp2/fifo/ll8_shortfifo.v b/usrp2/fifo/ll8_shortfifo.v index 39ada9a4f..49b3a3139 100644 --- a/usrp2/fifo/ll8_shortfifo.v +++ b/usrp2/fifo/ll8_shortfifo.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module ll8_shortfifo diff --git a/usrp2/fifo/ll8_to_fifo19.v b/usrp2/fifo/ll8_to_fifo19.v index ac8ac19a6..4503d0c3d 100644 --- a/usrp2/fifo/ll8_to_fifo19.v +++ b/usrp2/fifo/ll8_to_fifo19.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module ll8_to_fifo19 (input clk, input reset, input clear, diff --git a/usrp2/fifo/ll8_to_fifo36.v b/usrp2/fifo/ll8_to_fifo36.v index 108daa903..b26f745d2 100644 --- a/usrp2/fifo/ll8_to_fifo36.v +++ b/usrp2/fifo/ll8_to_fifo36.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module ll8_to_fifo36 (input clk, input reset, input clear, diff --git a/usrp2/fifo/packet32_tb.v b/usrp2/fifo/packet32_tb.v index 82bb09c29..8a7cfcec5 100644 --- a/usrp2/fifo/packet32_tb.v +++ b/usrp2/fifo/packet32_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module packet32_tb(); diff --git a/usrp2/fifo/packet_generator.v b/usrp2/fifo/packet_generator.v index 2ae911e24..5e9d3c2ab 100644 --- a/usrp2/fifo/packet_generator.v +++ b/usrp2/fifo/packet_generator.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module packet_generator diff --git a/usrp2/fifo/packet_generator32.v b/usrp2/fifo/packet_generator32.v index 1dc57191d..7b4e3bd57 100644 --- a/usrp2/fifo/packet_generator32.v +++ b/usrp2/fifo/packet_generator32.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module packet_generator32 diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 04c17b647..7bfa6893d 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module packet_router #( parameter BUF_SIZE = 9, diff --git a/usrp2/fifo/packet_tb.v b/usrp2/fifo/packet_tb.v index 3c423d2ba..ec0665e0a 100644 --- a/usrp2/fifo/packet_tb.v +++ b/usrp2/fifo/packet_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module packet_tb(); diff --git a/usrp2/fifo/packet_verifier.v b/usrp2/fifo/packet_verifier.v index 21a4c136e..3cc7b0a04 100644 --- a/usrp2/fifo/packet_verifier.v +++ b/usrp2/fifo/packet_verifier.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Packet format -- diff --git a/usrp2/fifo/packet_verifier32.v b/usrp2/fifo/packet_verifier32.v index ec08e657d..3579a9bcf 100644 --- a/usrp2/fifo/packet_verifier32.v +++ b/usrp2/fifo/packet_verifier32.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module packet_verifier32 diff --git a/usrp2/fifo/splitter36.v b/usrp2/fifo/splitter36.v index ed998b4f5..d002d7afd 100644 --- a/usrp2/fifo/splitter36.v +++ b/usrp2/fifo/splitter36.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Split packets from a fifo based interface so it goes out identically on two interfaces diff --git a/usrp2/fifo/valve36.v b/usrp2/fifo/valve36.v index d45eee497..795fe511e 100644 --- a/usrp2/fifo/valve36.v +++ b/usrp2/fifo/valve36.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module valve36 diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index 3649654ed..51d6e8ba9 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + ////////////////////////////////////////////////////////////////////////////////// module gpif diff --git a/usrp2/gpif/gpif_rd.v b/usrp2/gpif/gpif_rd.v index 1639f0132..b05c3cfb6 100644 --- a/usrp2/gpif/gpif_rd.v +++ b/usrp2/gpif/gpif_rd.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module gpif_rd (input gpif_clk, input gpif_rst, diff --git a/usrp2/gpif/gpif_tb.v b/usrp2/gpif/gpif_tb.v index fe12c83b3..686284c2b 100644 --- a/usrp2/gpif/gpif_tb.v +++ b/usrp2/gpif/gpif_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module gpif_tb(); diff --git a/usrp2/gpif/gpif_wr.v b/usrp2/gpif/gpif_wr.v index bf95931dc..89fae282e 100644 --- a/usrp2/gpif/gpif_wr.v +++ b/usrp2/gpif/gpif_wr.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module gpif_wr (input gpif_clk, input gpif_rst, diff --git a/usrp2/gpif/gpif_wr_tb.v b/usrp2/gpif/gpif_wr_tb.v index 134365c87..171bb96a1 100644 --- a/usrp2/gpif/gpif_wr_tb.v +++ b/usrp2/gpif/gpif_wr_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module gpif_wr_tb(); diff --git a/usrp2/gpif/packet_reframer.v b/usrp2/gpif/packet_reframer.v index 336c36369..923d499ae 100644 --- a/usrp2/gpif/packet_reframer.v +++ b/usrp2/gpif/packet_reframer.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Join vita packets longer than one GPIF frame, drop padding on short frames diff --git a/usrp2/gpif/packet_splitter.v b/usrp2/gpif/packet_splitter.v index a55f4cb4f..ba4c8cded 100644 --- a/usrp2/gpif/packet_splitter.v +++ b/usrp2/gpif/packet_splitter.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Split vita packets longer than one GPIF frame, add padding on short frames diff --git a/usrp2/gpif/packet_splitter_tb.v b/usrp2/gpif/packet_splitter_tb.v index 877f6ae1c..329b58e0d 100644 --- a/usrp2/gpif/packet_splitter_tb.v +++ b/usrp2/gpif/packet_splitter_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module packet_splitter_tb(); diff --git a/usrp2/gpmc/dbsm.v b/usrp2/gpmc/dbsm.v index 530af7205..1ee250738 100644 --- a/usrp2/gpmc/dbsm.v +++ b/usrp2/gpmc/dbsm.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module bsm (input clk, input reset, input clear, diff --git a/usrp2/gpmc/edge_sync.v b/usrp2/gpmc/edge_sync.v index 5d9417c08..74f1a2f1c 100644 --- a/usrp2/gpmc/edge_sync.v +++ b/usrp2/gpmc/edge_sync.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module edge_sync diff --git a/usrp2/gpmc/fifo_to_gpmc_async.v b/usrp2/gpmc/fifo_to_gpmc_async.v index 9a8e37ce9..bb4c58ec4 100644 --- a/usrp2/gpmc/fifo_to_gpmc_async.v +++ b/usrp2/gpmc/fifo_to_gpmc_async.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module fifo_to_gpmc_async (input clk, input reset, input clear, diff --git a/usrp2/gpmc/fifo_to_gpmc_sync.v b/usrp2/gpmc/fifo_to_gpmc_sync.v index ef59d7137..9da9caf86 100644 --- a/usrp2/gpmc/fifo_to_gpmc_sync.v +++ b/usrp2/gpmc/fifo_to_gpmc_sync.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Assumes a GPMC cycle with GPMC clock, as in the timing diagrams // If a packet bigger or smaller than we are told is sent, behavior is undefined. diff --git a/usrp2/gpmc/fifo_watcher.v b/usrp2/gpmc/fifo_watcher.v index fe4e35de3..b139f5143 100644 --- a/usrp2/gpmc/fifo_watcher.v +++ b/usrp2/gpmc/fifo_watcher.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module fifo_watcher diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 02bf45b8a..c0bec683a 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + ////////////////////////////////////////////////////////////////////////////////// module gpmc_async diff --git a/usrp2/gpmc/gpmc_sync.v b/usrp2/gpmc/gpmc_sync.v index 61c54a793..ba7251c8d 100644 --- a/usrp2/gpmc/gpmc_sync.v +++ b/usrp2/gpmc/gpmc_sync.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + ////////////////////////////////////////////////////////////////////////////////// module gpmc_sync diff --git a/usrp2/gpmc/gpmc_to_fifo_async.v b/usrp2/gpmc/gpmc_to_fifo_async.v index 55c0cef50..aa93e52af 100644 --- a/usrp2/gpmc/gpmc_to_fifo_async.v +++ b/usrp2/gpmc/gpmc_to_fifo_async.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module gpmc_to_fifo_async (input [15:0] EM_D, input [1:0] EM_NBE, input EM_NCS, input EM_NWE, diff --git a/usrp2/gpmc/gpmc_to_fifo_sync.v b/usrp2/gpmc/gpmc_to_fifo_sync.v index 688de0e17..7ff7afdc2 100644 --- a/usrp2/gpmc/gpmc_to_fifo_sync.v +++ b/usrp2/gpmc/gpmc_to_fifo_sync.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Assumes a GPMC cycle with GPMC clock, as in the timing diagrams // If a packet bigger or smaller than we are told is sent, behavior is undefined. diff --git a/usrp2/gpmc/gpmc_wb.v b/usrp2/gpmc/gpmc_wb.v index db6fbc6e9..645201ef7 100644 --- a/usrp2/gpmc/gpmc_wb.v +++ b/usrp2/gpmc/gpmc_wb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module gpmc_wb diff --git a/usrp2/gpmc/ram_to_fifo.v b/usrp2/gpmc/ram_to_fifo.v index 8549dcc35..958c88b0f 100644 --- a/usrp2/gpmc/ram_to_fifo.v +++ b/usrp2/gpmc/ram_to_fifo.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module ram_to_fifo diff --git a/usrp2/models/CY7C1356C/cy1356.v b/usrp2/models/CY7C1356C/cy1356.v index 9197eea6d..ab7ace610 100644 --- a/usrp2/models/CY7C1356C/cy1356.v +++ b/usrp2/models/CY7C1356C/cy1356.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + `define sb200 //************************************************************************ //************************************************************************ diff --git a/usrp2/models/CY7C1356C/testbench.v b/usrp2/models/CY7C1356C/testbench.v index 5dde89e6c..01e0cbe00 100644 --- a/usrp2/models/CY7C1356C/testbench.v +++ b/usrp2/models/CY7C1356C/testbench.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + `timescale 1ns / 10ps diff --git a/usrp2/models/M24LC024B.v b/usrp2/models/M24LC024B.v index 45e04b450..5531f80fc 100644 --- a/usrp2/models/M24LC024B.v +++ b/usrp2/models/M24LC024B.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Modified 11/14/07 to simulate the 24lc024, which responds to the address pins // ******************************************************************************************************* diff --git a/usrp2/models/M24LC02B.v b/usrp2/models/M24LC02B.v index 4d9e2c6e2..00ed6f44a 100644 --- a/usrp2/models/M24LC02B.v +++ b/usrp2/models/M24LC02B.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // ******************************************************************************************************* // ** ** // ** M24LC02B.v - 24LC02B 2K-BIT I2C SERIAL EEPROM (VCC = +2.5V TO +5.5V) ** diff --git a/usrp2/models/MULT18X18S.v b/usrp2/models/MULT18X18S.v index 5d39eeaa6..3ce2a267a 100644 --- a/usrp2/models/MULT18X18S.v +++ b/usrp2/models/MULT18X18S.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Model of the Xilinx mult18x18s for signed 18x18 bit multiplies, // As in the Spartan 3 series diff --git a/usrp2/models/adc_model.v b/usrp2/models/adc_model.v index e5a3ee0d8..1d1f1c929 100644 --- a/usrp2/models/adc_model.v +++ b/usrp2/models/adc_model.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module adc_model (input clk, input rst, diff --git a/usrp2/models/cpld_model.v b/usrp2/models/cpld_model.v index c886433ae..900577852 100644 --- a/usrp2/models/cpld_model.v +++ b/usrp2/models/cpld_model.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module cpld_model (input aux_clk, input start, input mode, input done, diff --git a/usrp2/models/gpmc_model_async.v b/usrp2/models/gpmc_model_async.v index beeaee028..22b3cdf9f 100644 --- a/usrp2/models/gpmc_model_async.v +++ b/usrp2/models/gpmc_model_async.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + `timescale 1ps/1ps module gpmc_model_async diff --git a/usrp2/models/gpmc_model_sync.v b/usrp2/models/gpmc_model_sync.v index 641720c15..0f66961e7 100644 --- a/usrp2/models/gpmc_model_sync.v +++ b/usrp2/models/gpmc_model_sync.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module gpmc_model_sync diff --git a/usrp2/models/math_real.v b/usrp2/models/math_real.v index e30f68ee7..d88f72669 100644 --- a/usrp2/models/math_real.v +++ b/usrp2/models/math_real.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + /* * This is a general recreation of the VHDL ieee.math_real package. */ diff --git a/usrp2/models/miim_model.v b/usrp2/models/miim_model.v index 936d99a80..8eb8e571d 100644 --- a/usrp2/models/miim_model.v +++ b/usrp2/models/miim_model.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Skeleton PHY interface simulator diff --git a/usrp2/models/serdes_model.v b/usrp2/models/serdes_model.v index f10e55554..5e1602163 100644 --- a/usrp2/models/serdes_model.v +++ b/usrp2/models/serdes_model.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module serdes_model (input ser_tx_clk, diff --git a/usrp2/models/uart_rx.v b/usrp2/models/uart_rx.v index f698a50fe..738ffb45b 100644 --- a/usrp2/models/uart_rx.v +++ b/usrp2/models/uart_rx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Simple printout of characters from the UART diff --git a/usrp2/models/xlnx_glbl.v b/usrp2/models/xlnx_glbl.v index 662a60e35..62e29fef4 100644 --- a/usrp2/models/xlnx_glbl.v +++ b/usrp2/models/xlnx_glbl.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module xlnx_glbl ( GSR, diff --git a/usrp2/sdr_lib/acc.v b/usrp2/sdr_lib/acc.v index a2da9c86d..d5fc4b910 100644 --- a/usrp2/sdr_lib/acc.v +++ b/usrp2/sdr_lib/acc.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module acc #(parameter IWIDTH=16, OWIDTH=30) diff --git a/usrp2/sdr_lib/add2.v b/usrp2/sdr_lib/add2.v index 13fff803e..dcca84fd3 100644 --- a/usrp2/sdr_lib/add2.v +++ b/usrp2/sdr_lib/add2.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module add2 #(parameter WIDTH=16) diff --git a/usrp2/sdr_lib/add2_and_round.v b/usrp2/sdr_lib/add2_and_round.v index 146af28da..7c347527c 100644 --- a/usrp2/sdr_lib/add2_and_round.v +++ b/usrp2/sdr_lib/add2_and_round.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module add2_and_round #(parameter WIDTH=16) diff --git a/usrp2/sdr_lib/add2_and_round_reg.v b/usrp2/sdr_lib/add2_and_round_reg.v index e7fcbf1a1..5c783bda3 100644 --- a/usrp2/sdr_lib/add2_and_round_reg.v +++ b/usrp2/sdr_lib/add2_and_round_reg.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module add2_and_round_reg #(parameter WIDTH=16) diff --git a/usrp2/sdr_lib/add2_reg.v b/usrp2/sdr_lib/add2_reg.v index 456cf315b..58d822a61 100644 --- a/usrp2/sdr_lib/add2_reg.v +++ b/usrp2/sdr_lib/add2_reg.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module add2_reg #(parameter WIDTH=16) diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v index a315234cf..0e69e53f7 100644 --- a/usrp2/sdr_lib/dsp_core_rx.v +++ b/usrp2/sdr_lib/dsp_core_rx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module dsp_core_rx #(parameter BASE = 160) diff --git a/usrp2/sdr_lib/dsp_core_rx_old.v b/usrp2/sdr_lib/dsp_core_rx_old.v index ba301e91b..90d5d839f 100644 --- a/usrp2/sdr_lib/dsp_core_rx_old.v +++ b/usrp2/sdr_lib/dsp_core_rx_old.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + `define DSP_CORE_RX_BASE 160 module dsp_core_rx_old diff --git a/usrp2/sdr_lib/dsp_core_rx_udp.v b/usrp2/sdr_lib/dsp_core_rx_udp.v index 1e689fc7f..08dab37e6 100644 --- a/usrp2/sdr_lib/dsp_core_rx_udp.v +++ b/usrp2/sdr_lib/dsp_core_rx_udp.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module dsp_core_rx #(parameter BASE = 160) diff --git a/usrp2/sdr_lib/dsp_core_tx.v b/usrp2/sdr_lib/dsp_core_tx.v index 79d92c9b3..58bd82f6e 100644 --- a/usrp2/sdr_lib/dsp_core_tx.v +++ b/usrp2/sdr_lib/dsp_core_tx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module dsp_core_tx #(parameter BASE=0) diff --git a/usrp2/sdr_lib/dummy_rx.v b/usrp2/sdr_lib/dummy_rx.v index 99290ecec..b22d5f896 100644 --- a/usrp2/sdr_lib/dummy_rx.v +++ b/usrp2/sdr_lib/dummy_rx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + `define DSP_CORE_RX_BASE 160 module dummy_rx diff --git a/usrp2/sdr_lib/halfband_ideal.v b/usrp2/sdr_lib/halfband_ideal.v index 484cfff2a..e0b04cf86 100644 --- a/usrp2/sdr_lib/halfband_ideal.v +++ b/usrp2/sdr_lib/halfband_ideal.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module halfband_ideal ( input clock, input reset, diff --git a/usrp2/sdr_lib/halfband_tb.v b/usrp2/sdr_lib/halfband_tb.v index 231dd00d7..80f46fe36 100644 --- a/usrp2/sdr_lib/halfband_tb.v +++ b/usrp2/sdr_lib/halfband_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module halfband_tb( ) ; // Parameters for instantiation diff --git a/usrp2/sdr_lib/hb/acc.v b/usrp2/sdr_lib/hb/acc.v index 195d5ea94..d7be895c6 100644 --- a/usrp2/sdr_lib/hb/acc.v +++ b/usrp2/sdr_lib/hb/acc.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module acc (input clock, input reset, input clear, input enable_in, output reg enable_out, diff --git a/usrp2/sdr_lib/hb/coeff_ram.v b/usrp2/sdr_lib/hb/coeff_ram.v index 65460822f..525c22abc 100644 --- a/usrp2/sdr_lib/hb/coeff_ram.v +++ b/usrp2/sdr_lib/hb/coeff_ram.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module coeff_ram (input clock, input [3:0] rd_addr, output reg [15:0] rd_data); diff --git a/usrp2/sdr_lib/hb/coeff_rom.v b/usrp2/sdr_lib/hb/coeff_rom.v index 7f8886b4e..a43c8391a 100644 --- a/usrp2/sdr_lib/hb/coeff_rom.v +++ b/usrp2/sdr_lib/hb/coeff_rom.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module coeff_rom (input clock, input [2:0] addr, output reg [15:0] data); diff --git a/usrp2/sdr_lib/hb/halfband_interp.v b/usrp2/sdr_lib/hb/halfband_interp.v index cdb11c1f6..83bdc9fad 100644 --- a/usrp2/sdr_lib/hb/halfband_interp.v +++ b/usrp2/sdr_lib/hb/halfband_interp.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module halfband_interp diff --git a/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v b/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v index 01ab5e7e0..450f90e66 100644 --- a/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v +++ b/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module test_hbd(); diff --git a/usrp2/sdr_lib/hb/mac.v b/usrp2/sdr_lib/hb/mac.v index 5a270bc73..8058a6db4 100644 --- a/usrp2/sdr_lib/hb/mac.v +++ b/usrp2/sdr_lib/hb/mac.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module mac (input clock, input reset, input enable, input clear, diff --git a/usrp2/sdr_lib/hb/mult.v b/usrp2/sdr_lib/hb/mult.v index a8d4cb1b7..a50ae69e2 100644 --- a/usrp2/sdr_lib/hb/mult.v +++ b/usrp2/sdr_lib/hb/mult.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module mult (input clock, input signed [15:0] x, input signed [15:0] y, output reg signed [30:0] product, diff --git a/usrp2/sdr_lib/hb/ram16_2port.v b/usrp2/sdr_lib/hb/ram16_2port.v index e1761a926..631cf5a41 100644 --- a/usrp2/sdr_lib/hb/ram16_2port.v +++ b/usrp2/sdr_lib/hb/ram16_2port.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module ram16_2port (input clock, input write, diff --git a/usrp2/sdr_lib/hb/ram16_2sum.v b/usrp2/sdr_lib/hb/ram16_2sum.v index 559b06fd5..f9ec1837e 100644 --- a/usrp2/sdr_lib/hb/ram16_2sum.v +++ b/usrp2/sdr_lib/hb/ram16_2sum.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module ram16_2sum (input clock, input write, diff --git a/usrp2/sdr_lib/hb/ram32_2sum.v b/usrp2/sdr_lib/hb/ram32_2sum.v index d1f55b7d0..f7032835e 100644 --- a/usrp2/sdr_lib/hb/ram32_2sum.v +++ b/usrp2/sdr_lib/hb/ram32_2sum.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module ram32_2sum (input clock, input write, diff --git a/usrp2/sdr_lib/hb_dec.v b/usrp2/sdr_lib/hb_dec.v index 8fb5ba222..9747f0adb 100644 --- a/usrp2/sdr_lib/hb_dec.v +++ b/usrp2/sdr_lib/hb_dec.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Final halfband decimator // Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A] // Strobe in cannot come faster than every 2nd clock cycle diff --git a/usrp2/sdr_lib/hb_dec_tb.v b/usrp2/sdr_lib/hb_dec_tb.v index 3e5faa80a..256f6085d 100644 --- a/usrp2/sdr_lib/hb_dec_tb.v +++ b/usrp2/sdr_lib/hb_dec_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module hb_dec_tb( ) ; // Parameters for instantiation diff --git a/usrp2/sdr_lib/hb_interp.v b/usrp2/sdr_lib/hb_interp.v index d16807e15..deb4fe056 100644 --- a/usrp2/sdr_lib/hb_interp.v +++ b/usrp2/sdr_lib/hb_interp.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // First halfband iterpolator // Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A] // Strobe in cannot come faster than every 4th clock cycle, diff --git a/usrp2/sdr_lib/hb_interp_tb.v b/usrp2/sdr_lib/hb_interp_tb.v index 52f137f28..239412155 100644 --- a/usrp2/sdr_lib/hb_interp_tb.v +++ b/usrp2/sdr_lib/hb_interp_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module hb_interp_tb( ) ; // Parameters for instantiation diff --git a/usrp2/sdr_lib/hb_tb.v b/usrp2/sdr_lib/hb_tb.v index 7e960fd13..3260ac738 100644 --- a/usrp2/sdr_lib/hb_tb.v +++ b/usrp2/sdr_lib/hb_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module hb_tb(); diff --git a/usrp2/sdr_lib/integrate.v b/usrp2/sdr_lib/integrate.v index db33de979..ce674d470 100644 --- a/usrp2/sdr_lib/integrate.v +++ b/usrp2/sdr_lib/integrate.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module integrate #(parameter INPUTW = 16, parameter ACCUMW = 32, diff --git a/usrp2/sdr_lib/med_hb_int.v b/usrp2/sdr_lib/med_hb_int.v index bc8066509..f619dc81b 100644 --- a/usrp2/sdr_lib/med_hb_int.v +++ b/usrp2/sdr_lib/med_hb_int.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Medium halfband decimator (intended to be followed by another stage) // Implements impulse responses of the form [A 0 B 0 C 0 D 0.5 D 0 C 0 B 0 A] // diff --git a/usrp2/sdr_lib/rssi.v b/usrp2/sdr_lib/rssi.v index e45e2148c..e931ff865 100644 --- a/usrp2/sdr_lib/rssi.v +++ b/usrp2/sdr_lib/rssi.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module rssi (input clock, input reset, input enable, diff --git a/usrp2/sdr_lib/rx_control.v b/usrp2/sdr_lib/rx_control.v index 0adeb0794..12f411ffe 100644 --- a/usrp2/sdr_lib/rx_control.v +++ b/usrp2/sdr_lib/rx_control.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + `define DSP_CORE_RX_BASE 160 diff --git a/usrp2/sdr_lib/rx_dcoffset.v b/usrp2/sdr_lib/rx_dcoffset.v index bedbd40e6..64ff4110d 100644 --- a/usrp2/sdr_lib/rx_dcoffset.v +++ b/usrp2/sdr_lib/rx_dcoffset.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module rx_dcoffset diff --git a/usrp2/sdr_lib/rx_dcoffset_tb.v b/usrp2/sdr_lib/rx_dcoffset_tb.v index a8b4ec20f..b0dd8cb05 100644 --- a/usrp2/sdr_lib/rx_dcoffset_tb.v +++ b/usrp2/sdr_lib/rx_dcoffset_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + `timescale 1ns/1ns module rx_dcoffset_tb(); diff --git a/usrp2/sdr_lib/small_hb_dec.v b/usrp2/sdr_lib/small_hb_dec.v index 8519b628a..151b8c287 100644 --- a/usrp2/sdr_lib/small_hb_dec.v +++ b/usrp2/sdr_lib/small_hb_dec.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Short halfband decimator (intended to be followed by another stage) // Implements impulse responses of the form [A 0 B 0.5 B 0 A] // diff --git a/usrp2/sdr_lib/small_hb_dec_tb.v b/usrp2/sdr_lib/small_hb_dec_tb.v index 0d6a0689e..1e713321a 100644 --- a/usrp2/sdr_lib/small_hb_dec_tb.v +++ b/usrp2/sdr_lib/small_hb_dec_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module hb_dec_tb( ) ; // Parameters for instantiation diff --git a/usrp2/sdr_lib/small_hb_int.v b/usrp2/sdr_lib/small_hb_int.v index f80d3cac3..387f9e1cb 100644 --- a/usrp2/sdr_lib/small_hb_int.v +++ b/usrp2/sdr_lib/small_hb_int.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Short halfband decimator (intended to be followed by another stage) // Implements impulse responses of the form [A 0 B 0.5 B 0 A] // diff --git a/usrp2/sdr_lib/small_hb_int_tb.v b/usrp2/sdr_lib/small_hb_int_tb.v index 71d77f0a8..fe1e1a7dd 100644 --- a/usrp2/sdr_lib/small_hb_int_tb.v +++ b/usrp2/sdr_lib/small_hb_int_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module small_hb_int_tb( ) ; // Parameters for instantiation diff --git a/usrp2/sdr_lib/tx_control.v b/usrp2/sdr_lib/tx_control.v index e5fed0b93..e6866a40c 100644 --- a/usrp2/sdr_lib/tx_control.v +++ b/usrp2/sdr_lib/tx_control.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + `define DSP_CORE_TX_BASE 128 diff --git a/usrp2/serdes/serdes.v b/usrp2/serdes/serdes.v index 17049bfe6..edbc46419 100644 --- a/usrp2/serdes/serdes.v +++ b/usrp2/serdes/serdes.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // SERDES TX and RX along with all flow control logic diff --git a/usrp2/serdes/serdes_fc_rx.v b/usrp2/serdes/serdes_fc_rx.v index 4dd46e27f..9ea32cf8d 100644 --- a/usrp2/serdes/serdes_fc_rx.v +++ b/usrp2/serdes/serdes_fc_rx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module serdes_fc_rx diff --git a/usrp2/serdes/serdes_fc_tx.v b/usrp2/serdes/serdes_fc_tx.v index 2fe967c8d..0a62ae2e5 100644 --- a/usrp2/serdes/serdes_fc_tx.v +++ b/usrp2/serdes/serdes_fc_tx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module serdes_fc_tx diff --git a/usrp2/serdes/serdes_rx.v b/usrp2/serdes/serdes_rx.v index b6688e858..1950d4e2a 100644 --- a/usrp2/serdes/serdes_rx.v +++ b/usrp2/serdes/serdes_rx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // SERDES Interface diff --git a/usrp2/serdes/serdes_tb.v b/usrp2/serdes/serdes_tb.v index eb8e019fc..685a8580d 100644 --- a/usrp2/serdes/serdes_tb.v +++ b/usrp2/serdes/serdes_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // FIXME need to add flow control diff --git a/usrp2/serdes/serdes_tx.v b/usrp2/serdes/serdes_tx.v index 2e5e3bd80..0cd077e5c 100644 --- a/usrp2/serdes/serdes_tx.v +++ b/usrp2/serdes/serdes_tx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // SERDES Interface diff --git a/usrp2/simple_gemac/address_filter.v b/usrp2/simple_gemac/address_filter.v index 50a52b954..bf6194600 100644 --- a/usrp2/simple_gemac/address_filter.v +++ b/usrp2/simple_gemac/address_filter.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module address_filter diff --git a/usrp2/simple_gemac/address_filter_promisc.v b/usrp2/simple_gemac/address_filter_promisc.v index 6047e7c93..3ff05fbe1 100644 --- a/usrp2/simple_gemac/address_filter_promisc.v +++ b/usrp2/simple_gemac/address_filter_promisc.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module address_filter_promisc diff --git a/usrp2/simple_gemac/crc.v b/usrp2/simple_gemac/crc.v index ac019083a..ef62f8ff8 100644 --- a/usrp2/simple_gemac/crc.v +++ b/usrp2/simple_gemac/crc.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module crc (input clk, diff --git a/usrp2/simple_gemac/delay_line.v b/usrp2/simple_gemac/delay_line.v index d371bb9c5..5a559a504 100644 --- a/usrp2/simple_gemac/delay_line.v +++ b/usrp2/simple_gemac/delay_line.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module delay_line diff --git a/usrp2/simple_gemac/eth_tasks.v b/usrp2/simple_gemac/eth_tasks.v index d49f30e24..731fd6d52 100644 --- a/usrp2/simple_gemac/eth_tasks.v +++ b/usrp2/simple_gemac/eth_tasks.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + task SendFlowCtrl; diff --git a/usrp2/simple_gemac/eth_tasks_f19.v b/usrp2/simple_gemac/eth_tasks_f19.v index ff3ae5407..3ff23a413 100644 --- a/usrp2/simple_gemac/eth_tasks_f19.v +++ b/usrp2/simple_gemac/eth_tasks_f19.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + task SendFlowCtrl; diff --git a/usrp2/simple_gemac/eth_tasks_f36.v b/usrp2/simple_gemac/eth_tasks_f36.v index dc64971d4..dee651d80 100644 --- a/usrp2/simple_gemac/eth_tasks_f36.v +++ b/usrp2/simple_gemac/eth_tasks_f36.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + task SendFlowCtrl; diff --git a/usrp2/simple_gemac/ethrx_realign.v b/usrp2/simple_gemac/ethrx_realign.v index 0a369c914..a08feb91e 100644 --- a/usrp2/simple_gemac/ethrx_realign.v +++ b/usrp2/simple_gemac/ethrx_realign.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // NOTE: Will not work with single-line frames diff --git a/usrp2/simple_gemac/ethtx_realign.v b/usrp2/simple_gemac/ethtx_realign.v index be53abf4c..236b2d4e1 100644 --- a/usrp2/simple_gemac/ethtx_realign.v +++ b/usrp2/simple_gemac/ethtx_realign.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + //////////////////////////////////////////////////////////////////////// // Ethernet TX - Realign diff --git a/usrp2/simple_gemac/flow_ctrl_rx.v b/usrp2/simple_gemac/flow_ctrl_rx.v index d09bf377f..aa12875f2 100644 --- a/usrp2/simple_gemac/flow_ctrl_rx.v +++ b/usrp2/simple_gemac/flow_ctrl_rx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // RX side of flow control -- when we are running out of RX space, send a PAUSE diff --git a/usrp2/simple_gemac/flow_ctrl_tx.v b/usrp2/simple_gemac/flow_ctrl_tx.v index f80f5a76d..bdc1e4701 100644 --- a/usrp2/simple_gemac/flow_ctrl_tx.v +++ b/usrp2/simple_gemac/flow_ctrl_tx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // TX side of flow control -- when other side sends PAUSE, we wait diff --git a/usrp2/simple_gemac/ll8_to_txmac.v b/usrp2/simple_gemac/ll8_to_txmac.v index 3530a0c59..ac81afa63 100644 --- a/usrp2/simple_gemac/ll8_to_txmac.v +++ b/usrp2/simple_gemac/ll8_to_txmac.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module ll8_to_txmac (input clk, input reset, input clear, diff --git a/usrp2/simple_gemac/rxmac_to_ll8.v b/usrp2/simple_gemac/rxmac_to_ll8.v index 5ec233d95..5acb08bb7 100644 --- a/usrp2/simple_gemac/rxmac_to_ll8.v +++ b/usrp2/simple_gemac/rxmac_to_ll8.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module rxmac_to_ll8 (input clk, input reset, input clear, diff --git a/usrp2/simple_gemac/simple_gemac.v b/usrp2/simple_gemac/simple_gemac.v index 2dd8deb99..ec13d3c96 100644 --- a/usrp2/simple_gemac/simple_gemac.v +++ b/usrp2/simple_gemac/simple_gemac.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module simple_gemac (input clk125, input reset, diff --git a/usrp2/simple_gemac/simple_gemac_rx.v b/usrp2/simple_gemac/simple_gemac_rx.v index 32f517bb3..e6c0424bd 100644 --- a/usrp2/simple_gemac/simple_gemac_rx.v +++ b/usrp2/simple_gemac/simple_gemac_rx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module simple_gemac_rx diff --git a/usrp2/simple_gemac/simple_gemac_tb.v b/usrp2/simple_gemac/simple_gemac_tb.v index 6091751a7..ed7d796dc 100644 --- a/usrp2/simple_gemac/simple_gemac_tb.v +++ b/usrp2/simple_gemac/simple_gemac_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module simple_gemac_tb; diff --git a/usrp2/simple_gemac/simple_gemac_tx.v b/usrp2/simple_gemac/simple_gemac_tx.v index dd870d04d..ecabc3dad 100644 --- a/usrp2/simple_gemac/simple_gemac_tx.v +++ b/usrp2/simple_gemac/simple_gemac_tx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module simple_gemac_tx (input clk125, input reset, diff --git a/usrp2/simple_gemac/simple_gemac_wb.v b/usrp2/simple_gemac/simple_gemac_wb.v index 1ef38be11..bcf18f9a8 100644 --- a/usrp2/simple_gemac/simple_gemac_wb.v +++ b/usrp2/simple_gemac/simple_gemac_wb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module wb_reg #(parameter ADDR=0, diff --git a/usrp2/simple_gemac/simple_gemac_wrapper.v b/usrp2/simple_gemac/simple_gemac_wrapper.v index 8390eb2c6..9763578b9 100644 --- a/usrp2/simple_gemac/simple_gemac_wrapper.v +++ b/usrp2/simple_gemac/simple_gemac_wrapper.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module simple_gemac_wrapper #(parameter RXFIFOSIZE=9, diff --git a/usrp2/simple_gemac/simple_gemac_wrapper19.v b/usrp2/simple_gemac/simple_gemac_wrapper19.v index 2ac8b9be1..3e1793d82 100644 --- a/usrp2/simple_gemac/simple_gemac_wrapper19.v +++ b/usrp2/simple_gemac/simple_gemac_wrapper19.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module simple_gemac_wrapper19 #(parameter RXFIFOSIZE=9, diff --git a/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v b/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v index b61d60d30..78f525fd7 100644 --- a/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v +++ b/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module simple_gemac_wrapper19_tb; diff --git a/usrp2/simple_gemac/simple_gemac_wrapper_f36_tb.v b/usrp2/simple_gemac/simple_gemac_wrapper_f36_tb.v index 804fa8748..2904e38d4 100644 --- a/usrp2/simple_gemac/simple_gemac_wrapper_f36_tb.v +++ b/usrp2/simple_gemac/simple_gemac_wrapper_f36_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module simple_gemac_wrapper_f36_tb; diff --git a/usrp2/simple_gemac/simple_gemac_wrapper_tb.v b/usrp2/simple_gemac/simple_gemac_wrapper_tb.v index 0aadc7e93..5a3f3f832 100644 --- a/usrp2/simple_gemac/simple_gemac_wrapper_tb.v +++ b/usrp2/simple_gemac/simple_gemac_wrapper_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module simple_gemac_wrapper_tb; diff --git a/usrp2/testbench/single_u2_sim.v b/usrp2/testbench/single_u2_sim.v index 2a7b24849..f25374613 100644 --- a/usrp2/testbench/single_u2_sim.v +++ b/usrp2/testbench/single_u2_sim.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// diff --git a/usrp2/timing/simple_timer.v b/usrp2/timing/simple_timer.v index 17c7f1c36..56ba8ffe8 100644 --- a/usrp2/timing/simple_timer.v +++ b/usrp2/timing/simple_timer.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module simple_timer diff --git a/usrp2/timing/time_64bit.v b/usrp2/timing/time_64bit.v index 8122cc6ea..d32f4220b 100644 --- a/usrp2/timing/time_64bit.v +++ b/usrp2/timing/time_64bit.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module time_64bit diff --git a/usrp2/timing/time_compare.v b/usrp2/timing/time_compare.v index cb2b6d860..54ea000d6 100644 --- a/usrp2/timing/time_compare.v +++ b/usrp2/timing/time_compare.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Top 32 bits are integer seconds, bottom 32 are clock ticks within a second diff --git a/usrp2/timing/time_receiver.v b/usrp2/timing/time_receiver.v index 897f71186..a03337552 100644 --- a/usrp2/timing/time_receiver.v +++ b/usrp2/timing/time_receiver.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module time_receiver (input clk, input rst, diff --git a/usrp2/timing/time_sender.v b/usrp2/timing/time_sender.v index f4ee5226a..fdf6b1240 100644 --- a/usrp2/timing/time_sender.v +++ b/usrp2/timing/time_sender.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module time_sender diff --git a/usrp2/timing/time_sync.v b/usrp2/timing/time_sync.v index c0c8e195f..a823e9e1b 100644 --- a/usrp2/timing/time_sync.v +++ b/usrp2/timing/time_sync.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module time_sync diff --git a/usrp2/timing/time_transfer_tb.v b/usrp2/timing/time_transfer_tb.v index 0c164f82c..288540702 100644 --- a/usrp2/timing/time_transfer_tb.v +++ b/usrp2/timing/time_transfer_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + `timescale 1ns / 1ps diff --git a/usrp2/timing/timer.v b/usrp2/timing/timer.v index 70c9746be..216a9294c 100644 --- a/usrp2/timing/timer.v +++ b/usrp2/timing/timer.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module timer diff --git a/usrp2/top/B100/u1plus.v b/usrp2/top/B100/u1plus.v index 9aafef3ce..5e3200580 100644 --- a/usrp2/top/B100/u1plus.v +++ b/usrp2/top/B100/u1plus.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v index 898f5950c..8a02f0fb8 100644 --- a/usrp2/top/B100/u1plus_core.v +++ b/usrp2/top/B100/u1plus_core.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module u1plus_core diff --git a/usrp2/top/E1x0/passthru.v b/usrp2/top/E1x0/passthru.v index 12e4db017..486257366 100644 --- a/usrp2/top/E1x0/passthru.v +++ b/usrp2/top/E1x0/passthru.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// diff --git a/usrp2/top/E1x0/tb_u1e.v b/usrp2/top/E1x0/tb_u1e.v index 5fc8134fb..188190f04 100644 --- a/usrp2/top/E1x0/tb_u1e.v +++ b/usrp2/top/E1x0/tb_u1e.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + `timescale 1ps / 1ps ////////////////////////////////////////////////////////////////////////////////// diff --git a/usrp2/top/E1x0/u1e.v b/usrp2/top/E1x0/u1e.v index 445b14a03..adf42fd07 100644 --- a/usrp2/top/E1x0/u1e.v +++ b/usrp2/top/E1x0/u1e.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v index d10a3ab30..4c513587b 100644 --- a/usrp2/top/E1x0/u1e_core.v +++ b/usrp2/top/E1x0/u1e_core.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module u1e_core diff --git a/usrp2/top/N2x0/capture_ddrlvds.v b/usrp2/top/N2x0/capture_ddrlvds.v index d263e0cfa..e261dcbe8 100644 --- a/usrp2/top/N2x0/capture_ddrlvds.v +++ b/usrp2/top/N2x0/capture_ddrlvds.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module capture_ddrlvds diff --git a/usrp2/top/N2x0/rev4_defs.v b/usrp2/top/N2x0/rev4_defs.v index e37f34851..f8f6667ac 100644 --- a/usrp2/top/N2x0/rev4_defs.v +++ b/usrp2/top/N2x0/rev4_defs.v @@ -1 +1,18 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + `define LVDS 1 diff --git a/usrp2/top/N2x0/u2plus.v b/usrp2/top/N2x0/u2plus.v index 7bf467fde..be6cdeeca 100644 --- a/usrp2/top/N2x0/u2plus.v +++ b/usrp2/top/N2x0/u2plus.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + `timescale 1ns / 1ps //`define LVDS 1 //`define DCM_FOR_RAMCLK diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v index ee5d7efcd..8a7c6ddee 100644 --- a/usrp2/top/N2x0/u2plus_core.v +++ b/usrp2/top/N2x0/u2plus_core.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // //////////////////////////////////////////////////////////////////////////////// // Module Name: u2_core // //////////////////////////////////////////////////////////////////////////////// diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v index 0e6120ec6..ca9762ac5 100644 --- a/usrp2/top/USRP2/u2_core.v +++ b/usrp2/top/USRP2/u2_core.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // //////////////////////////////////////////////////////////////////////////////// // Module Name: u2_core // //////////////////////////////////////////////////////////////////////////////// diff --git a/usrp2/top/USRP2/u2_rev3.v b/usrp2/top/USRP2/u2_rev3.v index bc7ae5f16..4b0bb5541 100644 --- a/usrp2/top/USRP2/u2_rev3.v +++ b/usrp2/top/USRP2/u2_rev3.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// diff --git a/usrp2/udp/add_onescomp.v b/usrp2/udp/add_onescomp.v index 048842a86..e02604114 100644 --- a/usrp2/udp/add_onescomp.v +++ b/usrp2/udp/add_onescomp.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module add_onescomp diff --git a/usrp2/udp/fifo19_rxrealign.v b/usrp2/udp/fifo19_rxrealign.v index 35ad90951..da5fd20af 100644 --- a/usrp2/udp/fifo19_rxrealign.v +++ b/usrp2/udp/fifo19_rxrealign.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + // Adds a junk line at the beginning of every packet, which the diff --git a/usrp2/udp/prot_eng_rx.v b/usrp2/udp/prot_eng_rx.v index 5df158b2b..ccb59b7ff 100644 --- a/usrp2/udp/prot_eng_rx.v +++ b/usrp2/udp/prot_eng_rx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + diff --git a/usrp2/udp/prot_eng_tx.v b/usrp2/udp/prot_eng_tx.v index b4f6e55b8..40abf3c04 100644 --- a/usrp2/udp/prot_eng_tx.v +++ b/usrp2/udp/prot_eng_tx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module prot_eng_tx #(parameter BASE=0) diff --git a/usrp2/udp/prot_eng_tx_tb.v b/usrp2/udp/prot_eng_tx_tb.v index 138794e57..866093ef5 100644 --- a/usrp2/udp/prot_eng_tx_tb.v +++ b/usrp2/udp/prot_eng_tx_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module prot_eng_tx_tb(); localparam BASE = 128; diff --git a/usrp2/udp/udp_wrapper.v b/usrp2/udp/udp_wrapper.v index f4c642615..20bcb477b 100644 --- a/usrp2/udp/udp_wrapper.v +++ b/usrp2/udp/udp_wrapper.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module udp_wrapper #(parameter BASE=0) diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v index cc34cceed..bdfca8237 100644 --- a/usrp2/vrt/gen_context_pkt.v +++ b/usrp2/vrt/gen_context_pkt.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module gen_context_pkt diff --git a/usrp2/vrt/trigger_context_pkt.v b/usrp2/vrt/trigger_context_pkt.v index 1d456814b..3d9c2e5c6 100644 --- a/usrp2/vrt/trigger_context_pkt.v +++ b/usrp2/vrt/trigger_context_pkt.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module trigger_context_pkt diff --git a/usrp2/vrt/vita_pkt_gen.v b/usrp2/vrt/vita_pkt_gen.v index fea312188..b962254a6 100644 --- a/usrp2/vrt/vita_pkt_gen.v +++ b/usrp2/vrt/vita_pkt_gen.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module vita_pkt_gen diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v index 28955d108..1986743b3 100644 --- a/usrp2/vrt/vita_rx_chain.v +++ b/usrp2/vrt/vita_rx_chain.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module vita_rx_chain #(parameter BASE=0, diff --git a/usrp2/vrt/vita_rx_control.v b/usrp2/vrt/vita_rx_control.v index 4c0cef50d..39f32d7fe 100644 --- a/usrp2/vrt/vita_rx_control.v +++ b/usrp2/vrt/vita_rx_control.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module vita_rx_control #(parameter BASE=0, diff --git a/usrp2/vrt/vita_rx_framer.v b/usrp2/vrt/vita_rx_framer.v index 04b636778..bd09315bc 100644 --- a/usrp2/vrt/vita_rx_framer.v +++ b/usrp2/vrt/vita_rx_framer.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module vita_rx_framer #(parameter BASE=0, diff --git a/usrp2/vrt/vita_rx_tb.v b/usrp2/vrt/vita_rx_tb.v index 023934f39..8cd08a972 100644 --- a/usrp2/vrt/vita_rx_tb.v +++ b/usrp2/vrt/vita_rx_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module vita_rx_tb; diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index fa84d7a2f..542968afa 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module vita_tx_chain #(parameter BASE_CTRL=0, diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index 14b97a215..5df89bdbe 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module vita_tx_control #(parameter BASE=0, diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index 163c2af20..06ca27767 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module vita_tx_deframer #(parameter BASE=0, diff --git a/usrp2/vrt/vita_tx_tb.v b/usrp2/vrt/vita_tx_tb.v index a118ffd4e..b686a8a16 100644 --- a/usrp2/vrt/vita_tx_tb.v +++ b/usrp2/vrt/vita_tx_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + module vita_tx_tb; -- cgit v1.2.3 From 23c373f4ebea614a59f2032293b0264d93468fef Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 7 Jun 2011 19:46:49 -0700 Subject: fix copyright notice --- usrp2/top/tcl/ise_helper.tcl | 2 -- 1 file changed, 2 deletions(-) diff --git a/usrp2/top/tcl/ise_helper.tcl b/usrp2/top/tcl/ise_helper.tcl index a4bee76b8..f11596f8b 100644 --- a/usrp2/top/tcl/ise_helper.tcl +++ b/usrp2/top/tcl/ise_helper.tcl @@ -1,8 +1,6 @@ # # Copyright 2008 Ettus Research LLC # -# This file is part of GNU Radio -# # GNU Radio is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 3, or (at your option) -- cgit v1.2.3 From c0fadece89314f3a00892122c28caf187ce1a717 Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Fri, 10 Jun 2011 15:03:19 -0700 Subject: N2XX: this method for defining R3/R4 actually works --- usrp2/top/N2x0/Makefile.N200R4 | 4 ++-- usrp2/top/N2x0/Makefile.N210R4 | 4 ++-- usrp2/top/N2x0/rev4_defs.v | 18 ------------------ 3 files changed, 4 insertions(+), 22 deletions(-) delete mode 100644 usrp2/top/N2x0/rev4_defs.v diff --git a/usrp2/top/N2x0/Makefile.N200R4 b/usrp2/top/N2x0/Makefile.N200R4 index 955aadc59..0ca40e1bd 100644 --- a/usrp2/top/N2x0/Makefile.N200R4 +++ b/usrp2/top/N2x0/Makefile.N200R4 @@ -45,7 +45,6 @@ simulator "ISE Simulator (VHDL/Verilog)" \ # Sources ################################################## TOP_SRCS = \ -rev4_defs.v \ capture_ddrlvds.v \ u2plus_core.v \ u2plus.v \ @@ -67,7 +66,8 @@ SYNTHESIZE_PROPERTIES = \ "Register Balancing" Yes \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto +"Use Synchronous Set" Auto \ +"Verilog Macros" "LVDS=1" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" diff --git a/usrp2/top/N2x0/Makefile.N210R4 b/usrp2/top/N2x0/Makefile.N210R4 index 73747e544..01a9e19fd 100644 --- a/usrp2/top/N2x0/Makefile.N210R4 +++ b/usrp2/top/N2x0/Makefile.N210R4 @@ -45,7 +45,6 @@ simulator "ISE Simulator (VHDL/Verilog)" \ # Sources ################################################## TOP_SRCS = \ -rev4_defs.v \ capture_ddrlvds.v \ u2plus_core.v \ u2plus.v \ @@ -67,7 +66,8 @@ SYNTHESIZE_PROPERTIES = \ "Register Balancing" Yes \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto +"Use Synchronous Set" Auto \ +"Verilog Macros" "LVDS=1" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" diff --git a/usrp2/top/N2x0/rev4_defs.v b/usrp2/top/N2x0/rev4_defs.v deleted file mode 100644 index f8f6667ac..000000000 --- a/usrp2/top/N2x0/rev4_defs.v +++ /dev/null @@ -1,18 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -`define LVDS 1 -- cgit v1.2.3 From f914195053060d4274ea4f9b11589b7e4ef47e40 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Sun, 12 Jun 2011 18:00:03 -0700 Subject: usrp-e-loopback : Fix transfer rate calculation. Calculation now uses fractional seconds, not integer seconds. --- host/usrp_e_utils/usrp-e-loopback.c | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/host/usrp_e_utils/usrp-e-loopback.c b/host/usrp_e_utils/usrp-e-loopback.c index 0bd3d3100..762e55ac8 100644 --- a/host/usrp_e_utils/usrp-e-loopback.c +++ b/host/usrp_e_utils/usrp-e-loopback.c @@ -51,12 +51,27 @@ static int calc_checksum(struct pkt *p) return sum; } +static struct timeval delta_time(struct timeval f, struct timeval s) +{ + struct timeval d; + + if (f.tv_usec > s.tv_usec) { + d.tv_usec = f.tv_usec - s.tv_usec; + d.tv_sec = f.tv_sec - s.tv_sec; + } else { + d.tv_usec = f.tv_usec - s.tv_usec + 1e6; + d.tv_sec = f.tv_sec - s.tv_sec - 1; + } + + return d; +} + static void *read_thread(void *threadid) { int cnt, prev_seq_num, pkt_count, seq_num_failure; struct pkt *p; - unsigned long bytes_transfered, elapsed_seconds; - struct timeval start_time, finish_time; + unsigned long bytes_transfered; + struct timeval start_time; int rb_read; printf("Greetings from the reading thread!\n"); @@ -125,11 +140,15 @@ static void *read_thread(void *threadid) bytes_transfered += cnt; if (bytes_transfered > (100 * 1000000)) { + struct timeval finish_time, d_time; + float elapsed_seconds; + gettimeofday(&finish_time, NULL); - elapsed_seconds = finish_time.tv_sec - start_time.tv_sec; + d_time = delta_time(finish_time, start_time); + elapsed_seconds = (float)d_time.tv_sec + ((float)d_time.tv_usec * 1e-6f); printf("RX data transfer rate = %f K Samples/second\n", - (float) bytes_transfered / (float) elapsed_seconds / 4000); + (float) bytes_transfered / elapsed_seconds / 4000.0f); start_time = finish_time; -- cgit v1.2.3 From a6ca4778f8ae05b7f24e8c64bd58d7f39b3a9c14 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Sun, 12 Jun 2011 18:09:59 -0700 Subject: usrp-e-timed : Fix stupid typo in tx rate calculation. --- host/usrp_e_utils/usrp-e-timed.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/host/usrp_e_utils/usrp-e-timed.c b/host/usrp_e_utils/usrp-e-timed.c index 06dfdf512..407564429 100644 --- a/host/usrp_e_utils/usrp-e-timed.c +++ b/host/usrp_e_utils/usrp-e-timed.c @@ -273,7 +273,7 @@ static void *write_thread(void *threadid) d_time = delta_time(finish_time, start_time); - elapsed_seconds = (float)d_time.tv_sec - ((float)d_time.tv_usec * 1e-6f); + elapsed_seconds = (float)d_time.tv_sec + ((float)d_time.tv_usec * 1e-6f); printf("Bytes transfered = %ld, elapsed seconds = %f\n", bytes_transfered, elapsed_seconds); printf("TX data transfer rate = %f K Samples/second\n", -- cgit v1.2.3 From 86f12cd1c1c606bbfbc6f0ddbd98166fe9251a13 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 23 May 2011 13:37:05 -0700 Subject: uhd: added scaling factor to conversion routines --- host/include/uhd/convert.hpp | 2 +- host/lib/convert/convert_common.hpp | 40 +++++++++++++------------------ host/lib/convert/convert_with_neon.cpp | 8 +++---- host/lib/convert/convert_with_sse2.cpp | 16 ++++++------- host/lib/convert/gen_convert_general.py | 8 +++---- host/lib/transport/vrt_packet_handler.hpp | 4 ++-- host/tests/convert_test.cpp | 12 +++++----- 7 files changed, 41 insertions(+), 49 deletions(-) diff --git a/host/include/uhd/convert.hpp b/host/include/uhd/convert.hpp index 8fc2f38db..99f1860ae 100644 --- a/host/include/uhd/convert.hpp +++ b/host/include/uhd/convert.hpp @@ -29,7 +29,7 @@ namespace uhd{ namespace convert{ typedef uhd::ref_vector output_type; typedef uhd::ref_vector input_type; - typedef boost::function function_type; + typedef boost::function function_type; /*! * Describe the priority of a converter function. diff --git a/host/lib/convert/convert_common.hpp b/host/lib/convert/convert_common.hpp index c2ca233d9..7f513b124 100644 --- a/host/lib/convert/convert_common.hpp +++ b/host/lib/convert/convert_common.hpp @@ -27,7 +27,7 @@ static void fcn( \ const uhd::convert::input_type &inputs, \ const uhd::convert::output_type &outputs, \ - size_t nsamps \ + size_t nsamps, double scale_factor \ ); \ UHD_STATIC_BLOCK(register_##fcn##_##prio){ \ uhd::convert::register_converter(#fcn, fcn, prio); \ @@ -35,7 +35,7 @@ static void fcn( \ const uhd::convert::input_type &inputs, \ const uhd::convert::output_type &outputs, \ - size_t nsamps \ + size_t nsamps, double scale_factor \ ) /*********************************************************************** @@ -50,7 +50,7 @@ typedef boost::uint32_t item32_t; /*********************************************************************** * Convert complex short buffer to items32 **********************************************************************/ -static UHD_INLINE item32_t sc16_to_item32(sc16_t num){ +static UHD_INLINE item32_t sc16_to_item32(sc16_t num, double){ boost::uint16_t real = num.real(); boost::uint16_t imag = num.imag(); return (item32_t(real) << 16) | (item32_t(imag) << 0); @@ -59,7 +59,7 @@ static UHD_INLINE item32_t sc16_to_item32(sc16_t num){ /*********************************************************************** * Convert items32 buffer to complex short **********************************************************************/ -static UHD_INLINE sc16_t item32_to_sc16(item32_t item){ +static UHD_INLINE sc16_t item32_to_sc16(item32_t item, double){ return sc16_t( boost::int16_t(item >> 16), boost::int16_t(item >> 0) @@ -69,46 +69,38 @@ static UHD_INLINE sc16_t item32_to_sc16(item32_t item){ /*********************************************************************** * Convert complex float buffer to items32 (no swap) **********************************************************************/ -static const float shorts_per_float = float(32767); - -static UHD_INLINE item32_t fc32_to_item32(fc32_t num){ - boost::uint16_t real = boost::int16_t(num.real()*shorts_per_float); - boost::uint16_t imag = boost::int16_t(num.imag()*shorts_per_float); +static UHD_INLINE item32_t fc32_to_item32(fc32_t num, float scale_factor){ + boost::uint16_t real = boost::int16_t(num.real()*scale_factor); + boost::uint16_t imag = boost::int16_t(num.imag()*scale_factor); return (item32_t(real) << 16) | (item32_t(imag) << 0); } /*********************************************************************** * Convert items32 buffer to complex float **********************************************************************/ -static const float floats_per_short = float(1.0/shorts_per_float); - -static UHD_INLINE fc32_t item32_to_fc32(item32_t item){ +static UHD_INLINE fc32_t item32_to_fc32(item32_t item, float scale_factor){ return fc32_t( - float(boost::int16_t(item >> 16)*floats_per_short), - float(boost::int16_t(item >> 0)*floats_per_short) + float(boost::int16_t(item >> 16)*scale_factor), + float(boost::int16_t(item >> 0)*scale_factor) ); } /*********************************************************************** * Convert complex double buffer to items32 (no swap) **********************************************************************/ -static const double shorts_per_double = double(32767); - -static UHD_INLINE item32_t fc64_to_item32(fc64_t num){ - boost::uint16_t real = boost::int16_t(num.real()*shorts_per_double); - boost::uint16_t imag = boost::int16_t(num.imag()*shorts_per_double); +static UHD_INLINE item32_t fc64_to_item32(fc64_t num, double scale_factor){ + boost::uint16_t real = boost::int16_t(num.real()*scale_factor); + boost::uint16_t imag = boost::int16_t(num.imag()*scale_factor); return (item32_t(real) << 16) | (item32_t(imag) << 0); } /*********************************************************************** * Convert items32 buffer to complex double **********************************************************************/ -static const double doubles_per_short = double(1.0/shorts_per_double); - -static UHD_INLINE fc64_t item32_to_fc64(item32_t item){ +static UHD_INLINE fc64_t item32_to_fc64(item32_t item, double scale_factor){ return fc64_t( - float(boost::int16_t(item >> 16)*doubles_per_short), - float(boost::int16_t(item >> 0)*doubles_per_short) + float(boost::int16_t(item >> 16)*scale_factor), + float(boost::int16_t(item >> 0)*scale_factor) ); } diff --git a/host/lib/convert/convert_with_neon.cpp b/host/lib/convert/convert_with_neon.cpp index 3d677db5b..e5f08cad9 100644 --- a/host/lib/convert/convert_with_neon.cpp +++ b/host/lib/convert/convert_with_neon.cpp @@ -26,7 +26,7 @@ DECLARE_CONVERTER(convert_fc32_1_to_item32_1_nswap, PRIORITY_CUSTOM){ size_t i; - float32x4_t Q0 = vdupq_n_f32(shorts_per_float); + float32x4_t Q0 = vdupq_n_f32(float(scale_factor)); for (i=0; i < (nsamps & ~0x03); i+=2) { float32x4_t Q1 = vld1q_f32(reinterpret_cast(&input[i])); float32x4_t Q2 = vmulq_f32(Q1, Q0); @@ -37,7 +37,7 @@ DECLARE_CONVERTER(convert_fc32_1_to_item32_1_nswap, PRIORITY_CUSTOM){ } for (; i < nsamps; i++) - output[i] = fc32_to_item32(input[i]); + output[i] = fc32_to_item32(input[i], float(scale_factor)); } DECLARE_CONVERTER(convert_item32_1_to_fc32_1_nswap, PRIORITY_CUSTOM){ @@ -46,7 +46,7 @@ DECLARE_CONVERTER(convert_item32_1_to_fc32_1_nswap, PRIORITY_CUSTOM){ size_t i; - float32x4_t Q1 = vdupq_n_f32(floats_per_short); + float32x4_t Q1 = vdupq_n_f32(float(scale_factor)); for (i=0; i < (nsamps & ~0x03); i+=2) { int16x4_t D0 = vld1_s16(reinterpret_cast(&input[i])); int16x4_t D1 = vrev32_s16(D0); @@ -57,5 +57,5 @@ DECLARE_CONVERTER(convert_item32_1_to_fc32_1_nswap, PRIORITY_CUSTOM){ } for (; i < nsamps; i++) - output[i] = item32_to_fc32(input[i]); + output[i] = item32_to_fc32(input[i], float(scale_factor)); } diff --git a/host/lib/convert/convert_with_sse2.cpp b/host/lib/convert/convert_with_sse2.cpp index 96ee9134c..52beea24a 100644 --- a/host/lib/convert/convert_with_sse2.cpp +++ b/host/lib/convert/convert_with_sse2.cpp @@ -25,7 +25,7 @@ DECLARE_CONVERTER(convert_fc32_1_to_item32_1_nswap, PRIORITY_CUSTOM){ const fc32_t *input = reinterpret_cast(inputs[0]); item32_t *output = reinterpret_cast(outputs[0]); - __m128 scalar = _mm_set_ps1(shorts_per_float); + __m128 scalar = _mm_set_ps1(float(scale_factor)); //convert blocks of samples with intrinsics size_t i = 0; for (; i < (nsamps & ~0x3); i+=4){ @@ -48,7 +48,7 @@ DECLARE_CONVERTER(convert_fc32_1_to_item32_1_nswap, PRIORITY_CUSTOM){ //convert remainder for (; i < nsamps; i++){ - output[i] = fc32_to_item32(input[i]); + output[i] = fc32_to_item32(input[i], float(scale_factor)); } } @@ -56,7 +56,7 @@ DECLARE_CONVERTER(convert_fc32_1_to_item32_1_bswap, PRIORITY_CUSTOM){ const fc32_t *input = reinterpret_cast(inputs[0]); item32_t *output = reinterpret_cast(outputs[0]); - __m128 scalar = _mm_set_ps1(shorts_per_float); + __m128 scalar = _mm_set_ps1(float(scale_factor)); //convert blocks of samples with intrinsics size_t i = 0; for (; i < (nsamps & ~0x3); i+=4){ @@ -78,7 +78,7 @@ DECLARE_CONVERTER(convert_fc32_1_to_item32_1_bswap, PRIORITY_CUSTOM){ //convert remainder for (; i < nsamps; i++){ - output[i] = uhd::byteswap(fc32_to_item32(input[i])); + output[i] = uhd::byteswap(fc32_to_item32(input[i], float(scale_factor))); } } @@ -86,7 +86,7 @@ DECLARE_CONVERTER(convert_item32_1_to_fc32_1_nswap, PRIORITY_CUSTOM){ const item32_t *input = reinterpret_cast(inputs[0]); fc32_t *output = reinterpret_cast(outputs[0]); - __m128 scalar = _mm_set_ps1(floats_per_short/(1 << 16)); + __m128 scalar = _mm_set_ps1(float(scale_factor)/(1 << 16)); __m128i zeroi = _mm_setzero_si128(); //convert blocks of samples with intrinsics @@ -111,7 +111,7 @@ DECLARE_CONVERTER(convert_item32_1_to_fc32_1_nswap, PRIORITY_CUSTOM){ //convert remainder for (; i < nsamps; i++){ - output[i] = item32_to_fc32(input[i]); + output[i] = item32_to_fc32(input[i], float(scale_factor)); } } @@ -119,7 +119,7 @@ DECLARE_CONVERTER(convert_item32_1_to_fc32_1_bswap, PRIORITY_CUSTOM){ const item32_t *input = reinterpret_cast(inputs[0]); fc32_t *output = reinterpret_cast(outputs[0]); - __m128 scalar = _mm_set_ps1(floats_per_short/(1 << 16)); + __m128 scalar = _mm_set_ps1(float(scale_factor)/(1 << 16)); __m128i zeroi = _mm_setzero_si128(); //convert blocks of samples with intrinsics @@ -143,6 +143,6 @@ DECLARE_CONVERTER(convert_item32_1_to_fc32_1_bswap, PRIORITY_CUSTOM){ //convert remainder for (; i < nsamps; i++){ - output[i] = item32_to_fc32(uhd::byteswap(input[i])); + output[i] = item32_to_fc32(uhd::byteswap(input[i]), float(scale_factor)); } } diff --git a/host/lib/convert/gen_convert_general.py b/host/lib/convert/gen_convert_general.py index f03448047..8c3138bda 100644 --- a/host/lib/convert/gen_convert_general.py +++ b/host/lib/convert/gen_convert_general.py @@ -34,7 +34,7 @@ DECLARE_CONVERTER(convert_$(cpu_type)_1_to_item32_1_$(swap), PRIORITY_GENERAL){ item32_t *output = reinterpret_cast(outputs[0]); for (size_t i = 0; i < nsamps; i++){ - output[i] = $(swap_fcn)($(cpu_type)_to_item32(input[i])); + output[i] = $(swap_fcn)($(cpu_type)_to_item32(input[i], float(scale_factor))); } } @@ -43,7 +43,7 @@ DECLARE_CONVERTER(convert_item32_1_to_$(cpu_type)_1_$(swap), PRIORITY_GENERAL){ $(cpu_type)_t *output = reinterpret_cast<$(cpu_type)_t *>(outputs[0]); for (size_t i = 0; i < nsamps; i++){ - output[i] = item32_to_$(cpu_type)($(swap_fcn)(input[i])); + output[i] = item32_to_$(cpu_type)($(swap_fcn)(input[i]), float(scale_factor)); } } """ @@ -56,7 +56,7 @@ DECLARE_CONVERTER(convert_$(cpu_type)_$(width)_to_item32_1_$(swap), PRIORITY_GEN for (size_t i = 0, j = 0; i < nsamps; i++){ #for $w in range($width) - output[j++] = $(swap_fcn)($(cpu_type)_to_item32(input$(w)[i])); + output[j++] = $(swap_fcn)($(cpu_type)_to_item32(input$(w)[i], float(scale_factor))); #end for } } @@ -69,7 +69,7 @@ DECLARE_CONVERTER(convert_item32_1_to_$(cpu_type)_$(width)_$(swap), PRIORITY_GEN for (size_t i = 0, j = 0; i < nsamps; i++){ #for $w in range($width) - output$(w)[i] = item32_to_$(cpu_type)($(swap_fcn)(input[j++])); + output$(w)[i] = item32_to_$(cpu_type)($(swap_fcn)(input[j++]), float(scale_factor)); #end for } } diff --git a/host/lib/transport/vrt_packet_handler.hpp b/host/lib/transport/vrt_packet_handler.hpp index d74b2c13c..26dbe1806 100644 --- a/host/lib/transport/vrt_packet_handler.hpp +++ b/host/lib/transport/vrt_packet_handler.hpp @@ -203,7 +203,7 @@ template UHD_INLINE T get_context_code( } //copy-convert the samples from the recv buffer - converter(state.copy_buffs[i], state.io_buffs, nsamps_to_copy_per_io_buff); + converter(state.copy_buffs[i], state.io_buffs, nsamps_to_copy_per_io_buff, 1/32767.); //update the rx copy buffer to reflect the bytes copied state.copy_buffs[i] += bytes_to_copy; @@ -354,7 +354,7 @@ template UHD_INLINE T get_context_code( otw_mem += if_packet_info.num_header_words32; //copy-convert the samples into the send buffer - converter(state.io_buffs, otw_mem, num_samps); + converter(state.io_buffs, otw_mem, num_samps, 32767.); //commit the samples to the zero-copy interface size_t num_bytes_total = (vrt_header_offset_words32+if_packet_info.num_packet_words32)*sizeof(boost::uint32_t); diff --git a/host/tests/convert_test.cpp b/host/tests/convert_test.cpp index d1c2b7625..ff37d4a0a 100644 --- a/host/tests/convert_test.cpp +++ b/host/tests/convert_test.cpp @@ -55,12 +55,12 @@ template static void loopback( //convert to intermediate type convert::get_converter_cpu_to_otw( io_type, otw_type, input0.size(), output0.size() - )(input0, output0, nsamps); + )(input0, output0, nsamps, 1/32767.); //convert back to host type convert::get_converter_otw_to_cpu( io_type, otw_type, input1.size(), output1.size() - )(input1, output1, nsamps); + )(input1, output1, nsamps, 32767.); } /*********************************************************************** @@ -207,12 +207,12 @@ BOOST_AUTO_TEST_CASE(test_convert_types_fc32_to_sc16){ //convert float to intermediate convert::get_converter_cpu_to_otw( io_type_in, otw_type, input0.size(), output0.size() - )(input0, output0, nsamps); + )(input0, output0, nsamps, 1/32767.); //convert intermediate to short convert::get_converter_otw_to_cpu( io_type_out, otw_type, input1.size(), output1.size() - )(input1, output1, nsamps); + )(input1, output1, nsamps, 32767.); //test that the inputs and outputs match for (size_t i = 0; i < nsamps; i++){ @@ -247,12 +247,12 @@ BOOST_AUTO_TEST_CASE(test_convert_types_sc16_to_fc32){ //convert short to intermediate convert::get_converter_cpu_to_otw( io_type_in, otw_type, input0.size(), output0.size() - )(input0, output0, nsamps); + )(input0, output0, nsamps, 32767.); //convert intermediate to float convert::get_converter_otw_to_cpu( io_type_out, otw_type, input1.size(), output1.size() - )(input1, output1, nsamps); + )(input1, output1, nsamps, 1/32767.); //test that the inputs and outputs match for (size_t i = 0; i < nsamps; i++){ -- cgit v1.2.3 From 29735b8e67138147ca5327b098274fa2bd2a44ca Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Mon, 23 May 2011 18:49:08 -0700 Subject: UHD: Orc implementation added and CMake magic put in. Won't link. --- host/lib/convert/CMakeLists.txt | 31 +++++++++++++++++++++++++++++++ host/lib/convert/convert_orc.orc | 11 +++++++++++ host/lib/convert/convert_with_orc.cpp | 30 ++++++++++++++++++++++++++++++ 3 files changed, 72 insertions(+) create mode 100644 host/lib/convert/convert_orc.orc create mode 100644 host/lib/convert/convert_with_orc.cpp diff --git a/host/lib/convert/CMakeLists.txt b/host/lib/convert/CMakeLists.txt index d189aa687..5b05bb72a 100644 --- a/host/lib/convert/CMakeLists.txt +++ b/host/lib/convert/CMakeLists.txt @@ -54,6 +54,37 @@ IF(HAVE_ARM_NEON_H) ) ENDIF(HAVE_ARM_NEON_H) +######################################################################## +# Look for Orc support +######################################################################## +FIND_PACKAGE(PkgConfig) +IF(PKG_CONFIG_FOUND) +PKG_CHECK_MODULES(ORC "orc-0.4") +ENDIF(PKG_CONFIG_FOUND) + +FIND_PROGRAM(ORCC_EXECUTABLE orcc) + +IF(ORC_FOUND AND ORCC_EXECUTABLE) + INCLUDE_DIRECTORIES(${ORC_INCLUDE_DIRS}) + LINK_DIRECTORIES(${ORC_LIBRARY_DIRS}) + + SET(orcc_src ${CMAKE_CURRENT_SOURCE_DIR}/convert_orc.orc) + + GET_FILENAME_COMPONENT(orc_file_name_we ${orcc_src} NAME_WE) + SET(orcc_gen ${CMAKE_CURRENT_BINARY_DIR}/${orc_file_name_we}.c) + MESSAGE(STATUS "orcc_gen is ${orcc_gen}, orcc_src is ${orcc_src}") + ADD_CUSTOM_COMMAND( + COMMAND ${ORCC_EXECUTABLE} --implementation -o ${orcc_gen} ${orcc_src} + DEPENDS ${orcc_src} OUTPUT ${orcc_gen} + ) + LIBUHD_APPEND_SOURCES(${orcc_gen}) + LIBUHD_APPEND_SOURCES( + ${CMAKE_CURRENT_SOURCE_DIR}/convert_with_orc.cpp + ) +ELSE() + MESSAGE(STATUS "Orc not found, disabling orc support...") +ENDIF(ORC_FOUND AND ORCC_EXECUTABLE) + ######################################################################## # Convert types generation ######################################################################## diff --git a/host/lib/convert/convert_orc.orc b/host/lib/convert/convert_orc.orc new file mode 100644 index 000000000..5704d4b58 --- /dev/null +++ b/host/lib/convert/convert_orc.orc @@ -0,0 +1,11 @@ +.function _convert_fc32_1_to_item32_1_nswap_orc +.source 8 src +.dest 4 dst +.floatparam 4 scalar +.temp 8 scaled +.temp 4 converted + +x2 mulf scaled, src, scalar +x2 convfw converted, scaled +swapl converted, converted +x2 swapw dst, converted diff --git a/host/lib/convert/convert_with_orc.cpp b/host/lib/convert/convert_with_orc.cpp new file mode 100644 index 000000000..dded22b9d --- /dev/null +++ b/host/lib/convert/convert_with_orc.cpp @@ -0,0 +1,30 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "convert_common.hpp" +#include +#include + +using namespace uhd::convert; + +extern "C" { +extern void _convert_fc32_1_to_item32_1_nswap_orc(void *, const void *, float, int); +} + +DECLARE_CONVERTER(convert_fc32_1_to_item32_1_nswap, PRIORITY_LIBORC){ + _convert_fc32_1_to_item32_1_nswap_orc(outputs[0], inputs[0], scale_factor, nsamps); +} -- cgit v1.2.3 From 75d0a41c3a7a2c7cd62a6c6b27e648d5617d488e Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Mon, 23 May 2011 19:06:43 -0700 Subject: UHD: Orc conversion routine works --- host/lib/convert/CMakeLists.txt | 2 ++ host/lib/convert/convert_orc.orc | 10 ++++++---- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/host/lib/convert/CMakeLists.txt b/host/lib/convert/CMakeLists.txt index 5b05bb72a..e8d933f34 100644 --- a/host/lib/convert/CMakeLists.txt +++ b/host/lib/convert/CMakeLists.txt @@ -67,6 +67,7 @@ FIND_PROGRAM(ORCC_EXECUTABLE orcc) IF(ORC_FOUND AND ORCC_EXECUTABLE) INCLUDE_DIRECTORIES(${ORC_INCLUDE_DIRS}) LINK_DIRECTORIES(${ORC_LIBRARY_DIRS}) + ENABLE_LANGUAGE(C) SET(orcc_src ${CMAKE_CURRENT_SOURCE_DIR}/convert_orc.orc) @@ -81,6 +82,7 @@ IF(ORC_FOUND AND ORCC_EXECUTABLE) LIBUHD_APPEND_SOURCES( ${CMAKE_CURRENT_SOURCE_DIR}/convert_with_orc.cpp ) + LIBUHD_APPEND_LIBS(${ORC_LIBRARIES}) ELSE() MESSAGE(STATUS "Orc not found, disabling orc support...") ENDIF(ORC_FOUND AND ORCC_EXECUTABLE) diff --git a/host/lib/convert/convert_orc.orc b/host/lib/convert/convert_orc.orc index 5704d4b58..c1c3d3c24 100644 --- a/host/lib/convert/convert_orc.orc +++ b/host/lib/convert/convert_orc.orc @@ -3,9 +3,11 @@ .dest 4 dst .floatparam 4 scalar .temp 8 scaled -.temp 4 converted +.temp 8 converted +.temp 4 short x2 mulf scaled, src, scalar -x2 convfw converted, scaled -swapl converted, converted -x2 swapw dst, converted +x2 convfl converted, scaled +x2 convlw short, converted +swapl short, short +x2 swapw dst, short -- cgit v1.2.3 From 3dca19a3e7f56c64423789ee025f16150b1a2cdb Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Mon, 23 May 2011 21:49:28 -0700 Subject: UHD: Fixed convert_test (scalars backwards), fixed Orc conversions (endianness backwards). --- host/include/uhd/convert.hpp | 2 +- host/lib/convert/convert_orc.orc | 13 +++++++++++++ host/lib/convert/convert_with_orc.cpp | 5 +++++ host/tests/convert_test.cpp | 10 +++++----- 4 files changed, 24 insertions(+), 6 deletions(-) diff --git a/host/include/uhd/convert.hpp b/host/include/uhd/convert.hpp index 99f1860ae..c30484384 100644 --- a/host/include/uhd/convert.hpp +++ b/host/include/uhd/convert.hpp @@ -40,7 +40,7 @@ namespace uhd{ namespace convert{ */ enum priority_type{ PRIORITY_GENERAL = 0, - PRIORITY_LIBORC = 1, + PRIORITY_LIBORC = 4, PRIORITY_CUSTOM = 2, PRIORITY_EMPTY = -1, }; diff --git a/host/lib/convert/convert_orc.orc b/host/lib/convert/convert_orc.orc index c1c3d3c24..83e63f22c 100644 --- a/host/lib/convert/convert_orc.orc +++ b/host/lib/convert/convert_orc.orc @@ -11,3 +11,16 @@ x2 convfl converted, scaled x2 convlw short, converted swapl short, short x2 swapw dst, short + +.function _convert_fc32_1_to_item32_1_bswap_orc +.source 8 src +.dest 4 dst +.floatparam 4 scalar +.temp 8 scaled +.temp 8 converted +.temp 4 short + +x2 mulf scaled, src, scalar +x2 convfl converted, scaled +x2 convlw short, converted +x2 swapw dst, short diff --git a/host/lib/convert/convert_with_orc.cpp b/host/lib/convert/convert_with_orc.cpp index dded22b9d..2d50351e4 100644 --- a/host/lib/convert/convert_with_orc.cpp +++ b/host/lib/convert/convert_with_orc.cpp @@ -23,8 +23,13 @@ using namespace uhd::convert; extern "C" { extern void _convert_fc32_1_to_item32_1_nswap_orc(void *, const void *, float, int); +extern void _convert_fc32_1_to_item32_1_bswap_orc(void *, const void *, float, int); } DECLARE_CONVERTER(convert_fc32_1_to_item32_1_nswap, PRIORITY_LIBORC){ _convert_fc32_1_to_item32_1_nswap_orc(outputs[0], inputs[0], scale_factor, nsamps); } + +DECLARE_CONVERTER(convert_fc32_1_to_item32_1_bswap, PRIORITY_LIBORC){ + _convert_fc32_1_to_item32_1_bswap_orc(outputs[0], inputs[0], scale_factor, nsamps); +} diff --git a/host/tests/convert_test.cpp b/host/tests/convert_test.cpp index ff37d4a0a..d828ed64a 100644 --- a/host/tests/convert_test.cpp +++ b/host/tests/convert_test.cpp @@ -31,7 +31,7 @@ typedef std::complex sc16_t; typedef std::complex fc32_t; typedef std::complex fc64_t; -#define MY_CHECK_CLOSE(a, b, f) if ((std::abs(a) > (f) and std::abs(b) > (f))) \ +#define MY_CHECK_CLOSE(a, b, f) if ((std::abs(a) > (f))) \ BOOST_CHECK_CLOSE_FRACTION(a, b, f) /*********************************************************************** @@ -55,12 +55,12 @@ template static void loopback( //convert to intermediate type convert::get_converter_cpu_to_otw( io_type, otw_type, input0.size(), output0.size() - )(input0, output0, nsamps, 1/32767.); + )(input0, output0, nsamps, 32767.); //convert back to host type convert::get_converter_otw_to_cpu( io_type, otw_type, input1.size(), output1.size() - )(input1, output1, nsamps, 32767.); + )(input1, output1, nsamps, 1/32767.); } /*********************************************************************** @@ -207,12 +207,12 @@ BOOST_AUTO_TEST_CASE(test_convert_types_fc32_to_sc16){ //convert float to intermediate convert::get_converter_cpu_to_otw( io_type_in, otw_type, input0.size(), output0.size() - )(input0, output0, nsamps, 1/32767.); + )(input0, output0, nsamps, 32767.); //convert intermediate to short convert::get_converter_otw_to_cpu( io_type_out, otw_type, input1.size(), output1.size() - )(input1, output1, nsamps, 32767.); + )(input1, output1, nsamps, 1/32767.); //test that the inputs and outputs match for (size_t i = 0; i < nsamps; i++){ -- cgit v1.2.3 From 00ee732c00fa74054117ef703afa1bf30bf53f50 Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Mon, 23 May 2011 22:36:51 -0700 Subject: UHD: added item32<->sc16 conversions in Orc --- host/include/uhd/convert.hpp | 2 +- host/lib/convert/convert_orc.orc | 39 +++++++++++++++++++++++++++++++++-- host/lib/convert/convert_with_orc.cpp | 20 ++++++++++++++++++ 3 files changed, 58 insertions(+), 3 deletions(-) diff --git a/host/include/uhd/convert.hpp b/host/include/uhd/convert.hpp index c30484384..99f1860ae 100644 --- a/host/include/uhd/convert.hpp +++ b/host/include/uhd/convert.hpp @@ -40,7 +40,7 @@ namespace uhd{ namespace convert{ */ enum priority_type{ PRIORITY_GENERAL = 0, - PRIORITY_LIBORC = 4, + PRIORITY_LIBORC = 1, PRIORITY_CUSTOM = 2, PRIORITY_EMPTY = -1, }; diff --git a/host/lib/convert/convert_orc.orc b/host/lib/convert/convert_orc.orc index 83e63f22c..78718d229 100644 --- a/host/lib/convert/convert_orc.orc +++ b/host/lib/convert/convert_orc.orc @@ -5,7 +5,6 @@ .temp 8 scaled .temp 8 converted .temp 4 short - x2 mulf scaled, src, scalar x2 convfl converted, scaled x2 convlw short, converted @@ -19,8 +18,44 @@ x2 swapw dst, short .temp 8 scaled .temp 8 converted .temp 4 short - x2 mulf scaled, src, scalar x2 convfl converted, scaled x2 convlw short, converted x2 swapw dst, short + +.function _convert_item32_1_to_fc32_1_nswap_orc +.source 4 src +.dest 8 dst +.floatparam 4 scalar +.temp 4 tmp1 +.temp 8 tmp2 +x2 swapw tmp1, src +swapl tmp1, tmp1 +x2 convswl tmp2, tmp1 +x2 convlf tmp2, tmp2 +x2 mulf dst, tmp2, scalar + +.function _convert_item32_1_to_fc32_1_bswap_orc +.source 4 src +.dest 8 dst +.floatparam 4 scalar +.temp 4 tmp1 +.temp 8 tmp2 +x2 swapw tmp1, src +x2 convswl tmp2, tmp1 +x2 convlf tmp2, tmp2 +x2 mulf dst, tmp2, scalar + +.function _convert_sc16_1_to_item32_1_nswap_orc +.source 4 src +.dest 4 dst +.floatparam 4 scalar +swapl dst, src +x2 swapw dst, dst + +.function _convert_item32_1_to_sc16_1_nswap_orc +.source 4 src +.dest 4 dst +.floatparam 4 scalar +x2 swapw dst, src +swapl dst, dst diff --git a/host/lib/convert/convert_with_orc.cpp b/host/lib/convert/convert_with_orc.cpp index 2d50351e4..6f2f47784 100644 --- a/host/lib/convert/convert_with_orc.cpp +++ b/host/lib/convert/convert_with_orc.cpp @@ -24,6 +24,10 @@ using namespace uhd::convert; extern "C" { extern void _convert_fc32_1_to_item32_1_nswap_orc(void *, const void *, float, int); extern void _convert_fc32_1_to_item32_1_bswap_orc(void *, const void *, float, int); +extern void _convert_item32_1_to_fc32_1_nswap_orc(void *, const void *, float, int); +extern void _convert_item32_1_to_fc32_1_bswap_orc(void *, const void *, float, int); +extern void _convert_sc16_1_to_item32_1_nswap_orc(void *, const void *, float, int); +extern void _convert_item32_1_to_sc16_1_nswap_orc(void *, const void *, float, int); } DECLARE_CONVERTER(convert_fc32_1_to_item32_1_nswap, PRIORITY_LIBORC){ @@ -33,3 +37,19 @@ DECLARE_CONVERTER(convert_fc32_1_to_item32_1_nswap, PRIORITY_LIBORC){ DECLARE_CONVERTER(convert_fc32_1_to_item32_1_bswap, PRIORITY_LIBORC){ _convert_fc32_1_to_item32_1_bswap_orc(outputs[0], inputs[0], scale_factor, nsamps); } + +DECLARE_CONVERTER(convert_item32_1_to_fc32_1_nswap, PRIORITY_LIBORC){ + _convert_item32_1_to_fc32_1_nswap_orc(outputs[0], inputs[0], scale_factor, nsamps); +} + +DECLARE_CONVERTER(convert_item32_1_to_fc32_1_bswap, PRIORITY_LIBORC){ + _convert_item32_1_to_fc32_1_bswap_orc(outputs[0], inputs[0], scale_factor, nsamps); +} + +DECLARE_CONVERTER(convert_sc16_1_to_item32_1_nswap, PRIORITY_LIBORC){ + _convert_sc16_1_to_item32_1_nswap_orc(outputs[0], inputs[0], scale_factor, nsamps); +} + +DECLARE_CONVERTER(convert_item32_1_to_sc16_1_nswap, PRIORITY_LIBORC){ + _convert_item32_1_to_sc16_1_nswap_orc(outputs[0], inputs[0], scale_factor, nsamps); +} -- cgit v1.2.3 From 179505fd5b5cefa11eaf7d159506c921af725855 Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Mon, 6 Jun 2011 10:27:52 -0700 Subject: use temp vars in sc16->item32 to make orcc happy --- host/lib/convert/convert_orc.orc | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/host/lib/convert/convert_orc.orc b/host/lib/convert/convert_orc.orc index 78718d229..5450bf4db 100644 --- a/host/lib/convert/convert_orc.orc +++ b/host/lib/convert/convert_orc.orc @@ -49,13 +49,15 @@ x2 mulf dst, tmp2, scalar .function _convert_sc16_1_to_item32_1_nswap_orc .source 4 src .dest 4 dst +.temp 4 tmp .floatparam 4 scalar -swapl dst, src -x2 swapw dst, dst +swapl tmp, src +x2 swapw dst, tmp .function _convert_item32_1_to_sc16_1_nswap_orc .source 4 src .dest 4 dst .floatparam 4 scalar -x2 swapw dst, src -swapl dst, dst +.temp 4 tmp +x2 swapw tmp, src +swapl dst, tmp -- cgit v1.2.3 From a1b675a4d8e902a45ff0f58e5e018536814e16bb Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Mon, 6 Jun 2011 15:53:15 -0700 Subject: Remove unnecessary include --- host/lib/convert/convert_with_orc.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/host/lib/convert/convert_with_orc.cpp b/host/lib/convert/convert_with_orc.cpp index 6f2f47784..844c2595c 100644 --- a/host/lib/convert/convert_with_orc.cpp +++ b/host/lib/convert/convert_with_orc.cpp @@ -17,7 +17,6 @@ #include "convert_common.hpp" #include -#include using namespace uhd::convert; -- cgit v1.2.3 From 85ebb705fa567e8093aa68c0ad88996d434ed2bf Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Tue, 7 Jun 2011 10:53:54 -0700 Subject: NEON detection for E100 in convert/ --- host/lib/convert/CMakeLists.txt | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/host/lib/convert/CMakeLists.txt b/host/lib/convert/CMakeLists.txt index e8d933f34..5f05b0cb8 100644 --- a/host/lib/convert/CMakeLists.txt +++ b/host/lib/convert/CMakeLists.txt @@ -26,6 +26,7 @@ MESSAGE(STATUS "") ######################################################################## IF(CMAKE_COMPILER_IS_GNUCXX) SET(EMMINTRIN_FLAGS -msse2) + SET(NEON_FLAGS "-mfloat-abi=softfp -mfpu=neon") ELSEIF(MSVC) SET(EMMINTRIN_FLAGS /arch:SSE2) ENDIF() @@ -47,13 +48,21 @@ ENDIF(HAVE_EMMINTRIN_H) ######################################################################## # Check for NEON SIMD headers ######################################################################## +SET(CMAKE_REQUIRED_FLAGS ${NEON_FLAGS}) CHECK_INCLUDE_FILE_CXX(arm_neon.h HAVE_ARM_NEON_H) -IF(HAVE_ARM_NEON_H) +UNSET(CMAKE_REQUIRED_FLAGS) +if(HAVE_ARM_NEON_H) + MESSAGE(STATUS "Enabling NEON support") + SET_SOURCE_FILES_PROPERTIES( + ${CMAKE_CURRENT_SOURCE_DIR}/convert_with_neon.cpp + PROPERTIES COMPILE_FLAGS "${NEON_FLAGS}" + ) LIBUHD_APPEND_SOURCES( ${CMAKE_CURRENT_SOURCE_DIR}/convert_with_neon.cpp ) -ENDIF(HAVE_ARM_NEON_H) - +else(HAVE_ARM_NEON_H) + MESSAGE(STATUS "Disabling NEON support") +endif(HAVE_ARM_NEON_H) ######################################################################## # Look for Orc support ######################################################################## @@ -73,7 +82,7 @@ IF(ORC_FOUND AND ORCC_EXECUTABLE) GET_FILENAME_COMPONENT(orc_file_name_we ${orcc_src} NAME_WE) SET(orcc_gen ${CMAKE_CURRENT_BINARY_DIR}/${orc_file_name_we}.c) - MESSAGE(STATUS "orcc_gen is ${orcc_gen}, orcc_src is ${orcc_src}") + MESSAGE(STATUS "Orc found, enabling Orc support") ADD_CUSTOM_COMMAND( COMMAND ${ORCC_EXECUTABLE} --implementation -o ${orcc_gen} ${orcc_src} DEPENDS ${orcc_src} OUTPUT ${orcc_gen} -- cgit v1.2.3 From c65a1f8e40960d5016788de2cc4775c9e603293a Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 12 Jun 2011 19:46:06 -0700 Subject: uhd: supper packet handler support squashed --- host/lib/transport/gen_vrt_if_packet.py | 44 +- host/lib/transport/super_recv_packet_handler.hpp | 637 ++++++++++++++++++++ host/lib/transport/super_send_packet_handler.hpp | 287 +++++++++ host/tests/CMakeLists.txt | 2 + host/tests/sph_recv_test.cpp | 715 +++++++++++++++++++++++ host/tests/sph_send_test.cpp | 204 +++++++ 6 files changed, 1876 insertions(+), 13 deletions(-) create mode 100644 host/lib/transport/super_recv_packet_handler.hpp create mode 100644 host/lib/transport/super_send_packet_handler.hpp create mode 100644 host/tests/sph_recv_test.cpp create mode 100644 host/tests/sph_send_test.cpp diff --git a/host/lib/transport/gen_vrt_if_packet.py b/host/lib/transport/gen_vrt_if_packet.py index 7440def6a..5f048d8c7 100755 --- a/host/lib/transport/gen_vrt_if_packet.py +++ b/host/lib/transport/gen_vrt_if_packet.py @@ -62,6 +62,8 @@ static pred_table_type get_pred_unpack_table(void){ if(vrt_hdr_word & $hex(0x3 << 22)) table[i] |= $hex($tsi_p); if(vrt_hdr_word & $hex(0x3 << 20)) table[i] |= $hex($tsf_p); if(vrt_hdr_word & $hex(0x1 << 26)) table[i] |= $hex($tlr_p); + if(vrt_hdr_word & $hex(0x1 << 24)) table[i] |= $hex($eob_p); + if(vrt_hdr_word & $hex(0x1 << 25)) table[i] |= $hex($sob_p); } return table; } @@ -84,9 +86,11 @@ void vrt::if_hdr_pack_$(suffix)( if (if_packet_info.has_tsi) pred |= $hex($tsi_p); if (if_packet_info.has_tsf) pred |= $hex($tsf_p); if (if_packet_info.has_tlr) pred |= $hex($tlr_p); + if (if_packet_info.eob) pred |= $hex($eob_p); + if (if_packet_info.sob) pred |= $hex($sob_p); switch(pred){ - #for $pred in range(2**5) + #for $pred in range(2**7) case $pred: #set $num_header_words = 1 #set $flags = 0 @@ -126,6 +130,13 @@ void vrt::if_hdr_pack_$(suffix)( #else #set $num_trailer_words = 0; #end if + ########## Burst Flags ########## + #if $pred & $eob_p + #set $flags |= (0x1 << 24); + #end if + #if $pred & $sob_p + #set $flags |= (0x1 << 25); + #end if ########## Variables ########## if_packet_info.num_header_words32 = $num_header_words; if_packet_info.num_packet_words32 = $($num_header_words + $num_trailer_words) + if_packet_info.num_payload_words32; @@ -134,10 +145,6 @@ void vrt::if_hdr_pack_$(suffix)( #end for } - //set the burst flags - if (if_packet_info.sob) vrt_hdr_flags |= $hex(0x1 << 25); - if (if_packet_info.eob) vrt_hdr_flags |= $hex(0x1 << 24); - //fill in complete header word packet_buff[0] = $(XE_MACRO)(boost::uint32_t(0 | (if_packet_info.packet_type << 29) @@ -162,13 +169,11 @@ void vrt::if_hdr_unpack_$(suffix)( //extract fields from the header if_packet_info.packet_type = if_packet_info_t::packet_type_t(vrt_hdr_word >> 29); if_packet_info.packet_count = (vrt_hdr_word >> 16) & 0xf; - //if_packet_info.sob = bool(vrt_hdr_word & $hex(0x1 << 25)); //not implemented - //if_packet_info.eob = bool(vrt_hdr_word & $hex(0x1 << 24)); //not implemented const pred_type pred = pred_unpack_table[pred_table_index(vrt_hdr_word)]; switch(pred){ - #for $pred in range(2**5) + #for $pred in range(2**7) case $pred: #set $has_time_spec = False #set $num_header_words = 1 @@ -215,6 +220,17 @@ void vrt::if_hdr_unpack_$(suffix)( if_packet_info.has_tlr = false; #set $num_trailer_words = 0; #end if + ########## Burst Flags ########## + #if $pred & $eob_p + if_packet_info.eob = true; + #else + if_packet_info.eob = false; + #end if + #if $pred & $sob_p + if_packet_info.sob = true; + #else + if_packet_info.sob = false; + #end if ########## Variables ########## //another failure case if (packet_words32 < $($num_header_words + $num_trailer_words)) @@ -243,9 +259,11 @@ if __name__ == '__main__': open(sys.argv[1], 'w').write(parse_tmpl( TMPL_TEXT, file=__file__, - sid_p = 0b00001, - cid_p = 0b00010, - tsi_p = 0b00100, - tsf_p = 0b01000, - tlr_p = 0b10000, + sid_p = 0b0000001, + cid_p = 0b0000010, + tsi_p = 0b0000100, + tsf_p = 0b0001000, + tlr_p = 0b0010000, + sob_p = 0b0100000, + eob_p = 0b1000000, )) diff --git a/host/lib/transport/super_recv_packet_handler.hpp b/host/lib/transport/super_recv_packet_handler.hpp new file mode 100644 index 000000000..78d8dfce8 --- /dev/null +++ b/host/lib/transport/super_recv_packet_handler.hpp @@ -0,0 +1,637 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_LIBUHD_TRANSPORT_SUPER_RECV_PACKET_HANDLER_HPP +#define INCLUDED_LIBUHD_TRANSPORT_SUPER_RECV_PACKET_HANDLER_HPP + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +namespace uhd{ namespace transport{ namespace sph{ + +UHD_INLINE boost::uint32_t get_context_code( + const boost::uint32_t *vrt_hdr, const vrt::if_packet_info_t &if_packet_info +){ + //extract the context word (we dont know the endianness so mirror the bytes) + boost::uint32_t word0 = vrt_hdr[if_packet_info.num_header_words32] | + uhd::byteswap(vrt_hdr[if_packet_info.num_header_words32]); + return word0 & 0xff; +} + +typedef boost::function handle_overflow_type; +static inline void handle_overflow_nop(void){} + +/*********************************************************************** + * Alignment indexes class: + * - Access an integer set with very quick operations. + **********************************************************************/ +class alignment_indexes{ +public: + typedef boost::uint16_t index_type; //16 buffers + + alignment_indexes(void): + _indexes(0), + _sizes(256, 0), + _fronts(256, ~0) + { + //fill the O(1) look up tables for a single byte + for (size_t i = 0; i < 256; i++){ + for (size_t j = 0; j < 8; j++){ + if (i & (1 << j)){ + _sizes[i]++; + _fronts[i] = j; + } + } + } + } + + UHD_INLINE void reset(size_t len){_indexes = (1 << len) - 1;} + + UHD_INLINE size_t front(void){ + //check one byte per iteration + for (size_t i = 0; i < sizeof(_indexes)*8; i+=8){ + size_t front = _fronts[(_indexes >> i) & 0xff]; + if (front != size_t(~0)) return front + i; + } + if (empty()) throw uhd::runtime_error("cannot call front() when empty"); + UHD_THROW_INVALID_CODE_PATH(); + } + + UHD_INLINE void remove(size_t index){_indexes &= ~(1 << index);} + + UHD_INLINE bool empty(void){return _indexes == 0;} + + UHD_INLINE size_t size(void){ + size_t size = 0; + //check one byte per iteration + for (size_t i = 0; i < sizeof(_indexes)*8; i+=8){ + size += _sizes[(_indexes >> i) & 0xff]; + } + return size; + } + +private: + index_type _indexes; + std::vector _sizes; + std::vector _fronts; +}; + +/*********************************************************************** + * Super receive packet handler + * + * A receive packet handler represents a group of channels. + * The channel group shares a common sample rate. + * All channels are received in unison in recv(). + **********************************************************************/ +class recv_packet_handler{ +public: + typedef boost::function get_buff_type; + typedef void(*vrt_unpacker_type)(const boost::uint32_t *, vrt::if_packet_info_t &); + //typedef boost::function vrt_unpacker_type; + + /*! + * Make a new packet handler for receive + * \param size the number of transport channels + */ + recv_packet_handler(const size_t size = 1): + _queue_error_for_next_call(false), + _buffers_infos_index(0) + { + UHD_ASSERT_THROW(size <= sizeof(alignment_indexes::index_type)*8); + this->resize(size); + set_alignment_failure_threshold(1000); + } + + //! Resize the number of transport channels + void resize(const size_t size){ + if (this->size() == size) return; + _props.resize(size); + _buffers_infos.resize(4, buffers_info_type(size)); + } + + //! Get the channel width of this handler + size_t size(void) const{ + return _props.size(); + } + + //! Setup the vrt unpacker function and offset + void set_vrt_unpacker(const vrt_unpacker_type &vrt_unpacker, const size_t header_offset_words32 = 0){ + _vrt_unpacker = vrt_unpacker; + _header_offset_words32 = header_offset_words32; + } + + /*! + * Set the threshold for alignment failure. + * How many packets throw out before giving up? + * \param threshold number of packets per channel + */ + void set_alignment_failure_threshold(const size_t threshold){ + _alignment_faulure_threshold = threshold*this->size(); + } + + //! Set the rate of ticks per second + void set_tick_rate(const double rate){ + _tick_rate = rate; + } + + //! Set the rate of samples per second + void set_samp_rate(const double rate){ + _samp_rate = rate; + } + + /*! + * Set the function to get a managed buffer. + * \param xport_chan which transport channel + * \param get_buff the getter function + */ + void set_xport_chan_get_buff(const size_t xport_chan, const get_buff_type &get_buff){ + _props.at(xport_chan).get_buff = get_buff; + } + + /*! + * Setup the conversion functions (homogeneous across transports). + * Here, we load a table of converters for all possible io types. + * This makes the converter look-up an O(1) operation. + * \param otw_type the channel data type + * \param width the streams per channel (usually 1) + */ + void set_converter(const uhd::otw_type_t &otw_type, const size_t width = 1){ + _io_buffs.resize(width); + _converters.resize(128); + for (size_t io_type = 0; io_type < _converters.size(); io_type++){ + try{ + _converters[io_type] = uhd::convert::get_converter_otw_to_cpu( + io_type_t::tid_t(io_type), otw_type, 1, width + ); + }catch(const uhd::value_error &e){} //we expect this, not all io_types valid... + } + _bytes_per_item = otw_type.get_sample_size(); + } + + //! Set the transport channel's overflow handler + void set_overflow_handler(const size_t xport_chan, const handle_overflow_type &handle_overflow){ + _props.at(xport_chan).handle_overflow = handle_overflow; + } + + //! Get a scoped lock object for this instance + boost::mutex::scoped_lock get_scoped_lock(void){ + return boost::mutex::scoped_lock(_mutex); + } + + /******************************************************************* + * Receive: + * The entry point for the fast-path receive calls. + * Dispatch into combinations of single packet receive calls. + ******************************************************************/ + UHD_INLINE size_t recv( + const uhd::device::recv_buffs_type &buffs, + const size_t nsamps_per_buff, + uhd::rx_metadata_t &metadata, + const uhd::io_type_t &io_type, + uhd::device::recv_mode_t recv_mode, + double timeout + ){ + boost::mutex::scoped_lock lock(_mutex); + + //handle metadata queued from a previous receive + if (_queue_error_for_next_call){ + _queue_error_for_next_call = false; + metadata = _queue_metadata; + //We want to allow a full buffer recv to be cut short by a timeout, + //but do not want to generate an inline timeout message packet. + if (_queue_metadata.error_code != rx_metadata_t::ERROR_CODE_TIMEOUT) return 0; + } + + switch(recv_mode){ + + //////////////////////////////////////////////////////////////// + case uhd::device::RECV_MODE_ONE_PACKET:{ + //////////////////////////////////////////////////////////////// + return recv_one_packet(buffs, nsamps_per_buff, metadata, io_type, timeout); + } + + //////////////////////////////////////////////////////////////// + case uhd::device::RECV_MODE_FULL_BUFF:{ + //////////////////////////////////////////////////////////////// + size_t accum_num_samps = recv_one_packet( + buffs, nsamps_per_buff, metadata, io_type, timeout + ); + + //first recv had an error code set, return immediately + if (metadata.error_code != rx_metadata_t::ERROR_CODE_NONE) return accum_num_samps; + + //loop until buffer is filled or error code + while(accum_num_samps < nsamps_per_buff){ + size_t num_samps = recv_one_packet( + buffs, nsamps_per_buff - accum_num_samps, _queue_metadata, + io_type, timeout, accum_num_samps*io_type.size + ); + + //metadata had an error code set, store for next call and return + if (_queue_metadata.error_code != rx_metadata_t::ERROR_CODE_NONE){ + _queue_error_for_next_call = true; + break; + } + accum_num_samps += num_samps; + } + return accum_num_samps; + } + + default: throw uhd::value_error("unknown recv mode"); + }//switch(recv_mode) + } + +private: + + boost::mutex _mutex; + vrt_unpacker_type _vrt_unpacker; + size_t _header_offset_words32; + double _tick_rate, _samp_rate; + bool _queue_error_for_next_call; + size_t _alignment_faulure_threshold; + rx_metadata_t _queue_metadata; + struct xport_chan_props_type{ + xport_chan_props_type(void): + packet_count(0), + handle_overflow(&handle_overflow_nop) + {} + get_buff_type get_buff; + size_t packet_count; + handle_overflow_type handle_overflow; + }; + std::vector _props; + std::vector _io_buffs; //used in conversion + size_t _bytes_per_item; //used in conversion + std::vector _converters; //used in conversion + + //! information stored for a received buffer + struct per_buffer_info_type{ + managed_recv_buffer::sptr buff; + const boost::uint32_t *vrt_hdr; + vrt::if_packet_info_t ifpi; + time_spec_t time; + const char *copy_buff; + }; + + //!information stored for a set of aligned buffers + struct buffers_info_type : std::vector { + buffers_info_type(const size_t size): + std::vector(size), + alignment_time_valid(false), + data_bytes_to_copy(0), + fragment_offset_in_samps(0) + { + indexes_to_do.reset(size); + } + alignment_indexes indexes_to_do; //used in alignment logic + time_spec_t alignment_time; //used in alignment logic + bool alignment_time_valid; //used in alignment logic + size_t data_bytes_to_copy; //keeps track of state + size_t fragment_offset_in_samps; //keeps track of state + rx_metadata_t metadata; //packet description + }; + + //! a circular queue of buffer infos + std::vector _buffers_infos; + size_t _buffers_infos_index; + buffers_info_type &get_curr_buffer_info(void){return _buffers_infos[_buffers_infos_index];} + buffers_info_type &get_prev_buffer_info(void){return _buffers_infos[(_buffers_infos_index + 3)%4];} + buffers_info_type &get_next_buffer_info(void){return _buffers_infos[(_buffers_infos_index + 1)%4];} + void increment_buffer_info(void){_buffers_infos_index = (_buffers_infos_index + 1)%4;} + + //! possible return options for the packet receiver + enum packet_type{ + PACKET_IF_DATA, + PACKET_TIMESTAMP_ERROR, + PACKET_INLINE_MESSAGE, + PACKET_TIMEOUT_ERROR, + PACKET_SEQUENCE_ERROR + }; + + /******************************************************************* + * Get and process a single packet from the transport: + * Receive a single packet at the given index. + * Extract all the relevant info and store. + * Check the info to determine the return code. + ******************************************************************/ + UHD_INLINE packet_type get_and_process_single_packet( + const size_t index, + buffers_info_type &prev_buffer_info, + buffers_info_type &curr_buffer_info, + double timeout + ){ + //get a single packet from the transport layer + managed_recv_buffer::sptr &buff = curr_buffer_info[index].buff; + buff = _props[index].get_buff(timeout); + if (buff.get() == NULL) return PACKET_TIMEOUT_ERROR; + + //bounds check before extract + size_t num_packet_words32 = buff->size()/sizeof(boost::uint32_t); + if (num_packet_words32 <= _header_offset_words32){ + throw std::runtime_error("recv buffer smaller than vrt packet offset"); + } + + //extract packet info + per_buffer_info_type &info = curr_buffer_info[index]; + info.ifpi.num_packet_words32 = num_packet_words32 - _header_offset_words32; + info.vrt_hdr = buff->cast() + _header_offset_words32; + _vrt_unpacker(info.vrt_hdr, info.ifpi); + info.time = time_spec_t(time_t(info.ifpi.tsi), size_t(info.ifpi.tsf), _tick_rate); //assumes has_tsi and has_tsf are true + info.copy_buff = reinterpret_cast(info.vrt_hdr + info.ifpi.num_header_words32); + + //store the packet count for the next iteration + #ifndef SRPH_DONT_CHECK_SEQUENCE + const size_t expected_packet_count = _props[index].packet_count; + _props[index].packet_count = (info.ifpi.packet_count + 1)%16; + #endif + + //-------------------------------------------------------------- + //-- Determine return conditions: + //-- The order of these checks is HOLY. + //-------------------------------------------------------------- + + //1) check for out of order timestamps + if (info.ifpi.has_tsi and info.ifpi.has_tsf and prev_buffer_info[index].time > info.time){ + return PACKET_TIMESTAMP_ERROR; + } + + //2) check for inline IF message packets + if (info.ifpi.packet_type != vrt::if_packet_info_t::PACKET_TYPE_DATA){ + return PACKET_INLINE_MESSAGE; + } + + //3) check for sequence errors + #ifndef SRPH_DONT_CHECK_SEQUENCE + if (expected_packet_count != info.ifpi.packet_count){ + return PACKET_SEQUENCE_ERROR; + } + #endif + + //4) otherwise the packet is normal! + return PACKET_IF_DATA; + } + + /******************************************************************* + * Alignment check: + * Check the received packet for alignment and mark accordingly. + ******************************************************************/ + UHD_INLINE void alignment_check( + const size_t index, buffers_info_type &info + ){ + //if alignment time was not valid or if the sequence id is newer: + // use this index's time as the alignment time + // reset the indexes list and remove this index + if (not info.alignment_time_valid or info[index].time > info.alignment_time){ + info.alignment_time_valid = true; + info.alignment_time = info[index].time; + info.indexes_to_do.reset(this->size()); + info.indexes_to_do.remove(index); + info.data_bytes_to_copy = info[index].ifpi.num_payload_words32*sizeof(boost::uint32_t); + } + + //if the sequence id matches: + // remove this index from the list and continue + else if (info[index].time == info.alignment_time){ + info.indexes_to_do.remove(index); + } + + //if the sequence id is older: + // continue with the same index to try again + //else if (info[index].time < info.alignment_time)... + } + + /******************************************************************* + * Get aligned buffers: + * Iterate through each index and try to accumulate aligned buffers. + * Handle all of the edge cases like inline messages and errors. + * The logic will throw out older packets until it finds a match. + ******************************************************************/ + UHD_INLINE void get_aligned_buffs(double timeout){ + + increment_buffer_info(); //increment to next buffer + buffers_info_type &prev_info = get_prev_buffer_info(); + buffers_info_type &curr_info = get_curr_buffer_info(); + buffers_info_type &next_info = get_next_buffer_info(); + + //Loop until we get a message of an aligned set of buffers: + // - Receive a single packet and extract its info. + // - Handle the packet type yielded by the receive. + // - Check the timestamps for alignment conditions. + size_t iterations = 0; + while (not curr_info.indexes_to_do.empty()){ + + //get the index to process for this iteration + const size_t index = curr_info.indexes_to_do.front(); + packet_type packet; + + //receive a single packet from the transport + try{ + packet = get_and_process_single_packet( + index, prev_info, curr_info, timeout + ); + } + + //handle the case when the get packet throws + catch(const std::exception &e){ + UHD_MSG(error) << boost::format( + "The receive packet handler caught an exception.\n%s" + ) % e.what() << std::endl; + std::swap(curr_info, next_info); //save progress from curr -> next + curr_info.metadata.has_time_spec = false; + curr_info.metadata.time_spec = time_spec_t(0.0); + curr_info.metadata.more_fragments = false; + curr_info.metadata.fragment_offset = 0; + curr_info.metadata.start_of_burst = false; + curr_info.metadata.end_of_burst = false; + curr_info.metadata.error_code = rx_metadata_t::ERROR_CODE_BAD_PACKET; + return; + } + + switch(packet){ + case PACKET_IF_DATA: + alignment_check(index, curr_info); + break; + + case PACKET_TIMESTAMP_ERROR: + //If the user changes the device time while streaming or without flushing, + //we can receive a packet that comes before the previous packet in time. + //This could cause the alignment logic to discard future received packets. + //Therefore, when this occurs, we reset the info to restart from scratch. + if (curr_info.alignment_time_valid and curr_info.alignment_time != curr_info[index].time){ + curr_info.alignment_time_valid = false; + } + alignment_check(index, curr_info); + break; + + case PACKET_INLINE_MESSAGE: + std::swap(curr_info, next_info); //save progress from curr -> next + curr_info.metadata.has_time_spec = next_info[index].ifpi.has_tsi and next_info[index].ifpi.has_tsf; + curr_info.metadata.time_spec = next_info[index].time; + curr_info.metadata.more_fragments = false; + curr_info.metadata.fragment_offset = 0; + curr_info.metadata.start_of_burst = false; + curr_info.metadata.end_of_burst = false; + curr_info.metadata.error_code = rx_metadata_t::error_code_t(get_context_code(next_info[index].vrt_hdr, next_info[index].ifpi)); + if (curr_info.metadata.error_code == rx_metadata_t::ERROR_CODE_OVERFLOW) _props[index].handle_overflow(); + UHD_MSG(fastpath) << "O"; + return; + + case PACKET_TIMEOUT_ERROR: + std::swap(curr_info, next_info); //save progress from curr -> next + curr_info.metadata.has_time_spec = false; + curr_info.metadata.time_spec = time_spec_t(0.0); + curr_info.metadata.more_fragments = false; + curr_info.metadata.fragment_offset = 0; + curr_info.metadata.start_of_burst = false; + curr_info.metadata.end_of_burst = false; + curr_info.metadata.error_code = rx_metadata_t::ERROR_CODE_TIMEOUT; + return; + + case PACKET_SEQUENCE_ERROR: + alignment_check(index, curr_info); + std::swap(curr_info, next_info); //save progress from curr -> next + curr_info.metadata.has_time_spec = prev_info.metadata.has_time_spec; + curr_info.metadata.time_spec = prev_info.metadata.time_spec + time_spec_t( + 0.0, prev_info[index].ifpi.num_payload_words32*sizeof(boost::uint32_t)/_bytes_per_item, _samp_rate); + curr_info.metadata.more_fragments = false; + curr_info.metadata.fragment_offset = 0; + curr_info.metadata.start_of_burst = false; + curr_info.metadata.end_of_burst = false; + curr_info.metadata.error_code = rx_metadata_t::ERROR_CODE_OVERFLOW; + UHD_MSG(fastpath) << "O"; + return; + + } + + //too many iterations: detect alignment failure + if (iterations++ > _alignment_faulure_threshold){ + UHD_MSG(error) << boost::format( + "The receive packet handler failed to time-align packets.\n" + "%u received packets were processed by the handler.\n" + "However, a timestamp match could not be determined.\n" + ) % iterations << std::endl; + std::swap(curr_info, next_info); //save progress from curr -> next + curr_info.metadata.has_time_spec = false; + curr_info.metadata.time_spec = time_spec_t(0.0); + curr_info.metadata.more_fragments = false; + curr_info.metadata.fragment_offset = 0; + curr_info.metadata.start_of_burst = false; + curr_info.metadata.end_of_burst = false; + curr_info.metadata.error_code = rx_metadata_t::ERROR_CODE_ALIGNMENT; + return; + } + + } + + //set the metadata from the buffer information at index zero + curr_info.metadata.has_time_spec = curr_info[0].ifpi.has_tsi and curr_info[0].ifpi.has_tsf; + curr_info.metadata.time_spec = curr_info[0].time; + curr_info.metadata.more_fragments = false; + curr_info.metadata.fragment_offset = 0; + /* TODO SOB on RX not supported in hardware + static const int tlr_sob_flags = (1 << 21) | (1 << 9); //enable and indicator bits + curr_info.metadata.start_of_burst = curr_info[0].ifpi.has_tlr and (int(curr_info[0].ifpi.tlr & tlr_sob_flags) != 0); + */ + curr_info.metadata.start_of_burst = false; + static const int tlr_eob_flags = (1 << 20) | (1 << 8); //enable and indicator bits + curr_info.metadata.end_of_burst = curr_info[0].ifpi.has_tlr and (int(curr_info[0].ifpi.tlr & tlr_eob_flags) != 0); + curr_info.metadata.error_code = rx_metadata_t::ERROR_CODE_NONE; + + } + + /******************************************************************* + * Receive a single packet: + * Handles fragmentation, messages, errors, and copy-conversion. + * When no fragments are available, call the get aligned buffers. + * Then copy-convert available data into the user's IO buffers. + ******************************************************************/ + UHD_INLINE size_t recv_one_packet( + const uhd::device::recv_buffs_type &buffs, + const size_t nsamps_per_buff, + uhd::rx_metadata_t &metadata, + const uhd::io_type_t &io_type, + double timeout, + const size_t buffer_offset_bytes = 0 + ){ + //get the next buffer if the current one has expired + if (get_curr_buffer_info().data_bytes_to_copy == 0){ + + //reset current buffer info members for reuse + get_curr_buffer_info().fragment_offset_in_samps = 0; + get_curr_buffer_info().alignment_time_valid = false; + get_curr_buffer_info().indexes_to_do.reset(this->size()); + + //perform receive with alignment logic + get_aligned_buffs(timeout); + } + + buffers_info_type &info = get_curr_buffer_info(); + metadata = info.metadata; + + //interpolate the time spec (useful when this is a fragment) + metadata.time_spec += time_spec_t(0, info.fragment_offset_in_samps, _samp_rate); + + //extract the number of samples available to copy + const size_t nsamps_available = info.data_bytes_to_copy/_bytes_per_item; + const size_t nsamps_to_copy = std::min(nsamps_per_buff*_io_buffs.size(), nsamps_available); + const size_t bytes_to_copy = nsamps_to_copy*_bytes_per_item; + const size_t nsamps_to_copy_per_io_buff = nsamps_to_copy/_io_buffs.size(); + + size_t buff_index = 0; + BOOST_FOREACH(per_buffer_info_type &buff_info, info){ + + //fill a vector with pointers to the io buffers + BOOST_FOREACH(void *&io_buff, _io_buffs){ + io_buff = reinterpret_cast(buffs[buff_index++]) + buffer_offset_bytes; + } + + //copy-convert the samples from the recv buffer + _converters[io_type.tid](buff_info.copy_buff, _io_buffs, nsamps_to_copy_per_io_buff, 1/32767.); + + //update the rx copy buffer to reflect the bytes copied + buff_info.copy_buff += bytes_to_copy; + } + //update the copy buffer's availability + info.data_bytes_to_copy -= bytes_to_copy; + + //setup the fragment flags and offset + metadata.more_fragments = info.data_bytes_to_copy != 0; + metadata.fragment_offset = info.fragment_offset_in_samps; + info.fragment_offset_in_samps += nsamps_to_copy; //set for next call + + return nsamps_to_copy_per_io_buff; + } +}; + +}}} //namespace + +#endif /* INCLUDED_LIBUHD_TRANSPORT_SUPER_RECV_PACKET_HANDLER_HPP */ diff --git a/host/lib/transport/super_send_packet_handler.hpp b/host/lib/transport/super_send_packet_handler.hpp new file mode 100644 index 000000000..99d445180 --- /dev/null +++ b/host/lib/transport/super_send_packet_handler.hpp @@ -0,0 +1,287 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_LIBUHD_TRANSPORT_SUPER_SEND_PACKET_HANDLER_HPP +#define INCLUDED_LIBUHD_TRANSPORT_SUPER_SEND_PACKET_HANDLER_HPP + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +namespace uhd{ namespace transport{ namespace sph{ + +/*********************************************************************** + * Super send packet handler + * + * A send packet handler represents a group of channels. + * The channel group shares a common sample rate. + * All channels are sent in unison in send(). + **********************************************************************/ +class send_packet_handler{ +public: + typedef boost::function get_buff_type; + typedef void(*vrt_packer_type)(boost::uint32_t *, vrt::if_packet_info_t &); + //typedef boost::function vrt_packer_type; + + /*! + * Make a new packet handler for send + * \param size the number of transport channels + */ + send_packet_handler(const size_t size = 1): + _next_packet_seq(0) + { + this->resize(size); + } + + //! Resize the number of transport channels + void resize(const size_t size){ + if (this->size() == size) return; + _props.resize(size); + static const boost::uint64_t zero = 0; + _zero_buffs.resize(size, &zero); + } + + //! Get the channel width of this handler + size_t size(void) const{ + return _props.size(); + } + + //! Setup the vrt packer function and offset + void set_vrt_packer(const vrt_packer_type &vrt_packer, const size_t header_offset_words32 = 0){ + _vrt_packer = vrt_packer; + _header_offset_words32 = header_offset_words32; + } + + //! Set the rate of ticks per second + void set_tick_rate(const double rate){ + _tick_rate = rate; + } + + //! Set the rate of samples per second + void set_samp_rate(const double rate){ + _samp_rate = rate; + } + + /*! + * Set the function to get a managed buffer. + * \param xport_chan which transport channel + * \param get_buff the getter function + */ + void set_xport_chan_get_buff(const size_t xport_chan, const get_buff_type &get_buff){ + _props.at(xport_chan).get_buff = get_buff; + } + + /*! + * Setup the conversion functions (homogeneous across transports). + * Here, we load a table of converters for all possible io types. + * This makes the converter look-up an O(1) operation. + * \param otw_type the channel data type + * \param width the streams per channel (usually 1) + */ + void set_converter(const uhd::otw_type_t &otw_type, const size_t width = 1){ + _io_buffs.resize(width); + _converters.resize(128); + for (size_t io_type = 0; io_type < _converters.size(); io_type++){ + try{ + _converters[io_type] = uhd::convert::get_converter_cpu_to_otw( + io_type_t::tid_t(io_type), otw_type, 1, width + ); + }catch(const uhd::value_error &e){} //we expect this, not all io_types valid... + } + _bytes_per_item = otw_type.get_sample_size(); + } + + /*! + * Set the maximum number of samples per host packet. + * Ex: A USRP1 in dual channel mode would be half. + * \param num_samps the maximum samples in a packet + */ + void set_max_samples_per_packet(const size_t num_samps){ + _max_samples_per_packet = num_samps; + } + + //! Get a scoped lock object for this instance + boost::mutex::scoped_lock get_scoped_lock(void){ + return boost::mutex::scoped_lock(_mutex); + } + + /******************************************************************* + * Send: + * The entry point for the fast-path send calls. + * Dispatch into combinations of single packet send calls. + ******************************************************************/ + UHD_INLINE size_t send( + const uhd::device::send_buffs_type &buffs, + const size_t nsamps_per_buff, + const uhd::tx_metadata_t &metadata, + const uhd::io_type_t &io_type, + uhd::device::send_mode_t send_mode, + double timeout + ){ + boost::mutex::scoped_lock lock(_mutex); + + //translate the metadata to vrt if packet info + vrt::if_packet_info_t if_packet_info; + if_packet_info.has_sid = false; + if_packet_info.has_cid = false; + if_packet_info.has_tlr = false; + if_packet_info.has_tsi = metadata.has_time_spec; + if_packet_info.has_tsf = metadata.has_time_spec; + if_packet_info.tsi = boost::uint32_t(metadata.time_spec.get_full_secs()); + if_packet_info.tsf = boost::uint64_t(metadata.time_spec.get_tick_count(_tick_rate)); + if_packet_info.sob = metadata.start_of_burst; + if_packet_info.eob = metadata.end_of_burst; + + if (nsamps_per_buff <= _max_samples_per_packet) send_mode = uhd::device::SEND_MODE_ONE_PACKET; + switch(send_mode){ + + //////////////////////////////////////////////////////////////// + case uhd::device::SEND_MODE_ONE_PACKET:{ + //////////////////////////////////////////////////////////////// + + //TODO remove this code when sample counts of zero are supported by hardware + if (nsamps_per_buff == 0) return send_one_packet( + _zero_buffs, 1, if_packet_info, io_type, timeout + ); + + return send_one_packet( + buffs, + std::min(nsamps_per_buff, _max_samples_per_packet), + if_packet_info, io_type, timeout + ); + } + + //////////////////////////////////////////////////////////////// + case uhd::device::SEND_MODE_FULL_BUFF:{ + //////////////////////////////////////////////////////////////// + size_t total_num_samps_sent = 0; + + //false until final fragment + if_packet_info.eob = false; + + const size_t num_fragments = (nsamps_per_buff-1)/_max_samples_per_packet; + const size_t final_length = ((nsamps_per_buff-1)%_max_samples_per_packet)+1; + + //loop through the following fragment indexes + for (size_t i = 0; i < num_fragments; i++){ + + //send a fragment with the helper function + const size_t num_samps_sent = send_one_packet( + buffs, _max_samples_per_packet, + if_packet_info, io_type, timeout, + total_num_samps_sent*io_type.size + ); + total_num_samps_sent += num_samps_sent; + if (num_samps_sent == 0) return total_num_samps_sent; + + //setup metadata for the next fragment + const time_spec_t time_spec = metadata.time_spec + time_spec_t(0, total_num_samps_sent, _samp_rate); + if_packet_info.tsi = boost::uint32_t(time_spec.get_full_secs()); + if_packet_info.tsf = boost::uint64_t(time_spec.get_tick_count(_tick_rate)); + if_packet_info.sob = false; + + } + + //send the final fragment with the helper function + if_packet_info.eob = metadata.end_of_burst; + return total_num_samps_sent + send_one_packet( + buffs, final_length, + if_packet_info, io_type, timeout, + total_num_samps_sent*io_type.size + ); + } + + default: throw uhd::value_error("unknown send mode"); + }//switch(send_mode) + } + +private: + + boost::mutex _mutex; + vrt_packer_type _vrt_packer; + size_t _header_offset_words32; + double _tick_rate, _samp_rate; + struct xport_chan_props_type{ + get_buff_type get_buff; + }; + std::vector _props; + std::vector _io_buffs; //used in conversion + size_t _bytes_per_item; //used in conversion + std::vector _converters; //used in conversion + size_t _max_samples_per_packet; + std::vector _zero_buffs; + size_t _next_packet_seq; + + /******************************************************************* + * Send a single packet: + ******************************************************************/ + size_t send_one_packet( + const uhd::device::send_buffs_type &buffs, + const size_t nsamps_per_buff, + vrt::if_packet_info_t &if_packet_info, + const uhd::io_type_t &io_type, + double timeout, + const size_t buffer_offset_bytes = 0 + ){ + //load the rest of the if_packet_info in here + if_packet_info.num_payload_words32 = (nsamps_per_buff*_io_buffs.size()*_bytes_per_item)/sizeof(boost::uint32_t); + if_packet_info.packet_count = _next_packet_seq; + + size_t buff_index = 0; + BOOST_FOREACH(xport_chan_props_type &props, _props){ + managed_send_buffer::sptr buff = props.get_buff(timeout); + if (buff.get() == NULL) return 0; //timeout + + //fill a vector with pointers to the io buffers + BOOST_FOREACH(const void *&io_buff, _io_buffs){ + io_buff = reinterpret_cast(buffs[buff_index++]) + buffer_offset_bytes; + } + boost::uint32_t *otw_mem = buff->cast() + _header_offset_words32; + + //pack metadata into a vrt header + _vrt_packer(otw_mem, if_packet_info); + otw_mem += if_packet_info.num_header_words32; + + //copy-convert the samples into the send buffer + _converters[io_type.tid](_io_buffs, otw_mem, nsamps_per_buff, 32767.); + + //commit the samples to the zero-copy interface + size_t num_bytes_total = (_header_offset_words32+if_packet_info.num_packet_words32)*sizeof(boost::uint32_t); + buff->commit(num_bytes_total); + + } + _next_packet_seq++; //increment sequence after commits + return nsamps_per_buff; + } +}; + +}}} //namespace + +#endif /* INCLUDED_LIBUHD_TRANSPORT_SUPER_SEND_PACKET_HANDLER_HPP */ diff --git a/host/tests/CMakeLists.txt b/host/tests/CMakeLists.txt index b38afccf0..b7bcfb7d5 100644 --- a/host/tests/CMakeLists.txt +++ b/host/tests/CMakeLists.txt @@ -28,6 +28,8 @@ SET(test_sources gain_group_test.cpp msg_test.cpp ranges_test.cpp + sph_recv_test.cpp + sph_send_test.cpp subdev_spec_test.cpp time_spec_test.cpp tune_helper_test.cpp diff --git a/host/tests/sph_recv_test.cpp b/host/tests/sph_recv_test.cpp new file mode 100644 index 000000000..6bb5d1175 --- /dev/null +++ b/host/tests/sph_recv_test.cpp @@ -0,0 +1,715 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include "../lib/transport/super_recv_packet_handler.hpp" +#include +#include +#include +#include +#include + +#define BOOST_CHECK_TS_CLOSE(a, b) \ + BOOST_CHECK_CLOSE((a).get_real_secs(), (b).get_real_secs(), 0.001) + +/*********************************************************************** + * A dummy managed receive buffer for testing + **********************************************************************/ +class dummy_mrb : public uhd::transport::managed_recv_buffer{ +public: + void release(void){ + //NOP + } + + sptr get_new(boost::shared_array mem, size_t len){ + _mem = mem; + _len = len; + return make_managed_buffer(this); + } + +private: + const void *get_buff(void) const{return _mem.get();} + size_t get_size(void) const{return _len;} + + boost::shared_array _mem; + size_t _len; +}; + +/*********************************************************************** + * A dummy transport class to fill with fake data + **********************************************************************/ +class dummy_recv_xport_class{ +public: + dummy_recv_xport_class(const uhd::otw_type_t &otw_type){ + _otw_type = otw_type; + } + + void push_back_packet( + uhd::transport::vrt::if_packet_info_t &ifpi, + const boost::uint32_t optional_msg_word = 0 + ){ + const size_t max_pkt_len = (ifpi.num_payload_words32 + uhd::transport::vrt::max_if_hdr_words32 + 1/*tlr*/)*sizeof(boost::uint32_t); + _mems.push_back(boost::shared_array(new char[max_pkt_len])); + if (_otw_type.byteorder == uhd::otw_type_t::BO_BIG_ENDIAN){ + uhd::transport::vrt::if_hdr_pack_be(reinterpret_cast(_mems.back().get()), ifpi); + } + if (_otw_type.byteorder == uhd::otw_type_t::BO_LITTLE_ENDIAN){ + uhd::transport::vrt::if_hdr_pack_le(reinterpret_cast(_mems.back().get()), ifpi); + } + (reinterpret_cast(_mems.back().get()) + ifpi.num_header_words32)[0] = optional_msg_word | uhd::byteswap(optional_msg_word); + _lens.push_back(ifpi.num_packet_words32*sizeof(boost::uint32_t)); + } + + uhd::transport::managed_recv_buffer::sptr get_recv_buff(double){ + if (_mems.empty()) return uhd::transport::managed_recv_buffer::sptr(); //timeout + _mrbs.push_back(dummy_mrb()); + uhd::transport::managed_recv_buffer::sptr mrb = _mrbs.back().get_new(_mems.front(), _lens.front()); + _mems.pop_front(); + _lens.pop_front(); + return mrb; + } + +private: + std::list > _mems; + std::list _lens; + std::list _mrbs; //list means no-realloc + uhd::otw_type_t _otw_type; +}; + +//////////////////////////////////////////////////////////////////////// +BOOST_AUTO_TEST_CASE(test_sph_recv_one_channel_normal){ +//////////////////////////////////////////////////////////////////////// + uhd::otw_type_t otw_type; + otw_type.width = 16; + otw_type.shift = 0; + otw_type.byteorder = uhd::otw_type_t::BO_BIG_ENDIAN; + + dummy_recv_xport_class dummy_recv_xport(otw_type); + uhd::transport::vrt::if_packet_info_t ifpi; + ifpi.packet_type = uhd::transport::vrt::if_packet_info_t::PACKET_TYPE_DATA; + ifpi.num_payload_words32 = 0; + ifpi.packet_count = 0; + ifpi.sob = true; + ifpi.eob = false; + ifpi.has_sid = false; + ifpi.has_cid = false; + ifpi.has_tsi = true; + ifpi.has_tsf = true; + ifpi.tsi = 0; + ifpi.tsf = 0; + ifpi.has_tlr = false; + + static const double TICK_RATE = 100e6; + static const double SAMP_RATE = 10e6; + static const size_t NUM_PKTS_TO_TEST = 30; + + //generate a bunch of packets + for (size_t i = 0; i < NUM_PKTS_TO_TEST; i++){ + ifpi.num_payload_words32 = 10 + i%10; + dummy_recv_xport.push_back_packet(ifpi); + ifpi.packet_count++; + ifpi.tsf += ifpi.num_payload_words32*size_t(TICK_RATE/SAMP_RATE); + } + + //create the super receive packet handler + uhd::transport::sph::recv_packet_handler handler(1); + handler.set_vrt_unpacker(&uhd::transport::vrt::if_hdr_unpack_be); + handler.set_tick_rate(TICK_RATE); + handler.set_samp_rate(SAMP_RATE); + handler.set_xport_chan_get_buff(0, boost::bind(&dummy_recv_xport_class::get_recv_buff, &dummy_recv_xport, _1)); + handler.set_converter(otw_type); + + //check the received packets + size_t num_accum_samps = 0; + std::vector > buff(20); + uhd::rx_metadata_t metadata; + for (size_t i = 0; i < NUM_PKTS_TO_TEST; i++){ + std::cout << "data check " << i << std::endl; + size_t num_samps_ret = handler.recv( + &buff.front(), buff.size(), metadata, + uhd::io_type_t::COMPLEX_FLOAT32, + uhd::device::RECV_MODE_ONE_PACKET, 1.0 + ); + BOOST_CHECK_EQUAL(metadata.error_code, uhd::rx_metadata_t::ERROR_CODE_NONE); + BOOST_CHECK(not metadata.more_fragments); + BOOST_CHECK(metadata.has_time_spec); + BOOST_CHECK_TS_CLOSE(metadata.time_spec, uhd::time_spec_t(0, num_accum_samps, SAMP_RATE)); + BOOST_CHECK_EQUAL(num_samps_ret, 10 + i%10); + num_accum_samps += num_samps_ret; + } + + //subsequent receives should be a timeout + for (size_t i = 0; i < 3; i++){ + std::cout << "timeout check " << i << std::endl; + handler.recv( + &buff.front(), buff.size(), metadata, + uhd::io_type_t::COMPLEX_FLOAT32, + uhd::device::RECV_MODE_ONE_PACKET, 1.0 + ); + BOOST_CHECK_EQUAL(metadata.error_code, uhd::rx_metadata_t::ERROR_CODE_TIMEOUT); + } +} + +//////////////////////////////////////////////////////////////////////// +BOOST_AUTO_TEST_CASE(test_sph_recv_one_channel_sequence_error){ +//////////////////////////////////////////////////////////////////////// + uhd::otw_type_t otw_type; + otw_type.width = 16; + otw_type.shift = 0; + otw_type.byteorder = uhd::otw_type_t::BO_BIG_ENDIAN; + + dummy_recv_xport_class dummy_recv_xport(otw_type); + uhd::transport::vrt::if_packet_info_t ifpi; + ifpi.packet_type = uhd::transport::vrt::if_packet_info_t::PACKET_TYPE_DATA; + ifpi.num_payload_words32 = 0; + ifpi.packet_count = 0; + ifpi.sob = true; + ifpi.eob = false; + ifpi.has_sid = false; + ifpi.has_cid = false; + ifpi.has_tsi = true; + ifpi.has_tsf = true; + ifpi.tsi = 0; + ifpi.tsf = 0; + ifpi.has_tlr = false; + + static const double TICK_RATE = 100e6; + static const double SAMP_RATE = 10e6; + static const size_t NUM_PKTS_TO_TEST = 30; + + //generate a bunch of packets + for (size_t i = 0; i < NUM_PKTS_TO_TEST; i++){ + ifpi.num_payload_words32 = 10 + i%10; + if (i != NUM_PKTS_TO_TEST/2){ //simulate a lost packet + dummy_recv_xport.push_back_packet(ifpi); + } + ifpi.packet_count++; + ifpi.tsf += ifpi.num_payload_words32*size_t(TICK_RATE/SAMP_RATE); + } + + //create the super receive packet handler + uhd::transport::sph::recv_packet_handler handler(1); + handler.set_vrt_unpacker(&uhd::transport::vrt::if_hdr_unpack_be); + handler.set_tick_rate(TICK_RATE); + handler.set_samp_rate(SAMP_RATE); + handler.set_xport_chan_get_buff(0, boost::bind(&dummy_recv_xport_class::get_recv_buff, &dummy_recv_xport, _1)); + handler.set_converter(otw_type); + + //check the received packets + size_t num_accum_samps = 0; + std::vector > buff(20); + uhd::rx_metadata_t metadata; + for (size_t i = 0; i < NUM_PKTS_TO_TEST; i++){ + std::cout << "data check " << i << std::endl; + size_t num_samps_ret = handler.recv( + &buff.front(), buff.size(), metadata, + uhd::io_type_t::COMPLEX_FLOAT32, + uhd::device::RECV_MODE_ONE_PACKET, 1.0 + ); + if (i == NUM_PKTS_TO_TEST/2){ + //must get the soft overflow here + BOOST_REQUIRE(metadata.error_code == uhd::rx_metadata_t::ERROR_CODE_OVERFLOW); + BOOST_CHECK_TS_CLOSE(metadata.time_spec, uhd::time_spec_t(0, num_accum_samps, SAMP_RATE)); + num_accum_samps += 10 + i%10; + } + else{ + BOOST_CHECK_EQUAL(metadata.error_code, uhd::rx_metadata_t::ERROR_CODE_NONE); + BOOST_CHECK(not metadata.more_fragments); + BOOST_CHECK(metadata.has_time_spec); + BOOST_CHECK_TS_CLOSE(metadata.time_spec, uhd::time_spec_t(0, num_accum_samps, SAMP_RATE)); + BOOST_CHECK_EQUAL(num_samps_ret, 10 + i%10); + num_accum_samps += num_samps_ret; + } + } + + //subsequent receives should be a timeout + for (size_t i = 0; i < 3; i++){ + std::cout << "timeout check " << i << std::endl; + handler.recv( + &buff.front(), buff.size(), metadata, + uhd::io_type_t::COMPLEX_FLOAT32, + uhd::device::RECV_MODE_ONE_PACKET, 1.0 + ); + BOOST_CHECK_EQUAL(metadata.error_code, uhd::rx_metadata_t::ERROR_CODE_TIMEOUT); + } +} + +//////////////////////////////////////////////////////////////////////// +BOOST_AUTO_TEST_CASE(test_sph_recv_one_channel_inline_message){ +//////////////////////////////////////////////////////////////////////// + uhd::otw_type_t otw_type; + otw_type.width = 16; + otw_type.shift = 0; + otw_type.byteorder = uhd::otw_type_t::BO_BIG_ENDIAN; + + dummy_recv_xport_class dummy_recv_xport(otw_type); + uhd::transport::vrt::if_packet_info_t ifpi; + ifpi.packet_type = uhd::transport::vrt::if_packet_info_t::PACKET_TYPE_DATA; + ifpi.num_payload_words32 = 0; + ifpi.packet_count = 0; + ifpi.sob = true; + ifpi.eob = false; + ifpi.has_sid = false; + ifpi.has_cid = false; + ifpi.has_tsi = true; + ifpi.has_tsf = true; + ifpi.tsi = 0; + ifpi.tsf = 0; + ifpi.has_tlr = false; + + static const double TICK_RATE = 100e6; + static const double SAMP_RATE = 10e6; + static const size_t NUM_PKTS_TO_TEST = 30; + + //generate a bunch of packets + for (size_t i = 0; i < NUM_PKTS_TO_TEST; i++){ + ifpi.num_payload_words32 = 10 + i%10; + dummy_recv_xport.push_back_packet(ifpi); + ifpi.packet_count++; + ifpi.tsf += ifpi.num_payload_words32*size_t(TICK_RATE/SAMP_RATE); + + //simulate overflow + if (i == NUM_PKTS_TO_TEST/2){ + ifpi.packet_type = uhd::transport::vrt::if_packet_info_t::PACKET_TYPE_EXTENSION; + ifpi.num_payload_words32 = 1; + dummy_recv_xport.push_back_packet(ifpi, uhd::rx_metadata_t::ERROR_CODE_OVERFLOW); + ifpi.packet_count++; + ifpi.packet_type = uhd::transport::vrt::if_packet_info_t::PACKET_TYPE_DATA; + } + } + + //create the super receive packet handler + uhd::transport::sph::recv_packet_handler handler(1); + handler.set_vrt_unpacker(&uhd::transport::vrt::if_hdr_unpack_be); + handler.set_tick_rate(TICK_RATE); + handler.set_samp_rate(SAMP_RATE); + handler.set_xport_chan_get_buff(0, boost::bind(&dummy_recv_xport_class::get_recv_buff, &dummy_recv_xport, _1)); + handler.set_converter(otw_type); + + //check the received packets + size_t num_accum_samps = 0; + std::vector > buff(20); + uhd::rx_metadata_t metadata; + for (size_t i = 0; i < NUM_PKTS_TO_TEST; i++){ + std::cout << "data check " << i << std::endl; + size_t num_samps_ret = handler.recv( + &buff.front(), buff.size(), metadata, + uhd::io_type_t::COMPLEX_FLOAT32, + uhd::device::RECV_MODE_ONE_PACKET, 1.0 + ); + BOOST_CHECK_EQUAL(metadata.error_code, uhd::rx_metadata_t::ERROR_CODE_NONE); + BOOST_CHECK(not metadata.more_fragments); + BOOST_CHECK(metadata.has_time_spec); + BOOST_CHECK_TS_CLOSE(metadata.time_spec, uhd::time_spec_t(0, num_accum_samps, SAMP_RATE)); + BOOST_CHECK_EQUAL(num_samps_ret, 10 + i%10); + num_accum_samps += num_samps_ret; + if (i == NUM_PKTS_TO_TEST/2){ + handler.recv( + &buff.front(), buff.size(), metadata, + uhd::io_type_t::COMPLEX_FLOAT32, + uhd::device::RECV_MODE_ONE_PACKET, 1.0 + ); + std::cout << "metadata.error_code " << metadata.error_code << std::endl; + BOOST_REQUIRE(metadata.error_code == uhd::rx_metadata_t::ERROR_CODE_OVERFLOW); + BOOST_CHECK_TS_CLOSE(metadata.time_spec, uhd::time_spec_t(0, num_accum_samps, SAMP_RATE)); + } + } + + //subsequent receives should be a timeout + for (size_t i = 0; i < 3; i++){ + std::cout << "timeout check " << i << std::endl; + handler.recv( + &buff.front(), buff.size(), metadata, + uhd::io_type_t::COMPLEX_FLOAT32, + uhd::device::RECV_MODE_ONE_PACKET, 1.0 + ); + BOOST_CHECK_EQUAL(metadata.error_code, uhd::rx_metadata_t::ERROR_CODE_TIMEOUT); + } +} + +//////////////////////////////////////////////////////////////////////// +BOOST_AUTO_TEST_CASE(test_sph_recv_multi_channel_normal){ +//////////////////////////////////////////////////////////////////////// + uhd::otw_type_t otw_type; + otw_type.width = 16; + otw_type.shift = 0; + otw_type.byteorder = uhd::otw_type_t::BO_BIG_ENDIAN; + + uhd::transport::vrt::if_packet_info_t ifpi; + ifpi.packet_type = uhd::transport::vrt::if_packet_info_t::PACKET_TYPE_DATA; + ifpi.num_payload_words32 = 0; + ifpi.packet_count = 0; + ifpi.sob = true; + ifpi.eob = false; + ifpi.has_sid = false; + ifpi.has_cid = false; + ifpi.has_tsi = true; + ifpi.has_tsf = true; + ifpi.tsi = 0; + ifpi.tsf = 0; + ifpi.has_tlr = false; + + static const double TICK_RATE = 100e6; + static const double SAMP_RATE = 10e6; + static const size_t NUM_PKTS_TO_TEST = 30; + static const size_t NUM_SAMPS_PER_BUFF = 20; + static const size_t NCHANNELS = 4; + + std::vector dummy_recv_xports(NCHANNELS, dummy_recv_xport_class(otw_type)); + + //generate a bunch of packets + for (size_t i = 0; i < NUM_PKTS_TO_TEST; i++){ + ifpi.num_payload_words32 = 10 + i%10; + for (size_t ch = 0; ch < NCHANNELS; ch++){ + dummy_recv_xports[ch].push_back_packet(ifpi); + } + ifpi.packet_count++; + ifpi.tsf += ifpi.num_payload_words32*size_t(TICK_RATE/SAMP_RATE); + } + + //create the super receive packet handler + uhd::transport::sph::recv_packet_handler handler(NCHANNELS); + handler.set_vrt_unpacker(&uhd::transport::vrt::if_hdr_unpack_be); + handler.set_tick_rate(TICK_RATE); + handler.set_samp_rate(SAMP_RATE); + for (size_t ch = 0; ch < NCHANNELS; ch++){ + handler.set_xport_chan_get_buff(ch, boost::bind(&dummy_recv_xport_class::get_recv_buff, &dummy_recv_xports[ch], _1)); + } + handler.set_converter(otw_type); + + //check the received packets + size_t num_accum_samps = 0; + std::vector > mem(NUM_SAMPS_PER_BUFF*NCHANNELS); + std::vector *> buffs(NCHANNELS); + for (size_t ch = 0; ch < NCHANNELS; ch++){ + buffs[ch] = &mem[ch*NUM_SAMPS_PER_BUFF]; + } + uhd::rx_metadata_t metadata; + for (size_t i = 0; i < NUM_PKTS_TO_TEST; i++){ + std::cout << "data check " << i << std::endl; + size_t num_samps_ret = handler.recv( + buffs, NUM_SAMPS_PER_BUFF, metadata, + uhd::io_type_t::COMPLEX_FLOAT32, + uhd::device::RECV_MODE_ONE_PACKET, 1.0 + ); + BOOST_CHECK_EQUAL(metadata.error_code, uhd::rx_metadata_t::ERROR_CODE_NONE); + BOOST_CHECK(not metadata.more_fragments); + BOOST_CHECK(metadata.has_time_spec); + BOOST_CHECK_TS_CLOSE(metadata.time_spec, uhd::time_spec_t(0, num_accum_samps, SAMP_RATE)); + BOOST_CHECK_EQUAL(num_samps_ret, 10 + i%10); + num_accum_samps += num_samps_ret; + } + + //subsequent receives should be a timeout + for (size_t i = 0; i < 3; i++){ + std::cout << "timeout check " << i << std::endl; + handler.recv( + buffs, NUM_SAMPS_PER_BUFF, metadata, + uhd::io_type_t::COMPLEX_FLOAT32, + uhd::device::RECV_MODE_ONE_PACKET, 1.0 + ); + BOOST_CHECK_EQUAL(metadata.error_code, uhd::rx_metadata_t::ERROR_CODE_TIMEOUT); + } + +} + +//////////////////////////////////////////////////////////////////////// +BOOST_AUTO_TEST_CASE(test_sph_recv_multi_channel_sequence_error){ +//////////////////////////////////////////////////////////////////////// + uhd::otw_type_t otw_type; + otw_type.width = 16; + otw_type.shift = 0; + otw_type.byteorder = uhd::otw_type_t::BO_BIG_ENDIAN; + + uhd::transport::vrt::if_packet_info_t ifpi; + ifpi.packet_type = uhd::transport::vrt::if_packet_info_t::PACKET_TYPE_DATA; + ifpi.num_payload_words32 = 0; + ifpi.packet_count = 0; + ifpi.sob = true; + ifpi.eob = false; + ifpi.has_sid = false; + ifpi.has_cid = false; + ifpi.has_tsi = true; + ifpi.has_tsf = true; + ifpi.tsi = 0; + ifpi.tsf = 0; + ifpi.has_tlr = false; + + static const double TICK_RATE = 100e6; + static const double SAMP_RATE = 10e6; + static const size_t NUM_PKTS_TO_TEST = 30; + static const size_t NUM_SAMPS_PER_BUFF = 20; + static const size_t NCHANNELS = 4; + + std::vector dummy_recv_xports(NCHANNELS, dummy_recv_xport_class(otw_type)); + + //generate a bunch of packets + for (size_t i = 0; i < NUM_PKTS_TO_TEST; i++){ + ifpi.num_payload_words32 = 10 + i%10; + for (size_t ch = 0; ch < NCHANNELS; ch++){ + if (i == NUM_PKTS_TO_TEST/2 and ch == 2){ + continue; //simulates a lost packet + } + dummy_recv_xports[ch].push_back_packet(ifpi); + } + ifpi.packet_count++; + ifpi.tsf += ifpi.num_payload_words32*size_t(TICK_RATE/SAMP_RATE); + } + + //create the super receive packet handler + uhd::transport::sph::recv_packet_handler handler(NCHANNELS); + handler.set_vrt_unpacker(&uhd::transport::vrt::if_hdr_unpack_be); + handler.set_tick_rate(TICK_RATE); + handler.set_samp_rate(SAMP_RATE); + for (size_t ch = 0; ch < NCHANNELS; ch++){ + handler.set_xport_chan_get_buff(ch, boost::bind(&dummy_recv_xport_class::get_recv_buff, &dummy_recv_xports[ch], _1)); + } + handler.set_converter(otw_type); + + //check the received packets + size_t num_accum_samps = 0; + std::vector > mem(NUM_SAMPS_PER_BUFF*NCHANNELS); + std::vector *> buffs(NCHANNELS); + for (size_t ch = 0; ch < NCHANNELS; ch++){ + buffs[ch] = &mem[ch*NUM_SAMPS_PER_BUFF]; + } + uhd::rx_metadata_t metadata; + for (size_t i = 0; i < NUM_PKTS_TO_TEST; i++){ + std::cout << "data check " << i << std::endl; + size_t num_samps_ret = handler.recv( + buffs, NUM_SAMPS_PER_BUFF, metadata, + uhd::io_type_t::COMPLEX_FLOAT32, + uhd::device::RECV_MODE_ONE_PACKET, 1.0 + ); + if (i == NUM_PKTS_TO_TEST/2){ + //must get the soft overflow here + BOOST_REQUIRE(metadata.error_code == uhd::rx_metadata_t::ERROR_CODE_OVERFLOW); + BOOST_CHECK_TS_CLOSE(metadata.time_spec, uhd::time_spec_t(0, num_accum_samps, SAMP_RATE)); + num_accum_samps += 10 + i%10; + } + else{ + BOOST_CHECK_EQUAL(metadata.error_code, uhd::rx_metadata_t::ERROR_CODE_NONE); + BOOST_CHECK(not metadata.more_fragments); + BOOST_CHECK(metadata.has_time_spec); + BOOST_CHECK_TS_CLOSE(metadata.time_spec, uhd::time_spec_t(0, num_accum_samps, SAMP_RATE)); + BOOST_CHECK_EQUAL(num_samps_ret, 10 + i%10); + num_accum_samps += num_samps_ret; + } + } + + //subsequent receives should be a timeout + for (size_t i = 0; i < 3; i++){ + std::cout << "timeout check " << i << std::endl; + handler.recv( + buffs, NUM_SAMPS_PER_BUFF, metadata, + uhd::io_type_t::COMPLEX_FLOAT32, + uhd::device::RECV_MODE_ONE_PACKET, 1.0 + ); + BOOST_CHECK_EQUAL(metadata.error_code, uhd::rx_metadata_t::ERROR_CODE_TIMEOUT); + } +} + +//////////////////////////////////////////////////////////////////////// +BOOST_AUTO_TEST_CASE(test_sph_recv_multi_channel_time_error){ +//////////////////////////////////////////////////////////////////////// + uhd::otw_type_t otw_type; + otw_type.width = 16; + otw_type.shift = 0; + otw_type.byteorder = uhd::otw_type_t::BO_BIG_ENDIAN; + + uhd::transport::vrt::if_packet_info_t ifpi; + ifpi.packet_type = uhd::transport::vrt::if_packet_info_t::PACKET_TYPE_DATA; + ifpi.num_payload_words32 = 0; + ifpi.packet_count = 0; + ifpi.sob = true; + ifpi.eob = false; + ifpi.has_sid = false; + ifpi.has_cid = false; + ifpi.has_tsi = true; + ifpi.has_tsf = true; + ifpi.tsi = 0; + ifpi.tsf = 0; + ifpi.has_tlr = false; + + static const double TICK_RATE = 100e6; + static const double SAMP_RATE = 10e6; + static const size_t NUM_PKTS_TO_TEST = 30; + static const size_t NUM_SAMPS_PER_BUFF = 20; + static const size_t NCHANNELS = 4; + + std::vector dummy_recv_xports(NCHANNELS, dummy_recv_xport_class(otw_type)); + + //generate a bunch of packets + for (size_t i = 0; i < NUM_PKTS_TO_TEST; i++){ + ifpi.num_payload_words32 = 10 + i%10; + for (size_t ch = 0; ch < NCHANNELS; ch++){ + dummy_recv_xports[ch].push_back_packet(ifpi); + } + ifpi.packet_count++; + ifpi.tsf += ifpi.num_payload_words32*size_t(TICK_RATE/SAMP_RATE); + if (i == NUM_PKTS_TO_TEST/2){ + ifpi.tsf = 0; //simulate the user changing the time + } + } + + //create the super receive packet handler + uhd::transport::sph::recv_packet_handler handler(NCHANNELS); + handler.set_vrt_unpacker(&uhd::transport::vrt::if_hdr_unpack_be); + handler.set_tick_rate(TICK_RATE); + handler.set_samp_rate(SAMP_RATE); + for (size_t ch = 0; ch < NCHANNELS; ch++){ + handler.set_xport_chan_get_buff(ch, boost::bind(&dummy_recv_xport_class::get_recv_buff, &dummy_recv_xports[ch], _1)); + } + handler.set_converter(otw_type); + + //check the received packets + size_t num_accum_samps = 0; + std::vector > mem(NUM_SAMPS_PER_BUFF*NCHANNELS); + std::vector *> buffs(NCHANNELS); + for (size_t ch = 0; ch < NCHANNELS; ch++){ + buffs[ch] = &mem[ch*NUM_SAMPS_PER_BUFF]; + } + uhd::rx_metadata_t metadata; + for (size_t i = 0; i < NUM_PKTS_TO_TEST; i++){ + std::cout << "data check " << i << std::endl; + size_t num_samps_ret = handler.recv( + buffs, NUM_SAMPS_PER_BUFF, metadata, + uhd::io_type_t::COMPLEX_FLOAT32, + uhd::device::RECV_MODE_ONE_PACKET, 1.0 + ); + BOOST_CHECK_EQUAL(metadata.error_code, uhd::rx_metadata_t::ERROR_CODE_NONE); + BOOST_CHECK(not metadata.more_fragments); + BOOST_CHECK(metadata.has_time_spec); + BOOST_CHECK_TS_CLOSE(metadata.time_spec, uhd::time_spec_t(0, num_accum_samps, SAMP_RATE)); + BOOST_CHECK_EQUAL(num_samps_ret, 10 + i%10); + num_accum_samps += num_samps_ret; + if (i == NUM_PKTS_TO_TEST/2){ + num_accum_samps = 0; //simulate the user changing the time + } + } + + //subsequent receives should be a timeout + for (size_t i = 0; i < 3; i++){ + std::cout << "timeout check " << i << std::endl; + handler.recv( + buffs, NUM_SAMPS_PER_BUFF, metadata, + uhd::io_type_t::COMPLEX_FLOAT32, + uhd::device::RECV_MODE_ONE_PACKET, 1.0 + ); + BOOST_CHECK_EQUAL(metadata.error_code, uhd::rx_metadata_t::ERROR_CODE_TIMEOUT); + } +} + +//////////////////////////////////////////////////////////////////////// +BOOST_AUTO_TEST_CASE(test_sph_recv_multi_channel_fragment){ +//////////////////////////////////////////////////////////////////////// + uhd::otw_type_t otw_type; + otw_type.width = 16; + otw_type.shift = 0; + otw_type.byteorder = uhd::otw_type_t::BO_BIG_ENDIAN; + + uhd::transport::vrt::if_packet_info_t ifpi; + ifpi.packet_type = uhd::transport::vrt::if_packet_info_t::PACKET_TYPE_DATA; + ifpi.num_payload_words32 = 0; + ifpi.packet_count = 0; + ifpi.sob = true; + ifpi.eob = false; + ifpi.has_sid = false; + ifpi.has_cid = false; + ifpi.has_tsi = true; + ifpi.has_tsf = true; + ifpi.tsi = 0; + ifpi.tsf = 0; + ifpi.has_tlr = false; + + static const double TICK_RATE = 100e6; + static const double SAMP_RATE = 10e6; + static const size_t NUM_PKTS_TO_TEST = 30; + static const size_t NUM_SAMPS_PER_BUFF = 10; + static const size_t NCHANNELS = 4; + + std::vector dummy_recv_xports(NCHANNELS, dummy_recv_xport_class(otw_type)); + + //generate a bunch of packets + for (size_t i = 0; i < NUM_PKTS_TO_TEST; i++){ + ifpi.num_payload_words32 = 10 + i%10; + for (size_t ch = 0; ch < NCHANNELS; ch++){ + dummy_recv_xports[ch].push_back_packet(ifpi); + } + ifpi.packet_count++; + ifpi.tsf += ifpi.num_payload_words32*size_t(TICK_RATE/SAMP_RATE); + } + + //create the super receive packet handler + uhd::transport::sph::recv_packet_handler handler(NCHANNELS); + handler.set_vrt_unpacker(&uhd::transport::vrt::if_hdr_unpack_be); + handler.set_tick_rate(TICK_RATE); + handler.set_samp_rate(SAMP_RATE); + for (size_t ch = 0; ch < NCHANNELS; ch++){ + handler.set_xport_chan_get_buff(ch, boost::bind(&dummy_recv_xport_class::get_recv_buff, &dummy_recv_xports[ch], _1)); + } + handler.set_converter(otw_type); + + //check the received packets + size_t num_accum_samps = 0; + std::vector > mem(NUM_SAMPS_PER_BUFF*NCHANNELS); + std::vector *> buffs(NCHANNELS); + for (size_t ch = 0; ch < NCHANNELS; ch++){ + buffs[ch] = &mem[ch*NUM_SAMPS_PER_BUFF]; + } + uhd::rx_metadata_t metadata; + for (size_t i = 0; i < NUM_PKTS_TO_TEST; i++){ + std::cout << "data check " << i << std::endl; + size_t num_samps_ret = handler.recv( + buffs, NUM_SAMPS_PER_BUFF, metadata, + uhd::io_type_t::COMPLEX_FLOAT32, + uhd::device::RECV_MODE_ONE_PACKET, 1.0 + ); + BOOST_CHECK_EQUAL(metadata.error_code, uhd::rx_metadata_t::ERROR_CODE_NONE); + BOOST_CHECK(metadata.has_time_spec); + BOOST_CHECK_TS_CLOSE(metadata.time_spec, uhd::time_spec_t(0, num_accum_samps, SAMP_RATE)); + BOOST_CHECK_EQUAL(num_samps_ret, 10); + num_accum_samps += num_samps_ret; + + if (not metadata.more_fragments) continue; + + num_samps_ret = handler.recv( + buffs, NUM_SAMPS_PER_BUFF, metadata, + uhd::io_type_t::COMPLEX_FLOAT32, + uhd::device::RECV_MODE_ONE_PACKET, 1.0 + ); + BOOST_CHECK_EQUAL(metadata.error_code, uhd::rx_metadata_t::ERROR_CODE_NONE); + BOOST_CHECK(not metadata.more_fragments); + BOOST_CHECK_EQUAL(metadata.fragment_offset, 10); + BOOST_CHECK(metadata.has_time_spec); + BOOST_CHECK_TS_CLOSE(metadata.time_spec, uhd::time_spec_t(0, num_accum_samps, SAMP_RATE)); + BOOST_CHECK_EQUAL(num_samps_ret, i%10); + num_accum_samps += num_samps_ret; + } + + //subsequent receives should be a timeout + for (size_t i = 0; i < 3; i++){ + std::cout << "timeout check " << i << std::endl; + handler.recv( + buffs, NUM_SAMPS_PER_BUFF, metadata, + uhd::io_type_t::COMPLEX_FLOAT32, + uhd::device::RECV_MODE_ONE_PACKET, 1.0 + ); + BOOST_CHECK_EQUAL(metadata.error_code, uhd::rx_metadata_t::ERROR_CODE_TIMEOUT); + } + +} diff --git a/host/tests/sph_send_test.cpp b/host/tests/sph_send_test.cpp new file mode 100644 index 000000000..ed2f54371 --- /dev/null +++ b/host/tests/sph_send_test.cpp @@ -0,0 +1,204 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include "../lib/transport/super_send_packet_handler.hpp" +#include +#include +#include +#include +#include + +#define BOOST_CHECK_TS_CLOSE(a, b) \ + BOOST_CHECK_CLOSE((a).get_real_secs(), (b).get_real_secs(), 0.001) + +/*********************************************************************** + * A dummy managed send buffer for testing + **********************************************************************/ +class dummy_msb : public uhd::transport::managed_send_buffer{ +public: + void commit(size_t len){ + if (len == 0) return; + *_len = len; + } + + sptr get_new(boost::shared_array mem, size_t *len){ + _mem = mem; + _len = len; + return make_managed_buffer(this); + } + +private: + void *get_buff(void) const{return _mem.get();} + size_t get_size(void) const{return *_len;} + + boost::shared_array _mem; + size_t *_len; +}; + +/*********************************************************************** + * A dummy transport class to fill with fake data + **********************************************************************/ +class dummy_send_xport_class{ +public: + dummy_send_xport_class(const uhd::otw_type_t &otw_type){ + _otw_type = otw_type; + } + + void pop_front_packet( + uhd::transport::vrt::if_packet_info_t &ifpi + ){ + ifpi.num_packet_words32 = _lens.front()/sizeof(boost::uint32_t); + if (_otw_type.byteorder == uhd::otw_type_t::BO_BIG_ENDIAN){ + uhd::transport::vrt::if_hdr_unpack_be(reinterpret_cast(_mems.front().get()), ifpi); + } + if (_otw_type.byteorder == uhd::otw_type_t::BO_LITTLE_ENDIAN){ + uhd::transport::vrt::if_hdr_unpack_le(reinterpret_cast(_mems.front().get()), ifpi); + } + _mems.pop_front(); + _lens.pop_front(); + } + + uhd::transport::managed_send_buffer::sptr get_send_buff(double){ + _msbs.push_back(dummy_msb()); + _mems.push_back(boost::shared_array(new char[1000])); + _lens.push_back(1000); + uhd::transport::managed_send_buffer::sptr mrb = _msbs.back().get_new(_mems.back(), &_lens.back()); + return mrb; + } + +private: + std::list > _mems; + std::list _lens; + std::list _msbs; //list means no-realloc + uhd::otw_type_t _otw_type; +}; + +//////////////////////////////////////////////////////////////////////// +BOOST_AUTO_TEST_CASE(test_sph_send_one_channel_one_packet_mode){ +//////////////////////////////////////////////////////////////////////// + uhd::otw_type_t otw_type; + otw_type.width = 16; + otw_type.shift = 0; + otw_type.byteorder = uhd::otw_type_t::BO_BIG_ENDIAN; + + dummy_send_xport_class dummy_send_xport(otw_type); + + static const double TICK_RATE = 100e6; + static const double SAMP_RATE = 10e6; + static const size_t NUM_PKTS_TO_TEST = 30; + + //create the super send packet handler + uhd::transport::sph::send_packet_handler handler(1); + handler.set_vrt_packer(&uhd::transport::vrt::if_hdr_pack_be); + handler.set_tick_rate(TICK_RATE); + handler.set_samp_rate(SAMP_RATE); + handler.set_xport_chan_get_buff(0, boost::bind(&dummy_send_xport_class::get_send_buff, &dummy_send_xport, _1)); + handler.set_converter(otw_type); + handler.set_max_samples_per_packet(20); + + //allocate metadata and buffer + std::vector > buff(20); + uhd::tx_metadata_t metadata; + metadata.has_time_spec = true; + metadata.time_spec = uhd::time_spec_t(0.0); + + //generate the test data + for (size_t i = 0; i < NUM_PKTS_TO_TEST; i++){ + metadata.start_of_burst = (i == 0); + metadata.end_of_burst = (i == NUM_PKTS_TO_TEST-1); + const size_t num_sent = handler.send( + &buff.front(), 10 + i%10, metadata, + uhd::io_type_t::COMPLEX_FLOAT32, + uhd::device::SEND_MODE_ONE_PACKET, 1.0 + ); + BOOST_CHECK_EQUAL(num_sent, 10 + i%10); + metadata.time_spec += uhd::time_spec_t(0, num_sent, SAMP_RATE); + } + + //check the sent packets + size_t num_accum_samps = 0; + uhd::transport::vrt::if_packet_info_t ifpi; + for (size_t i = 0; i < NUM_PKTS_TO_TEST; i++){ + std::cout << "data check " << i << std::endl; + dummy_send_xport.pop_front_packet(ifpi); + BOOST_CHECK_EQUAL(ifpi.num_payload_words32, 10+i%10); + BOOST_CHECK(ifpi.has_tsi); + BOOST_CHECK(ifpi.has_tsf); + BOOST_CHECK_EQUAL(ifpi.tsi, 0); + BOOST_CHECK_EQUAL(ifpi.tsf, num_accum_samps*TICK_RATE/SAMP_RATE); + BOOST_CHECK_EQUAL(ifpi.sob, i == 0); + BOOST_CHECK_EQUAL(ifpi.eob, i == NUM_PKTS_TO_TEST-1); + num_accum_samps += ifpi.num_payload_words32; + } +} + +//////////////////////////////////////////////////////////////////////// +BOOST_AUTO_TEST_CASE(test_sph_send_one_channel_full_buffer_mode){ +//////////////////////////////////////////////////////////////////////// + uhd::otw_type_t otw_type; + otw_type.width = 16; + otw_type.shift = 0; + otw_type.byteorder = uhd::otw_type_t::BO_BIG_ENDIAN; + + dummy_send_xport_class dummy_send_xport(otw_type); + + static const double TICK_RATE = 100e6; + static const double SAMP_RATE = 10e6; + static const size_t NUM_PKTS_TO_TEST = 30; + + //create the super send packet handler + uhd::transport::sph::send_packet_handler handler(1); + handler.set_vrt_packer(&uhd::transport::vrt::if_hdr_pack_be); + handler.set_tick_rate(TICK_RATE); + handler.set_samp_rate(SAMP_RATE); + handler.set_xport_chan_get_buff(0, boost::bind(&dummy_send_xport_class::get_send_buff, &dummy_send_xport, _1)); + handler.set_converter(otw_type); + handler.set_max_samples_per_packet(20); + + //allocate metadata and buffer + std::vector > buff(20*NUM_PKTS_TO_TEST); + uhd::tx_metadata_t metadata; + metadata.start_of_burst = true; + metadata.end_of_burst = true; + metadata.has_time_spec = true; + metadata.time_spec = uhd::time_spec_t(0.0); + + //generate the test data + const size_t num_sent = handler.send( + &buff.front(), buff.size(), metadata, + uhd::io_type_t::COMPLEX_FLOAT32, + uhd::device::SEND_MODE_FULL_BUFF, 1.0 + ); + BOOST_CHECK_EQUAL(num_sent, buff.size()); + + //check the sent packets + size_t num_accum_samps = 0; + uhd::transport::vrt::if_packet_info_t ifpi; + for (size_t i = 0; i < NUM_PKTS_TO_TEST; i++){ + std::cout << "data check " << i << std::endl; + dummy_send_xport.pop_front_packet(ifpi); + BOOST_CHECK_EQUAL(ifpi.num_payload_words32, 20); + BOOST_CHECK(ifpi.has_tsi); + BOOST_CHECK(ifpi.has_tsf); + BOOST_CHECK_EQUAL(ifpi.tsi, 0); + BOOST_CHECK_EQUAL(ifpi.tsf, num_accum_samps*TICK_RATE/SAMP_RATE); + BOOST_CHECK_EQUAL(ifpi.sob, i == 0); + BOOST_CHECK_EQUAL(ifpi.eob, i == NUM_PKTS_TO_TEST-1); + num_accum_samps += ifpi.num_payload_words32; + } +} -- cgit v1.2.3 From 397521fcdbe88d4d797bf9a5bcd2cdb097003ab3 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 12 Jun 2011 19:54:09 -0700 Subject: usrp2: super packet handler support squashed --- host/lib/usrp/usrp2/dsp_impl.cpp | 8 +- host/lib/usrp/usrp2/io_impl.cpp | 286 ++++++++++--------------------------- host/lib/usrp/usrp2/usrp2_impl.hpp | 1 - 3 files changed, 77 insertions(+), 218 deletions(-) diff --git a/host/lib/usrp/usrp2/dsp_impl.cpp b/host/lib/usrp/usrp2/dsp_impl.cpp index 292659f36..03cdeae42 100644 --- a/host/lib/usrp/usrp2/dsp_impl.cpp +++ b/host/lib/usrp/usrp2/dsp_impl.cpp @@ -118,12 +118,6 @@ void usrp2_mboard_impl::issue_ddc_stream_cmd(const stream_cmd_t &stream_cmd, siz _iface->poke32(U2_REG_RX_CTRL_TIME_TICKS(which_dsp), stream_cmd.time_spec.get_tick_count(get_master_clock_freq())); } -void usrp2_mboard_impl::handle_overflow(size_t which_dsp){ - if (_dsp_impl->continuous_streaming[which_dsp]){ //re-issue the stream command if already continuous - this->issue_ddc_stream_cmd(stream_cmd_t::STREAM_MODE_START_CONTINUOUS, which_dsp); - } -} - /*********************************************************************** * DDC Properties **********************************************************************/ @@ -186,6 +180,7 @@ void usrp2_mboard_impl::ddc_set(const wax::obj &key_, const wax::obj &val, size_ dsp_type1::calc_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq) ); } + _device.update_xport_channel_mapping(); //rate changed -> update return; default: UHD_THROW_PROP_SET_ERROR(); @@ -259,6 +254,7 @@ void usrp2_mboard_impl::duc_set(const wax::obj &key_, const wax::obj &val, size_ //set the scaling _iface->poke32(U2_REG_DSP_TX_SCALE_IQ, dsp_type1::calc_iq_scale_word(_dsp_impl->duc_interp[which_dsp])); } + _device.update_xport_channel_mapping(); //rate changed -> update return; default: UHD_THROW_PROP_SET_ERROR(); diff --git a/host/lib/usrp/usrp2/io_impl.cpp b/host/lib/usrp/usrp2/io_impl.cpp index 33f249599..ffe9a88e7 100644 --- a/host/lib/usrp/usrp2/io_impl.cpp +++ b/host/lib/usrp/usrp2/io_impl.cpp @@ -15,18 +15,21 @@ // along with this program. If not, see . // -#include "../../transport/vrt_packet_handler.hpp" +#include "../../transport/super_recv_packet_handler.hpp" +#include "../../transport/super_send_packet_handler.hpp" #include "usrp2_impl.hpp" #include "usrp2_regs.hpp" #include #include #include #include +#include #include #include #include #include #include +#include #include #include #include @@ -79,15 +82,22 @@ public: _ready_fcn = boost::bind(&flow_control_monitor::ready, this); } + /*! + * Gets the current sequence number to go out. + * Increments the sequence for the next call + * \return the sequence to be sent to the dsp + */ + UHD_INLINE seq_type get_curr_seq_out(void){ + return _last_seq_out++; + } + /*! * Check the flow control condition. - * \param seq the sequence to go out * \param timeout the timeout in seconds * \return false on timeout */ - UHD_INLINE bool check_fc_condition(seq_type seq, double timeout){ - boost::unique_lock lock(_fc_mutex); - _last_seq_out = seq; + UHD_INLINE bool check_fc_condition(double timeout){ + boost::mutex::scoped_lock lock(_fc_mutex); if (this->ready()) return true; boost::this_thread::disable_interruption di; //disable because the wait can throw return _fc_cond.timed_wait(lock, to_time_dur(timeout), _ready_fcn); @@ -98,7 +108,7 @@ public: * \param seq the last sequence number to be ACK'd */ UHD_INLINE void update_fc_condition(seq_type seq){ - boost::unique_lock lock(_fc_mutex); + boost::mutex::scoped_lock lock(_fc_mutex); _last_seq_ack = seq; lock.unlock(); _fc_cond.notify_one(); @@ -115,23 +125,6 @@ private: boost::function _ready_fcn; }; -/*********************************************************************** - * Alignment indexes class: keeps track of indexes - **********************************************************************/ -class alignment_indexes{ -public: - alignment_indexes(void){_indexes = 0;} - void reset(size_t len){_indexes = (1 << len) - 1;} - size_t front(void){ //TODO replace with look-up table - size_t index = 0; - while ((_indexes & (1 << index)) == 0) index++; - return index; - } - void remove(size_t index){_indexes &= ~(1 << index);} - bool empty(void){return _indexes == 0;} -private: size_t _indexes; -}; - /*********************************************************************** * io impl details (internal to this file) * - pirate crew @@ -143,24 +136,13 @@ struct usrp2_impl::io_impl{ io_impl(std::vector &dsp_xports): dsp_xports(dsp_xports), //the assumption is that all data transports should be identical - get_recv_buffs_fcn(boost::bind(&usrp2_impl::io_impl::get_recv_buffs, this, _1)), - get_send_buffs_fcn(boost::bind(&usrp2_impl::io_impl::get_send_buffs, this, _1)), async_msg_fifo(100/*messages deep*/) { for (size_t i = 0; i < dsp_xports.size(); i++){ fc_mons.push_back(flow_control_monitor::sptr(new flow_control_monitor( usrp2_impl::sram_bytes/dsp_xports.front()->get_send_frame_size() - )));; + ))); } - - //init empty packet infos - vrt::if_packet_info_t packet_info = vrt::if_packet_info_t(); - packet_info.packet_count = 0xf; - packet_info.has_tsi = true; - packet_info.tsi = 0; - packet_info.has_tsf = true; - packet_info.tsf = 0; - prev_infos.resize(dsp_xports.size(), packet_info); } ~io_impl(void){ @@ -169,38 +151,27 @@ struct usrp2_impl::io_impl{ recv_pirate_crew.join_all(); } - bool get_send_buffs(vrt_packet_handler::managed_send_buffs_t &buffs){ - UHD_ASSERT_THROW(send_map.size() == buffs.size()); + managed_send_buffer::sptr get_send_buff(size_t chan, double timeout){ + const size_t index = send_map[chan]; + flow_control_monitor &fc_mon = *fc_mons[index]; - //calculate the flow control word - const boost::uint32_t fc_word32 = packet_handler_send_state.next_packet_seq; + //wait on flow control w/ timeout + if (not fc_mon.check_fc_condition(timeout)) return managed_send_buffer::sptr(); - //grab a managed buffer for each index - for (size_t i = 0; i < buffs.size(); i++){ - if (not fc_mons[send_map[i]]->check_fc_condition(fc_word32, send_timeout)) return false; - buffs[i] = dsp_xports[send_map[i]]->get_send_buff(send_timeout); - if (not buffs[i].get()) return false; - buffs[i]->cast()[0] = uhd::htonx(fc_word32); - } - return true; - } + //get a buffer from the transport w/ timeout + managed_send_buffer::sptr buff = dsp_xports[index]->get_send_buff(timeout); + + //write the flow control word into the buffer + if (buff.get()) buff->cast()[0] = uhd::htonx(fc_mon.get_curr_seq_out()); - alignment_indexes indexes_to_do; //used in alignment logic - time_spec_t expected_time; //used in alignment logic - bool get_recv_buffs(vrt_packet_handler::managed_recv_buffs_t &buffs); + return buff; + } std::vector &dsp_xports; //mappings from channel index to dsp xport std::vector send_map, recv_map; - //timeouts set on calls to recv/send (passed into get buffs methods) - double recv_timeout, send_timeout; - - //bound callbacks for get buffs (bound once here, not in fast-path) - vrt_packet_handler::get_recv_buffs_t get_recv_buffs_fcn; - vrt_packet_handler::get_send_buffs_t get_send_buffs_fcn; - //previous state for each buffer std::vector prev_infos; @@ -208,8 +179,8 @@ struct usrp2_impl::io_impl{ std::vector fc_mons; //state management for the vrt packet handler code - vrt_packet_handler::recv_state packet_handler_recv_state; - vrt_packet_handler::send_state packet_handler_send_state; + sph::recv_packet_handler recv_handler; + sph::send_packet_handler send_handler; //methods and variables for the pirate crew void recv_pirate_loop(boost::barrier &, usrp2_mboard_impl::sptr, zero_copy_if::sptr, size_t); @@ -258,7 +229,7 @@ void usrp2_impl::io_impl::recv_pirate_loop( metadata.time_spec = time_spec_t( time_t(if_packet_info.tsi), size_t(if_packet_info.tsf), mboard->get_master_clock_freq() ); - metadata.event_code = vrt_packet_handler::get_context_code(vrt_hdr, if_packet_info); + metadata.event_code = async_metadata_t::event_code_t(sph::get_context_code(vrt_hdr, if_packet_info)); //catch the flow control packets and react if (metadata.event_code == 0){ @@ -327,8 +298,39 @@ void usrp2_impl::update_xport_channel_mapping(void){ } - _io_impl->packet_handler_recv_state = vrt_packet_handler::recv_state(_io_impl->recv_map.size()); - _io_impl->packet_handler_send_state = vrt_packet_handler::send_state(_io_impl->send_map.size()); + //set all of the relevant properties on the handler + boost::mutex::scoped_lock recv_lock = _io_impl->recv_handler.get_scoped_lock(); + _io_impl->recv_handler.resize(_io_impl->recv_map.size()); + _io_impl->recv_handler.set_vrt_unpacker(&vrt::if_hdr_unpack_be); + _io_impl->recv_handler.set_tick_rate(_mboards.front()->get_master_clock_freq()); + //TODO temporarily use the first dsp rate until we support non-homo rates + const std::string rx_dsp_name = _mboards.at(0)->get_link()[MBOARD_PROP_RX_DSP_NAMES].as().at(0); + const double rx_host_rate = _mboards.at(0)->get_link()[named_prop_t(MBOARD_PROP_RX_DSP, rx_dsp_name)][DSP_PROP_HOST_RATE].as(); + _io_impl->recv_handler.set_samp_rate(rx_host_rate); + for (size_t chan = 0; chan < _io_impl->recv_handler.size(); chan++){ + _io_impl->recv_handler.set_xport_chan_get_buff(chan, boost::bind( + &uhd::transport::zero_copy_if::get_recv_buff, + _io_impl->dsp_xports[_io_impl->recv_map[chan]], _1 + )); + } + _io_impl->recv_handler.set_converter(_rx_otw_type); + + //set all of the relevant properties on the handler + boost::mutex::scoped_lock send_lock = _io_impl->send_handler.get_scoped_lock(); + _io_impl->send_handler.resize(_io_impl->send_map.size()); + _io_impl->send_handler.set_vrt_packer(&vrt::if_hdr_pack_be, vrt_send_header_offset_words32); + _io_impl->send_handler.set_tick_rate(_mboards.front()->get_master_clock_freq()); + //TODO temporarily use the first dsp rate until we support non-homo rates + const std::string tx_dsp_name = _mboards.at(0)->get_link()[MBOARD_PROP_TX_DSP_NAMES].as().at(0); + const double tx_host_rate = _mboards.at(0)->get_link()[named_prop_t(MBOARD_PROP_TX_DSP, tx_dsp_name)][DSP_PROP_HOST_RATE].as(); + _io_impl->send_handler.set_samp_rate(tx_host_rate); + for (size_t chan = 0; chan < _io_impl->send_handler.size(); chan++){ + _io_impl->send_handler.set_xport_chan_get_buff(chan, boost::bind( + &usrp2_impl::io_impl::get_send_buff, _io_impl.get(), chan, _1 + )); + } + _io_impl->send_handler.set_converter(_tx_otw_type); + _io_impl->send_handler.set_max_samples_per_packet(get_max_send_samps_per_packet()); } /*********************************************************************** @@ -355,143 +357,17 @@ size_t usrp2_impl::get_max_send_samps_per_packet(void) const{ } size_t usrp2_impl::send( - const send_buffs_type &buffs, size_t num_samps, + const send_buffs_type &buffs, size_t nsamps_per_buff, const tx_metadata_t &metadata, const io_type_t &io_type, send_mode_t send_mode, double timeout ){ - _io_impl->send_timeout = timeout; - return vrt_packet_handler::send( - _io_impl->packet_handler_send_state, //last state of the send handler - buffs, num_samps, //buffer to fill - metadata, send_mode, //samples metadata - io_type, _tx_otw_type, //input and output types to convert - _mboards.front()->get_master_clock_freq(), //master clock tick rate - uhd::transport::vrt::if_hdr_pack_be, - _io_impl->get_send_buffs_fcn, - get_max_send_samps_per_packet(), - vrt_send_header_offset_words32 - ); -} - -/*********************************************************************** - * Alignment logic on receive - **********************************************************************/ -static UHD_INLINE time_spec_t extract_time_spec( - const vrt::if_packet_info_t &packet_info -){ - return time_spec_t( //assumes has_tsi and has_tsf are true - time_t(packet_info.tsi), size_t(packet_info.tsf), - 100e6 //tick rate does not have to be correct for comparison purposes + return _io_impl->send_handler.send( + buffs, nsamps_per_buff, + metadata, io_type, + send_mode, timeout ); } -static UHD_INLINE void extract_packet_info( - managed_recv_buffer::sptr &buff, - vrt::if_packet_info_t &prev_info, - time_spec_t &time, bool &clear, bool &msg -){ - //extract packet info - vrt::if_packet_info_t next_info; - next_info.num_packet_words32 = buff->size()/sizeof(boost::uint32_t); - vrt::if_hdr_unpack_be(buff->cast(), next_info); - - //handle the packet count / sequence number - if ((prev_info.packet_count+1)%16 != next_info.packet_count){ - UHD_MSG(fastpath) << "O"; //report overflow (drops in the kernel) - } - - time = extract_time_spec(next_info); - clear = extract_time_spec(prev_info) > time; - msg = next_info.packet_type != vrt::if_packet_info_t::PACKET_TYPE_DATA; - prev_info = next_info; -} - -static UHD_INLINE bool handle_msg_packet( - vrt_packet_handler::managed_recv_buffs_t &buffs, size_t index -){ - for (size_t i = 0; i < buffs.size(); i++){ - if (i == index) continue; - buffs[i].reset(); //set NULL - } - return true; -} - -UHD_INLINE bool usrp2_impl::io_impl::get_recv_buffs( - vrt_packet_handler::managed_recv_buffs_t &buffs -){ - if (buffs.size() == 1){ - buffs[0] = dsp_xports[recv_map[0]]->get_recv_buff(recv_timeout); - if (buffs[0].get() == NULL) return false; - bool clear, msg; time_spec_t time; //unused variables - //call extract_packet_info to handle printing the overflows - extract_packet_info(buffs[0], this->prev_infos[recv_map[0]], time, clear, msg); - return true; - } - //-------------------- begin alignment logic ---------------------// - UHD_ASSERT_THROW(recv_map.size() == buffs.size()); - boost::system_time exit_time = boost::get_system_time() + to_time_dur(recv_timeout); - managed_recv_buffer::sptr buff_tmp; - bool clear, msg; - size_t index; - - //If we did not enter this routine with an empty indexes set, - //jump to after the clear so we can preserve the previous state. - //This saves buffers from being lost when using non-blocking recv. - if (not indexes_to_do.empty()) goto skip_pop_initial; - - //respond to a clear by starting from scratch - got_clear: - indexes_to_do.reset(buffs.size()); - clear = false; - - //do an initial pop to load an initial sequence id - index = indexes_to_do.front(); - buff_tmp = dsp_xports[recv_map[index]]->get_recv_buff(from_time_dur(exit_time - boost::get_system_time())); - if (buff_tmp.get() == NULL) return false; - extract_packet_info(buff_tmp, this->prev_infos[recv_map[index]], expected_time, clear, msg); - if (clear) goto got_clear; - buffs[index] = buff_tmp; - if (msg) return handle_msg_packet(buffs, index); - indexes_to_do.remove(index); - skip_pop_initial: - - //get an aligned set of elements from the buffers: - while(not indexes_to_do.empty()){ - - //pop an element off for this index - index = indexes_to_do.front(); - buff_tmp = dsp_xports[recv_map[index]]->get_recv_buff(from_time_dur(exit_time - boost::get_system_time())); - if (buff_tmp.get() == NULL) return false; - time_spec_t this_time; - extract_packet_info(buff_tmp, this->prev_infos[recv_map[index]], this_time, clear, msg); - if (clear) goto got_clear; - buffs[index] = buff_tmp; - if (msg) return handle_msg_packet(buffs, index); - - //if the sequence id matches: - // remove this index from the list and continue - if (this_time == expected_time){ - indexes_to_do.remove(index); - } - - //if the sequence id is newer: - // use the new expected time for comparison - // add all other indexes back into the list - else if (this_time > expected_time){ - expected_time = this_time; - indexes_to_do.reset(buffs.size()); - indexes_to_do.remove(index); - } - - //if the sequence id is older: - // continue with the same index to try again - //else if (this_time < expected_time)... - - } - return true; - //-------------------- end alignment logic -----------------------// -} - /*********************************************************************** * Receive Data **********************************************************************/ @@ -505,26 +381,14 @@ size_t usrp2_impl::get_max_recv_samps_per_packet(void) const{ return bpp/_rx_otw_type.get_sample_size(); } -void usrp2_impl::handle_overflow(size_t chan){ - UHD_MSG(fastpath) << "O"; - ldiv_t indexes = ldiv(chan, usrp2_mboard_impl::NUM_RX_DSPS); - _mboards.at(indexes.quot)->handle_overflow(indexes.rem); -} - size_t usrp2_impl::recv( - const recv_buffs_type &buffs, size_t num_samps, + const recv_buffs_type &buffs, size_t nsamps_per_buff, rx_metadata_t &metadata, const io_type_t &io_type, recv_mode_t recv_mode, double timeout ){ - _io_impl->recv_timeout = timeout; - return vrt_packet_handler::recv( - _io_impl->packet_handler_recv_state, //last state of the recv handler - buffs, num_samps, //buffer to fill - metadata, recv_mode, //samples metadata - io_type, _rx_otw_type, //input and output types to convert - _mboards.front()->get_master_clock_freq(), //master clock tick rate - uhd::transport::vrt::if_hdr_unpack_be, - _io_impl->get_recv_buffs_fcn, - boost::bind(&usrp2_impl::handle_overflow, this, _1) + return _io_impl->recv_handler.recv( + buffs, nsamps_per_buff, + metadata, io_type, + recv_mode, timeout ); } diff --git a/host/lib/usrp/usrp2/usrp2_impl.hpp b/host/lib/usrp/usrp2/usrp2_impl.hpp index ccaf0c9a8..4d19863b1 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.hpp +++ b/host/lib/usrp/usrp2/usrp2_impl.hpp @@ -220,7 +220,6 @@ private: uhd::otw_type_t _rx_otw_type, _tx_otw_type; UHD_PIMPL_DECL(io_impl) _io_impl; void io_init(void); - void handle_overflow(size_t); }; #endif /* INCLUDED_USRP2_IMPL_HPP */ -- cgit v1.2.3 From 89fa3291548b2b2c413c9613977db032b5dc048b Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 12 Jun 2011 19:54:42 -0700 Subject: usrp1: super packet handler support squashed --- host/lib/usrp/usrp1/dsp_impl.cpp | 5 +- host/lib/usrp/usrp1/io_impl.cpp | 180 +++++++++++++++++------------------- host/lib/usrp/usrp1/mboard_impl.cpp | 2 + host/lib/usrp/usrp1/usrp1_impl.cpp | 6 +- host/lib/usrp/usrp1/usrp1_impl.hpp | 3 + 5 files changed, 98 insertions(+), 98 deletions(-) diff --git a/host/lib/usrp/usrp1/dsp_impl.cpp b/host/lib/usrp/usrp1/dsp_impl.cpp index 66b11b989..0bddc49f0 100644 --- a/host/lib/usrp/usrp1/dsp_impl.cpp +++ b/host/lib/usrp/usrp1/dsp_impl.cpp @@ -114,6 +114,7 @@ void usrp1_impl::rx_dsp_set(const wax::obj &key_, const wax::obj &val, size_t wh _iface->poke32(FR_DECIM_RATE, _rx_dsp_decim/2 - 1); this->restore_rx(s); } + this->update_xport_channel_mapping(); //rate changed -> update return; case DSP_PROP_STREAM_CMD: @@ -211,8 +212,10 @@ void usrp1_impl::tx_dsp_set(const wax::obj &key_, const wax::obj &val, size_t wh bool s = this->disable_tx(); _iface->poke32(FR_INTERP_RATE, _tx_dsp_interp/2 - 1); this->restore_tx(s); - return; } + this->update_xport_channel_mapping(); //rate changed -> update + return; + default: UHD_THROW_PROP_SET_ERROR(); } diff --git a/host/lib/usrp/usrp1/io_impl.cpp b/host/lib/usrp/usrp1/io_impl.cpp index 8ac2696eb..90ed17cd8 100644 --- a/host/lib/usrp/usrp1/io_impl.cpp +++ b/host/lib/usrp/usrp1/io_impl.cpp @@ -15,12 +15,15 @@ // along with this program. If not, see . // -#include "../../transport/vrt_packet_handler.hpp" +#define SRPH_DONT_CHECK_SEQUENCE +#include "../../transport/super_recv_packet_handler.hpp" +#include "../../transport/super_send_packet_handler.hpp" #include "usrp_commands.h" #include "usrp1_impl.hpp" #include #include #include +#include #include #include #include @@ -87,14 +90,40 @@ private: commit_cb_type _commit_cb; }; +/*********************************************************************** + * BS VRT packer/unpacker functions (since samples don't have headers) + **********************************************************************/ +static void usrp1_bs_vrt_packer( + boost::uint32_t *, + vrt::if_packet_info_t &if_packet_info +){ + if_packet_info.num_header_words32 = 0; + if_packet_info.num_packet_words32 = if_packet_info.num_payload_words32; +} + +static void usrp1_bs_vrt_unpacker( + const boost::uint32_t *, + vrt::if_packet_info_t &if_packet_info +){ + if_packet_info.packet_type = vrt::if_packet_info_t::PACKET_TYPE_DATA; + if_packet_info.num_payload_words32 = if_packet_info.num_packet_words32; + if_packet_info.num_header_words32 = 0; + if_packet_info.packet_count = 0; + if_packet_info.sob = false; + if_packet_info.eob = false; + if_packet_info.has_sid = false; + if_packet_info.has_cid = false; + if_packet_info.has_tsi = false; + if_packet_info.has_tsf = false; + if_packet_info.has_tlr = false; +} + /*********************************************************************** * IO Implementation Details **********************************************************************/ struct usrp1_impl::io_impl{ io_impl(zero_copy_if::sptr data_transport): data_transport(data_transport), - get_recv_buffs_fcn(boost::bind(&usrp1_impl::io_impl::get_recv_buffs, this, _1)), - get_send_buffs_fcn(boost::bind(&usrp1_impl::io_impl::get_send_buffs, this, _1)), underflow_poll_samp_count(0), overflow_poll_samp_count(0), curr_buff(offset_send_buffer(data_transport->get_send_buff())), @@ -109,16 +138,9 @@ struct usrp1_impl::io_impl{ zero_copy_if::sptr data_transport; - //timeouts set on calls to recv/send (passed into get buffs methods) - double recv_timeout, send_timeout; - - //bound callbacks for get buffs (bound once here, not in fast-path) - vrt_packet_handler::get_recv_buffs_t get_recv_buffs_fcn; - vrt_packet_handler::get_send_buffs_t get_send_buffs_fcn; - //state management for the vrt packet handler code - vrt_packet_handler::recv_state packet_handler_recv_state; - vrt_packet_handler::send_state packet_handler_send_state; + sph::recv_packet_handler recv_handler; + sph::send_packet_handler send_handler; //state management for overflow and underflow size_t underflow_poll_samp_count; @@ -132,11 +154,13 @@ struct usrp1_impl::io_impl{ offset_managed_send_buffer omsb; void commit_send_buff(offset_send_buffer&, offset_send_buffer&, size_t); void flush_send_buff(void); - bool get_send_buffs(vrt_packet_handler::managed_send_buffs_t &); - bool get_recv_buffs(vrt_packet_handler::managed_recv_buffs_t &buffs){ - UHD_ASSERT_THROW(buffs.size() == 1); - buffs[0] = data_transport->get_recv_buff(recv_timeout); - return buffs[0].get() != NULL; + managed_send_buffer::sptr get_send_buff(double timeout){ + //try to get a new managed buffer with timeout + offset_send_buffer next_buff(data_transport->get_send_buff(timeout)); + if (not next_buff.buff.get()) return managed_send_buffer::sptr(); /* propagate timeout here */ + + //make a new managed buffer with the offset buffs + return omsb.get_new(curr_buff, next_buff); } }; @@ -185,32 +209,13 @@ void usrp1_impl::io_impl::flush_send_buff(void){ if (bytes_to_pad == 0) bytes_to_pad = alignment_padding; //get the buffer, clear, and commit (really current buffer) - vrt_packet_handler::managed_send_buffs_t buffs(1); - if (this->get_send_buffs(buffs)){ - std::memset(buffs[0]->cast(), 0, bytes_to_pad); - buffs[0]->commit(bytes_to_pad); + managed_send_buffer::sptr buff = this->get_send_buff(.1); + if (buff.get() != NULL){ + std::memset(buff->cast(), 0, bytes_to_pad); + buff->commit(bytes_to_pad); } } -/*! - * Get a managed send buffer with the alignment padding: - * Always grab the next send buffer so we can timeout here. - */ -bool usrp1_impl::io_impl::get_send_buffs( - vrt_packet_handler::managed_send_buffs_t &buffs -){ - UHD_ASSERT_THROW(buffs.size() == 1); - - //try to get a new managed buffer with timeout - offset_send_buffer next_buff(data_transport->get_send_buff(send_timeout)); - if (not next_buff.buff.get()) return false; /* propagate timeout here */ - - //make a new managed buffer with the offset buffs - buffs[0] = omsb.get_new(curr_buff, next_buff); - - return true; -} - /*********************************************************************** * Initialize internals within this file **********************************************************************/ @@ -232,6 +237,34 @@ void usrp1_impl::io_init(void){ this->enable_tx(true); //always enabled rx_stream_on_off(false); _io_impl->flush_send_buff(); + + //update mapping here since it didnt b4 when io init not called first + update_xport_channel_mapping(); +} + +void usrp1_impl::update_xport_channel_mapping(void){ + if (_io_impl.get() == NULL) return; //not inited yet + + //set all of the relevant properties on the handler + boost::mutex::scoped_lock recv_lock = _io_impl->recv_handler.get_scoped_lock(); + _io_impl->recv_handler.set_vrt_unpacker(&usrp1_bs_vrt_unpacker); + _io_impl->recv_handler.set_tick_rate(_clock_ctrl->get_master_clock_freq()); + _io_impl->recv_handler.set_samp_rate(_rx_dsp_proxies[_rx_dsp_proxies.keys().at(0)]->get_link()[DSP_PROP_HOST_RATE].as()); + _io_impl->recv_handler.set_xport_chan_get_buff(0, boost::bind( + &uhd::transport::zero_copy_if::get_recv_buff, _io_impl->data_transport, _1 + )); + _io_impl->recv_handler.set_converter(_rx_otw_type, _rx_subdev_spec.size()); + + //set all of the relevant properties on the handler + boost::mutex::scoped_lock send_lock = _io_impl->send_handler.get_scoped_lock(); + _io_impl->send_handler.set_vrt_packer(&usrp1_bs_vrt_packer); + _io_impl->send_handler.set_tick_rate(_clock_ctrl->get_master_clock_freq()); + _io_impl->send_handler.set_samp_rate(_tx_dsp_proxies[_tx_dsp_proxies.keys().at(0)]->get_link()[DSP_PROP_HOST_RATE].as()); + _io_impl->send_handler.set_xport_chan_get_buff(0, boost::bind( + &usrp1_impl::io_impl::get_send_buff, _io_impl.get(), _1 + )); + _io_impl->send_handler.set_converter(_tx_otw_type, _tx_subdev_spec.size()); + _io_impl->send_handler.set_max_samples_per_packet(get_max_send_samps_per_packet()); } void usrp1_impl::rx_stream_on_off(bool enb){ @@ -245,14 +278,6 @@ void usrp1_impl::rx_stream_on_off(bool enb){ /*********************************************************************** * Data send + helper functions **********************************************************************/ -static void usrp1_bs_vrt_packer( - boost::uint32_t *, - vrt::if_packet_info_t &if_packet_info -){ - if_packet_info.num_header_words32 = 0; - if_packet_info.num_packet_words32 = if_packet_info.num_payload_words32; -} - size_t usrp1_impl::get_max_send_samps_per_packet(void) const { return (_data_transport->get_send_frame_size() - alignment_padding) / _tx_otw_type.get_sample_size() @@ -261,29 +286,21 @@ size_t usrp1_impl::get_max_send_samps_per_packet(void) const { } size_t usrp1_impl::send( - const send_buffs_type &buffs, size_t num_samps, + const send_buffs_type &buffs, size_t nsamps_per_buff, const tx_metadata_t &metadata, const io_type_t &io_type, send_mode_t send_mode, double timeout ){ - if (_soft_time_ctrl->send_pre(metadata, timeout)) return num_samps; - - _io_impl->send_timeout = timeout; - size_t num_samps_sent = vrt_packet_handler::send( - _io_impl->packet_handler_send_state, //last state of the send handler - buffs, num_samps, //buffer to fill - metadata, send_mode, //samples metadata - io_type, _tx_otw_type, //input and output types to convert - _clock_ctrl->get_master_clock_freq(), //master clock tick rate - &usrp1_bs_vrt_packer, - _io_impl->get_send_buffs_fcn, - get_max_send_samps_per_packet(), - 0, //vrt header offset - _tx_subdev_spec.size() //num channels + if (_soft_time_ctrl->send_pre(metadata, timeout)) return 0; + + size_t num_samps_sent = _io_impl->send_handler.send( + buffs, nsamps_per_buff, + metadata, io_type, + send_mode, timeout ); //handle eob flag (commit the buffer, disable the DACs) //check num samps sent to avoid flush on incomplete/timeout - if (metadata.end_of_burst and num_samps_sent == num_samps){ + if (metadata.end_of_burst and num_samps_sent == nsamps_per_buff){ _io_impl->flush_send_buff(); } @@ -306,23 +323,6 @@ size_t usrp1_impl::send( /*********************************************************************** * Data recv + helper functions **********************************************************************/ -static void usrp1_bs_vrt_unpacker( - const boost::uint32_t *, - vrt::if_packet_info_t &if_packet_info -){ - if_packet_info.packet_type = vrt::if_packet_info_t::PACKET_TYPE_DATA; - if_packet_info.num_payload_words32 = if_packet_info.num_packet_words32; - if_packet_info.num_header_words32 = 0; - if_packet_info.packet_count = 0; - if_packet_info.sob = false; - if_packet_info.eob = false; - if_packet_info.has_sid = false; - if_packet_info.has_cid = false; - if_packet_info.has_tsi = false; - if_packet_info.has_tsf = false; - if_packet_info.has_tlr = false; -} - size_t usrp1_impl::get_max_recv_samps_per_packet(void) const { return _data_transport->get_recv_frame_size() / _rx_otw_type.get_sample_size() @@ -331,22 +331,14 @@ size_t usrp1_impl::get_max_recv_samps_per_packet(void) const { } size_t usrp1_impl::recv( - const recv_buffs_type &buffs, size_t num_samps, + const recv_buffs_type &buffs, size_t nsamps_per_buff, rx_metadata_t &metadata, const io_type_t &io_type, recv_mode_t recv_mode, double timeout ){ - _io_impl->recv_timeout = timeout; - size_t num_samps_recvd = vrt_packet_handler::recv( - _io_impl->packet_handler_recv_state, //last state of the recv handler - buffs, num_samps, //buffer to fill - metadata, recv_mode, //samples metadata - io_type, _rx_otw_type, //input and output types to convert - _clock_ctrl->get_master_clock_freq(), //master clock tick rate - &usrp1_bs_vrt_unpacker, - _io_impl->get_recv_buffs_fcn, - &vrt_packet_handler::handle_overflow_nop, - 0, //vrt header offset - _rx_subdev_spec.size() //num channels + size_t num_samps_recvd = _io_impl->recv_handler.recv( + buffs, nsamps_per_buff, + metadata, io_type, + recv_mode, timeout ); _soft_time_ctrl->recv_post(metadata, num_samps_recvd); diff --git a/host/lib/usrp/usrp1/mboard_impl.cpp b/host/lib/usrp/usrp1/mboard_impl.cpp index f699c8e12..87911b312 100644 --- a/host/lib/usrp/usrp1/mboard_impl.cpp +++ b/host/lib/usrp/usrp1/mboard_impl.cpp @@ -352,6 +352,7 @@ void usrp1_impl::mboard_set(const wax::obj &key, const wax::obj &val) bool s = this->disable_rx(); _iface->poke32(FR_RX_MUX, calc_rx_mux(_rx_subdev_spec, _mboard_proxy->get_link())); this->restore_rx(s); + this->update_xport_channel_mapping(); }return; case MBOARD_PROP_TX_SUBDEV_SPEC:{ @@ -367,6 +368,7 @@ void usrp1_impl::mboard_set(const wax::obj &key, const wax::obj &val) bool s = this->disable_tx(); _iface->poke32(FR_TX_MUX, calc_tx_mux(_tx_subdev_spec, _mboard_proxy->get_link())); this->restore_tx(s); + this->update_xport_channel_mapping(); }return; case MBOARD_PROP_EEPROM_MAP: diff --git a/host/lib/usrp/usrp1/usrp1_impl.cpp b/host/lib/usrp/usrp1/usrp1_impl.cpp index 37955d628..a3d502038 100644 --- a/host/lib/usrp/usrp1/usrp1_impl.cpp +++ b/host/lib/usrp/usrp1/usrp1_impl.cpp @@ -199,12 +199,12 @@ usrp1_impl::usrp1_impl(uhd::transport::usb_zero_copy::sptr data_transport, //initialize the dsps tx_dsp_init(); - //initialize the send/recv - io_init(); - //init the subdev specs this->mboard_set(MBOARD_PROP_RX_SUBDEV_SPEC, subdev_spec_t()); this->mboard_set(MBOARD_PROP_TX_SUBDEV_SPEC, subdev_spec_t()); + + //initialize the send/recv + io_init(); } usrp1_impl::~usrp1_impl(void){UHD_SAFE_CALL( diff --git a/host/lib/usrp/usrp1/usrp1_impl.hpp b/host/lib/usrp/usrp1/usrp1_impl.hpp index fbae2a3b9..bea1dbe3b 100644 --- a/host/lib/usrp/usrp1/usrp1_impl.hpp +++ b/host/lib/usrp/usrp1/usrp1_impl.hpp @@ -114,6 +114,9 @@ private: const uhd::usrp::dboard_id_t &rx_dboard_id ); + //!call when the channel mapping is changed + void update_xport_channel_mapping(void); + //soft time control emulation uhd::usrp::soft_time_ctrl::sptr _soft_time_ctrl; -- cgit v1.2.3 From bafe93a272129b4974b2f8386a3a33c793c59a9b Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 12 Jun 2011 19:54:54 -0700 Subject: usrp_e100: super packet handler support squashed --- host/lib/usrp/usrp_e100/dsp_impl.cpp | 2 + host/lib/usrp/usrp_e100/io_impl.cpp | 110 ++++++++++++++++------------- host/lib/usrp/usrp_e100/usrp_e100_impl.hpp | 1 + 3 files changed, 65 insertions(+), 48 deletions(-) diff --git a/host/lib/usrp/usrp_e100/dsp_impl.cpp b/host/lib/usrp/usrp_e100/dsp_impl.cpp index 8d084f066..93034b5dc 100644 --- a/host/lib/usrp/usrp_e100/dsp_impl.cpp +++ b/host/lib/usrp/usrp_e100/dsp_impl.cpp @@ -104,6 +104,7 @@ void usrp_e100_impl::rx_ddc_set(const wax::obj &key_, const wax::obj &val){ dsp_type1::calc_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq) ); } + this->update_xport_channel_mapping(); //rate changed -> update return; default: UHD_THROW_PROP_SET_ERROR(); @@ -181,6 +182,7 @@ void usrp_e100_impl::tx_duc_set(const wax::obj &key_, const wax::obj &val){ //set the scaling _iface->poke32(UE_REG_DSP_TX_SCALE_IQ, dsp_type1::calc_iq_scale_word(_duc_interp)); } + this->update_xport_channel_mapping(); //rate changed -> update return; default: UHD_THROW_PROP_SET_ERROR(); diff --git a/host/lib/usrp/usrp_e100/io_impl.cpp b/host/lib/usrp/usrp_e100/io_impl.cpp index aa6e7c485..91b129276 100644 --- a/host/lib/usrp/usrp_e100/io_impl.cpp +++ b/host/lib/usrp/usrp_e100/io_impl.cpp @@ -15,14 +15,16 @@ // along with this program. If not, see . // +#include "../../transport/super_recv_packet_handler.hpp" +#include "../../transport/super_send_packet_handler.hpp" #include "usrp_e100_impl.hpp" #include "usrp_e100_regs.hpp" #include #include #include +#include #include #include -#include "../../transport/vrt_packet_handler.hpp" #include #include #include @@ -51,8 +53,6 @@ static const int underflow_flags = async_metadata_t::EVENT_CODE_UNDERFLOW | asyn struct usrp_e100_impl::io_impl{ io_impl(zero_copy_if::sptr &xport): data_xport(xport), - get_recv_buffs_fcn(boost::bind(&usrp_e100_impl::io_impl::get_recv_buffs, this, _1)), - get_send_buffs_fcn(boost::bind(&usrp_e100_impl::io_impl::get_send_buffs, this, _1)), recv_pirate_booty(data_xport->get_num_recv_frames()), async_msg_fifo(100/*messages deep*/) { @@ -65,16 +65,11 @@ struct usrp_e100_impl::io_impl{ recv_pirate_crew.join_all(); } - bool get_recv_buffs(vrt_packet_handler::managed_recv_buffs_t &buffs){ - UHD_ASSERT_THROW(buffs.size() == 1); + managed_recv_buffer::sptr get_recv_buff(double timeout){ boost::this_thread::disable_interruption di; //disable because the wait can throw - return recv_pirate_booty.pop_with_timed_wait(buffs.front(), recv_timeout); - } - - bool get_send_buffs(vrt_packet_handler::managed_send_buffs_t &buffs){ - UHD_ASSERT_THROW(buffs.size() == 1); - buffs[0] = data_xport->get_send_buff(send_timeout); - return buffs[0].get() != NULL; + managed_recv_buffer::sptr buff; + recv_pirate_booty.pop_with_timed_wait(buff, timeout); + return buff; //ASSUME buff == NULL when pop times-out } //The data transport is listed first so that it is deconstructed last, @@ -82,16 +77,9 @@ struct usrp_e100_impl::io_impl{ //This comment is invalid because its now a reference and not stored here. zero_copy_if::sptr &data_xport; - //bound callbacks for get buffs (bound once here, not in fast-path) - vrt_packet_handler::get_recv_buffs_t get_recv_buffs_fcn; - vrt_packet_handler::get_send_buffs_t get_send_buffs_fcn; - - //timeouts set on calls to recv/send (passed into get buffs methods) - double recv_timeout, send_timeout; - //state management for the vrt packet handler code - vrt_packet_handler::recv_state packet_handler_recv_state; - vrt_packet_handler::send_state packet_handler_send_state; + sph::recv_packet_handler recv_handler; + sph::send_packet_handler send_handler; bool continuous_streaming; //a pirate's life is the life for me! @@ -133,16 +121,18 @@ void usrp_e100_impl::io_impl::recv_pirate_loop( vrt::if_packet_info_t if_packet_info; if_packet_info.num_packet_words32 = buff->size()/sizeof(boost::uint32_t); const boost::uint32_t *vrt_hdr = buff->cast(); - vrt::if_hdr_unpack_le(vrt_hdr, if_packet_info); //handle an rx data packet or inline message - if (if_packet_info.sid == rx_data_inline_sid){ + if (uhd::ntohx(vrt_hdr[1]) == rx_data_inline_sid){ //ASSUME has_sid if (fp_recv_debug) UHD_LOGV(always) << "this is rx_data_inline_sid\n"; //same number of frames as the data transport -> always immediate recv_pirate_booty.push_with_wait(buff); continue; } + //unpack the vrt header and process below... + vrt::if_hdr_unpack_le(vrt_hdr, if_packet_info); + //handle a tx async report message if (if_packet_info.sid == tx_async_report_sid and if_packet_info.packet_type != vrt::if_packet_info_t::PACKET_TYPE_DATA){ if (fp_recv_debug) UHD_LOGV(always) << "this is tx_async_report_sid\n"; @@ -154,7 +144,7 @@ void usrp_e100_impl::io_impl::recv_pirate_loop( metadata.time_spec = time_spec_t( time_t(if_packet_info.tsi), size_t(if_packet_info.tsf), clock_ctrl->get_fpga_clock_rate() ); - metadata.event_code = vrt_packet_handler::get_context_code(vrt_hdr, if_packet_info); + metadata.event_code = async_metadata_t::event_code_t(sph::get_context_code(vrt_hdr, if_packet_info)); //print the famous U, and push the metadata into the message queue if (metadata.event_code & underflow_flags) UHD_MSG(fastpath) << "U"; @@ -162,6 +152,7 @@ void usrp_e100_impl::io_impl::recv_pirate_loop( continue; } + //TODO replace this below with a UHD_MSG(error) if (fp_recv_debug) UHD_LOGV(always) << "this is unknown packet\n"; }catch(const std::exception &e){ @@ -213,6 +204,42 @@ void usrp_e100_impl::io_init(void){ boost::ref(spawn_barrier), _clock_ctrl )); spawn_barrier.wait(); + //update mapping here since it didnt b4 when io init not called first + update_xport_channel_mapping(); +} + +void usrp_e100_impl::update_xport_channel_mapping(void){ + if (_io_impl.get() == NULL) return; //not inited yet + + //set all of the relevant properties on the handler + boost::mutex::scoped_lock recv_lock = _io_impl->recv_handler.get_scoped_lock(); + _io_impl->recv_handler.resize(_rx_subdev_spec.size()); + _io_impl->recv_handler.set_vrt_unpacker(&vrt::if_hdr_unpack_le); + _io_impl->recv_handler.set_tick_rate(_clock_ctrl->get_fpga_clock_rate()); + _io_impl->recv_handler.set_samp_rate(_rx_ddc_proxy->get_link()[DSP_PROP_HOST_RATE].as()); + for (size_t chan = 0; chan < _io_impl->recv_handler.size(); chan++){ + _io_impl->recv_handler.set_xport_chan_get_buff(chan, boost::bind( + &usrp_e100_impl::io_impl::get_recv_buff, _io_impl.get(), _1 + )); + _io_impl->recv_handler.set_overflow_handler(chan, boost::bind( + &usrp_e100_impl::handle_overrun, this, chan + )); + } + _io_impl->recv_handler.set_converter(_recv_otw_type); + + //set all of the relevant properties on the handler + boost::mutex::scoped_lock send_lock = _io_impl->send_handler.get_scoped_lock(); + _io_impl->send_handler.resize(_tx_subdev_spec.size()); + _io_impl->send_handler.set_vrt_packer(&vrt::if_hdr_pack_le); + _io_impl->send_handler.set_tick_rate(_clock_ctrl->get_fpga_clock_rate()); + _io_impl->send_handler.set_samp_rate(_tx_duc_proxy->get_link()[DSP_PROP_HOST_RATE].as()); + for (size_t chan = 0; chan < _io_impl->send_handler.size(); chan++){ + _io_impl->send_handler.set_xport_chan_get_buff(chan, boost::bind( + &uhd::transport::zero_copy_if::get_send_buff, _io_impl->data_xport, _1 + )); + } + _io_impl->send_handler.set_converter(_send_otw_type); + _io_impl->send_handler.set_max_samples_per_packet(get_max_send_samps_per_packet()); } void usrp_e100_impl::issue_stream_cmd(const stream_cmd_t &stream_cmd){ @@ -222,8 +249,7 @@ void usrp_e100_impl::issue_stream_cmd(const stream_cmd_t &stream_cmd){ _iface->poke32(UE_REG_CTRL_RX_TIME_TICKS, stream_cmd.time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate())); } -void usrp_e100_impl::handle_overrun(size_t){ - UHD_MSG(fastpath) << "O"; //the famous OOOOOOOOOOO +void usrp_e100_impl::handle_overrun(size_t /*chan*/){ if (_io_impl->continuous_streaming){ this->issue_stream_cmd(stream_cmd_t::STREAM_MODE_START_CONTINUOUS); } @@ -242,20 +268,14 @@ size_t usrp_e100_impl::get_max_send_samps_per_packet(void) const{ } size_t usrp_e100_impl::send( - const send_buffs_type &buffs, size_t num_samps, + const send_buffs_type &buffs, size_t nsamps_per_buff, const tx_metadata_t &metadata, const io_type_t &io_type, send_mode_t send_mode, double timeout ){ - _io_impl->send_timeout = timeout; - return vrt_packet_handler::send( - _io_impl->packet_handler_send_state, //last state of the send handler - buffs, num_samps, //buffer to fill - metadata, send_mode, //samples metadata - io_type, _send_otw_type, //input and output types to convert - _clock_ctrl->get_fpga_clock_rate(), //master clock tick rate - uhd::transport::vrt::if_hdr_pack_le, - _io_impl->get_send_buffs_fcn, - get_max_send_samps_per_packet() + return _io_impl->send_handler.send( + buffs, nsamps_per_buff, + metadata, io_type, + send_mode, timeout ); } @@ -273,20 +293,14 @@ size_t usrp_e100_impl::get_max_recv_samps_per_packet(void) const{ } size_t usrp_e100_impl::recv( - const recv_buffs_type &buffs, size_t num_samps, + const recv_buffs_type &buffs, size_t nsamps_per_buff, rx_metadata_t &metadata, const io_type_t &io_type, recv_mode_t recv_mode, double timeout ){ - _io_impl->recv_timeout = timeout; - return vrt_packet_handler::recv( - _io_impl->packet_handler_recv_state, //last state of the recv handler - buffs, num_samps, //buffer to fill - metadata, recv_mode, //samples metadata - io_type, _recv_otw_type, //input and output types to convert - _clock_ctrl->get_fpga_clock_rate(), //master clock tick rate - uhd::transport::vrt::if_hdr_unpack_le, - _io_impl->get_recv_buffs_fcn, - boost::bind(&usrp_e100_impl::handle_overrun, this, _1) + return _io_impl->recv_handler.recv( + buffs, nsamps_per_buff, + metadata, io_type, + recv_mode, timeout ); } diff --git a/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp b/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp index 318a75191..1c17863fb 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp @@ -104,6 +104,7 @@ private: void io_init(void); void issue_stream_cmd(const uhd::stream_cmd_t &stream_cmd); void handle_overrun(size_t); + void update_xport_channel_mapping(void); //configuration shadows uhd::clock_config_t _clock_config; -- cgit v1.2.3 From f7c8ee26f9925d525615cf5a306832e64f7d4c1f Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 12 Jun 2011 19:58:23 -0700 Subject: uhd: removed vrt packet handler code --- host/lib/transport/CMakeLists.txt | 1 - host/lib/transport/vrt_packet_handler.hpp | 470 ------------------------------ 2 files changed, 471 deletions(-) delete mode 100644 host/lib/transport/vrt_packet_handler.hpp diff --git a/host/lib/transport/CMakeLists.txt b/host/lib/transport/CMakeLists.txt index 90360977a..439c3d230 100644 --- a/host/lib/transport/CMakeLists.txt +++ b/host/lib/transport/CMakeLists.txt @@ -98,5 +98,4 @@ LIBUHD_APPEND_SOURCES( ${CMAKE_CURRENT_SOURCE_DIR}/if_addrs.cpp ${CMAKE_CURRENT_SOURCE_DIR}/udp_simple.cpp ${CMAKE_CURRENT_SOURCE_DIR}/udp_zero_copy.cpp - ${CMAKE_CURRENT_SOURCE_DIR}/vrt_packet_handler.hpp ) diff --git a/host/lib/transport/vrt_packet_handler.hpp b/host/lib/transport/vrt_packet_handler.hpp deleted file mode 100644 index 26dbe1806..000000000 --- a/host/lib/transport/vrt_packet_handler.hpp +++ /dev/null @@ -1,470 +0,0 @@ -// -// Copyright 2010-2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#ifndef INCLUDED_LIBUHD_TRANSPORT_VRT_PACKET_HANDLER_HPP -#define INCLUDED_LIBUHD_TRANSPORT_VRT_PACKET_HANDLER_HPP - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -namespace vrt_packet_handler{ - -//this may change in the future but its a constant for now -static const size_t OTW_BYTES_PER_SAMP = sizeof(boost::uint32_t); - -template UHD_INLINE T get_context_code( - const boost::uint32_t *vrt_hdr, - const uhd::transport::vrt::if_packet_info_t &if_packet_info -){ - //extract the context word (we dont know the endianness so mirror the bytes) - boost::uint32_t word0 = vrt_hdr[if_packet_info.num_header_words32] | - uhd::byteswap(vrt_hdr[if_packet_info.num_header_words32]); - return T(word0 & 0xff); -} - -/*********************************************************************** - * vrt packet handler for recv - **********************************************************************/ - typedef std::vector managed_recv_buffs_t; - typedef boost::function get_recv_buffs_t; - typedef boost::function handle_overflow_t; - typedef boost::function vrt_unpacker_t; - - static inline void handle_overflow_nop(size_t){} - - struct recv_state{ - //width of the receiver in channels - size_t width; - - //state variables to handle fragments - managed_recv_buffs_t managed_buffs; - std::vector copy_buffs; - size_t size_of_copy_buffs; - size_t fragment_offset_in_samps; - std::vector io_buffs; - std::vector otw_buffs; - - recv_state(size_t width = 1): - width(width), - managed_buffs(width), - copy_buffs(width, NULL), - size_of_copy_buffs(0), - fragment_offset_in_samps(0), - io_buffs(0) //resized later - { - /* NOP */ - } - }; - - /******************************************************************* - * Unpack a received vrt header and set the copy buffer. - * - helper function for vrt_packet_handler::_recv1 - ******************************************************************/ - static UHD_INLINE void _recv1_helper( - recv_state &state, - uhd::rx_metadata_t &metadata, - double tick_rate, - const vrt_unpacker_t &vrt_unpacker, - const handle_overflow_t &handle_overflow, - size_t vrt_header_offset_words32 - ){ - //vrt unpack each managed buffer - uhd::transport::vrt::if_packet_info_t if_packet_info; - for (size_t i = 0; i < state.width; i++){ - if (state.managed_buffs[i].get() == NULL) continue; //better have a message packet coming up... - - //extract packet words and check thats its enough to move on - size_t num_packet_words32 = state.managed_buffs[i]->size()/sizeof(boost::uint32_t); - if (num_packet_words32 <= vrt_header_offset_words32){ - throw std::runtime_error("recv buffer smaller than vrt packet offset"); - } - - //unpack the vrt header into the info struct - const boost::uint32_t *vrt_hdr = state.managed_buffs[i]->cast() + vrt_header_offset_words32; - if_packet_info.num_packet_words32 = num_packet_words32 - vrt_header_offset_words32; - vrt_unpacker(vrt_hdr, if_packet_info); - - //handle the non-data packet case and parse its contents - if (if_packet_info.packet_type != uhd::transport::vrt::if_packet_info_t::PACKET_TYPE_DATA){ - - metadata.error_code = get_context_code(vrt_hdr, if_packet_info); - if (metadata.error_code == uhd::rx_metadata_t::ERROR_CODE_OVERFLOW) handle_overflow(i); - - //break to exit loop and store metadata below - state.size_of_copy_buffs = 0; break; - } - - //setup the buffer to point to the data - state.copy_buffs[i] = reinterpret_cast(vrt_hdr + if_packet_info.num_header_words32); - - //store the minimum payload length into the copy buffer length - size_t num_payload_bytes = if_packet_info.num_payload_words32*sizeof(boost::uint32_t); - if (i == 0 or state.size_of_copy_buffs > num_payload_bytes){ - state.size_of_copy_buffs = num_payload_bytes; - } - } - - //store the last vrt info into the metadata - metadata.has_time_spec = if_packet_info.has_tsi and if_packet_info.has_tsf; - metadata.time_spec = uhd::time_spec_t( - time_t(if_packet_info.tsi), size_t(if_packet_info.tsf), tick_rate - ); - static const int tlr_sob_flags = (1 << 21) | (1 << 9); //enable and indicator bits - metadata.start_of_burst = if_packet_info.has_tlr and (int(if_packet_info.tlr & tlr_sob_flags) == tlr_sob_flags); - static const int tlr_eob_flags = (1 << 20) | (1 << 8); //enable and indicator bits - metadata.end_of_burst = if_packet_info.has_tlr and (int(if_packet_info.tlr & tlr_eob_flags) == tlr_eob_flags); - } - - /******************************************************************* - * Recv data, unpack a vrt header, and copy-convert the data. - * - helper function for vrt_packet_handler::recv - ******************************************************************/ - static UHD_INLINE size_t _recv1( - recv_state &state, - const uhd::device::recv_buffs_type &buffs, - size_t offset_bytes, - size_t total_samps, - uhd::rx_metadata_t &metadata, - uhd::convert::function_type &converter, - double tick_rate, - const vrt_unpacker_t &vrt_unpacker, - const get_recv_buffs_t &get_recv_buffs, - const handle_overflow_t &handle_overflow, - size_t vrt_header_offset_words32, - size_t chans_per_otw_buff - ){ - metadata.error_code = uhd::rx_metadata_t::ERROR_CODE_NONE; - - //perform a receive if no rx data is waiting to be copied - if (state.size_of_copy_buffs == 0){ - state.fragment_offset_in_samps = 0; - if (not get_recv_buffs(state.managed_buffs)){ - metadata.error_code = uhd::rx_metadata_t::ERROR_CODE_TIMEOUT; - return 0; - } - try{ - _recv1_helper( - state, metadata, tick_rate, - vrt_unpacker, handle_overflow, - vrt_header_offset_words32 - ); - }catch(const std::exception &e){ - state.size_of_copy_buffs = 0; //reset copy buffs size - std::cerr << "Error (recv): " << e.what() << std::endl; - metadata.error_code = uhd::rx_metadata_t::ERROR_CODE_BAD_PACKET; - return 0; - } - } - //defaults for the metadata when this is a fragment - else{ - metadata.has_time_spec = false; - metadata.start_of_burst = false; - metadata.end_of_burst = false; - } - - //extract the number of samples available to copy - size_t bytes_per_item = OTW_BYTES_PER_SAMP; - size_t nsamps_available = state.size_of_copy_buffs/bytes_per_item; - size_t nsamps_to_copy = std::min(total_samps*chans_per_otw_buff, nsamps_available); - size_t bytes_to_copy = nsamps_to_copy*bytes_per_item; - size_t nsamps_to_copy_per_io_buff = nsamps_to_copy/chans_per_otw_buff; - - for (size_t i = 0; i < buffs.size(); i+=chans_per_otw_buff){ - - //fill a vector with pointers to the io buffers - for (size_t j = 0; j < chans_per_otw_buff; j++){ - state.io_buffs[j] = reinterpret_cast(buffs[i+j]) + offset_bytes; - } - - //copy-convert the samples from the recv buffer - converter(state.copy_buffs[i], state.io_buffs, nsamps_to_copy_per_io_buff, 1/32767.); - - //update the rx copy buffer to reflect the bytes copied - state.copy_buffs[i] += bytes_to_copy; - } - //update the copy buffer's availability - state.size_of_copy_buffs -= bytes_to_copy; - - //setup the fragment flags and offset - metadata.more_fragments = state.size_of_copy_buffs != 0; - metadata.fragment_offset = state.fragment_offset_in_samps; - state.fragment_offset_in_samps += nsamps_to_copy; //set for next call - - return nsamps_to_copy_per_io_buff; - } - - /******************************************************************* - * Recv vrt packets and copy convert the samples into the buffer. - ******************************************************************/ - static UHD_INLINE size_t recv( - recv_state &state, - const uhd::device::recv_buffs_type &buffs, - const size_t total_num_samps, - uhd::rx_metadata_t &metadata, - uhd::device::recv_mode_t recv_mode, - const uhd::io_type_t &io_type, - const uhd::otw_type_t &otw_type, - double tick_rate, - const vrt_unpacker_t &vrt_unpacker, - const get_recv_buffs_t &get_recv_buffs, - const handle_overflow_t &handle_overflow = &handle_overflow_nop, - size_t vrt_header_offset_words32 = 0, - size_t chans_per_otw_buff = 1 - ){ - state.io_buffs.resize(chans_per_otw_buff); - - uhd::convert::function_type converter( - uhd::convert::get_converter_otw_to_cpu( - io_type, otw_type, 1, chans_per_otw_buff - )); - - switch(recv_mode){ - - //////////////////////////////////////////////////////////////// - case uhd::device::RECV_MODE_ONE_PACKET:{ - //////////////////////////////////////////////////////////////// - return _recv1( - state, - buffs, 0, - total_num_samps, - metadata, - converter, - tick_rate, - vrt_unpacker, - get_recv_buffs, - handle_overflow, - vrt_header_offset_words32, - chans_per_otw_buff - ); - } - - //////////////////////////////////////////////////////////////// - case uhd::device::RECV_MODE_FULL_BUFF:{ - //////////////////////////////////////////////////////////////// - size_t accum_num_samps = 0; - uhd::rx_metadata_t tmp_md; - while(accum_num_samps < total_num_samps){ - size_t num_samps = _recv1( - state, - buffs, accum_num_samps*io_type.size, - total_num_samps - accum_num_samps, - (accum_num_samps == 0)? metadata : tmp_md, //only the first metadata gets kept - converter, - tick_rate, - vrt_unpacker, - get_recv_buffs, - handle_overflow, - vrt_header_offset_words32, - chans_per_otw_buff - ); - if (num_samps == 0) break; //had a recv timeout or error, break loop - accum_num_samps += num_samps; - } - return accum_num_samps; - } - - default: throw std::runtime_error("unknown recv mode"); - }//switch(recv_mode) - } - -/*********************************************************************** - * vrt packet handler for send - **********************************************************************/ - typedef std::vector managed_send_buffs_t; - typedef boost::function get_send_buffs_t; - typedef boost::function vrt_packer_t; - - static const boost::uint64_t zeros = 0; - - struct send_state{ - //init the expected seq number - size_t next_packet_seq; - managed_send_buffs_t managed_buffs; - std::vector zero_buffs; - std::vector io_buffs; - - send_state(size_t width = 1): - next_packet_seq(0), - managed_buffs(width), - zero_buffs(width, &zeros), - io_buffs(0) //resized later - { - /* NOP */ - } - }; - - /******************************************************************* - * Pack a vrt header, copy-convert the data, and send it. - * - helper function for vrt_packet_handler::send - ******************************************************************/ - static UHD_INLINE size_t _send1( - send_state &state, - const uhd::device::send_buffs_type &buffs, - const size_t offset_bytes, - const size_t num_samps, - uhd::transport::vrt::if_packet_info_t &if_packet_info, - uhd::convert::function_type &converter, - const vrt_packer_t &vrt_packer, - const get_send_buffs_t &get_send_buffs, - const size_t vrt_header_offset_words32, - const size_t chans_per_otw_buff - ){ - //load the rest of the if_packet_info in here - if_packet_info.num_payload_words32 = (num_samps*chans_per_otw_buff*OTW_BYTES_PER_SAMP)/sizeof(boost::uint32_t); - if_packet_info.packet_count = state.next_packet_seq; - - //get send buffers for each otw channel - if (not get_send_buffs(state.managed_buffs)) return 0; - - for (size_t i = 0; i < buffs.size(); i+=chans_per_otw_buff){ - //calculate pointers with offsets to io and otw memory - for (size_t j = 0; j < chans_per_otw_buff; j++){ - state.io_buffs[j] = reinterpret_cast(buffs[i+j]) + offset_bytes; - } - boost::uint32_t *otw_mem = state.managed_buffs[i]->cast() + vrt_header_offset_words32; - - //pack metadata into a vrt header - vrt_packer(otw_mem, if_packet_info); - otw_mem += if_packet_info.num_header_words32; - - //copy-convert the samples into the send buffer - converter(state.io_buffs, otw_mem, num_samps, 32767.); - - //commit the samples to the zero-copy interface - size_t num_bytes_total = (vrt_header_offset_words32+if_packet_info.num_packet_words32)*sizeof(boost::uint32_t); - state.managed_buffs[i]->commit(num_bytes_total); - } - state.next_packet_seq++; //increment sequence after commits - return num_samps; - } - - /******************************************************************* - * Send vrt packets and copy convert the samples into the buffer. - ******************************************************************/ - static UHD_INLINE size_t send( - send_state &state, - const uhd::device::send_buffs_type &buffs, - const size_t total_num_samps, - const uhd::tx_metadata_t &metadata, - uhd::device::send_mode_t send_mode, - const uhd::io_type_t &io_type, - const uhd::otw_type_t &otw_type, - double tick_rate, - const vrt_packer_t &vrt_packer, - const get_send_buffs_t &get_send_buffs, - size_t max_samples_per_packet, - size_t vrt_header_offset_words32 = 0, - size_t chans_per_otw_buff = 1 - ){ - state.io_buffs.resize(chans_per_otw_buff); - - uhd::convert::function_type converter( - uhd::convert::get_converter_cpu_to_otw( - io_type, otw_type, chans_per_otw_buff, 1 - )); - - //translate the metadata to vrt if packet info - uhd::transport::vrt::if_packet_info_t if_packet_info; - if_packet_info.has_sid = false; - if_packet_info.has_cid = false; - if_packet_info.has_tlr = false; - if_packet_info.tsi = boost::uint32_t(metadata.time_spec.get_full_secs()); - if_packet_info.tsf = boost::uint64_t(metadata.time_spec.get_tick_count(tick_rate)); - - if (total_num_samps <= max_samples_per_packet) send_mode = uhd::device::SEND_MODE_ONE_PACKET; - switch(send_mode){ - - //////////////////////////////////////////////////////////////// - case uhd::device::SEND_MODE_ONE_PACKET:{ - //////////////////////////////////////////////////////////////// - - //fill in parts of the packet info overwrote in full buff mode - if_packet_info.has_tsi = metadata.has_time_spec; - if_packet_info.has_tsf = metadata.has_time_spec; - if_packet_info.sob = metadata.start_of_burst; - if_packet_info.eob = metadata.end_of_burst; - - return _send1( - state, - //TODO remove this code when sample counts of zero are supported by hardware - (total_num_samps)?buffs : state.zero_buffs, 0, - std::max(1, std::min(total_num_samps, max_samples_per_packet)), - if_packet_info, - converter, - vrt_packer, - get_send_buffs, - vrt_header_offset_words32, - chans_per_otw_buff - ); - } - - //////////////////////////////////////////////////////////////// - case uhd::device::SEND_MODE_FULL_BUFF:{ - //////////////////////////////////////////////////////////////// - size_t total_num_samps_sent = 0; - - //loop through the following fragment indexes - while(total_num_samps_sent < total_num_samps){ - - //calculate per-loop-iteration variables - const size_t total_num_samps_unsent = total_num_samps - total_num_samps_sent; - const bool first_fragment = (total_num_samps_sent == 0); - const bool final_fragment = (total_num_samps_unsent <= max_samples_per_packet); - - //calculate new flags for the fragments - if_packet_info.has_tsi = metadata.has_time_spec and first_fragment; - if_packet_info.has_tsf = if_packet_info.has_tsi; - if_packet_info.sob = metadata.start_of_burst and first_fragment; - if_packet_info.eob = metadata.end_of_burst and final_fragment; - - //send the fragment with the helper function - const size_t num_samps_sent = _send1( - state, - buffs, total_num_samps_sent*io_type.size, - std::min(total_num_samps_unsent, max_samples_per_packet), - if_packet_info, - converter, - vrt_packer, - get_send_buffs, - vrt_header_offset_words32, - chans_per_otw_buff - ); - total_num_samps_sent += num_samps_sent; - if (num_samps_sent == 0) return total_num_samps_sent; - } - return total_num_samps_sent; - } - - default: throw std::runtime_error("unknown send mode"); - }//switch(send_mode) - } - -} //namespace vrt_packet_handler - -#endif /* INCLUDED_LIBUHD_TRANSPORT_VRT_PACKET_HANDLER_HPP */ -- cgit v1.2.3 From b092b291082612dca65bd8910feb89856550e3f0 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 12 Jun 2011 20:08:37 -0700 Subject: uhd: fix some warnings under msvc in sph --- host/lib/transport/super_recv_packet_handler.hpp | 6 +++--- host/lib/transport/super_send_packet_handler.hpp | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/host/lib/transport/super_recv_packet_handler.hpp b/host/lib/transport/super_recv_packet_handler.hpp index 78d8dfce8..61b4379b6 100644 --- a/host/lib/transport/super_recv_packet_handler.hpp +++ b/host/lib/transport/super_recv_packet_handler.hpp @@ -192,7 +192,7 @@ public: _converters[io_type] = uhd::convert::get_converter_otw_to_cpu( io_type_t::tid_t(io_type), otw_type, 1, width ); - }catch(const uhd::value_error &e){} //we expect this, not all io_types valid... + }catch(const uhd::value_error &){} //we expect this, not all io_types valid... } _bytes_per_item = otw_type.get_sample_size(); } @@ -520,8 +520,8 @@ private: alignment_check(index, curr_info); std::swap(curr_info, next_info); //save progress from curr -> next curr_info.metadata.has_time_spec = prev_info.metadata.has_time_spec; - curr_info.metadata.time_spec = prev_info.metadata.time_spec + time_spec_t( - 0.0, prev_info[index].ifpi.num_payload_words32*sizeof(boost::uint32_t)/_bytes_per_item, _samp_rate); + curr_info.metadata.time_spec = prev_info.metadata.time_spec + time_spec_t(0, + prev_info[index].ifpi.num_payload_words32*sizeof(boost::uint32_t)/_bytes_per_item, _samp_rate); curr_info.metadata.more_fragments = false; curr_info.metadata.fragment_offset = 0; curr_info.metadata.start_of_burst = false; diff --git a/host/lib/transport/super_send_packet_handler.hpp b/host/lib/transport/super_send_packet_handler.hpp index 99d445180..8ebc264ef 100644 --- a/host/lib/transport/super_send_packet_handler.hpp +++ b/host/lib/transport/super_send_packet_handler.hpp @@ -113,7 +113,7 @@ public: _converters[io_type] = uhd::convert::get_converter_cpu_to_otw( io_type_t::tid_t(io_type), otw_type, 1, width ); - }catch(const uhd::value_error &e){} //we expect this, not all io_types valid... + }catch(const uhd::value_error &){} //we expect this, not all io_types valid... } _bytes_per_item = otw_type.get_sample_size(); } -- cgit v1.2.3 From d04fe45f552daa98be18995674ee34fa24f9652f Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 13 Jun 2011 08:43:07 -0700 Subject: uhd: update packet handlers when the clock rate is changed --- host/lib/usrp/usrp1/mboard_impl.cpp | 1 + host/lib/usrp/usrp2/mboard_impl.cpp | 1 + host/lib/usrp/usrp_e100/mboard_impl.cpp | 1 + 3 files changed, 3 insertions(+) diff --git a/host/lib/usrp/usrp1/mboard_impl.cpp b/host/lib/usrp/usrp1/mboard_impl.cpp index 87911b312..a265a5089 100644 --- a/host/lib/usrp/usrp1/mboard_impl.cpp +++ b/host/lib/usrp/usrp1/mboard_impl.cpp @@ -389,6 +389,7 @@ void usrp1_impl::mboard_set(const wax::obj &key, const wax::obj &val) << "See the application notes for USRP1 for further instructions.\n" ; _clock_ctrl->set_master_clock_freq(val.as()); + this->update_xport_channel_mapping(); return; case MBOARD_PROP_CLOCK_CONFIG:{ diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp index 4a28ea9c4..6bf412a3e 100644 --- a/host/lib/usrp/usrp2/mboard_impl.cpp +++ b/host/lib/usrp/usrp2/mboard_impl.cpp @@ -466,6 +466,7 @@ void usrp2_mboard_impl::set(const wax::obj &key, const wax::obj &val){ case MBOARD_PROP_CLOCK_RATE: UHD_ASSERT_THROW(val.as() == this->get_master_clock_freq()); + _device.update_xport_channel_mapping(); return; default: UHD_THROW_PROP_SET_ERROR(); diff --git a/host/lib/usrp/usrp_e100/mboard_impl.cpp b/host/lib/usrp/usrp_e100/mboard_impl.cpp index 483286e47..f4b8d79f6 100644 --- a/host/lib/usrp/usrp_e100/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e100/mboard_impl.cpp @@ -214,6 +214,7 @@ void usrp_e100_impl::mboard_set(const wax::obj &key, const wax::obj &val){ << "See the application notes for USRP-E1XX for further instructions.\n" ; _clock_ctrl->set_fpga_clock_rate(val.as()); + this->update_xport_channel_mapping(); return; default: UHD_THROW_PROP_SET_ERROR(); -- cgit v1.2.3 From e59b6652d77b5326b5eb813a34bcf3ad51b44750 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 13 Jun 2011 16:12:38 -0700 Subject: uhd: fix for resize routine of super packet handler --- host/lib/transport/super_recv_packet_handler.hpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/host/lib/transport/super_recv_packet_handler.hpp b/host/lib/transport/super_recv_packet_handler.hpp index 61b4379b6..80ad17b6c 100644 --- a/host/lib/transport/super_recv_packet_handler.hpp +++ b/host/lib/transport/super_recv_packet_handler.hpp @@ -135,7 +135,8 @@ public: void resize(const size_t size){ if (this->size() == size) return; _props.resize(size); - _buffers_infos.resize(4, buffers_info_type(size)); + //re-initialize all buffers infos by re-creating the vector + _buffers_infos = std::vector(4, buffers_info_type(size)); } //! Get the channel width of this handler -- cgit v1.2.3 From 8173943ea945e685babe461c682622f1db05a413 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 13 Jun 2011 16:15:50 -0700 Subject: usrp_e100: init the subdev specs before calling io_init --- host/lib/usrp/usrp_e100/usrp_e100_impl.cpp | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp b/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp index e9e9b6e20..01a49c129 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp @@ -171,12 +171,13 @@ usrp_e100_impl::usrp_e100_impl( //init the codec properties codec_init(); - //init the io send/recv - io_init(); - //set default subdev specs this->mboard_set(MBOARD_PROP_RX_SUBDEV_SPEC, subdev_spec_t()); this->mboard_set(MBOARD_PROP_TX_SUBDEV_SPEC, subdev_spec_t()); + + //init the io send/recv + io_init(); + } usrp_e100_impl::~usrp_e100_impl(void){ -- cgit v1.2.3 From a1f36ebf436fccbb6cc81bb5f32a790d444772c2 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 14 Jun 2011 12:27:21 -0700 Subject: uhd: under/over flow app notes --- host/docs/general.rst | 54 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/host/docs/general.rst b/host/docs/general.rst index ff85fb0f9..cc00fc0f9 100644 --- a/host/docs/general.rst +++ b/host/docs/general.rst @@ -60,6 +60,42 @@ Pseudo-code for dealing with settling time after tuning on receive: } usrp->issue_stream_command(...); +------------------------------------------------------------------------ +Overflow/Underflow notes +------------------------------------------------------------------------ +**Note:** The following overflow/underflow notes do not apply to USRP1, +which does not support the advanced features available in newer products. + +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Overflow notes +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +When receiving, the device produces samples at a constant rate. +Overflows occurs when the host does not consume data fast enough. +When UHD detects the overflow, it prints an "O" to stdout, +and pushes an inline message packet into the receive stream. + +**Network-based devices**: +The host does not back-pressure the receive stream. +When the kernel's socket buffer becomes full, it will drop subsequent packets. +UHD detects the overflow as a discontinuity in the packet's sequence numbers, +and muxes an inline message packet into the receive stream. + +**Other devices**: +The host back-pressures the receive stream. +Therefore, overflows always occur in the device itself. +When the device's internal buffers become full, streaming is shutoff, +and an inline message packet is sent to the host. +If the device was in continuous streaming mode, +the UHD will automatically restart streaming. + +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Underflow notes +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +When transmitting, the device consumes samples at a constant rate. +Underflow occurs when the host does not produce data fast enough. +When the UHD detects underflow, it prints an "U" to stdout, +and pushes a message packet into the async message stream. + ------------------------------------------------------------------------ Threading notes ------------------------------------------------------------------------ @@ -114,3 +150,21 @@ For a module to be loaded at runtime, it must be: * found in the UHD_MODULE_PATH environment variable, * installed into the /share/uhd/modules directory, * or installed into /usr/share/uhd/modules directory (unix only). + +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Disabling or redirecting prints to stdout +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +The user can disable the UHD library from printing directly to stdout by registering a custom message handler. +The handler will intercept all messages, which can be dropped or redirected. +Only one handler can be registered at a time. +Make "register_handler" your first call into UHD: + +:: + + #include + + void my_handler(uhd::msg::type_t type, const std::string &msg){ + //handle the message... + } + + uhd::msg::register_handler(&my_handler); -- cgit v1.2.3 From 2d8d1a4d1ad15482e25f52e1fa3ad8ae94490a8e Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 14 Jun 2011 17:44:54 -0700 Subject: uhd: updated images Makefile --- images/Makefile | 94 +++++++++++++++++++++++++++++++++++++-------------------- 1 file changed, 61 insertions(+), 33 deletions(-) diff --git a/images/Makefile b/images/Makefile index 71b46d14e..f2ba21bdc 100644 --- a/images/Makefile +++ b/images/Makefile @@ -114,7 +114,7 @@ endif ######################################################################## ifdef HAS_XTCLSH -_usrp2_fpga_dir = $(TOP_FPGA_DIR)/usrp2/top/u2_rev3 +_usrp2_fpga_dir = $(TOP_FPGA_DIR)/usrp2/top/USRP2 _usrp2_fpga_bin = $(BUILT_IMAGES_DIR)/usrp2_fpga.bin IMAGES_LIST += $(_usrp2_fpga_bin) @@ -126,66 +126,94 @@ $(_usrp2_fpga_bin): $(GLOBAL_DEPS) endif ######################################################################## -# USRP-N200 fpga +# USRP-N200 R2/R3 fpga ######################################################################## ifdef HAS_XTCLSH -_usrp_n200_fpga_dir = $(TOP_FPGA_DIR)/usrp2/top/u2plus -_usrp_n200_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_n200_fpga.bin -IMAGES_LIST += $(_usrp_n200_fpga_bin) +_usrp_n200_r3_fpga_dir = $(TOP_FPGA_DIR)/usrp2/top/N2x0 +_usrp_n200_r3_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_n200_r3_fpga.bin +IMAGES_LIST += $(_usrp_n200_r3_fpga_bin) -$(_usrp_n200_fpga_bin): $(GLOBAL_DEPS) - cd $(_usrp_n200_fpga_dir) && make -f Makefile.N200 clean - cd $(_usrp_n200_fpga_dir) && make -f Makefile.N200 bin - cp $(_usrp_n200_fpga_dir)/build-N200/u2plus.bin $@ +$(_usrp_n200_r3_fpga_bin): $(GLOBAL_DEPS) + cd $(_usrp_n200_r3_fpga_dir) && make -f Makefile.N200R3 clean + cd $(_usrp_n200_r3_fpga_dir) && make -f Makefile.N200R3 bin + cp $(_usrp_n200_r3_fpga_dir)/build-N200R3/u2plus.bin $@ + +#its called r2 on the silkscreen, so make an r2 +_usrp_n200_r2_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_n200_r2_fpga.bin +IMAGES_LIST += $(_usrp_n200_r2_fpga_bin) +$(_usrp_n200_r2_fpga_bin): $(_usrp_n200_r3_fpga_bin) + cp $< $@ endif ######################################################################## -# USRP-N210 fpga +# USRP-N210 R2/R3 fpga ######################################################################## ifdef HAS_XTCLSH -_usrp_n210_fpga_dir = $(TOP_FPGA_DIR)/usrp2/top/u2plus -_usrp_n210_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_n210_fpga.bin -IMAGES_LIST += $(_usrp_n210_fpga_bin) +_usrp_n210_r3_fpga_dir = $(TOP_FPGA_DIR)/usrp2/top/N2x0 +_usrp_n210_r3_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_n210_r3_fpga.bin +IMAGES_LIST += $(_usrp_n210_r3_fpga_bin) + +$(_usrp_n210_r3_fpga_bin): $(GLOBAL_DEPS) + cd $(_usrp_n210_r3_fpga_dir) && make -f Makefile.N210R3 clean + cd $(_usrp_n210_r3_fpga_dir) && make -f Makefile.N210R3 bin + cp $(_usrp_n210_r3_fpga_dir)/build-N210R3/u2plus.bin $@ -$(_usrp_n210_fpga_bin): $(GLOBAL_DEPS) - cd $(_usrp_n210_fpga_dir) && make clean - cd $(_usrp_n210_fpga_dir) && make bin - cp $(_usrp_n210_fpga_dir)/build/u2plus.bin $@ +#its called r2 on the silkscreen, so make an r2 +_usrp_n210_r2_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_n210_r2_fpga.bin +IMAGES_LIST += $(_usrp_n210_r2_fpga_bin) +$(_usrp_n210_r2_fpga_bin): $(_usrp_n210_r3_fpga_bin) + cp $< $@ endif ######################################################################## -# USRP-E100 fpga +# USRP-N200 R4 fpga ######################################################################## ifdef HAS_XTCLSH -_usrp_e100_fpga_dir = $(TOP_FPGA_DIR)/usrp2/top/u1e -_usrp_e100_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_e100_fpga.bin -IMAGES_LIST += $(_usrp_e100_fpga_bin) +_usrp_n200_r4_fpga_dir = $(TOP_FPGA_DIR)/usrp2/top/N2x0 +_usrp_n200_r4_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_n200_r4_fpga.bin +IMAGES_LIST += $(_usrp_n200_r4_fpga_bin) -$(_usrp_e100_fpga_bin): $(GLOBAL_DEPS) - cd $(_usrp_e100_fpga_dir) && make clean - cd $(_usrp_e100_fpga_dir) && make bin - cp $(_usrp_e100_fpga_dir)/build/u1e.bin $@ +$(_usrp_n200_r4_fpga_bin): $(GLOBAL_DEPS) + cd $(_usrp_n200_r4_fpga_dir) && make -f Makefile.N200R4 clean + cd $(_usrp_n200_r4_fpga_dir) && make -f Makefile.N200R4 bin + cp $(_usrp_n200_r4_fpga_dir)/build-N200r4/u2plus.bin $@ + +endif + +######################################################################## +# USRP-N210 R4 fpga +######################################################################## +ifdef HAS_XTCLSH + +_usrp_n210_r4_fpga_dir = $(TOP_FPGA_DIR)/usrp2/top/N2x0 +_usrp_n210_r4_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_n210_r4_fpga.bin +IMAGES_LIST += $(_usrp_n210_r4_fpga_bin) + +$(_usrp_n210_r4_fpga_bin): $(GLOBAL_DEPS) + cd $(_usrp_n210_r4_fpga_dir) && make -f Makefile.N210R4 clean + cd $(_usrp_n210_r4_fpga_dir) && make -f Makefile.N210R4 bin + cp $(_usrp_n210_r4_fpga_dir)/build-N210r4/u2plus.bin $@ endif ######################################################################## -# USRP-E100 pass-through fpga +# USRP-E100 fpga ######################################################################## ifdef HAS_XTCLSH -_usrp_e100_pt_fpga_dir = $(TOP_FPGA_DIR)/usrp2/top/u1e_passthru -_usrp_e100_pt_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_e100_pt_fpga.bin -IMAGES_LIST += $(_usrp_e100_pt_fpga_bin) +_usrp_e100_fpga_dir = $(TOP_FPGA_DIR)/usrp2/top/E1x0 +_usrp_e100_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_e100_fpga.bin +IMAGES_LIST += $(_usrp_e100_fpga_bin) -$(_usrp_e100_pt_fpga_bin): $(GLOBAL_DEPS) - cd $(_usrp_e100_pt_fpga_dir) && make clean - cd $(_usrp_e100_pt_fpga_dir) && make bin - cp $(_usrp_e100_pt_fpga_dir)/build/passthru.bin $@ +$(_usrp_e100_fpga_bin): $(GLOBAL_DEPS) + cd $(_usrp_e100_fpga_dir) && make clean + cd $(_usrp_e100_fpga_dir) && make bin + cp $(_usrp_e100_fpga_dir)/build/u1e.bin $@ endif -- cgit v1.2.3 From deae10bc1c85726ed7c206abca37a869c6f77cea Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 14 Jun 2011 17:15:38 -0700 Subject: b100: added b100 firmware (squashed) --- firmware/fx2/CMakeLists.txt | 2 + firmware/fx2/b100/.gitignore | 19 ++ firmware/fx2/b100/CMakeLists.txt | 88 ++++++ firmware/fx2/b100/board_specific.c | 70 +++++ firmware/fx2/b100/eeprom_io.c | 65 +++++ firmware/fx2/b100/eeprom_io.h | 38 +++ firmware/fx2/b100/fpga_load.c | 193 +++++++++++++ firmware/fx2/b100/fpga_rev2.c | 51 ++++ firmware/fx2/b100/fpga_rev2.h | 44 +++ firmware/fx2/b100/gpif.c | 292 ++++++++++++++++++++ firmware/fx2/b100/usb_descriptors.a51 | 499 ++++++++++++++++++++++++++++++++++ firmware/fx2/b100/usrp_common.c | 108 ++++++++ firmware/fx2/b100/usrp_main.c | 394 +++++++++++++++++++++++++++ firmware/fx2/b100/usrp_regs.h | 126 +++++++++ firmware/fx2/common/fx2regs.h | 4 + firmware/fx2/common/usrp_commands.h | 6 + firmware/fx2/utils/build_eeprom.py | 12 +- firmware/fx2/utils/edit-gpif-b100.py | 120 ++++++++ 18 files changed, 2127 insertions(+), 4 deletions(-) create mode 100644 firmware/fx2/b100/.gitignore create mode 100644 firmware/fx2/b100/CMakeLists.txt create mode 100644 firmware/fx2/b100/board_specific.c create mode 100644 firmware/fx2/b100/eeprom_io.c create mode 100644 firmware/fx2/b100/eeprom_io.h create mode 100644 firmware/fx2/b100/fpga_load.c create mode 100644 firmware/fx2/b100/fpga_rev2.c create mode 100644 firmware/fx2/b100/fpga_rev2.h create mode 100644 firmware/fx2/b100/gpif.c create mode 100644 firmware/fx2/b100/usb_descriptors.a51 create mode 100644 firmware/fx2/b100/usrp_common.c create mode 100644 firmware/fx2/b100/usrp_main.c create mode 100644 firmware/fx2/b100/usrp_regs.h create mode 100755 firmware/fx2/utils/edit-gpif-b100.py diff --git a/firmware/fx2/CMakeLists.txt b/firmware/fx2/CMakeLists.txt index 80f16363f..f7f6e96ca 100644 --- a/firmware/fx2/CMakeLists.txt +++ b/firmware/fx2/CMakeLists.txt @@ -39,9 +39,11 @@ set(CMAKE_C_FLAGS "--no-xinit-opt") ######################################################################## set(REG_GENERATOR ${CMAKE_SOURCE_DIR}/utils/generate_regs.py) set(EDIT_GPIF_USRP1 ${CMAKE_SOURCE_DIR}/utils/edit-gpif.py) +set(EDIT_GPIF_B100 ${CMAKE_SOURCE_DIR}/utils/edit-gpif-b100.py) set(BUILD_EEPROM ${CMAKE_SOURCE_DIR}/utils/build_eeprom.py) ######################################################################## # Add the subdirectories ######################################################################## ADD_SUBDIRECTORY(usrp1) +ADD_SUBDIRECTORY(b100) diff --git a/firmware/fx2/b100/.gitignore b/firmware/fx2/b100/.gitignore new file mode 100644 index 000000000..e27ec2046 --- /dev/null +++ b/firmware/fx2/b100/.gitignore @@ -0,0 +1,19 @@ +/*.ihx +/*.lnk +/*.lst +/*.map +/*.mem +/*.rel +/*.rst +/*.sym +/blink_leds.asm +/usrp_common.asm +/command_loop.asm +/fpga.asm +/*.asm +/Makefile +/Makefile.in +/usrp_gpif.c +/usrp_gpif_inline.h +/Makefile.in +/burn-usrp1p-eeprom diff --git a/firmware/fx2/b100/CMakeLists.txt b/firmware/fx2/b100/CMakeLists.txt new file mode 100644 index 000000000..438aa9207 --- /dev/null +++ b/firmware/fx2/b100/CMakeLists.txt @@ -0,0 +1,88 @@ +# +# Copyright 2010 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + +include_directories(${CMAKE_SOURCE_DIR}/common) + +#for usrp_common.h and the regs files... +set(CMAKE_INCLUDE_CURRENT_DIR ON) + +#now make a lib to link against +set(libb100_sources + ${CMAKE_SOURCE_DIR}/common/delay.c + ${CMAKE_SOURCE_DIR}/common/fx2utils.c + ${CMAKE_SOURCE_DIR}/common/i2c.c + ${CMAKE_SOURCE_DIR}/common/init_gpif.c + ${CMAKE_SOURCE_DIR}/common/isr.c + ${CMAKE_SOURCE_DIR}/common/timer.c + ${CMAKE_SOURCE_DIR}/common/usb_common.c +# ${CMAKE_SOURCE_DIR}/common/spi.c +) + +#file(GLOB libb100_c_sources ${CMAKE_SOURCE_DIR}/common/*.c) +#file(GLOB libb100_a51_sources ${CMAKE_SOURCE_DIR}/common/*.a51) +#list(APPEND libb100_sources ${libb100_c_sources} ${libb100_a51_sources}) + +add_library(libb100 STATIC ${libb100_sources}) + +# edit-gpif hacks up gpif.c for our purposes. no major surgery, just moving stuff around. +set(GPIF_SOURCE ${CMAKE_CURRENT_SOURCE_DIR}/gpif.c) +set(GPIF_SOURCE_OUTPUT ${CMAKE_CURRENT_SOURCE_DIR}/usrp_gpif.c) +set(GPIF_HEADER_OUTPUT ${CMAKE_CURRENT_SOURCE_DIR}/usrp_gpif_inline.h) + +add_custom_command( + OUTPUT ${GPIF_SOURCE_OUTPUT} + DEPENDS ${EDIT_GPIF_B100} + COMMAND ${PYTHON_EXECUTABLE} ${EDIT_GPIF_B100} ${GPIF_SOURCE} ${GPIF_SOURCE_OUTPUT} ${GPIF_HEADER_OUTPUT} + COMMENT "Generating ${GPIF_SOURCE_OUTPUT}" +) + +#file(GLOB b100_sources *.c) +set(b100_sources + ${CMAKE_SOURCE_DIR}/common/vectors.a51 + usrp_main.c + usrp_common.c + board_specific.c + fpga_load.c + fpga_rev2.c + usrp_gpif.c + usb_descriptors.a51 + eeprom_io.c + ${CMAKE_SOURCE_DIR}/common/_startup.a51 +) + +set_source_files_properties( + ${CMAKE_CURRENT_SOURCE_DIR}/usrp_main.c + PROPERTIES COMPILE_FLAGS "--std-sdcc99 --opt-code-speed --fommit-frame-pointer" +) + +add_executable(b100_fw ${b100_sources}) +target_link_libraries(b100_fw libb100) + +set(eeprom1p_sources + ${CMAKE_SOURCE_DIR}/common/eeprom_boot.a51 + ${CMAKE_SOURCE_DIR}/common/eeprom_init.c + ${CMAKE_SOURCE_DIR}/common/_startup.a51 +) + +add_custom_target(b100_eeprom ALL + DEPENDS b100_boot + COMMAND objcopy -I ihex -O binary b100_boot.ihx b100_boot.bin + COMMAND ${PYTHON_EXECUTABLE} ${BUILD_EEPROM} -r2 b100_boot.bin b100_eeprom.bin +) + +add_executable(b100_boot ${eeprom1p_sources}) +target_link_libraries(b100_boot libb100) diff --git a/firmware/fx2/b100/board_specific.c b/firmware/fx2/b100/board_specific.c new file mode 100644 index 000000000..993d925b3 --- /dev/null +++ b/firmware/fx2/b100/board_specific.c @@ -0,0 +1,70 @@ +/* -*- c++ -*- */ +/* + * Copyright 2004 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#include "usrp_common.h" + +void +set_led_0 (unsigned char on) +{ + if (!on) // active low + USRP_PC |= bmPC_LED0; + else + USRP_PC &= ~bmPC_LED0; +} + +void +set_led_1 (unsigned char on) +{ + if (!on) // active low + USRP_PC |= bmPC_LED1; + else + USRP_PC &= ~bmPC_LED1; +} + +void +toggle_led_0 (void) +{ + USRP_PC ^= bmPC_LED0; +} + +void +toggle_led_1 (void) +{ + USRP_PC ^= bmPC_LED1; +} + +void +set_sleep_bits (unsigned char bits, unsigned char mask) +{ + // NOP on usrp1 +} + +static xdata unsigned char xbuf[1]; + +void +init_board (void) +{ + //init_spi (); + + //USRP_PC &= ~bmPC_nRESET; // active low reset + //USRP_PC |= bmPC_nRESET; +} diff --git a/firmware/fx2/b100/eeprom_io.c b/firmware/fx2/b100/eeprom_io.c new file mode 100644 index 000000000..9eeb53636 --- /dev/null +++ b/firmware/fx2/b100/eeprom_io.c @@ -0,0 +1,65 @@ +/* -*- c++ -*- */ +/* + * Copyright 2006 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#include "eeprom_io.h" +#include "i2c.h" +#include "delay.h" + +// returns non-zero if successful, else 0 +unsigned char +eeprom_read (unsigned char i2c_addr, unsigned char eeprom_offset, + xdata unsigned char *buf, unsigned char len) +{ + // We setup a random read by first doing a "zero byte write". + // Writes carry an address. Reads use an implicit address. + + static xdata unsigned char cmd[1]; + cmd[0] = eeprom_offset; + if (!i2c_write(i2c_addr, cmd, 1)) + return 0; + + return i2c_read(i2c_addr, buf, len); +} + + +#if 0 + +// returns non-zero if successful, else 0 +unsigned char +eeprom_write (unsigned char i2c_addr, unsigned char eeprom_offset, + const xdata unsigned char *buf, unsigned char len) +{ + static xdata unsigned char cmd[2]; + unsigned char ok; + + while (len-- > 0){ + cmd[0] = eeprom_offset++; + cmd[1] = *buf++; + ok = i2c_write(i2c_addr, cmd, 2); + mdelay(10); // delay 10ms worst case write time + if (!ok) + return 0; + } + return 1; +} + +#endif diff --git a/firmware/fx2/b100/eeprom_io.h b/firmware/fx2/b100/eeprom_io.h new file mode 100644 index 000000000..558017b12 --- /dev/null +++ b/firmware/fx2/b100/eeprom_io.h @@ -0,0 +1,38 @@ +/* -*- c++ -*- */ +/* + * Copyright 2006 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#ifndef INCLUDED_EEPROM_IO_H +#define INCLUDED_EEPROM_IO_H + + +// returns non-zero if successful, else 0 +unsigned char +eeprom_read (unsigned char i2c_addr, unsigned char eeprom_offset, + xdata unsigned char *buf, unsigned char len); + +// returns non-zero if successful, else 0 +unsigned char +eeprom_write (unsigned char i2c_addr, unsigned char eeprom_offset, + const xdata unsigned char *buf, unsigned char len); + + +#endif /* INCLUDED_EEPROM_IO_H */ diff --git a/firmware/fx2/b100/fpga_load.c b/firmware/fx2/b100/fpga_load.c new file mode 100644 index 000000000..54ef54ab3 --- /dev/null +++ b/firmware/fx2/b100/fpga_load.c @@ -0,0 +1,193 @@ +/* + * USRP - Universal Software Radio Peripheral + * + * Copyright (C) 2003 Free Software Foundation, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA + */ + +#include "usrp_common.h" +#include "fpga_load.h" +#include "delay.h" + +/* + * setup altera FPGA serial load (PS). + * + * On entry: + * don't care + * + * On exit: + * ALTERA_DCLK = 0 + * ALTERA_NCONFIG = 1 + * ALTERA_NSTATUS = 1 (input) + */ +unsigned char +fpga_load_begin (void) +{ + USRP_ALTERA_CONFIG &= ~bmALTERA_BITS; // clear all bits (NCONFIG low) + udelay (40); // wait 40 us + USRP_ALTERA_CONFIG |= bmALTERA_NCONFIG; // set NCONFIG high + + if (UC_BOARD_HAS_FPGA){ + // FIXME should really cap this loop with a counter so we + // don't hang forever on a hardware failure. + while ((USRP_ALTERA_CONFIG & bmALTERA_NSTATUS) == 0) // wait for NSTATUS to go high + ; + } + + // ready to xfer now + + return 1; +} + +/* + * clock out the low bit of bits. + * + * On entry: + * ALTERA_DCLK = 0 + * ALTERA_NCONFIG = 1 + * ALTERA_NSTATUS = 1 (input) + * + * On exit: + * ALTERA_DCLK = 0 + * ALTERA_NCONFIG = 1 + * ALTERA_NSTATUS = 1 (input) + */ + + +#if 0 + +static void +clock_out_config_byte (unsigned char bits) +{ + unsigned char i; + + // clock out configuration byte, least significant bit first + + for (i = 0; i < 8; i++){ + + USRP_ALTERA_CONFIG = ((USRP_ALTERA_CONFIG & ~bmALTERA_DATA0) | ((bits & 1) ? bmALTERA_DATA0 : 0)); + USRP_ALTERA_CONFIG |= bmALTERA_DCLK; /* set DCLK to 1 */ + USRP_ALTERA_CONFIG &= ~bmALTERA_DCLK; /* set DCLK to 0 */ + + bits = bits >> 1; + } +} + +#else + +static void +clock_out_config_byte (unsigned char bits) _naked +{ + _asm + mov a, dpl + + rlc a + mov _bitALTERA_DATA0,c + setb _bitALTERA_DCLK + clr _bitALTERA_DCLK + + rlc a + mov _bitALTERA_DATA0,c + setb _bitALTERA_DCLK + clr _bitALTERA_DCLK + + rlc a + mov _bitALTERA_DATA0,c + setb _bitALTERA_DCLK + clr _bitALTERA_DCLK + + rlc a + mov _bitALTERA_DATA0,c + setb _bitALTERA_DCLK + clr _bitALTERA_DCLK + + rlc a + mov _bitALTERA_DATA0,c + setb _bitALTERA_DCLK + clr _bitALTERA_DCLK + + rlc a + mov _bitALTERA_DATA0,c + setb _bitALTERA_DCLK + clr _bitALTERA_DCLK + + rlc a + mov _bitALTERA_DATA0,c + setb _bitALTERA_DCLK + clr _bitALTERA_DCLK + + rlc a + mov _bitALTERA_DATA0,c + setb _bitALTERA_DCLK + clr _bitALTERA_DCLK + + ret + + _endasm; +} + +#endif + +static void +clock_out_bytes (unsigned char bytecount, + unsigned char xdata *p) +{ + while (bytecount-- > 0) + clock_out_config_byte (*p++); +} + +/* + * Transfer block of bytes from packet to FPGA serial configuration port + * + * On entry: + * ALTERA_DCLK = 0 + * ALTERA_NCONFIG = 1 + * ALTERA_NSTATUS = 1 (input) + * + * On exit: + * ALTERA_DCLK = 0 + * ALTERA_NCONFIG = 1 + * ALTERA_NSTATUS = 1 (input) + */ +unsigned char +fpga_load_xfer (xdata unsigned char *p, unsigned char bytecount) +{ + clock_out_bytes (bytecount, p); + return 1; +} + +/* + * check for successful load... + */ +unsigned char +fpga_load_end (void) +{ + unsigned char status = USRP_ALTERA_CONFIG; + + if (!UC_BOARD_HAS_FPGA) // always true if we don't have FPGA + return 1; + + if ((status & bmALTERA_NSTATUS) == 0) // failed to program + return 0; + + if ((status & bmALTERA_CONF_DONE) == bmALTERA_CONF_DONE) + return 1; // everything's cool + + // I don't think this should happen. It indicates that + // programming is still in progress. + + return 0; +} diff --git a/firmware/fx2/b100/fpga_rev2.c b/firmware/fx2/b100/fpga_rev2.c new file mode 100644 index 000000000..326a01732 --- /dev/null +++ b/firmware/fx2/b100/fpga_rev2.c @@ -0,0 +1,51 @@ +/* -*- c++ -*- */ +/* + * Copyright 2004 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#include "fpga.h" +#include "fpga_regs_common.h" +#include "usrp_common.h" +#include "usrp_globals.h" + +unsigned char g_tx_reset = 0; +unsigned char g_rx_reset = 0; + +void +fpga_write_reg (unsigned char regno, const xdata unsigned char *regval) +{ + //nop +} + + +static xdata unsigned char regval[4] = {0, 0, 0, 0}; + +// Resets both AD9862's and the FPGA serial bus interface. + +void +fpga_set_reset (unsigned char on) +{ + on &= 0x1; + + if (on){ + } + else + ; +} diff --git a/firmware/fx2/b100/fpga_rev2.h b/firmware/fx2/b100/fpga_rev2.h new file mode 100644 index 000000000..0773d1cd7 --- /dev/null +++ b/firmware/fx2/b100/fpga_rev2.h @@ -0,0 +1,44 @@ +/* + * USRP - Universal Software Radio Peripheral + * + * Copyright (C) 2003,2004 Free Software Foundation, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA + */ + +#ifndef INCLUDED_FPGA_REV1_H +#define INCLUDED_FPGA_REV1_H + +/* + * return TRUE if FPGA internal fifo has room for a single packet + */ +#define fpga_has_room_for_data_packet() (!(GPIFREADYSTAT & bmDATA_FIFO_FULL)) +#define fpga_has_room_for_ctrl_packet() (!(GPIFREADYSTAT & bmCTRL_FIFO_FULL)) + +/* + * return TRUE if FPGA internal fifo has at least one packet available + */ +#define fpga_has_data_packet_avail() (!(GPIFREADYSTAT & bmDATA_EMPTY)) +#define fpga_has_ctrl_packet_avail() (!(GPIFREADYSTAT & bmCTRL_EMPTY)) + +#define fx2_has_ctrl_packet_avail() (!(EP24FIFOFLGS & EP4FIFOEMPTY)) +#define fx2_has_data_packet_avail() (!(EP24FIFOFLGS & EP2FIFOEMPTY)) + +#define fx2_has_room_for_ctrl_packet() (!(EP8CS & bmEPFULL)) +#define fx2_has_room_for_data_packet() (!(EP6CS & bmEPFULL)) + +#define fx2_gpif_is_idle() (GPIFTRIG & bmGPIF_IDLE) + +#endif /* INCLUDED_FPGA_REV1_H */ diff --git a/firmware/fx2/b100/gpif.c b/firmware/fx2/b100/gpif.c new file mode 100644 index 000000000..b499e4fcf --- /dev/null +++ b/firmware/fx2/b100/gpif.c @@ -0,0 +1,292 @@ +// This program configures the General Programmable Interface (GPIF) for FX2. +// Please do not modify sections of text which are marked as "DO NOT EDIT ...". +// +// DO NOT EDIT ... +// GPIF Initialization +// Interface Timing Async +// Internal Ready Init IntRdy=1 +// CTL Out Tristate-able Binary +// SingleWrite WF Select 1 +// SingleRead WF Select 0 +// FifoWrite WF Select 3 +// FifoRead WF Select 2 +// Data Bus Idle Drive Tristate +// END DO NOT EDIT + +// DO NOT EDIT ... +// GPIF Wave Names +// Wave 0 = singlerd +// Wave 1 = singlewr +// Wave 2 = FIFORd +// Wave 3 = FIFOWr + +// GPIF Ctrl Outputs Level +// CTL 0 = WEN# CMOS +// CTL 1 = REN# CMOS +// CTL 2 = OE# CMOS +// CTL 3 = EP CMOS +// CTL 4 = unused CMOS +// CTL 5 = unused CMOS + +// GPIF Rdy Inputs +// RDY0 = EF# +// RDY1 = FF# +// RDY2 = DRDY +// RDY3 = CRDY +// RDY4 = unused +// RDY5 = TCXpire +// FIFOFlag = FIFOFlag +// IntReady = IntReady +// END DO NOT EDIT +// DO NOT EDIT ... +// +// GPIF Waveform 0: singlerd +// +// Interval 0 1 2 3 4 5 6 Idle (7) +// _________ _________ _________ _________ _________ _________ _________ _________ +// +// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val +// DataMode NO Data NO Data NO Data NO Data NO Data NO Data NO Data +// NextData SameData SameData SameData SameData SameData SameData SameData +// Int Trig No Int No Int No Int No Int No Int No Int No Int +// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 +// Term A +// LFunc +// Term B +// Branch1 +// Branch0 +// Re-Exec +// Sngl/CRC Default Default Default Default Default Default Default +// WEN# 0 0 0 0 0 0 0 0 +// REN# 0 0 0 0 0 0 0 0 +// OE# 0 0 0 0 0 0 0 0 +// CLRST 0 0 0 0 0 0 0 0 +// unused 0 0 0 0 0 0 0 0 +// BOGUS 0 0 0 0 0 0 0 0 +// +// END DO NOT EDIT +// DO NOT EDIT ... +// +// GPIF Waveform 1: singlewr +// +// Interval 0 1 2 3 4 5 6 Idle (7) +// _________ _________ _________ _________ _________ _________ _________ _________ +// +// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val +// DataMode Activate Activate Activate Activate Activate Activate Activate +// NextData SameData SameData SameData SameData SameData SameData SameData +// Int Trig No Int No Int No Int No Int No Int No Int No Int +// IF/Wait Wait 1 IF Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 +// Term A EF# +// LFunc AND +// Term B EF# +// Branch1 ThenIdle +// Branch0 ElseIdle +// Re-Exec No +// Sngl/CRC Default Default Default Default Default Default Default +// WEN# 0 1 1 1 1 1 1 0 +// REN# 0 0 0 0 0 0 0 0 +// OE# 0 0 0 0 0 0 0 0 +// CLRST 0 0 0 0 0 0 0 0 +// unused 0 0 0 0 0 0 0 0 +// BOGUS 0 0 0 0 0 0 0 0 +// +// END DO NOT EDIT +// DO NOT EDIT ... +// +// GPIF Waveform 2: FIFORd +// +// Interval 0 1 2 3 4 5 6 Idle (7) +// _________ _________ _________ _________ _________ _________ _________ _________ +// +// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val +// DataMode NO Data Activate NO Data NO Data NO Data NO Data NO Data +// NextData SameData SameData SameData SameData SameData SameData SameData +// Int Trig No Int No Int No Int No Int No Int No Int No Int +// IF/Wait Wait 1 IF Wait 1 IF Wait 1 Wait 1 Wait 1 +// Term A TCXpire TCXpire +// LFunc AND AND +// Term B TCXpire TCXpire +// Branch1 Then 2 ThenIdle +// Branch0 Else 1 ElseIdle +// Re-Exec No No +// Sngl/CRC Default Default Default Default Default Default Default +// WEN# 0 0 0 0 0 0 0 0 +// REN# 1 0 0 0 0 0 0 0 +// OE# 1 1 1 0 0 0 0 0 +// CLRST 0 0 0 0 0 0 0 0 +// unused 0 0 0 0 0 0 0 0 +// BOGUS 0 0 0 0 0 0 0 0 +// +// END DO NOT EDIT +// DO NOT EDIT ... +// +// GPIF Waveform 3: FIFOWr +// +// Interval 0 1 2 3 4 5 6 Idle (7) +// _________ _________ _________ _________ _________ _________ _________ _________ +// +// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val +// DataMode NO Data Activate Activate Activate Activate Activate Activate +// NextData SameData SameData SameData SameData SameData SameData SameData +// Int Trig No Int No Int No Int No Int No Int No Int No Int +// IF/Wait Wait 1 IF Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 +// Term A TCXpire +// LFunc AND +// Term B TCXpire +// Branch1 ThenIdle +// Branch0 Else 1 +// Re-Exec No +// Sngl/CRC Default Default Default Default Default Default Default +// WEN# 0 0 0 0 0 0 0 0 +// REN# 0 0 0 0 0 0 0 0 +// OE# 0 0 0 0 0 0 0 0 +// CLRST 0 0 0 0 0 0 0 0 +// unused 0 0 0 0 0 0 0 0 +// BOGUS 0 0 0 0 0 0 0 0 +// +// END DO NOT EDIT + +// GPIF Program Code + +// DO NOT EDIT ... +#include "fx2.h" +#include "fx2regs.h" +#include "fx2sdly.h" // SYNCDELAY macro +// END DO NOT EDIT + +// DO NOT EDIT ... +const char xdata WaveData[128] = +{ +// Wave 0 +/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07, +/* Opcode*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* Output*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, +// Wave 1 +/* LenBr */ 0x01, 0x3F, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07, +/* Opcode*/ 0x22, 0x03, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00, +/* Output*/ 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, +/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, +// Wave 2 +/* LenBr */ 0x01, 0x11, 0x01, 0x3F, 0x01, 0x01, 0x01, 0x07, +/* Opcode*/ 0x00, 0x03, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, +/* Output*/ 0x06, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, +/* LFun */ 0x00, 0x2D, 0x00, 0x2D, 0x00, 0x00, 0x00, 0x3F, +// Wave 3 +/* LenBr */ 0x01, 0x39, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07, +/* Opcode*/ 0x00, 0x03, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00, +/* Output*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* LFun */ 0x00, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, +}; +// END DO NOT EDIT + +// DO NOT EDIT ... +const char xdata FlowStates[36] = +{ +/* Wave 0 FlowStates */ 0x81,0x2D,0x0E,0x00,0x00,0x04,0x03,0x02,0x00, +/* Wave 1 FlowStates */ 0x81,0x2D,0x09,0x00,0x00,0x04,0x03,0x02,0x00, +/* Wave 2 FlowStates */ 0x81,0x2D,0x06,0x00,0x00,0x04,0x03,0x02,0x00, +/* Wave 3 FlowStates */ 0x81,0x2D,0x01,0x00,0x00,0x04,0x03,0x02,0x00, +}; +// END DO NOT EDIT + +// DO NOT EDIT ... +const char xdata InitData[7] = +{ +/* Regs */ 0xA0,0x00,0x00,0x00,0xEE,0x4E,0x00 +}; +// END DO NOT EDIT + +// TO DO: You may add additional code below. + +void GpifInit( void ) +{ + BYTE i; + + // Registers which require a synchronization delay, see section 15.14 + // FIFORESET FIFOPINPOLAR + // INPKTEND OUTPKTEND + // EPxBCH:L REVCTL + // GPIFTCB3 GPIFTCB2 + // GPIFTCB1 GPIFTCB0 + // EPxFIFOPFH:L EPxAUTOINLENH:L + // EPxFIFOCFG EPxGPIFFLGSEL + // PINFLAGSxx EPxFIFOIRQ + // EPxFIFOIE GPIFIRQ + // GPIFIE GPIFADRH:L + // UDMACRCH:L EPxGPIFTRIG + // GPIFTRIG + + // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well... + // ...these have been replaced by GPIFTC[B3:B0] registers + + // 8051 doesn't have access to waveform memories 'til + // the part is in GPIF mode. + + IFCONFIG = 0xEE; + // IFCLKSRC=1 , FIFOs executes on internal clk source + // xMHz=1 , 48MHz internal clk rate + // IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz + // IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk + // ASYNC=1 , master samples asynchronous + // GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF + // IFCFG[1:0]=10, FX2 in GPIF master mode + + GPIFABORT = 0xFF; // abort any waveforms pending + + GPIFREADYCFG = InitData[ 0 ]; + GPIFCTLCFG = InitData[ 1 ]; + GPIFIDLECS = InitData[ 2 ]; + GPIFIDLECTL = InitData[ 3 ]; + GPIFWFSELECT = InitData[ 5 ]; + GPIFREADYSTAT = InitData[ 6 ]; + + // use dual autopointer feature... + AUTOPTRSETUP = 0x07; // inc both pointers, + // ...warning: this introduces pdata hole(s) + // ...at E67B (XAUTODAT1) and E67C (XAUTODAT2) + + // source + AUTOPTRH1 = MSB( &WaveData ); + AUTOPTRL1 = LSB( &WaveData ); + + // destination + AUTOPTRH2 = 0xE4; + AUTOPTRL2 = 0x00; + + // transfer + for ( i = 0x00; i < 128; i++ ) + { + EXTAUTODAT2 = EXTAUTODAT1; + } + +// Configure GPIF Address pins, output initial value, + PORTCCFG = 0xFF; // [7:0] as alt. func. GPIFADR[7:0] + OEC = 0xFF; // and as outputs + PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8] + OEE |= 0x80; // and as output + +// ...OR... tri-state GPIFADR[8:0] pins +// PORTCCFG = 0x00; // [7:0] as port I/O +// OEC = 0x00; // and as inputs +// PORTECFG &= 0x7F; // [8] as port I/O +// OEE &= 0x7F; // and as input + +// GPIF address pins update when GPIFADRH/L written + SYNCDELAY; // + GPIFADRH = 0x00; // bits[7:1] always 0 + SYNCDELAY; // + GPIFADRL = 0x00; // point to PERIPHERAL address 0x0000 + +// Configure GPIF FlowStates registers for Wave 0 of WaveData + FLOWSTATE = FlowStates[ 0 ]; + FLOWLOGIC = FlowStates[ 1 ]; + FLOWEQ0CTL = FlowStates[ 2 ]; + FLOWEQ1CTL = FlowStates[ 3 ]; + FLOWHOLDOFF = FlowStates[ 4 ]; + FLOWSTB = FlowStates[ 5 ]; + FLOWSTBEDGE = FlowStates[ 6 ]; + FLOWSTBHPERIOD = FlowStates[ 7 ]; +} + diff --git a/firmware/fx2/b100/usb_descriptors.a51 b/firmware/fx2/b100/usb_descriptors.a51 new file mode 100644 index 000000000..cc71833fe --- /dev/null +++ b/firmware/fx2/b100/usb_descriptors.a51 @@ -0,0 +1,499 @@ +;;; -*- asm -*- +;;; +;;; Copyright 2003 Free Software Foundation, Inc. +;;; +;;; This file is part of GNU Radio +;;; +;;; GNU Radio is free software; you can redistribute it and/or modify +;;; it under the terms of the GNU General Public License as published by +;;; the Free Software Foundation; either version 3, or (at your option) +;;; any later version. +;;; +;;; GNU Radio is distributed in the hope that it will be useful, +;;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;;; GNU General Public License for more details. +;;; +;;; You should have received a copy of the GNU General Public License +;;; along with GNU Radio; see the file COPYING. If not, write to +;;; the Free Software Foundation, Inc., 51 Franklin Street, +;;; Boston, MA 02110-1301, USA. +;;; + +;;; USB Descriptor table for the B100 +;;; +;;; We're a high-speed only device (480 Mb/sec) with 1 configuration +;;; and 5 interfaces. +;;; +;;; interface 0: command and status (ep0 COMMAND) +;;; interface 1: Transmit path (ep2 OUT BULK) +;;; interface 2: Receive path (ep6 IN BULK) + +;;; interface 3: Command transmit path (ep4 OUT BULK) for FPGA comms +;;; interface 4: Command receive path (ep8 IN BULK) for FPGA comms + + .module usb_descriptors + + VID_FREE = 0x2500 ; Free Software Folks + PID_USRP = 0x0001 ; B100 + + ;; We distinguish configured from unconfigured USRPs using the Device ID. + ;; If the MSB of the DID is 0, the device is unconfigured. + ;; The LSB of the DID is reserved for hardware revs. + + DID_USRP = 0x0100 ; Device ID (bcd) + + + DSCR_DEVICE = 1 ; Descriptor type: Device + DSCR_CONFIG = 2 ; Descriptor type: Configuration + DSCR_STRING = 3 ; Descriptor type: String + DSCR_INTRFC = 4 ; Descriptor type: Interface + DSCR_ENDPNT = 5 ; Descriptor type: Endpoint + DSCR_DEVQUAL = 6 ; Descriptor type: Device Qualifier + + DSCR_DEVICE_LEN = 18 + DSCR_CONFIG_LEN = 9 + DSCR_INTRFC_LEN = 9 + DSCR_ENDPNT_LEN = 7 + DSCR_DEVQUAL_LEN = 10 + + ET_CONTROL = 0 ; Endpoint type: Control + ET_ISO = 1 ; Endpoint type: Isochronous + ET_BULK = 2 ; Endpoint type: Bulk + ET_INT = 3 ; Endpoint type: Interrupt + + + ;; configuration attributes + bmSELF_POWERED = 1 << 6 + +;;; -------------------------------------------------------- +;;; external ram data +;;;-------------------------------------------------------- + + .area USBDESCSEG (XDATA) + +;;; ---------------------------------------------------------------- +;;; descriptors used when operating at high speed (480Mb/sec) +;;; ---------------------------------------------------------------- + + .even ; descriptors must be 2-byte aligned for SUDPTR{H,L} to work + + ;; The .even directive isn't really honored by the linker. Bummer! + ;; (There's no way to specify an alignment requirement for a given area, + ;; hence when they're concatenated together, even doesn't work.) + ;; + ;; We work around this by telling the linker to put USBDESCSEG + ;; at 0xE000 absolute. This means that the maximimum length of this + ;; segment is 480 bytes, leaving room for the two hash slots + ;; at 0xE1EO to 0xE1FF. + ;; + ;; As of July 7, 2004, this segment is 326 bytes long + ;; As of Sept 2, 2010, this segment is 416 bytes long + +_high_speed_device_descr:: + .db DSCR_DEVICE_LEN + .db DSCR_DEVICE + .db <0x0200 ; Specification version (LSB) + .db >0x0200 ; Specification version (MSB) + .db 0xff ; device class (vendor specific) + .db 0xff ; device subclass (vendor specific) + .db 0xff ; device protocol (vendor specific) + .db 64 ; bMaxPacketSize0 for endpoint 0 + .db VID_FREE ; idVendor + .db PID_USRP ; idProduct +_usb_desc_hw_rev_binary_patch_location_0:: + .db DID_USRP ; bcdDevice + .db SI_VENDOR ; iManufacturer (string index) + .db SI_PRODUCT ; iProduct (string index) + .db SI_SERIAL ; iSerial number (string index) + .db 1 ; bNumConfigurations + +;;; describes the other speed (12Mb/sec) + .even +_high_speed_devqual_descr:: + .db DSCR_DEVQUAL_LEN + .db DSCR_DEVQUAL + .db <0x0200 ; bcdUSB (LSB) + .db >0x0200 ; bcdUSB (MSB) + .db 0xff ; bDeviceClass + .db 0xff ; bDeviceSubClass + .db 0xff ; bDeviceProtocol + .db 64 ; bMaxPacketSize0 + .db 1 ; bNumConfigurations (one config at 12Mb/sec) + .db 0 ; bReserved + + .even +_high_speed_config_descr:: + .db DSCR_CONFIG_LEN + .db DSCR_CONFIG + .db <(_high_speed_config_descr_end - _high_speed_config_descr) ; LSB + .db >(_high_speed_config_descr_end - _high_speed_config_descr) ; MSB + .db 5 ; bNumInterfaces + .db 1 ; bConfigurationValue + .db 0 ; iConfiguration + .db 0x80 | bmSELF_POWERED ; bmAttributes + .db 0 ; bMaxPower + + ;; interface descriptor 0 (command & status, ep0 COMMAND) + + .db DSCR_INTRFC_LEN + .db DSCR_INTRFC + .db 0 ; bInterfaceNumber (zero based) + .db 0 ; bAlternateSetting + .db 0 ; bNumEndpoints + .db 0xff ; bInterfaceClass (vendor specific) + .db 0xff ; bInterfaceSubClass (vendor specific) + .db 0xff ; bInterfaceProtocol (vendor specific) + .db SI_COMMAND_AND_STATUS ; iInterface (description) + + ;; interface descriptor 1 (transmit path, ep2 OUT BULK) + + .db DSCR_INTRFC_LEN + .db DSCR_INTRFC + .db 1 ; bInterfaceNumber (zero based) + .db 0 ; bAlternateSetting + .db 1 ; bNumEndpoints + .db 0xff ; bInterfaceClass (vendor specific) + .db 0xff ; bInterfaceSubClass (vendor specific) + .db 0xff ; bInterfaceProtocol (vendor specific) + .db SI_TX_PATH ; iInterface (description) + + ;; interface 1's end point + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x02 ; bEndpointAddress (ep 2 OUT) + .db ET_BULK ; bmAttributes + .db <512 ; wMaxPacketSize (LSB) + .db >512 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + + ;; interface descriptor 2 (receive path, ep6 IN BULK) + + .db DSCR_INTRFC_LEN + .db DSCR_INTRFC + .db 2 ; bInterfaceNumber (zero based) + .db 0 ; bAlternateSetting + .db 1 ; bNumEndpoints + .db 0xff ; bInterfaceClass (vendor specific) + .db 0xff ; bInterfaceSubClass (vendor specific) + .db 0xff ; bInterfaceProtocol (vendor specific) + .db SI_RX_PATH ; iInterface (description) + + ;; interface 2's end point + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x86 ; bEndpointAddress (ep 6 IN) + .db ET_BULK ; bmAttributes + .db <512 ; wMaxPacketSize (LSB) + .db >512 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + + ;; interface descriptor 3 (FPGA command OUT path, ep4 OUT BULK) + + .db DSCR_INTRFC_LEN + .db DSCR_INTRFC + .db 3 ; bInterfaceNumber (zero based) + .db 0 ; bAlternateSetting + .db 1 ; bNumEndpoints + .db 0xff ; bInterfaceClass (vendor specific) + .db 0xff ; bInterfaceSubClass (vendor specific) + .db 0xff ; bInterfaceProtocol (vendor specific) + .db SI_FPGA_COMMAND_OUT_PATH ; iInterface (description) + + ;; interface 3's end point + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x04 ; bEndpointAddress (ep 4 OUT) + .db ET_BULK ; bmAttributes + .db <32 ; wMaxPacketSize (LSB) + .db >32 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + + ;; interface descriptor 4 (FPGA command IN path, ep8 IN BULK) + + .db DSCR_INTRFC_LEN + .db DSCR_INTRFC + .db 4 ; bInterfaceNumber (zero based) + .db 0 ; bAlternateSetting + .db 1 ; bNumEndpoints + .db 0xff ; bInterfaceClass (vendor specific) + .db 0xff ; bInterfaceSubClass (vendor specific) + .db 0xff ; bInterfaceProtocol (vendor specific) + .db SI_FPGA_COMMAND_IN_PATH ; iInterface (description) + + ;; interface 4's end point + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x88 ; bEndpointAddress (ep 8 IN) + .db ET_BULK ; bmAttributes + .db <32 ; wMaxPacketSize (LSB) + .db >32 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + + +_high_speed_config_descr_end: + +;;; ---------------------------------------------------------------- +;;; descriptors used when operating at full speed (12Mb/sec) +;;; ---------------------------------------------------------------- + + .even +_full_speed_device_descr:: + .db DSCR_DEVICE_LEN + .db DSCR_DEVICE + .db <0x0200 ; Specification version (LSB) + .db >0x0200 ; Specification version (MSB) + .db 0xff ; device class (vendor specific) + .db 0xff ; device subclass (vendor specific) + .db 0xff ; device protocol (vendor specific) + .db 64 ; bMaxPacketSize0 for endpoint 0 + .db VID_FREE ; idVendor + .db PID_USRP ; idProduct +_usb_desc_hw_rev_binary_patch_location_1:: + .db DID_USRP ; bcdDevice + .db SI_VENDOR ; iManufacturer (string index) + .db SI_PRODUCT ; iProduct (string index) + .db SI_NONE ; iSerial number (None) + .db 1 ; bNumConfigurations + + +;;; describes the other speed (480Mb/sec) + .even +_full_speed_devqual_descr:: + .db DSCR_DEVQUAL_LEN + .db DSCR_DEVQUAL + .db <0x0200 ; bcdUSB + .db >0x0200 ; bcdUSB + .db 0xff ; bDeviceClass + .db 0xff ; bDeviceSubClass + .db 0xff ; bDeviceProtocol + .db 64 ; bMaxPacketSize0 + .db 1 ; bNumConfigurations (one config at 480Mb/sec) + .db 0 ; bReserved + + .even +_full_speed_config_descr:: + .db DSCR_CONFIG_LEN + .db DSCR_CONFIG + .db <(_full_speed_config_descr_end - _full_speed_config_descr) ; LSB + .db >(_full_speed_config_descr_end - _full_speed_config_descr) ; MSB + .db 1 ; bNumInterfaces + .db 1 ; bConfigurationValue + .db 0 ; iConfiguration + .db 0x80 | bmSELF_POWERED ; bmAttributes + .db 0 ; bMaxPower + + ;; interface descriptor 0 (command & status, ep0 COMMAND) + + .db DSCR_INTRFC_LEN + .db DSCR_INTRFC + .db 0 ; bInterfaceNumber (zero based) + .db 0 ; bAlternateSetting + .db 0 ; bNumEndpoints + .db 0xff ; bInterfaceClass (vendor specific) + .db 0xff ; bInterfaceSubClass (vendor specific) + .db 0xff ; bInterfaceProtocol (vendor specific) + .db SI_COMMAND_AND_STATUS ; iInterface (description) + +_full_speed_config_descr_end: + +;;; ---------------------------------------------------------------- +;;; string descriptors +;;; ---------------------------------------------------------------- + +_nstring_descriptors:: + .db (_string_descriptors_end - _string_descriptors) / 2 + +_string_descriptors:: + .db str0 + .db str1 + .db str2 + .db str3 + .db str4 + .db str5 + .db str6 + .db str7 + .db str8 +_string_descriptors_end: + + SI_NONE = 0 + ;; str0 contains the language ID's. + .even +str0: .db str0_end - str0 + .db DSCR_STRING + .db 0 + .db 0 + .db <0x0409 ; magic code for US English (LSB) + .db >0x0409 ; magic code for US English (MSB) +str0_end: + + SI_VENDOR = 1 + .even +str1: .db str1_end - str1 + .db DSCR_STRING + .db 'F, 0 ; 16-bit unicode + .db 'r, 0 + .db 'e, 0 + .db 'e, 0 + .db ' , 0 + .db 'S, 0 + .db 'o, 0 + .db 'f, 0 + .db 't, 0 + .db 'w, 0 + .db 'a, 0 + .db 'r, 0 + .db 'e, 0 + .db ' , 0 + .db 'F, 0 + .db 'o, 0 + .db 'l, 0 + .db 'k, 0 + .db 's, 0 +str1_end: + + SI_PRODUCT = 2 + .even +str2: .db str2_end - str2 + .db DSCR_STRING + .db 'U, 0 + .db 'S, 0 + .db 'R, 0 + .db 'P, 0 + .db '1, 0 + .db 'P, 0 + .db ' , 0 + .db 'R, 0 + .db 'e, 0 + .db 'v, 0 + .db ' , 0 +_usb_desc_hw_rev_ascii_patch_location_0:: + .db '?, 0 +str2_end: + + SI_COMMAND_AND_STATUS = 3 + .even +str3: .db str3_end - str3 + .db DSCR_STRING + .db 'C, 0 + .db 'o, 0 + .db 'm, 0 + .db 'm, 0 + .db 'a, 0 + .db 'n, 0 + .db 'd, 0 + .db ' , 0 + .db '&, 0 + .db ' , 0 + .db 'S, 0 + .db 't, 0 + .db 'a, 0 + .db 't, 0 + .db 'u, 0 + .db 's, 0 +str3_end: + + SI_TX_PATH = 4 + .even +str4: .db str4_end - str4 + .db DSCR_STRING + .db 'T, 0 + .db 'r, 0 + .db 'a, 0 + .db 'n, 0 + .db 's, 0 + .db 'm, 0 + .db 'i, 0 + .db 't, 0 + .db ' , 0 + .db 'P, 0 + .db 'a, 0 + .db 't, 0 + .db 'h, 0 +str4_end: + + SI_RX_PATH = 5 + .even +str5: .db str5_end - str5 + .db DSCR_STRING + .db 'R, 0 + .db 'e, 0 + .db 'c, 0 + .db 'e, 0 + .db 'i, 0 + .db 'v, 0 + .db 'e, 0 + .db ' , 0 + .db 'P, 0 + .db 'a, 0 + .db 't, 0 + .db 'h, 0 +str5_end: + + SI_SERIAL = 6 + .even +str6: .db str6_end - str6 + .db DSCR_STRING +_usb_desc_serial_number_ascii:: + .db '3, 0 + .db '., 0 + .db '1, 0 + .db '4, 0 + .db '1, 0 + .db '5, 0 + .db '9, 0 + .db '3, 0 +str6_end: + + SI_FPGA_COMMAND_OUT_PATH = 7 + .even +str7: .db str7_end - str7 + .db DSCR_STRING + .db 'F, 0 + .db 'P, 0 + .db 'G, 0 + .db 'A, 0 + .db ' , 0 + .db 'C, 0 + .db 'o, 0 + .db 'm, 0 + .db 'm, 0 + .db 'a, 0 + .db 'n, 0 + .db 'd, 0 + .db ' , 0 + .db 'O, 0 + .db 'u, 0 + .db 't, 0 +str7_end: + + SI_FPGA_COMMAND_IN_PATH = 8 + .even +str8: .db str8_end - str8 + .db DSCR_STRING + .db 'F, 0 + .db 'P, 0 + .db 'G, 0 + .db 'A, 0 + .db ' , 0 + .db 'C, 0 + .db 'o, 0 + .db 'm, 0 + .db 'm, 0 + .db 'a, 0 + .db 'n, 0 + .db 'd, 0 + .db ' , 0 + .db 'I, 0 + .db 'n, 0 +str8_end: diff --git a/firmware/fx2/b100/usrp_common.c b/firmware/fx2/b100/usrp_common.c new file mode 100644 index 000000000..4b6dde881 --- /dev/null +++ b/firmware/fx2/b100/usrp_common.c @@ -0,0 +1,108 @@ +/* + * USRP - Universal Software Radio Peripheral + * + * Copyright (C) 2003 Free Software Foundation, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA + */ + +/* + * common code for USRP + */ + +#include "usrp_common.h" + +void init_board (void); + +void +init_usrp (void) +{ + CPUCS = bmCLKSPD1; // CPU runs @ 48 MHz + CKCON = 0; // MOVX takes 2 cycles + + // IFCLK is generated internally and runs at 48 MHz; GPIF "master mode" + + IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmIFCLKPOL | bmIFGPIF; + SYNCDELAY; + + // configure IO ports (B and D are used by GPIF) + + IOA = bmPORT_A_INITIAL; // Port A initial state + OEA = bmPORT_A_OUTPUTS; // Port A direction register + + IOC = bmPORT_C_INITIAL; // Port C initial state + OEC = bmPORT_C_OUTPUTS; // Port C direction register + + IOE = bmPORT_E_INITIAL; // Port E initial state + OEE = bmPORT_E_OUTPUTS; // Port E direction register + + + //REVCTL = bmDYN_OUT | bmENH_PKT; // highly recommended by docs + // SYNCDELAY; + + // configure end points + + EP1OUTCFG = bmVALID | bmBULK; SYNCDELAY; + EP1INCFG = bmVALID | bmBULK | bmIN; SYNCDELAY; + + EP2CFG = bmVALID | bmBULK | bmDOUBLEBUF; SYNCDELAY; // 512 dbl bulk OUT + EP4CFG = bmVALID | bmBULK | bmDOUBLEBUF; SYNCDELAY; // 512 dbl bulk OUT + EP6CFG = bmVALID | bmBULK | bmDOUBLEBUF | bmIN; SYNCDELAY; // 512 dbl bulk IN + EP8CFG = bmVALID | bmBULK | bmDOUBLEBUF | bmIN; SYNCDELAY; // 512 dbl bulk IN + + // reset FIFOs + + FIFORESET = bmNAKALL; SYNCDELAY; + FIFORESET = 2; SYNCDELAY; + FIFORESET = 4; SYNCDELAY; + FIFORESET = 6; SYNCDELAY; + FIFORESET = 8; SYNCDELAY; + FIFORESET = 0; SYNCDELAY; + + // configure end point FIFOs + + // let core see 0 to 1 transistion of autoout bit + + EP2FIFOCFG = bmWORDWIDE; SYNCDELAY; + EP2FIFOCFG = bmAUTOOUT | bmWORDWIDE; SYNCDELAY; + EP6FIFOCFG = bmZEROLENIN | bmWORDWIDE; SYNCDELAY; + //EP6FIFOCFG = bmWORDWIDE; SYNCDELAY; + EP4FIFOCFG = bmWORDWIDE; SYNCDELAY; + EP4FIFOCFG = bmAUTOOUT | bmWORDWIDE; SYNCDELAY; + EP8FIFOCFG = bmAUTOIN | bmWORDWIDE; SYNCDELAY; + + EP0BCH = 0; SYNCDELAY; + + // arm EP1OUT so we can receive "out" packets (TRM pg 8-8) + + EP1OUTBC = 0; SYNCDELAY; + + EP2GPIFFLGSEL = 0x00; SYNCDELAY; // For EP2OUT, GPIF uses EF flag + EP6GPIFFLGSEL = 0x00; SYNCDELAY; // For EP6IN, GPIF uses FF flag + EP4GPIFFLGSEL = 0x00; SYNCDELAY; + EP8GPIFFLGSEL = 0x00; SYNCDELAY; + + // set autoin length for EP6 + // FIXME should be f(enumeration) + + EP6AUTOINLENH = (512) >> 8; SYNCDELAY; // this is the length for high speed + EP6AUTOINLENL = (512) & 0xff; SYNCDELAY; + + EP8AUTOINLENH = (32) >> 8; SYNCDELAY; + EP8AUTOINLENL = (32) & 0xff; SYNCDELAY; + + init_board (); +} + diff --git a/firmware/fx2/b100/usrp_main.c b/firmware/fx2/b100/usrp_main.c new file mode 100644 index 000000000..7558fadb8 --- /dev/null +++ b/firmware/fx2/b100/usrp_main.c @@ -0,0 +1,394 @@ +/* + * USRP - Universal Software Radio Peripheral + * + * Copyright (C) 2003,2004 Free Software Foundation, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA + */ + +#include "usrp_common.h" +#include "usrp_commands.h" +#include "fpga.h" +#include "usrp_gpif_inline.h" +#include "timer.h" +#include "i2c.h" +#include "isr.h" +#include "usb_common.h" +#include "fx2utils.h" +#include "usrp_globals.h" +#include "usrp_i2c_addr.h" +#include +#include "eeprom_io.h" +#include "usb_descriptors.h" + +/* + * offsets into boot eeprom for configuration values + */ +#define HW_REV_OFFSET 5 +#define SERIAL_NO_OFFSET 248 +#define SERIAL_NO_LEN 8 + + +#define bRequestType SETUPDAT[0] +#define bRequest SETUPDAT[1] +#define wValueL SETUPDAT[2] +#define wValueH SETUPDAT[3] +#define wIndexL SETUPDAT[4] +#define wIndexH SETUPDAT[5] +#define wLengthL SETUPDAT[6] +#define wLengthH SETUPDAT[7] + + +unsigned char g_tx_enable = 0; +unsigned char g_rx_enable = 0; +unsigned char g_rx_overrun = 0; +unsigned char g_tx_underrun = 0; +bit enable_gpif = 0; + +/* + * the host side fpga loader code pushes an MD5 hash of the bitstream + * into hash1. + */ +#define USRP_HASH_SIZE 16 +xdata at USRP_HASH_SLOT_1_ADDR unsigned char hash1[USRP_HASH_SIZE]; + +void clear_fpga_data_fifo(void); + +static void +get_ep0_data (void) +{ + EP0BCL = 0; // arm EP0 for OUT xfer. This sets the busy bit + + while (EP0CS & bmEPBUSY) // wait for busy to clear + ; +} + +static void initialize_gpif_buffer(int ep) { + //clear the GPIF buffers on startup to keep crap out of the data path + FIFORESET = 0x80; SYNCDELAY; //activate NAKALL + FIFORESET = ep; SYNCDELAY; + FIFORESET = 0x00; SYNCDELAY; +} + +/* + * Handle our "Vendor Extension" commands on endpoint 0. + * If we handle this one, return non-zero. + */ +unsigned char +app_vendor_cmd (void) +{ + if (bRequestType == VRT_VENDOR_IN){ + + ///////////////////////////////// + // handle the IN requests + ///////////////////////////////// + + switch (bRequest){ + + case VRQ_GET_STATUS: //this is no longer done via FX2 -- the FPGA will be queried instead + return 0; + break; + + case VRQ_I2C_READ: + if (!i2c_read (wValueL, EP0BUF, wLengthL)) return 0; + EP0BCH = 0; + EP0BCL = wLengthL; + break; + + case VRQ_SPI_READ: + return 0; + + case VRQ_FW_COMPAT: + EP0BCH = 0; + EP0BCL = 2; + break; + + default: + return 0; + } + } + + else if (bRequestType == VRT_VENDOR_OUT){ + + ///////////////////////////////// + // handle the OUT requests + ///////////////////////////////// + + switch (bRequest){ + + case VRQ_SET_LED: + switch (wIndexL){ + case 0: + set_led_0 (wValueL); + break; + + case 1: + set_led_1 (wValueL); + break; + + default: + return 0; + } + break; + + case VRQ_FPGA_LOAD: + switch (wIndexL){ // sub-command + case FL_BEGIN: + return fpga_load_begin (); + + case FL_XFER: + get_ep0_data (); + return fpga_load_xfer (EP0BUF, EP0BCL); + + case FL_END: + return fpga_load_end (); + + default: + return 0; + } + break; + + case VRQ_FPGA_SET_RESET: + //fpga_set_reset (wValueL); + break; + + case VRQ_I2C_WRITE: + get_ep0_data (); + if (!i2c_write (wValueL, EP0BUF, EP0BCL)) return 0; + //USRP_LED_REG ^= bmLED1; + break; + + case VRQ_RESET_GPIF: + initialize_gpif_buffer(wValueL); + break; + + case VRQ_ENABLE_GPIF: + enable_gpif = (wValueL != 0) ? 1 : 0; + set_led_1(enable_gpif); + break; + + case VRQ_CLEAR_FPGA_FIFO: + clear_fpga_data_fifo(); + break; + + default: + return 0; + } + + } + else + return 0; // invalid bRequestType + + return 1; +} + +static int short_pkt_state = 0; +#define SHORT_PACKET_DETECTED (short_pkt_state != bitSHORT_PACKET_SIGNAL) + +//yes, this is a little opaque +//basically this is necessary because while all the logic to inform the FPGA +//of what we're trying to do via the CTL pins is contained within the flowstates, +//we need to assert the endpoint select pin one clock cycle before the flowstate starts. +//this is the job of the wave descriptor. rather than switch between waves, since that +//involves a little more setup, we just modify the wave table on the fly. +inline static void setup_wave_data_read(void) { + GPIF_WAVE_DATA[80] = 0x06; + GPIF_WAVE_DATA[81] = 0x06; +} + +inline static void setup_wave_ctrl_read(void) { + GPIF_WAVE_DATA[80] = 0x0E; + GPIF_WAVE_DATA[81] = 0x0E; +} + +inline static void setup_wave_data_write(void) { + GPIF_WAVE_DATA[112] = 0x00; + GPIF_WAVE_DATA[113] = 0x00; +} + +inline static void setup_wave_ctrl_write(void) { + GPIF_WAVE_DATA[112] = 0x08; + GPIF_WAVE_DATA[113] = 0x08; +} + +inline static void handle_data_write(void) { + GPIFTCB1 = 0x01; //SYNCDELAY; + GPIFTCB0 = 0x00; + setup_flowstate_data_write (); + setup_wave_data_write(); + GPIFTRIG = bmGPIF_EP2_START | bmGPIF_WRITE; // start the xfer + SYNCDELAY; + while (!(GPIFTRIG & bmGPIF_IDLE)); +} + +inline static void handle_ctrl_write(void) { + GPIFTCB1 = 0x00; + GPIFTCB0 = 0x10; + setup_flowstate_ctrl_write (); + setup_wave_ctrl_write(); + GPIFTRIG = bmGPIF_EP4_START | bmGPIF_WRITE; // start the xfer + SYNCDELAY; + while (!(GPIFTRIG & bmGPIF_IDLE)); +} + +inline static void handle_data_read(void) { + GPIFTCB1 = 0x01; + GPIFTCB0 = 0x00; + setup_flowstate_data_read (); + setup_wave_data_read(); + short_pkt_state = bitSHORT_PACKET_SIGNAL; + GPIFTRIG = bmGPIF_EP6_START | bmGPIF_READ; // start the xfer + SYNCDELAY; + while (!(GPIFTRIG & bmGPIF_IDLE)); + INPKTEND = 0x06; // tell USB we filled buffer (6 is our endpoint num) + SYNCDELAY; + if(SHORT_PACKET_DETECTED) { + while(!(EP6CS & bmEPEMPTY)); //wait for packet to send + INPKTEND = 0x06; //send a ZLP + //toggle_led_1(); //FIXME DEBUG + } +} + +inline static void handle_ctrl_read(void) { + GPIFTCB1 = 0x00; + GPIFTCB0 = 0x10; + setup_flowstate_ctrl_read (); + setup_wave_ctrl_read(); + GPIFTRIG = bmGPIF_EP8_START | bmGPIF_READ; // start the xfer + SYNCDELAY; + while (!(GPIFTRIG & bmGPIF_IDLE)); + INPKTEND = 8; // tell USB we filled buffer (8 is our endpoint num) +} + +//clear the FPGA datapath by reading but not submitting, instead clearing the FIFO after each transaction +void clear_fpga_data_fifo(void) { + while(fpga_has_data_packet_avail()) { + GPIFTCB1 = 0x01; + GPIFTCB0 = 0x00; + setup_flowstate_data_read (); + setup_wave_data_read(); + GPIFTRIG = bmGPIF_EP6_START | bmGPIF_READ; // start the xfer + SYNCDELAY; + while (!(GPIFTRIG & bmGPIF_IDLE)); + initialize_gpif_buffer(6); //reset the FIFO instead of committing it + } +} + +static void +main_loop (void) +{ + while (1){ + if (usb_setup_packet_avail ()) + usb_handle_setup_packet (); + + if(enable_gpif){ + if (fx2_has_ctrl_packet_avail() && fpga_has_room_for_ctrl_packet()) handle_ctrl_write(); + if (fx2_has_room_for_ctrl_packet() && fpga_has_ctrl_packet_avail()) handle_ctrl_read(); + + //we do this + if (fx2_has_data_packet_avail() && fpga_has_room_for_data_packet()) handle_data_write(); + if (fx2_has_room_for_data_packet() && fpga_has_data_packet_avail()) handle_data_read(); + //five times so that + if (fx2_has_data_packet_avail() && fpga_has_room_for_data_packet()) handle_data_write(); + if (fx2_has_room_for_data_packet() && fpga_has_data_packet_avail()) handle_data_read(); + //we can piggyback + if (fx2_has_data_packet_avail() && fpga_has_room_for_data_packet()) handle_data_write(); + if (fx2_has_room_for_data_packet() && fpga_has_data_packet_avail()) handle_data_read(); + //data transfers + if (fx2_has_data_packet_avail() && fpga_has_room_for_data_packet()) handle_data_write(); + if (fx2_has_room_for_data_packet() && fpga_has_data_packet_avail()) handle_data_read(); + //without loop overhead + if (fx2_has_data_packet_avail() && fpga_has_room_for_data_packet()) handle_data_write(); + if (fx2_has_room_for_data_packet() && fpga_has_data_packet_avail()) handle_data_read(); + } + } +} + +/* + * called at 100 Hz from timer2 interrupt + * + * Toggle led 0 + */ +void +isr_tick (void) interrupt +{ + static unsigned char count = 1; + + if (--count == 0){ + count = 50; + USRP_LED_REG ^= bmLED0; + } + + clear_timer_irq (); +} + +/* + * Read h/w rev code and serial number out of boot eeprom and + * patch the usb descriptors with the values. + */ +void +patch_usb_descriptors(void) +{ + static xdata unsigned char hw_rev; + static xdata unsigned char serial_no[8]; + unsigned char i; + + eeprom_read(I2C_ADDR_BOOT, HW_REV_OFFSET, &hw_rev, 1); // LSB of device id + usb_desc_hw_rev_binary_patch_location_0[0] = hw_rev; + usb_desc_hw_rev_binary_patch_location_1[0] = hw_rev; + usb_desc_hw_rev_ascii_patch_location_0[0] = hw_rev + '0'; // FIXME if we get > 9 + + eeprom_read(I2C_ADDR_BOOT, SERIAL_NO_OFFSET, serial_no, SERIAL_NO_LEN); + + for (i = 0; i < SERIAL_NO_LEN; i++){ + unsigned char ch = serial_no[i]; + if (ch == 0xff) // make unprogrammed EEPROM default to '0' + ch = '0'; + usb_desc_serial_number_ascii[i << 1] = ch; + } +} + +void +main (void) +{ + enable_gpif = 0; + + memset (hash1, 0, USRP_HASH_SIZE); // zero fpga bitstream hash. This forces reload + + init_usrp (); + init_gpif (); + + // if (UC_START_WITH_GSTATE_OUTPUT_ENABLED) + //IFCONFIG |= bmGSTATE; // no conflict, start with it on + + set_led_0 (0); + set_led_1 (0); + + EA = 0; // disable all interrupts + + patch_usb_descriptors(); + + setup_autovectors (); + usb_install_handlers (); + //hook_timer_tick ((unsigned short) isr_tick); + + EIEX4 = 1; // disable INT4 FIXME + EA = 1; // global interrupt enable + + fx2_renumerate (); // simulates disconnect / reconnect + + setup_flowstate_common(); + main_loop (); +} diff --git a/firmware/fx2/b100/usrp_regs.h b/firmware/fx2/b100/usrp_regs.h new file mode 100644 index 000000000..775b5dfd3 --- /dev/null +++ b/firmware/fx2/b100/usrp_regs.h @@ -0,0 +1,126 @@ +/* + * USRP - Universal Software Radio Peripheral + * + * Copyright (C) 2003 Free Software Foundation, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA + */ + +/* + * These are the register definitions for the Rev 1 USRP prototype + * The Rev 1 is the version with the AD9862's and daughterboards + */ + +#ifndef _B100_REGS_H_ +#define _B100_REGS_H_ + +#include "fx2regs.h" + +/* + * Port A (bit addressable): + */ + +#define USRP_PA IOA // Port A +#define USRP_PA_OE OEA // Port A direction register + +#define USRP_ALTERA_CONFIG USRP_PA // Now on port A, not C + +#define bmALTERA_DCLK bmBIT0 +#define bmALTERA_NCONFIG bmBIT1 +#define bmALTERA_DATA0 bmBIT3 +#define bmALTERA_NSTATUS bmBIT4 +#define bmALTERA_CONF_DONE bmBIT5 +#define bmRESET_FPGA_FIFOS bmBIT7 + + +#define bmALTERA_BITS (bmALTERA_DCLK \ + | bmALTERA_NCONFIG \ + | bmALTERA_DATA0 \ + | bmALTERA_NSTATUS \ + | bmALTERA_CONF_DONE \ + ) + + +#define bmPORT_A_OUTPUTS (bmALTERA_DCLK \ + | bmALTERA_NCONFIG \ + | bmALTERA_DATA0 \ + ) + +#define bmPORT_A_INITIAL 0 + +sbit at 0x80+0 bitALTERA_DCLK; // 0x80 is the bit address of PORT A +sbit at 0x80+2 bitSHORT_PACKET_SIGNAL; +sbit at 0x80+3 bitALTERA_DATA0; + + +/* Port B: GPIF FD[7:0] */ + +/* + * Port C (bit addressable): + * 5:1 FPGA configuration + */ + +#define USRP_PC IOC // Port C +#define USRP_PC_OE OEC // Port C direction register + +#define bmPC_nRESET 0 //bmBIT0 // reset line to codecs (active low) +#define bmPC_LED0 bmBIT0 // active low +#define bmPC_LED1 bmBIT1 // active low + +#define bmPORT_C_OUTPUTS (bmPC_LED0 | bmPC_LED1) +#define bmPORT_C_INITIAL (bmPC_LED0 | bmPC_LED1) + + +#define USRP_LED_REG USRP_PC +#define bmLED0 bmPC_LED0 +#define bmLED1 bmPC_LED1 + + +/* Port D: GPIF FD[15:8] */ + +/* Port E: not bit addressible */ + +#define USRP_PE IOE // Port E +#define USRP_PE_OE OEE // Port E direction register + +#define bmPORT_E_OUTPUTS (0) +#define bmPORT_E_INITIAL (0) + +/* + * FPGA output lines that are tied to FX2 RDYx inputs. + * These are readable using GPIFREADYSTAT. + */ +//#define bmFPGA_HAS_SPACE bmBIT0 // usbrdy[0] has room for 512 byte packet +//#define bmFPGA_PKT_AVAIL bmBIT1 // usbrdy[1] has >= 512 bytes available + +#define bmDATA_EMPTY bmBIT0 //data output FIFO has no data ready +#define bmDATA_FIFO_FULL bmBIT1 //data input FIFO is full +#define bmCTRL_EMPTY bmBIT2 //control output FIFO has no data ready +#define bmCTRL_FIFO_FULL bmBIT3 //control input FIFO is full + +// #define bmTX_UNDERRUN bmBIT2 // usbrdy[2] D/A ran out of data +// #define bmRX_OVERRUN bmBIT3 // usbrdy[3] A/D ran out of buffer + +/* + * FPGA input lines that are tied to the FX2 CTLx outputs. + * + * These are controlled by the GPIF microprogram... + */ +// WE bmBIT0 // usbctl[0] write enable +// RE bmBIT1 // usbctl[1] read enable +// OE bmBIT2 // usbctl[2] output enable +// EP bmBIT3 // usbctl[3] endpoint select (data/ctrl) + +#endif /* _USRP_REV1_REGS_H_ */ diff --git a/firmware/fx2/common/fx2regs.h b/firmware/fx2/common/fx2regs.h index 2f210f567..aa44791d0 100644 --- a/firmware/fx2/common/fx2regs.h +++ b/firmware/fx2/common/fx2regs.h @@ -664,6 +664,10 @@ sfr at 0xF8 EIP; // EIP Bit Values differ from Reg320 // must be zero bmBIT1 #define bmWORDWIDE bmBIT0 +/* EP 24 FIFO Flag bits (EP24FIFOFLGS) */ +#define EP2FIFOEMPTY bmBIT1 +#define EP4FIFOEMPTY bmBIT5 + /* * Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specific features */ diff --git a/firmware/fx2/common/usrp_commands.h b/firmware/fx2/common/usrp_commands.h index 20c28e264..2466729b2 100644 --- a/firmware/fx2/common/usrp_commands.h +++ b/firmware/fx2/common/usrp_commands.h @@ -54,6 +54,8 @@ // wIndexL: format // len: how much to read +#define VRQ_FW_COMPAT 0x83 //low 16 bits + // OUT commands #define VRQ_SET_LED 0x01 // wValueL off/on {0,1}; wIndexL: which {0,1} @@ -87,6 +89,10 @@ #define VRQ_FPGA_SET_TX_RESET 0x0a // wValueL: {0, 1} #define VRQ_FPGA_SET_RX_RESET 0x0b // wValueL: {0, 1} +#define VRQ_RESET_GPIF 0x0c +#define VRQ_ENABLE_GPIF 0x0d +#define VRQ_CLEAR_FPGA_FIFO 0x0e + // ------------------------------------------------------------------- // we store the hashes at fixed addresses in the FX2 internal memory diff --git a/firmware/fx2/utils/build_eeprom.py b/firmware/fx2/utils/build_eeprom.py index 298ccc00c..af425554a 100755 --- a/firmware/fx2/utils/build_eeprom.py +++ b/firmware/fx2/utils/build_eeprom.py @@ -27,8 +27,10 @@ from optparse import OptionParser # USB Vendor and Product ID's -VID = 0xfffe # Free Software Folks - +USRP1VID = 0xfffe # Free Software Folks +USRP1PID = 0x0002 +USRP1PVID= 0x2500 # Ettus Research +USRP1PPID= 0x0001 def msb (x): return (x >> 8) & 0xff @@ -50,9 +52,11 @@ def build_eeprom_image (filename, rev): start_addr = 0 #prove me wrong if(rev == 1): - PID = 0x0002 #USRP1 + VID = USRP1VID + PID = USRP1PPID else: - PID = 0x0003 #USRP1P + VID = USRP1PVID + PID = USRP1PPID rom_header = [ 0xC2, # boot from EEPROM diff --git a/firmware/fx2/utils/edit-gpif-b100.py b/firmware/fx2/utils/edit-gpif-b100.py new file mode 100755 index 000000000..fd949cd8a --- /dev/null +++ b/firmware/fx2/utils/edit-gpif-b100.py @@ -0,0 +1,120 @@ +#!/usr/bin/env python +# -*- Python -*- +# +# Copyright 2003 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + + +# Edit the gpif.c file generated by the Cypress GPIF Designer Tool and +# produce usrp_gpif.c, and usrp_gpif_inline.h, files suitable for our +# uses. + +import re +import string +import sys + +def check_flow_state (line, flow_state_dict): + mo = re.match (r'/\* Wave (\d) FlowStates \*/ (.*),', line) + if mo: + wave = int (mo.group (1)) + data = mo.group (2) + split = data.split (',', 8) + v = map (lambda x : int (x, 16), split) + # print "%s, %s" % (wave, data) + # print "split: ", split + # print "v : ", v + flow_state_dict[wave] = v + + +def delta (xseq, yseq): + # set subtraction + z = [] + for x in xseq: + if x not in yseq: + z.append (x) + return z + + +def write_define (output, name, pairs): + output.write ('#define %s()\t\\\n' % name) + output.write ('do {\t\t\t\t\t\\\n') + for reg, val in pairs: + output.write ('%14s = 0x%02x;\t\t\t\\\n' % (reg, val)) + output.write ('} while (0)\n\n') + +def write_inlines (output, dict): + regs = ['FLOWSTATE', 'FLOWLOGIC', 'FLOWEQ0CTL', 'FLOWEQ1CTL', 'FLOWHOLDOFF', + 'FLOWSTB', 'FLOWSTBEDGE', 'FLOWSTBHPERIOD', 'GPIFHOLDAMOUNT'] + + READ_CTRL_FLOW_STATE = 0 + WRITE_CTRL_FLOW_STATE = 1 + READ_DATA_FLOW_STATE = 2 + WRITE_DATA_FLOW_STATE = 3 + + read_data_info = zip (regs, dict[READ_DATA_FLOW_STATE]) + write_data_info = zip (regs, dict[WRITE_DATA_FLOW_STATE]) + read_ctrl_info = zip (regs, dict[READ_CTRL_FLOW_STATE]) + write_ctrl_info = zip (regs, dict[WRITE_CTRL_FLOW_STATE]) + + output.write ('''/* + * Machine generated by "edit-gpif". Do not edit by hand. + */ + +''') + write_define (output, 'setup_flowstate_common', read_data_info) #assumes that the same registers will change, this isn't really good + write_define (output, 'setup_flowstate_data_read', delta (read_data_info, write_data_info)) + write_define (output, 'setup_flowstate_data_write', delta (write_data_info, read_data_info)) + write_define (output, 'setup_flowstate_ctrl_read', delta (read_ctrl_info, write_ctrl_info)) + write_define (output, 'setup_flowstate_ctrl_write', delta (write_ctrl_info, read_ctrl_info)) + + +def edit_gpif (input_name, output_name, inline_name): + input = open (input_name, 'r') + output = open (output_name, 'w') + inline = open (inline_name, 'w') + flow_state_dict = {} + + output.write ('''/* + * Machine generated by "edit-gpif". Do not edit by hand. + */ + +''') + + while 1: + line = input.readline () + line = string.replace (line, '\r','') + line = re.sub (r' *$', r'', line) + + check_flow_state (line, flow_state_dict) + + line = re.sub (r'#include', r'// #include', line) + line = re.sub (r'xdata ', r'', line) + if re.search (r'GpifInit', line): + break + + output.write (line) + + output.close () + write_inlines (inline, flow_state_dict) + inline.close () + + +# gpif.c usrp_gpif.c usrp_gpif_inline.h +edit_gpif (sys.argv[1], sys.argv[2], sys.argv[3]) -- cgit v1.2.3 From 5dfc458188538a32f95c05f860587d2c542e14c1 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 14 Jun 2011 17:25:22 -0700 Subject: b100: added b100 host (squashed) --- host/docs/CMakeLists.txt | 1 + host/docs/index.rst | 1 + host/docs/usrp_b1xx.rst | 76 ++++ host/include/uhd/transport/usb_zero_copy.hpp | 21 +- host/lib/transport/CMakeLists.txt | 1 + host/lib/transport/libusb1_zero_copy.cpp | 33 +- host/lib/transport/usb_zero_copy_wrapper.cpp | 202 +++++++++++ host/lib/usrp/CMakeLists.txt | 1 + host/lib/usrp/dboard/db_basic_and_lf.cpp | 2 + host/lib/usrp/fx2/fx2_ctrl.hpp | 2 +- host/lib/usrp/usrp_b100/CMakeLists.txt | 47 +++ host/lib/usrp/usrp_b100/b100_ctrl.cpp | 245 +++++++++++++ host/lib/usrp/usrp_b100/b100_ctrl.hpp | 69 ++++ host/lib/usrp/usrp_b100/b100_iface.cpp | 336 +++++++++++++++++ host/lib/usrp/usrp_b100/b100_iface.hpp | 73 ++++ host/lib/usrp/usrp_b100/b100_impl.cpp | 277 ++++++++++++++ host/lib/usrp/usrp_b100/b100_impl.hpp | 204 +++++++++++ host/lib/usrp/usrp_b100/b100_regs.hpp | 264 ++++++++++++++ host/lib/usrp/usrp_b100/clock_ctrl.cpp | 525 +++++++++++++++++++++++++++ host/lib/usrp/usrp_b100/clock_ctrl.hpp | 118 ++++++ host/lib/usrp/usrp_b100/codec_ctrl.cpp | 283 +++++++++++++++ host/lib/usrp/usrp_b100/codec_ctrl.hpp | 90 +++++ host/lib/usrp/usrp_b100/codec_impl.cpp | 149 ++++++++ host/lib/usrp/usrp_b100/ctrl_packet.hpp | 75 ++++ host/lib/usrp/usrp_b100/dboard_iface.cpp | 298 +++++++++++++++ host/lib/usrp/usrp_b100/dboard_impl.cpp | 185 ++++++++++ host/lib/usrp/usrp_b100/dsp_impl.cpp | 189 ++++++++++ host/lib/usrp/usrp_b100/io_impl.cpp | 210 +++++++++++ host/lib/usrp/usrp_b100/mboard_impl.cpp | 246 +++++++++++++ host/lib/usrp/usrp_e100/usrp_e100_impl.cpp | 2 +- host/utils/usrp1p_gpif_loopback.cpp | 111 ++++++ host/utils/usrp1p_poketest.cpp | 134 +++++++ 32 files changed, 4456 insertions(+), 14 deletions(-) create mode 100644 host/docs/usrp_b1xx.rst create mode 100644 host/lib/transport/usb_zero_copy_wrapper.cpp create mode 100644 host/lib/usrp/usrp_b100/CMakeLists.txt create mode 100644 host/lib/usrp/usrp_b100/b100_ctrl.cpp create mode 100644 host/lib/usrp/usrp_b100/b100_ctrl.hpp create mode 100644 host/lib/usrp/usrp_b100/b100_iface.cpp create mode 100644 host/lib/usrp/usrp_b100/b100_iface.hpp create mode 100644 host/lib/usrp/usrp_b100/b100_impl.cpp create mode 100644 host/lib/usrp/usrp_b100/b100_impl.hpp create mode 100644 host/lib/usrp/usrp_b100/b100_regs.hpp create mode 100644 host/lib/usrp/usrp_b100/clock_ctrl.cpp create mode 100644 host/lib/usrp/usrp_b100/clock_ctrl.hpp create mode 100644 host/lib/usrp/usrp_b100/codec_ctrl.cpp create mode 100644 host/lib/usrp/usrp_b100/codec_ctrl.hpp create mode 100644 host/lib/usrp/usrp_b100/codec_impl.cpp create mode 100644 host/lib/usrp/usrp_b100/ctrl_packet.hpp create mode 100644 host/lib/usrp/usrp_b100/dboard_iface.cpp create mode 100644 host/lib/usrp/usrp_b100/dboard_impl.cpp create mode 100644 host/lib/usrp/usrp_b100/dsp_impl.cpp create mode 100644 host/lib/usrp/usrp_b100/io_impl.cpp create mode 100644 host/lib/usrp/usrp_b100/mboard_impl.cpp create mode 100644 host/utils/usrp1p_gpif_loopback.cpp create mode 100644 host/utils/usrp1p_poketest.cpp diff --git a/host/docs/CMakeLists.txt b/host/docs/CMakeLists.txt index 5926e062e..88afb9c98 100644 --- a/host/docs/CMakeLists.txt +++ b/host/docs/CMakeLists.txt @@ -30,6 +30,7 @@ SET(manual_sources transport.rst usrp1.rst usrp2.rst + usrp_b1xx.rst usrp_e1xx.rst ) diff --git a/host/docs/index.rst b/host/docs/index.rst index 40fe64599..b4ebdad6c 100644 --- a/host/docs/index.rst +++ b/host/docs/index.rst @@ -24,6 +24,7 @@ Application Notes * `USRP1 Application Notes <./usrp1.html>`_ * `USRP2 Application Notes <./usrp2.html>`_ * `USRP-N2XX Series Application Notes <./usrp2.html>`_ +* `USRP-B1XX Series Application Notes <./usrp_b1xx.html>`_ * `USRP-E1XX Series Application Notes <./usrp_e1xx.html>`_ * `Daughterboard Application Notes <./dboards.html>`_ * `Transport Application Notes <./transport.html>`_ diff --git a/host/docs/usrp_b1xx.rst b/host/docs/usrp_b1xx.rst new file mode 100644 index 000000000..2f7385070 --- /dev/null +++ b/host/docs/usrp_b1xx.rst @@ -0,0 +1,76 @@ +======================================================================== +UHD - USRP-B1XX Series Application Notes +======================================================================== + +.. contents:: Table of Contents + +------------------------------------------------------------------------ +Specify a non-standard image +------------------------------------------------------------------------ +The UHD will automatically select the USRP B-Series images from the installed images package. +The image selection can be overridden with the "fpga" and "fw" device address parameters. + +Example device address string representations to specify non-standard images: + +:: + + fpga=usrp_b100_fpga_firmware.bin + + -- OR -- + + fw=usrp_b100_fw_firmware.ihx + +------------------------------------------------------------------------ +Changing the master clock rate +------------------------------------------------------------------------ +The master clock rate of the USRP embedded feeds both the FPGA DSP and the codec chip. +Hundreds of rates between 32MHz and 64MHz are available. +A few notable rates are: + +* 64MHz - maximum rate of the codec chip +* 61.44MHz - good for UMTS/WCDMA applications +* 52Mhz - good for GSM applications + +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Set 61.44MHz - uses external VCXO +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +To use the 61.44MHz clock rate, the USRP embedded will require two jumpers to be moved. + +* J16 is a two pin header, remove the jumper (or leave it on pin1 only) +* J15 is a three pin header, move the jumper to (pin1, pin2) + +**Note:** See instructions below to communicate the desired clock rate into the UHD. + +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Set other rates - uses internal VCO +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +To use other clock rates, the jumpers will need to be in the default position. + +* J16 is a two pin header, move the jumper to (pin1, pin2) +* J15 is a three pin header, move the jumper to (pin2, pin3) + +To communicate the desired clock rate into the UHD, +specify the a special device address argument, +where the key is "master_clock_rate" and the value is a rate in Hz. +Example: +:: + + uhd_usrp_probe --args="master_clock_rate=52e6" + +------------------------------------------------------------------------ +OS specific notes +------------------------------------------------------------------------ + +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Linux - setup udev +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +On Linux, udev handles USB plug and unplug events. +The following commands create a udev rule for the B100 +so that non-root users may access the device: + +:: + + echo 'ACTION=="add", BUS=="usb", SYSFS{idVendor}=="2500", SYSFS{idProduct}=="0001", MODE:="0666"' > tmpfile + sudo chown root.root tmpfile + sudo mv tmpfile /etc/udev/rules.d/10-usrp_b100.rules + sudo udevadm control --reload-rules diff --git a/host/include/uhd/transport/usb_zero_copy.hpp b/host/include/uhd/transport/usb_zero_copy.hpp index b39171fba..dc344ad8b 100644 --- a/host/include/uhd/transport/usb_zero_copy.hpp +++ b/host/include/uhd/transport/usb_zero_copy.hpp @@ -1,5 +1,5 @@ // -// Copyright 2010 Ettus Research LLC +// Copyright 2010-2011 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -49,6 +49,7 @@ public: * \param recv_endpoint an integer specifiying an IN endpoint number * \param send_endpoint an integer specifiying an OUT endpoint number * \param hints optional parameters to pass to the underlying transport + * \return a new zero copy usb object */ static sptr make( usb_device_handle::sptr handle, @@ -56,6 +57,24 @@ public: size_t send_endpoint, const device_addr_t &hints = device_addr_t() ); + + /*! + * Make a wrapper around a zero copy implementation. + * The wrapper performs the following functions: + * - Pad commits to the frame boundary + * - Extract multiple packets on recv + * + * When enable multiple receive packets is set to true, + * the implementation inspects the vita length on transfers, + * and may split a single transfer into multiple managed buffers. + * + * \param usb_zc a usb zero copy interface object + * \param usb_frame_boundary bytes per frame + * \return a new zero copy wrapper object + */ + static sptr make_wrapper( + sptr usb_zc, size_t usb_frame_boundary = 512 + ); }; }} //namespace diff --git a/host/lib/transport/CMakeLists.txt b/host/lib/transport/CMakeLists.txt index 439c3d230..b1821956c 100644 --- a/host/lib/transport/CMakeLists.txt +++ b/host/lib/transport/CMakeLists.txt @@ -98,4 +98,5 @@ LIBUHD_APPEND_SOURCES( ${CMAKE_CURRENT_SOURCE_DIR}/if_addrs.cpp ${CMAKE_CURRENT_SOURCE_DIR}/udp_simple.cpp ${CMAKE_CURRENT_SOURCE_DIR}/udp_zero_copy.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/usb_zero_copy_wrapper.cpp ) diff --git a/host/lib/transport/libusb1_zero_copy.cpp b/host/lib/transport/libusb1_zero_copy.cpp index 28bea978b..19a7a3742 100644 --- a/host/lib/transport/libusb1_zero_copy.cpp +++ b/host/lib/transport/libusb1_zero_copy.cpp @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include @@ -44,15 +44,24 @@ static const size_t DEFAULT_XFER_SIZE = 32*512; //bytes * to ensure that they are compiled with the same calling convention as libusb. */ -//! helper function: handles all async callbacks -static void LIBUSB_CALL libusb_async_cb(libusb_transfer *lut){ +//! helper function: handles all rx async callbacks +static void LIBUSB_CALL libusb_async_rx_cb(libusb_transfer *lut){ + if(lut->actual_length == 0) { + UHD_ASSERT_THROW(libusb_submit_transfer(lut) == 0); //get out until you find some real data + return; + } + (*static_cast *>(lut->user_data))(); +} + +//! helper function: handles all tx async callbacks +static void LIBUSB_CALL libusb_async_tx_cb(libusb_transfer *lut) { (*static_cast *>(lut->user_data))(); } //! callback to free transfer upon cancellation static void LIBUSB_CALL cancel_transfer_cb(libusb_transfer *lut){ - if (lut->status == LIBUSB_TRANSFER_CANCELLED) libusb_free_transfer(lut); - else UHD_LOGV(rarely) << "libusb cancel_transfer unexpected status " << lut->status << std::endl; + if (lut->status == LIBUSB_TRANSFER_CANCELLED || lut->status == LIBUSB_TRANSFER_TIMED_OUT) libusb_free_transfer(lut); + else UHD_MSG(error) << "libusb cancel_transfer unexpected status " << lut->status << std::endl; } /*********************************************************************** @@ -97,7 +106,7 @@ public: void commit(size_t len){ if (_expired) return; _lut->length = len; - if(len == 0) libusb_async_cb(_lut); + if(len == 0) libusb_async_tx_cb(_lut); else UHD_ASSERT_THROW(libusb_submit_transfer(_lut) == 0); _expired = true; } @@ -157,9 +166,9 @@ public: (recv_endpoint & 0x7f) | 0x80, // endpoint static_cast(_recv_buffer_pool->at(i)), // buffer this->get_recv_frame_size(), // length - libusb_transfer_cb_fn(&libusb_async_cb), // callback + libusb_transfer_cb_fn(&libusb_async_rx_cb), // callback static_cast(&_callbacks.back()), // user_data - 0 // timeout + 0 // timeout (ms) ); _all_luts.push_back(lut); @@ -183,13 +192,13 @@ public: (send_endpoint & 0x7f) | 0x00, // endpoint static_cast(_send_buffer_pool->at(i)), // buffer this->get_send_frame_size(), // length - libusb_transfer_cb_fn(&libusb_async_cb), // callback + libusb_transfer_cb_fn(&libusb_async_tx_cb), // callback static_cast(&_callbacks.back()), // user_data 0 // timeout ); _all_luts.push_back(lut); - libusb_async_cb(lut); + libusb_async_tx_cb(lut); } //spawn the event handler threads @@ -206,7 +215,9 @@ public: BOOST_FOREACH(libusb_transfer *lut, _all_luts){ lut->callback = libusb_transfer_cb_fn(&cancel_transfer_cb); libusb_cancel_transfer(lut); - while(lut->status != LIBUSB_TRANSFER_CANCELLED && lut->status != LIBUSB_TRANSFER_COMPLETED) { + while(lut->status != LIBUSB_TRANSFER_CANCELLED + && lut->status != LIBUSB_TRANSFER_COMPLETED + && lut->status != LIBUSB_TRANSFER_TIMED_OUT) { boost::this_thread::sleep(boost::posix_time::milliseconds(10)); } } diff --git a/host/lib/transport/usb_zero_copy_wrapper.cpp b/host/lib/transport/usb_zero_copy_wrapper.cpp new file mode 100644 index 000000000..227c4b392 --- /dev/null +++ b/host/lib/transport/usb_zero_copy_wrapper.cpp @@ -0,0 +1,202 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include +#include +#include +#include +#include + +using namespace uhd::transport; +bool debug = true; + +static inline size_t next_boundary(size_t length, size_t boundary){ + //pad to the boundary, assumes boundary is a power of 2 + return (length + (boundary-1)) & ~(boundary-1); +} + +/*********************************************************************** + * USB zero copy wrapper - managed receive buffer + **********************************************************************/ +class usb_zero_copy_wrapper_mrb : public managed_recv_buffer{ +public: + usb_zero_copy_wrapper_mrb(bounded_buffer &queue): + _queue(queue){/*NOP*/} + + void release(void){ + if (_mrb.get() == NULL) return; + _mrb->release(); + _queue.push_with_haste(this); + _mrb.reset(); + } + + sptr get_new(managed_recv_buffer::sptr mrb, const void *mem, size_t len){ + _mrb = mrb; + _mem = mem; + _len = len; + return make_managed_buffer(this); + } + +private: + const void *get_buff(void) const{return _mem;} + size_t get_size(void) const{return _len;} + + bounded_buffer &_queue; + const void *_mem; + size_t _len; + managed_recv_buffer::sptr _mrb; +}; + +/*********************************************************************** + * USB zero copy wrapper - managed send buffer + **********************************************************************/ +class usb_zero_copy_wrapper_msb : public managed_send_buffer{ +public: + usb_zero_copy_wrapper_msb(bounded_buffer &queue, size_t boundary): + _queue(queue), _boundary(boundary){/*NOP*/} + + void commit(size_t len){ + if (_msb.get() == NULL) return; + _msb->commit(next_boundary(len, _boundary)); + _queue.push_with_haste(this); + _msb.reset(); + } + + sptr get_new(managed_send_buffer::sptr msb){ + _msb = msb; + return make_managed_buffer(this); + } + +private: + void *get_buff(void) const{return _msb->cast();} + size_t get_size(void) const{return _msb->size();} + + bounded_buffer &_queue; + size_t _boundary; + managed_send_buffer::sptr _msb; +}; + +/*********************************************************************** + * USB zero copy wrapper implementation + **********************************************************************/ +class usb_zero_copy_wrapper : public usb_zero_copy{ +public: + usb_zero_copy_wrapper( + sptr usb_zc, size_t usb_frame_boundary + ): + _internal_zc(usb_zc), + _usb_frame_boundary(usb_frame_boundary), + _available_recv_buffs(this->get_num_recv_frames()), + _available_send_buffs(this->get_num_send_frames()), + _mrb_pool(this->get_num_recv_frames(), usb_zero_copy_wrapper_mrb(_available_recv_buffs)), + _msb_pool(this->get_num_send_frames(), usb_zero_copy_wrapper_msb(_available_send_buffs, usb_frame_boundary)) + { + BOOST_FOREACH(usb_zero_copy_wrapper_mrb &mrb, _mrb_pool){ + _available_recv_buffs.push_with_haste(&mrb); + } + + BOOST_FOREACH(usb_zero_copy_wrapper_msb &msb, _msb_pool){ + _available_send_buffs.push_with_haste(&msb); + } + } + + managed_recv_buffer::sptr get_recv_buff(double timeout){ + //attempt to get a managed recv buffer + if (not _last_recv_buff.get()){ + _last_recv_buff = _internal_zc->get_recv_buff(timeout); + _last_recv_offset = 0; + } + + //attempt to get a wrapper for a managed recv buffer + usb_zero_copy_wrapper_mrb *wmrb = NULL; + if (_last_recv_buff.get() and _available_recv_buffs.pop_with_timed_wait(wmrb, timeout)){ + //extract this packet's memory address and length in bytes + const char *mem = _last_recv_buff->cast() + _last_recv_offset; + const boost::uint32_t *mem32 = reinterpret_cast(mem); + size_t len = (mem32[0] & 0xffff)*sizeof(boost::uint32_t); //length in bytes (from VRT header) + + managed_recv_buffer::sptr recv_buff; //the buffer to be returned to the user + + recv_buff = wmrb->get_new(_last_recv_buff, mem, len); + _last_recv_offset = next_boundary(_last_recv_offset + len, _usb_frame_boundary); + + //check if this receive buffer has been exhausted + if (_last_recv_offset >= _last_recv_buff->size()) { + _last_recv_buff.reset(); + } + + return recv_buff; + } + + //otherwise return a null sptr for failure + return managed_recv_buffer::sptr(); + } + + size_t get_num_recv_frames(void) const{ + return _internal_zc->get_num_recv_frames(); + } + + size_t get_recv_frame_size(void) const{ + return _internal_zc->get_recv_frame_size(); + } + + managed_send_buffer::sptr get_send_buff(double timeout){ + managed_send_buffer::sptr send_buff = _internal_zc->get_send_buff(timeout); + + //attempt to get a wrapper for a managed send buffer + usb_zero_copy_wrapper_msb *wmsb = NULL; + if (send_buff.get() and _available_send_buffs.pop_with_haste(wmsb)){ + return wmsb->get_new(send_buff); + } + + //otherwise return a null sptr for failure + return managed_send_buffer::sptr(); + } + + size_t get_num_send_frames(void) const{ + return _internal_zc->get_num_send_frames(); + } + + size_t get_send_frame_size(void) const{ + return _internal_zc->get_send_frame_size(); + } + +private: + sptr _internal_zc; + size_t _usb_frame_boundary; + bounded_buffer _available_recv_buffs; + bounded_buffer _available_send_buffs; + std::vector _mrb_pool; + std::vector _msb_pool; + + //buffer to store partially-received VRT packets in + buffer_pool::sptr _fragment_mem; + + //state for last recv buffer to create multiple managed buffers + managed_recv_buffer::sptr _last_recv_buff; + size_t _last_recv_offset; +}; + +/*********************************************************************** + * USB zero copy wrapper factory function + **********************************************************************/ +usb_zero_copy::sptr usb_zero_copy::make_wrapper( + sptr usb_zc, size_t usb_frame_boundary +){ + return sptr(new usb_zero_copy_wrapper(usb_zc, usb_frame_boundary)); +} diff --git a/host/lib/usrp/CMakeLists.txt b/host/lib/usrp/CMakeLists.txt index 281910735..a30a45977 100644 --- a/host/lib/usrp/CMakeLists.txt +++ b/host/lib/usrp/CMakeLists.txt @@ -37,4 +37,5 @@ INCLUDE_SUBDIRECTORY(dboard) INCLUDE_SUBDIRECTORY(fx2) INCLUDE_SUBDIRECTORY(usrp1) INCLUDE_SUBDIRECTORY(usrp2) +INCLUDE_SUBDIRECTORY(usrp_b100) INCLUDE_SUBDIRECTORY(usrp_e100) diff --git a/host/lib/usrp/dboard/db_basic_and_lf.cpp b/host/lib/usrp/dboard/db_basic_and_lf.cpp index 6f8de9a7b..566e24d97 100644 --- a/host/lib/usrp/dboard/db_basic_and_lf.cpp +++ b/host/lib/usrp/dboard/db_basic_and_lf.cpp @@ -111,6 +111,7 @@ basic_rx::basic_rx(ctor_args_t args, double max_freq) : rx_dboard_base(args){ this->get_iface()->set_pin_ctrl(dboard_iface::UNIT_RX, 0x0000); this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_RX, 0xFFFF); this->get_iface()->set_gpio_out(dboard_iface::UNIT_RX, 0x0000); + this->get_iface()->set_clock_enabled(dboard_iface::UNIT_RX, true); } basic_rx::~basic_rx(void){ @@ -216,6 +217,7 @@ void basic_rx::rx_set(const wax::obj &key_, const wax::obj &val){ **********************************************************************/ basic_tx::basic_tx(ctor_args_t args, double max_freq) : tx_dboard_base(args){ _max_freq = max_freq; + this->get_iface()->set_clock_enabled(dboard_iface::UNIT_TX, true); } basic_tx::~basic_tx(void){ diff --git a/host/lib/usrp/fx2/fx2_ctrl.hpp b/host/lib/usrp/fx2/fx2_ctrl.hpp index 98c98bb8c..37fa09605 100644 --- a/host/lib/usrp/fx2/fx2_ctrl.hpp +++ b/host/lib/usrp/fx2/fx2_ctrl.hpp @@ -57,7 +57,7 @@ public: * \param filename name of EEPROM image */ virtual void usrp_load_eeprom(std::string filestring) = 0; - + /*! * Submit an IN transfer * \param request device specific request diff --git a/host/lib/usrp/usrp_b100/CMakeLists.txt b/host/lib/usrp/usrp_b100/CMakeLists.txt new file mode 100644 index 000000000..f83a10935 --- /dev/null +++ b/host/lib/usrp/usrp_b100/CMakeLists.txt @@ -0,0 +1,47 @@ +# +# Copyright 2010-2011 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + +######################################################################## +# This file included, use CMake directory variables +######################################################################## + +######################################################################## +# Conditionally configure the B100 support +######################################################################## +LIBUHD_REGISTER_COMPONENT("B100" ENABLE_B100 ON "ENABLE_LIBUHD;ENABLE_USB" OFF) + +IF(ENABLE_B100) + LIBUHD_APPEND_SOURCES( + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/clock_ctrl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/clock_ctrl.hpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/codec_ctrl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/codec_ctrl.hpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/codec_impl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/ctrl_packet.hpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/dboard_impl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/dboard_iface.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/dsp_impl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/io_impl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/mboard_impl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/b100_ctrl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/b100_ctrl.hpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/b100_iface.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/b100_iface.hpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/b100_impl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/b100_impl.hpp + ) +ENDIF(ENABLE_B100) diff --git a/host/lib/usrp/usrp_b100/b100_ctrl.cpp b/host/lib/usrp/usrp_b100/b100_ctrl.cpp new file mode 100644 index 000000000..4d4520e1e --- /dev/null +++ b/host/lib/usrp/usrp_b100/b100_ctrl.cpp @@ -0,0 +1,245 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "../../transport/super_recv_packet_handler.hpp" +#include "b100_ctrl.hpp" +#include "b100_impl.hpp" +#include +#include +#include +#include +#include +#include +#include +#include "ctrl_packet.hpp" +#include +#include + +using namespace uhd::transport; +using namespace uhd; + +bool b100_ctrl_debug = false; + +class b100_ctrl_impl : public b100_ctrl { +public: + b100_ctrl_impl(uhd::transport::usb_zero_copy::sptr ctrl_transport) : + sync_ctrl_fifo(2), + async_msg_fifo(100), + _ctrl_transport(ctrl_transport), + _seq(0) + { + boost::barrier spawn_barrier(2); + viking_marauders.create_thread(boost::bind(&b100_ctrl_impl::viking_marauder_loop, this, boost::ref(spawn_barrier))); + spawn_barrier.wait(); + } + + int write(boost::uint32_t addr, const ctrl_data_t &data); + ctrl_data_t read(boost::uint32_t addr, size_t len); + + ~b100_ctrl_impl(void) { + bbl_out_marauding = false; + viking_marauders.interrupt_all(); + viking_marauders.join_all(); + } + + bool get_ctrl_data(ctrl_data_t &pkt_data, double timeout); + bool recv_async_msg(uhd::async_metadata_t &async_metadata, double timeout); + +private: + int send_pkt(boost::uint16_t *cmd); + + //änd hërë wë gö ä-Vïkïng för äsynchronous control packets + void viking_marauder_loop(boost::barrier &); + bounded_buffer sync_ctrl_fifo; + bounded_buffer async_msg_fifo; + boost::thread_group viking_marauders; + bool bbl_out_marauding; + + uhd::transport::usb_zero_copy::sptr _ctrl_transport; + boost::uint8_t _seq; +}; + +/*********************************************************************** + * helper functions for packing/unpacking control packets + **********************************************************************/ +void pack_ctrl_pkt(boost::uint16_t *pkt_buff, + const ctrl_pkt_t &pkt){ + //first two bits are OP + //next six bits are CALLBACKS + //next 8 bits are SEQUENCE + //next 16 bits are LENGTH (16-bit word) + //next 32 bits are ADDRESS (16-bit word LSW) + //then DATA (28 16-bit words) + pkt_buff[0] = (boost::uint16_t(pkt.pkt_meta.op) << 14) | (boost::uint16_t(pkt.pkt_meta.callbacks) << 8) | pkt.pkt_meta.seq; + pkt_buff[1] = pkt.pkt_meta.len; + pkt_buff[2] = (pkt.pkt_meta.addr & 0x00000FFF); + pkt_buff[3] = 0x0000; //address high bits always 0 on this device + + for(size_t i = 0; i < pkt.data.size(); i++) { + pkt_buff[4+i] = pkt.data[i]; + } +} + +void unpack_ctrl_pkt(const boost::uint16_t *pkt_buff, + ctrl_pkt_t &pkt){ + pkt.pkt_meta.seq = pkt_buff[0] & 0xFF; + pkt.pkt_meta.op = CTRL_PKT_OP_READ; //really this is useless + pkt.pkt_meta.len = pkt_buff[1]; + pkt.pkt_meta.callbacks = 0; //callbacks aren't implemented yet + pkt.pkt_meta.addr = pkt_buff[2] | boost::uint32_t(pkt_buff[3] << 16); + + //let's check this so we don't go pushing 64K of crap onto the pkt + if(pkt.pkt_meta.len > CTRL_PACKET_DATA_LENGTH) { + throw uhd::runtime_error("Received control packet too long"); + } + + for(int i = 4; i < 4+pkt.pkt_meta.len; i++) pkt.data.push_back(pkt_buff[i]); +} + +int b100_ctrl_impl::send_pkt(boost::uint16_t *cmd) { + managed_send_buffer::sptr sbuf = _ctrl_transport->get_send_buff(); + if(!sbuf.get()) { + throw uhd::runtime_error("Control channel send error"); + } + + //FIXME there's a better way to do this + for(size_t i = 0; i < (CTRL_PACKET_LENGTH / sizeof(boost::uint16_t)); i++) { + sbuf->cast()[i] = cmd[i]; + } + sbuf->commit(CTRL_PACKET_LENGTH); //fixed size transaction + return 0; +} + +int b100_ctrl_impl::write(boost::uint32_t addr, const ctrl_data_t &data) { + UHD_ASSERT_THROW(data.size() <= (CTRL_PACKET_DATA_LENGTH / sizeof(boost::uint16_t))); + ctrl_pkt_t pkt; + pkt.data = data; + pkt.pkt_meta.op = CTRL_PKT_OP_WRITE; + pkt.pkt_meta.callbacks = 0; + pkt.pkt_meta.seq = _seq++; + pkt.pkt_meta.len = pkt.data.size(); + pkt.pkt_meta.addr = addr; + boost::uint16_t pkt_buff[CTRL_PACKET_LENGTH / sizeof(boost::uint16_t)]; + + pack_ctrl_pkt(pkt_buff, pkt); + size_t result = send_pkt(pkt_buff); + return result; +} + +ctrl_data_t b100_ctrl_impl::read(boost::uint32_t addr, size_t len) { + UHD_ASSERT_THROW(len <= (CTRL_PACKET_DATA_LENGTH / sizeof(boost::uint16_t))); + + ctrl_pkt_t pkt; + pkt.pkt_meta.op = CTRL_PKT_OP_READ; + pkt.pkt_meta.callbacks = 0; + pkt.pkt_meta.seq = _seq++; + pkt.pkt_meta.len = len; + pkt.pkt_meta.addr = addr; + boost::uint16_t pkt_buff[CTRL_PACKET_LENGTH / sizeof(boost::uint16_t)]; + + pack_ctrl_pkt(pkt_buff, pkt); + send_pkt(pkt_buff); + + //loop around waiting for the response to appear + while(!get_ctrl_data(pkt.data, 0.05)); + + return pkt.data; +} + +/*********************************************************************** + * Viking marauders go pillaging for asynchronous control packets in the + * control response endpoint. Sync packets go in sync_ctrl_fifo, + * async TX error messages go in async_msg_fifo. sync_ctrl_fifo should + * never have more than 1 message in it, since it's expected that we'll + * wait for a control operation to finish before starting another one. + **********************************************************************/ +void b100_ctrl_impl::viking_marauder_loop(boost::barrier &spawn_barrier) { + bbl_out_marauding = true; + spawn_barrier.wait(); + set_thread_priority_safe(); + + while(bbl_out_marauding){ + managed_recv_buffer::sptr rbuf = _ctrl_transport->get_recv_buff(); + if(!rbuf.get()) continue; //that's ok, there are plenty of villages to pillage! + const boost::uint16_t *pkt_buf = rbuf->cast(); + + if(pkt_buf[0] >> 8 == CTRL_PACKET_HEADER_MAGIC) { + //so it's got a control packet header, let's parse it. + ctrl_pkt_t pkt; + unpack_ctrl_pkt(pkt_buf, pkt); + + if(pkt.pkt_meta.seq != boost::uint8_t(_seq - 1)) { + throw uhd::runtime_error("Sequence error on control channel"); + } + if(pkt.pkt_meta.len > (CTRL_PACKET_LENGTH - CTRL_PACKET_HEADER_LENGTH)) { + throw uhd::runtime_error("Control channel packet length too long"); + } + + //push it onto the queue + sync_ctrl_fifo.push_with_wait(pkt.data); + } else { //it's an async status pkt + //extract the vrt header packet info + vrt::if_packet_info_t if_packet_info; + if_packet_info.num_packet_words32 = rbuf->size()/sizeof(boost::uint32_t); + const boost::uint32_t *vrt_hdr = rbuf->cast(); + vrt::if_hdr_unpack_le(vrt_hdr, if_packet_info); + + if( if_packet_info.sid == 0 + and if_packet_info.packet_type != vrt::if_packet_info_t::PACKET_TYPE_DATA){ + //fill in the async metadata + async_metadata_t metadata; + metadata.channel = 0; + metadata.has_time_spec = if_packet_info.has_tsi and if_packet_info.has_tsf; + metadata.time_spec = time_spec_t( + time_t(if_packet_info.tsi), size_t(if_packet_info.tsf), 64e6 //FIXME get from clock_ctrl + ); + metadata.event_code = async_metadata_t::event_code_t(sph::get_context_code(vrt_hdr, if_packet_info)); + //print the famous U, and push the metadata into the message queue + if (metadata.event_code & + ( async_metadata_t::EVENT_CODE_UNDERFLOW + | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET) ) + UHD_MSG(fastpath) << "U"; + + if (metadata.event_code & + ( async_metadata_t::EVENT_CODE_SEQ_ERROR + | async_metadata_t::EVENT_CODE_SEQ_ERROR_IN_BURST) ) + UHD_MSG(fastpath) << "S"; + + async_msg_fifo.push_with_pop_on_full(metadata); + continue; + } + throw uhd::runtime_error("Control: unknown async response"); + } + } +} + +bool b100_ctrl_impl::get_ctrl_data(ctrl_data_t &pkt_data, double timeout){ + boost::this_thread::disable_interruption di; //disable because the wait can throw + return sync_ctrl_fifo.pop_with_timed_wait(pkt_data, timeout); +} + +bool b100_ctrl_impl::recv_async_msg(uhd::async_metadata_t &async_metadata, double timeout) { + boost::this_thread::disable_interruption di; //disable because the wait can throw + return async_msg_fifo.pop_with_timed_wait(async_metadata, timeout); +} + +/*********************************************************************** + * Public make function for b100_ctrl interface + **********************************************************************/ +b100_ctrl::sptr b100_ctrl::make(uhd::transport::usb_zero_copy::sptr ctrl_transport){ + return sptr(new b100_ctrl_impl(ctrl_transport)); +} diff --git a/host/lib/usrp/usrp_b100/b100_ctrl.hpp b/host/lib/usrp/usrp_b100/b100_ctrl.hpp new file mode 100644 index 000000000..ae706dbb4 --- /dev/null +++ b/host/lib/usrp/usrp_b100/b100_ctrl.hpp @@ -0,0 +1,69 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_B100_CTRL_HPP +#define INCLUDED_B100_CTRL_HPP + +#include +#include +#include +#include +#include +#include +#include "ctrl_packet.hpp" +#include + +class b100_ctrl : boost::noncopyable{ +public: + typedef boost::shared_ptr sptr; + + /*! + * Make a USRP control object from a data transport + * \param ctrl_transport a USB data transport + * \return a new b100 control object + */ + static sptr make(uhd::transport::usb_zero_copy::sptr ctrl_transport); + + /*! + * Write a byte vector to an FPGA register + * \param addr the FPGA register address + * \param bytes the data to write + * \return 0 on success, error code on failure + */ + virtual int write(boost::uint32_t addr, const ctrl_data_t &data) = 0; + + /*! + * Read a byte vector from an FPGA register (blocking read) + * \param addr the FPGA register address + * \param len the length of the read + * \return a vector of bytes from the register(s) in question + */ + virtual ctrl_data_t read(boost::uint32_t addr, size_t len) = 0; + + /*! + * Get a sync ctrl packet (blocking) + * \param the packet data buffer + * \param the timeout value + * \return true if it got something + */ + virtual bool get_ctrl_data(ctrl_data_t &pkt_data, double timeout) = 0; + + virtual bool recv_async_msg(uhd::async_metadata_t &async_metadata, double timeout) = 0; + +}; + +#endif /* INCLUDED_B100_CTRL_HPP */ diff --git a/host/lib/usrp/usrp_b100/b100_iface.cpp b/host/lib/usrp/usrp_b100/b100_iface.cpp new file mode 100644 index 000000000..17ea2e6ad --- /dev/null +++ b/host/lib/usrp/usrp_b100/b100_iface.cpp @@ -0,0 +1,336 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "b100_iface.hpp" +#include "usrp_commands.h" +#include +#include +#include +#include +#include +#include +#include + +//FOR TESTING ONLY +#include "b100_regs.hpp" +#include +#include "usrp_i2c_addr.h" + +using namespace uhd; +using namespace uhd::usrp; +using namespace uhd::transport; + +/*********************************************************************** + * Constants + **********************************************************************/ +static const bool iface_debug = true; +static const boost::uint16_t USRP_B_FW_COMPAT_NUM = 0x02; +static const boost::uint16_t USRP_B_FPGA_COMPAT_NUM = 0x03; + +/*********************************************************************** + * I2C + FX2 implementation wrapper + **********************************************************************/ +class b100_i2c_fx2_iface : public i2c_iface{ +public: + b100_i2c_fx2_iface(uhd::usrp::fx2_ctrl::sptr fx2_ctrl){ + _fx2_ctrl = fx2_ctrl; + } + + void write_i2c(boost::uint8_t addr, const byte_vector_t &bytes) + { + UHD_ASSERT_THROW(bytes.size() < max_i2c_data_bytes); + + unsigned char buff[max_i2c_data_bytes]; + std::copy(bytes.begin(), bytes.end(), buff); + + int ret = _fx2_ctrl->usrp_i2c_write(addr & 0xff, + buff, + bytes.size()); + + if (iface_debug && (ret < 0)) + uhd::runtime_error("USRP: failed i2c write"); + } + + byte_vector_t read_i2c(boost::uint8_t addr, size_t num_bytes) + { + UHD_ASSERT_THROW(num_bytes < max_i2c_data_bytes); + + unsigned char buff[max_i2c_data_bytes]; + int ret = _fx2_ctrl->usrp_i2c_read(addr & 0xff, + buff, + num_bytes); + + if (iface_debug && ((ret < 0) || (unsigned)ret < (num_bytes))) + uhd::runtime_error("USRP: failed i2c read"); + + byte_vector_t out_bytes; + for (size_t i = 0; i < num_bytes; i++) + out_bytes.push_back(buff[i]); + + return out_bytes; + } + +private: + static const size_t max_i2c_data_bytes = 64; + uhd::usrp::fx2_ctrl::sptr _fx2_ctrl; +}; + +/*********************************************************************** + * USRP-E100 interface implementation + **********************************************************************/ +class b100_iface_impl : public b100_iface{ +public: + /******************************************************************* + * Structors + ******************************************************************/ + b100_iface_impl(uhd::usrp::fx2_ctrl::sptr fx2_ctrl, + b100_ctrl::sptr fpga_ctrl) : + _fx2_i2c_iface(fx2_ctrl), + _fx2_ctrl(fx2_ctrl), + _fpga_ctrl(fpga_ctrl) + { + this->check_fw_compat(); + if (fpga_ctrl.get() != NULL){ + enable_gpif(1); + i2c_init(); + this->check_fpga_compat(); + } + mb_eeprom = mboard_eeprom_t(get_fx2_i2c_iface(), mboard_eeprom_t::MAP_B000); + } + + void check_fw_compat(void){ + unsigned char data[4]; //useless data buffer + const boost::uint16_t fw_compat_num = _fx2_ctrl->usrp_control_read( + VRQ_FW_COMPAT, 0, 0, data, sizeof(data) + ); + if (fw_compat_num != USRP_B_FW_COMPAT_NUM){ + throw uhd::runtime_error(str(boost::format( + "Expected firmware compatibility number 0x%x, but got 0x%x:\n" + "The firmware build is not compatible with the host code build." + ) % USRP_B_FW_COMPAT_NUM % fw_compat_num)); + } + } + + void check_fpga_compat(void){ + const boost::uint16_t fpga_compat_num = this->peek16(B100_REG_MISC_COMPAT); + if (fpga_compat_num != USRP_B_FPGA_COMPAT_NUM){ + throw uhd::runtime_error(str(boost::format( + "Expected FPGA compatibility number 0x%x, but got 0x%x:\n" + "The FPGA build is not compatible with the host code build." + ) % USRP_B_FPGA_COMPAT_NUM % fpga_compat_num)); + } + } + + ~b100_iface_impl(void) + { + /* NOP */ + } + + /******************************************************************* + * Peek and Poke + ******************************************************************/ + + void poke(boost::uint32_t addr, const ctrl_data_t &data) { + boost::mutex::scoped_lock lock(_ctrl_mutex); + _fpga_ctrl->write(addr, data); + } + + ctrl_data_t peek(boost::uint32_t addr, size_t len) { + boost::mutex::scoped_lock lock(_ctrl_mutex); + return _fpga_ctrl->read(addr, len); + } + + void poke16(boost::uint32_t addr, boost::uint16_t value) + { + ctrl_data_t words(1); + words[0] = value; + poke(addr, words); + } + + void poke32(boost::uint32_t addr, boost::uint32_t value) + { + //just a subset of poke() to maintain compatibility + ctrl_data_t words(2); + words[0] = value & 0x0000FFFF; + words[1] = value >> 16; + poke(addr, words); + } + + boost::uint32_t peek32(boost::uint32_t addr) + { + ctrl_data_t words = peek(addr, 2); + return boost::uint32_t((boost::uint32_t(words[1]) << 16) | words[0]); + } + + boost::uint16_t peek16(boost::uint32_t addr) + { + ctrl_data_t words = peek(addr, 1); + return boost::uint16_t(words[0]); + } + + /******************************************************************* + * I2C + ******************************************************************/ + static const boost::uint32_t i2c_datarate = 400000; + static const boost::uint32_t wishbone_clk = 64000000; //FIXME should go somewhere else + + void i2c_init(void) { + //init I2C FPGA interface. + poke16(B100_REG_I2C_CTRL, 0x0000); + //set prescalers to operate at 400kHz: WB_CLK is 64MHz... + boost::uint16_t prescaler = wishbone_clk / (i2c_datarate*5) - 1; + poke16(B100_REG_I2C_PRESCALER_LO, prescaler & 0xFF); + poke16(B100_REG_I2C_PRESCALER_HI, (prescaler >> 8) & 0xFF); + poke16(B100_REG_I2C_CTRL, I2C_CTRL_EN); //enable I2C core + } + + static const size_t max_i2c_data_bytes = 64; + + void i2c_wait_for_xfer(void) + { + while(this->peek16(B100_REG_I2C_CMD_STATUS) & I2C_ST_TIP) + boost::this_thread::sleep(boost::posix_time::milliseconds(10)); + } + + bool wait_chk_ack(void) { + i2c_wait_for_xfer(); + return (this->peek16(B100_REG_I2C_CMD_STATUS) & I2C_ST_RXACK) == 0; + } + + void write_i2c(boost::uint8_t addr, const byte_vector_t &bytes) + { + poke16(B100_REG_I2C_DATA, (addr << 1) | 0); //addr and read bit (0) + poke16(B100_REG_I2C_CMD_STATUS, I2C_CMD_WR | I2C_CMD_START | (bytes.size() == 0 ? I2C_CMD_STOP : 0)); + + //wait for previous transfer to complete + if(!wait_chk_ack()) { + poke16(B100_REG_I2C_CMD_STATUS, I2C_CMD_STOP); + return; + } + + for(size_t i = 0; i < bytes.size(); i++) { + poke16(B100_REG_I2C_DATA, bytes[i]); + poke16(B100_REG_I2C_CMD_STATUS, I2C_CMD_WR | ((i == (bytes.size() - 1)) ? I2C_CMD_STOP : 0)); + if(!wait_chk_ack()) { + poke16(B100_REG_I2C_CMD_STATUS, I2C_CMD_STOP); + return; + } + } + } + + byte_vector_t read_i2c(boost::uint8_t addr, size_t num_bytes) + { + byte_vector_t bytes; + if(num_bytes == 0) return bytes; + + while (peek16(B100_REG_I2C_CMD_STATUS) & I2C_ST_BUSY); + + poke16(B100_REG_I2C_DATA, (addr << 1) | 1); //addr and read bit (1) + poke16(B100_REG_I2C_CMD_STATUS, I2C_CMD_WR | I2C_CMD_START); + //wait for previous transfer to complete + if(!wait_chk_ack()) { + poke16(B100_REG_I2C_CMD_STATUS, I2C_CMD_STOP); + } + + for(; num_bytes > 0; num_bytes--) { + poke16(B100_REG_I2C_CMD_STATUS, I2C_CMD_RD | ((num_bytes == 1) ? (I2C_CMD_STOP | I2C_CMD_NACK) : 0)); + i2c_wait_for_xfer(); + boost::uint8_t readback = peek16(B100_REG_I2C_DATA) & 0xFF; + bytes.push_back(readback); + } + return bytes; + } + + i2c_iface &get_fx2_i2c_iface(void){ + return _fx2_i2c_iface; + } + + /******************************************************************* + * SPI interface + * Eventually this will be replaced with a control-channel system + * to let the firmware do the actual write/readback cycles. + * This keeps the bandwidth on the control channel down. + ******************************************************************/ + + void spi_wait(void) { + while(peek32(B100_REG_SPI_CTRL) & SPI_CTRL_GO_BSY); + } + + boost::uint32_t transact_spi(int which_slave, + const spi_config_t &config, + boost::uint32_t bits, + size_t num_bits, + bool readback) + { + UHD_ASSERT_THROW((num_bits <= 32) && !(num_bits % 8)); + + int edge_flags = ((config.miso_edge==spi_config_t::EDGE_FALL) ? SPI_CTRL_RXNEG : 0) | + ((config.mosi_edge==spi_config_t::EDGE_FALL) ? 0 : SPI_CTRL_TXNEG) + ; + + boost::uint16_t ctrl = SPI_CTRL_ASS | (SPI_CTRL_CHAR_LEN_MASK & num_bits) | edge_flags; + + poke16(B100_REG_SPI_DIV, 0x0001); // = fpga_clk / 4 + poke32(B100_REG_SPI_SS, which_slave & 0xFFFF); + poke32(B100_REG_SPI_TXRX0, bits); + poke16(B100_REG_SPI_CTRL, ctrl); + + poke16(B100_REG_SPI_CTRL, ctrl | SPI_CTRL_GO_BSY); + if(readback) { + spi_wait(); + return peek32(B100_REG_SPI_TXRX0); + } + else { + return 0; + } + } + + void reset_gpif(boost::uint16_t ep) { + _fx2_ctrl->usrp_control_write(VRQ_RESET_GPIF, ep, ep, 0, 0); + } + + void enable_gpif(bool en) { + _fx2_ctrl->usrp_control_write(VRQ_ENABLE_GPIF, en ? 1 : 0, 0, 0, 0); + } + + void clear_fpga_fifo(void) { + _fx2_ctrl->usrp_control_write(VRQ_CLEAR_FPGA_FIFO, 0, 0, 0, 0); + } + + void write_uart(boost::uint8_t, const std::string &) { + throw uhd::not_implemented_error("Unhandled command write_uart()"); + } + + std::string read_uart(boost::uint8_t) { + throw uhd::not_implemented_error("Unhandled command read_uart()"); + } + +private: + b100_i2c_fx2_iface _fx2_i2c_iface; + uhd::usrp::fx2_ctrl::sptr _fx2_ctrl; + b100_ctrl::sptr _fpga_ctrl; + boost::mutex _ctrl_mutex; +}; + +/*********************************************************************** + * Public Make Function + **********************************************************************/ +b100_iface::sptr b100_iface::make(uhd::usrp::fx2_ctrl::sptr fx2_ctrl, + b100_ctrl::sptr fpga_ctrl) +{ + return b100_iface::sptr(new b100_iface_impl(fx2_ctrl, fpga_ctrl)); +} diff --git a/host/lib/usrp/usrp_b100/b100_iface.hpp b/host/lib/usrp/usrp_b100/b100_iface.hpp new file mode 100644 index 000000000..4da43681d --- /dev/null +++ b/host/lib/usrp/usrp_b100/b100_iface.hpp @@ -0,0 +1,73 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_B100_IFACE_HPP +#define INCLUDED_B100_IFACE_HPP + +#include +#include +#include +#include +#include +#include "fx2_ctrl.hpp" +#include "b100_ctrl.hpp" + +/*! + * The usrp1 interface class: + * Provides a set of functions to implementation layer. + * Including spi, peek, poke, control... + */ +class b100_iface : boost::noncopyable, public uhd::usrp::mboard_iface{ +public: + typedef boost::shared_ptr sptr; + + /*! + * Make a new b100 interface with the control transport. + * \param fx2_ctrl the usrp control object + * \param fpga_ctrl the FPGA interface control object + * \return a new usrp1 interface object + */ + static sptr make(uhd::usrp::fx2_ctrl::sptr fx2_ctrl, + b100_ctrl::sptr fpga_ctrl = b100_ctrl::sptr() + ); + + /*! + * Reset the GPIF interface on the FX2 + * \param which endpoint to reset + * \return + */ + virtual void reset_gpif(boost::uint16_t ep) = 0; + + /*! + * Clear the GPIF FIFOs on the FPGA + * \return + */ + virtual void clear_fpga_fifo(void) = 0; + + /*! + * Enable/disable the GPIF interfaces on the FX2 + * \return + */ + virtual void enable_gpif(bool en) = 0; + + //! Get access to the FX2 I2C interface + virtual uhd::i2c_iface &get_fx2_i2c_iface(void) = 0; + + uhd::usrp::mboard_eeprom_t mb_eeprom; +}; + +#endif /* INCLUDED_USRP1_IFACE_HPP */ diff --git a/host/lib/usrp/usrp_b100/b100_impl.cpp b/host/lib/usrp/usrp_b100/b100_impl.cpp new file mode 100644 index 000000000..066831a92 --- /dev/null +++ b/host/lib/usrp/usrp_b100/b100_impl.cpp @@ -0,0 +1,277 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "b100_impl.hpp" +#include "b100_ctrl.hpp" +#include "fpga_regs_standard.h" +#include "usrp_spi_defs.h" +#include +#include "ctrl_packet.hpp" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "b100_regs.hpp" + +using namespace uhd; +using namespace uhd::usrp; +using namespace uhd::transport; + +const boost::uint16_t B100_VENDOR_ID = 0x2500; +const boost::uint16_t B100_PRODUCT_ID = 0x0001; +const boost::uint16_t FX2_VENDOR_ID = 0x04b4; +const boost::uint16_t FX2_PRODUCT_ID = 0x8613; + +/*********************************************************************** + * Discovery + **********************************************************************/ +static device_addrs_t b100_find(const device_addr_t &hint) +{ + device_addrs_t b100_addrs; + + //return an empty list of addresses when type is set to non-b100 + if (hint.has_key("type") and hint["type"] != "b100") return b100_addrs; + + //extract the firmware path for the b100 + std::string b100_fw_image; + try{ + b100_fw_image = find_image_path( + hint.has_key("fw")? hint["fw"] : "usrp_b100_fw_c2.ihx" + ); + } + catch(...){ + UHD_MSG(warning) << boost::format( + "Could not locate B100 firmware.\n" + "Please install the images package.\n" + ); + return b100_addrs; + } + + boost::uint16_t vid = hint.has_key("uninit") ? FX2_VENDOR_ID : B100_VENDOR_ID; + boost::uint16_t pid = hint.has_key("uninit") ? FX2_PRODUCT_ID : B100_PRODUCT_ID; + + // Important note: + // The get device list calls are nested inside the for loop. + // This allows the usb guts to decontruct when not in use, + // so that re-enumeration after fw load can occur successfully. + // This requirement is a courtesy of libusb1.0 on windows. + + //find the usrps and load firmware + BOOST_FOREACH(usb_device_handle::sptr handle, usb_device_handle::get_device_list(vid, pid)) { + try { + fx2_ctrl::make(usb_control::make(handle))->usrp_load_firmware(b100_fw_image); + } catch (...) { + UHD_MSG(status) << "Interface claimed, ignoring device" << std::endl; + } + } + + //get descriptors again with serial number, but using the initialized VID/PID now since we have firmware + vid = B100_VENDOR_ID; + pid = B100_PRODUCT_ID; + + BOOST_FOREACH(usb_device_handle::sptr handle, usb_device_handle::get_device_list(vid, pid)) { + device_addr_t new_addr; + new_addr["type"] = "b100"; + + //Attempt to read the name from the EEPROM and perform filtering. + //This operation can throw due to compatibility mismatch. + try{ + usb_control::sptr control = usb_control::make(handle); + b100_iface::sptr iface = b100_iface::make(fx2_ctrl::make(control)); + new_addr["name"] = iface->mb_eeprom["name"]; + new_addr["serial"] = handle->get_serial(); + } + catch(const uhd::exception &){ + //set these values as empty string so the device may still be found + //and the filter's below can still operate on the discovered device + new_addr["name"] = ""; + new_addr["serial"] = ""; + } + + //this is a found b100 when the hint serial and name match or blank + if ( + (not hint.has_key("name") or hint["name"] == new_addr["name"]) and + (not hint.has_key("serial") or hint["serial"] == new_addr["serial"]) + ){ + b100_addrs.push_back(new_addr); + } + } + + return b100_addrs; +} + +/*********************************************************************** + * Make + **********************************************************************/ +static device::sptr b100_make(const device_addr_t &device_addr){ + + //extract the FPGA path for the B100 + std::string b100_fpga_image = find_image_path( + device_addr.has_key("fpga")? device_addr["fpga"] : "usrp_b100_fpga_c3.bin" + ); + + //try to match the given device address with something on the USB bus + std::vector device_list = + usb_device_handle::get_device_list(B100_VENDOR_ID, B100_PRODUCT_ID); + + //locate the matching handle in the device list + usb_device_handle::sptr handle; + BOOST_FOREACH(usb_device_handle::sptr dev_handle, device_list) { + if (dev_handle->get_serial() == device_addr["serial"]){ + handle = dev_handle; + break; + } + } + UHD_ASSERT_THROW(handle.get() != NULL); //better be found + + //create control objects and a data transport + usb_control::sptr fx2_transport = usb_control::make(handle); + fx2_ctrl::sptr fx2_ctrl = fx2_ctrl::make(fx2_transport); + fx2_ctrl->usrp_load_fpga(b100_fpga_image); + + device_addr_t data_xport_args; + data_xport_args["recv_frame_size"] = device_addr.get("recv_frame_size", "16384"); + data_xport_args["num_recv_frames"] = device_addr.get("num_recv_frames", "16"); + data_xport_args["send_frame_size"] = device_addr.get("send_frame_size", "16384"); + data_xport_args["num_send_frames"] = device_addr.get("num_send_frames", "16"); + + usb_zero_copy::sptr data_transport = usb_zero_copy::make_wrapper( + usb_zero_copy::make( + handle, // identifier + 6, // IN endpoint + 2, // OUT endpoint + data_xport_args // param hints + ) + ); + + //create the control transport + device_addr_t ctrl_xport_args; + ctrl_xport_args["recv_frame_size"] = boost::lexical_cast(CTRL_PACKET_LENGTH); + ctrl_xport_args["num_recv_frames"] = "16"; + ctrl_xport_args["send_frame_size"] = boost::lexical_cast(CTRL_PACKET_LENGTH); + ctrl_xport_args["num_send_frames"] = "4"; + + usb_zero_copy::sptr ctrl_transport = usb_zero_copy::make( + handle, + 8, + 4, + ctrl_xport_args + ); + + const double master_clock_rate = device_addr.cast("master_clock_rate", 64e6); + + + //create the b100 implementation guts + return device::sptr(new b100_impl(data_transport, ctrl_transport, fx2_ctrl, master_clock_rate)); +} + +UHD_STATIC_BLOCK(register_b100_device){ + device::register_device(&b100_find, &b100_make); +} + +/*********************************************************************** + * Structors + **********************************************************************/ +b100_impl::b100_impl(uhd::transport::usb_zero_copy::sptr data_transport, + uhd::transport::usb_zero_copy::sptr ctrl_transport, + uhd::usrp::fx2_ctrl::sptr fx2_ctrl, + const double master_clock_rate) + : _data_transport(data_transport), _fx2_ctrl(fx2_ctrl) +{ + //this is the handler object for FPGA control packets + _fpga_ctrl = b100_ctrl::make(ctrl_transport); + + _iface = b100_iface::make(_fx2_ctrl, _fpga_ctrl); + + //create clock interface + _clock_ctrl = b100_clock_ctrl::make(_iface, master_clock_rate); + + //create codec interface + _codec_ctrl = b100_codec_ctrl::make(_iface); + + //initialize the codecs + codec_init(); + + //initialize the mboard + mboard_init(); + + //initialize the dboards + dboard_init(); + + //initialize the dsps + rx_ddc_init(); + + //initialize the dsps + tx_duc_init(); + + //init the subdev specs + this->mboard_set(MBOARD_PROP_RX_SUBDEV_SPEC, subdev_spec_t()); + this->mboard_set(MBOARD_PROP_TX_SUBDEV_SPEC, subdev_spec_t()); + + //initialize the send/recv buffs + io_init(); +} + +b100_impl::~b100_impl(void){ + /* NOP */ +} + +bool b100_impl::recv_async_msg(uhd::async_metadata_t &md, double timeout){ + return _fpga_ctrl->recv_async_msg(md, timeout); +} + +/*********************************************************************** + * Device Get + **********************************************************************/ +void b100_impl::get(const wax::obj &key_, wax::obj &val) +{ + named_prop_t key = named_prop_t::extract(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case DEVICE_PROP_NAME: + val = std::string("USRP-B100 device"); + return; + + case DEVICE_PROP_MBOARD: + UHD_ASSERT_THROW(key.name == ""); + val = _mboard_proxy->get_link(); + return; + + case DEVICE_PROP_MBOARD_NAMES: + val = prop_names_t(1, ""); //vector of size 1 with empty string + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +/*********************************************************************** + * Device Set + **********************************************************************/ +void b100_impl::set(const wax::obj &, const wax::obj &) +{ + UHD_THROW_PROP_SET_ERROR(); +} diff --git a/host/lib/usrp/usrp_b100/b100_impl.hpp b/host/lib/usrp/usrp_b100/b100_impl.hpp new file mode 100644 index 000000000..daec70bca --- /dev/null +++ b/host/lib/usrp/usrp_b100/b100_impl.hpp @@ -0,0 +1,204 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "b100_iface.hpp" +#include "b100_ctrl.hpp" +#include "clock_ctrl.hpp" +#include "codec_ctrl.hpp" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef INCLUDED_B100_IMPL_HPP +#define INCLUDED_B100_IMPL_HPP + +/*! + * Make a b100 dboard interface. + * \param iface the b100 interface object + * \param clock the clock control interface + * \param codec the codec control interface + * \return a sptr to a new dboard interface + */ +uhd::usrp::dboard_iface::sptr make_b100_dboard_iface( + b100_iface::sptr iface, + b100_clock_ctrl::sptr clock, + b100_codec_ctrl::sptr codec +); + +/*! + * Simple wax obj proxy class: + * Provides a wax obj interface for a set and a get function. + * This allows us to create nested properties structures + * while maintaining flattened code within the implementation. + */ +class wax_obj_proxy : public wax::obj { +public: + typedef boost::function get_t; + typedef boost::function set_t; + typedef boost::shared_ptr sptr; + + static sptr make(const get_t &get, const set_t &set){ + return sptr(new wax_obj_proxy(get, set)); + } + +private: + get_t _get; set_t _set; + wax_obj_proxy(const get_t &get, const set_t &set): _get(get), _set(set) {}; + void get(const wax::obj &key, wax::obj &val) {return _get(key, val);} + void set(const wax::obj &key, const wax::obj &val) {return _set(key, val);} +}; + +/*! + * USRP1 implementation guts: + * The implementation details are encapsulated here. + * Handles properties on the mboard, dboard, dsps... + */ +class b100_impl : public uhd::device { +public: + //structors + b100_impl(uhd::transport::usb_zero_copy::sptr data_transport, + uhd::transport::usb_zero_copy::sptr ctrl_transport, + uhd::usrp::fx2_ctrl::sptr fx2_ctrl, + double master_clock_rate); + + ~b100_impl(void); + + //the io interface + size_t send(const send_buffs_type &, + size_t, + const uhd::tx_metadata_t &, + const uhd::io_type_t &, + send_mode_t, double); + + size_t recv(const recv_buffs_type &, + size_t, uhd::rx_metadata_t &, + const uhd::io_type_t &, + recv_mode_t, double); + + size_t get_max_send_samps_per_packet(void) const; + + size_t get_max_recv_samps_per_packet(void) const; + + bool recv_async_msg(uhd::async_metadata_t &, double); + +private: + //clock control + b100_clock_ctrl::sptr _clock_ctrl; + + //interface to ioctls and file descriptor + b100_iface::sptr _iface; + + //handle io stuff + uhd::transport::zero_copy_if::sptr _data_transport; + UHD_PIMPL_DECL(io_impl) _io_impl; + void update_transport_channel_mapping(void); + void io_init(void); + void issue_stream_cmd(const uhd::stream_cmd_t &stream_cmd); + void handle_overrun(size_t); + + //otw types + uhd::otw_type_t _recv_otw_type; + uhd::otw_type_t _send_otw_type; + + //configuration shadows + uhd::clock_config_t _clock_config; + uhd::usrp::subdev_spec_t _rx_subdev_spec, _tx_subdev_spec; + + //ad9862 codec control interface + b100_codec_ctrl::sptr _codec_ctrl; + + //codec properties interfaces + void codec_init(void); + void rx_codec_get(const wax::obj &, wax::obj &); + void rx_codec_set(const wax::obj &, const wax::obj &); + void tx_codec_get(const wax::obj &, wax::obj &); + void tx_codec_set(const wax::obj &, const wax::obj &); + wax_obj_proxy::sptr _rx_codec_proxy, _tx_codec_proxy; + + //device functions and settings + void get(const wax::obj &, wax::obj &); + void set(const wax::obj &, const wax::obj &); + + //mboard functions and settings + void mboard_init(void); + void mboard_get(const wax::obj &, wax::obj &); + void mboard_set(const wax::obj &, const wax::obj &); + void update_clock_config(void); + wax_obj_proxy::sptr _mboard_proxy; + + /*! + * Make a usrp1 dboard interface. + * \param iface the usrp1 interface object + * \param clock the clock control interface + * \param codec the codec control interface + * \param dboard_slot the slot identifier + * \param rx_dboard_id the db id for the rx board (used for evil dbsrx purposes) + * \return a sptr to a new dboard interface + */ + static uhd::usrp::dboard_iface::sptr make_dboard_iface( + b100_iface::sptr iface, + b100_clock_ctrl::sptr clock, + b100_codec_ctrl::sptr codec, + const uhd::usrp::dboard_id_t &rx_dboard_id + ); + + //xx dboard functions and settings + void dboard_init(void); + uhd::usrp::dboard_manager::sptr _dboard_manager; + uhd::usrp::dboard_iface::sptr _dboard_iface; + + //rx dboard functions and settings + uhd::usrp::dboard_eeprom_t _rx_db_eeprom; + void rx_dboard_get(const wax::obj &, wax::obj &); + void rx_dboard_set(const wax::obj &, const wax::obj &); + wax_obj_proxy::sptr _rx_dboard_proxy; + + //tx dboard functions and settings + uhd::usrp::dboard_eeprom_t _tx_db_eeprom, _gdb_eeprom; + void tx_dboard_get(const wax::obj &, wax::obj &); + void tx_dboard_set(const wax::obj &, const wax::obj &); + wax_obj_proxy::sptr _tx_dboard_proxy; + + //rx ddc functions and settings + void rx_ddc_init(void); + void rx_ddc_get(const wax::obj &, wax::obj &); + void rx_ddc_set(const wax::obj &, const wax::obj &); + double _ddc_freq; size_t _ddc_decim; + wax_obj_proxy::sptr _rx_ddc_proxy; + + //tx duc functions and settings + void tx_duc_init(void); + void tx_duc_get(const wax::obj &, wax::obj &); + void tx_duc_set(const wax::obj &, const wax::obj &); + double _duc_freq; size_t _duc_interp; + wax_obj_proxy::sptr _tx_duc_proxy; + + //transports + b100_ctrl::sptr _fpga_ctrl; + uhd::usrp::fx2_ctrl::sptr _fx2_ctrl; + +}; + +#endif /* INCLUDED_b100_IMPL_HPP */ diff --git a/host/lib/usrp/usrp_b100/b100_regs.hpp b/host/lib/usrp/usrp_b100/b100_regs.hpp new file mode 100644 index 000000000..010df283e --- /dev/null +++ b/host/lib/usrp/usrp_b100/b100_regs.hpp @@ -0,0 +1,264 @@ + + +//////////////////////////////////////////////////////////////// +// +// Memory map for wishbone bus +// +//////////////////////////////////////////////////////////////// + +// All addresses are byte addresses. All accesses are word (16-bit) accesses. +// This means that address bit 0 is usually 0. +// There are 11 bits of address for the control. + +#ifndef __B100_REGS_H +#define __B100_REGS_H + +///////////////////////////////////////////////////// +// Slave pointers + +#define B100_REG_SLAVE(n) ((n)<<7) +#define B100_REG_SR_ADDR(n) ((B100_REG_SETTINGS_BASE) + (4*(n))) + +///////////////////////////////////////////////////// +// Slave 0 -- Misc Regs + +#define B100_REG_MISC_BASE B100_REG_SLAVE(0) + +#define B100_REG_MISC_LED B100_REG_MISC_BASE + 0 +#define B100_REG_MISC_SW B100_REG_MISC_BASE + 2 +#define B100_REG_MISC_CGEN_CTRL B100_REG_MISC_BASE + 4 +#define B100_REG_MISC_CGEN_ST B100_REG_MISC_BASE + 6 +#define B100_REG_MISC_TEST B100_REG_MISC_BASE + 8 +#define B100_REG_MISC_RX_LEN B100_REG_MISC_BASE + 10 +#define B100_REG_MISC_TX_LEN B100_REG_MISC_BASE + 12 +#define B100_REG_MISC_XFER_RATE B100_REG_MISC_BASE + 14 +#define B100_REG_MISC_COMPAT B100_REG_MISC_BASE + 16 + +///////////////////////////////////////////////////// +// Slave 1 -- UART +// CLKDIV is 16 bits, others are only 8 + +#define B100_REG_UART_BASE B100_REG_SLAVE(1) + +#define B100_REG_UART_CLKDIV B100_REG_UART_BASE + 0 +#define B100_REG_UART_TXLEVEL B100_REG_UART_BASE + 2 +#define B100_REG_UART_RXLEVEL B100_REG_UART_BASE + 4 +#define B100_REG_UART_TXCHAR B100_REG_UART_BASE + 6 +#define B100_REG_UART_RXCHAR B100_REG_UART_BASE + 8 + +///////////////////////////////////////////////////// +// Slave 2 -- SPI Core +//these are 32-bit registers mapped onto the 16-bit Wishbone bus. +//Using peek32/poke32 should allow transparent use of these registers. +#define B100_REG_SPI_BASE B100_REG_SLAVE(2) +#define B100_REG_SPI_TXRX0 B100_REG_SPI_BASE + 0 +#define B100_REG_SPI_TXRX1 B100_REG_SPI_BASE + 4 +#define B100_REG_SPI_TXRX2 B100_REG_SPI_BASE + 8 +#define B100_REG_SPI_TXRX3 B100_REG_SPI_BASE + 12 +#define B100_REG_SPI_CTRL B100_REG_SPI_BASE + 16 +#define B100_REG_SPI_DIV B100_REG_SPI_BASE + 20 +#define B100_REG_SPI_SS B100_REG_SPI_BASE + 24 + +//spi slave constants +#define B100_SPI_SS_AD9862 (1 << 2) +#define B100_SPI_SS_TX_DB (1 << 1) +#define B100_SPI_SS_RX_DB (1 << 0) + +//spi ctrl register bit definitions +#define SPI_CTRL_ASS (1<<13) +#define SPI_CTRL_IE (1<<12) +#define SPI_CTRL_LSB (1<<11) +#define SPI_CTRL_TXNEG (1<<10) //mosi edge, push on falling edge when 1 +#define SPI_CTRL_RXNEG (1<< 9) //miso edge, latch on falling edge when 1 +#define SPI_CTRL_GO_BSY (1<< 8) +#define SPI_CTRL_CHAR_LEN_MASK 0x7F + +//////////////////////////////////////////////// +// Slave 3 -- I2C Core + +#define B100_REG_I2C_BASE B100_REG_SLAVE(3) +#define B100_REG_I2C_PRESCALER_LO B100_REG_I2C_BASE + 0 +#define B100_REG_I2C_PRESCALER_HI B100_REG_I2C_BASE + 2 +#define B100_REG_I2C_CTRL B100_REG_I2C_BASE + 4 +#define B100_REG_I2C_DATA B100_REG_I2C_BASE + 6 +#define B100_REG_I2C_CMD_STATUS B100_REG_I2C_BASE + 8 + +//and while we're here... + +// +// STA, STO, RD, WR, and IACK bits are cleared automatically +// + +#define I2C_CTRL_EN (1 << 7) // core enable +#define I2C_CTRL_IE (1 << 6) // interrupt enable + +#define I2C_CMD_START (1 << 7) // generate (repeated) start condition +#define I2C_CMD_STOP (1 << 6) // generate stop condition +#define I2C_CMD_RD (1 << 5) // read from slave +#define I2C_CMD_WR (1 << 4) // write to slave +#define I2C_CMD_NACK (1 << 3) // when a rcvr, send ACK (ACK=0) or NACK (ACK=1) +#define I2C_CMD_RSVD_2 (1 << 2) // reserved +#define I2C_CMD_RSVD_1 (1 << 1) // reserved +#define I2C_CMD_IACK (1 << 0) // set to clear pending interrupt + +#define I2C_ST_RXACK (1 << 7) // Received acknowledgement from slave (1 = NAK, 0 = ACK) +#define I2C_ST_BUSY (1 << 6) // 1 after START signal detected; 0 after STOP signal detected +#define I2C_ST_AL (1 << 5) // Arbitration lost. 1 when core lost arbitration +#define I2C_ST_RSVD_4 (1 << 4) // reserved +#define I2C_ST_RSVD_3 (1 << 3) // reserved +#define I2C_ST_RSVD_2 (1 << 2) // reserved +#define I2C_ST_TIP (1 << 1) // Transfer-in-progress +#define I2C_ST_IP (1 << 0) // Interrupt pending + +//////////////////////////////////////////////// +// Slave 4 -- GPIO + +#define B100_REG_GPIO_BASE B100_REG_SLAVE(4) + +#define B100_REG_GPIO_RX_IO B100_REG_GPIO_BASE + 0 +#define B100_REG_GPIO_TX_IO B100_REG_GPIO_BASE + 2 +#define B100_REG_GPIO_RX_DDR B100_REG_GPIO_BASE + 4 +#define B100_REG_GPIO_TX_DDR B100_REG_GPIO_BASE + 6 +#define B100_REG_GPIO_RX_SEL B100_REG_GPIO_BASE + 8 +#define B100_REG_GPIO_TX_SEL B100_REG_GPIO_BASE + 10 +#define B100_REG_GPIO_RX_DBG B100_REG_GPIO_BASE + 12 +#define B100_REG_GPIO_TX_DBG B100_REG_GPIO_BASE + 14 + +//possible bit values for sel when dbg is 0: +#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg +#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic + +//possible bit values for sel when dbg is 1: +#define GPIO_SEL_DEBUG_0 0 // if pin is an output, debug lines from FPGA fabric +#define GPIO_SEL_DEBUG_1 1 // if pin is an output, debug lines from FPGA fabric + +/////////////////////////////////////////////////// +// Slave 6 -- ATR Controller +// 16 regs + +#define B100_REG_ATR_BASE B100_REG_SLAVE(6) + +#define B100_REG_ATR_IDLE_RXSIDE B100_REG_ATR_BASE + 0 +#define B100_REG_ATR_IDLE_TXSIDE B100_REG_ATR_BASE + 2 +#define B100_REG_ATR_INTX_RXSIDE B100_REG_ATR_BASE + 4 +#define B100_REG_ATR_INTX_TXSIDE B100_REG_ATR_BASE + 6 +#define B100_REG_ATR_INRX_RXSIDE B100_REG_ATR_BASE + 8 +#define B100_REG_ATR_INRX_TXSIDE B100_REG_ATR_BASE + 10 +#define B100_REG_ATR_FULL_RXSIDE B100_REG_ATR_BASE + 12 +#define B100_REG_ATR_FULL_TXSIDE B100_REG_ATR_BASE + 14 + +/////////////////////////////////////////////////// +// Slave 7 -- Readback Mux 32 + +#define B100_REG_RB_MUX_32_BASE B100_REG_SLAVE(7) + +#define B100_REG_RB_TIME_NOW_SECS B100_REG_RB_MUX_32_BASE + 0 +#define B100_REG_RB_TIME_NOW_TICKS B100_REG_RB_MUX_32_BASE + 4 +#define B100_REG_RB_TIME_PPS_SECS B100_REG_RB_MUX_32_BASE + 8 +#define B100_REG_RB_TIME_PPS_TICKS B100_REG_RB_MUX_32_BASE + 12 +#define B100_REG_RB_MISC_TEST32 B100_REG_RB_MUX_32_BASE + 16 + +//////////////////////////////////////////////////// +// Slaves 8 & 9 -- Settings Bus +// +// Output-only, no readback, 64 registers total +// Each register must be written 32 bits at a time +// First the address xxx_xx00 and then xxx_xx10 + +#define B100_REG_SETTINGS_BASE_ADDR(n) (B100_REG_SLAVE(8) + (4*(n))) + +#define B100_REG_SR_MISC_TEST32 B100_REG_SETTINGS_BASE_ADDR(52) + +///////////////////////////////////////////////// +// DSP RX Regs +//////////////////////////////////////////////// +#define B100_REG_DSP_RX_ADDR(n) (B100_REG_SETTINGS_BASE_ADDR(16) + (4*(n))) +#define B100_REG_DSP_RX_FREQ B100_REG_DSP_RX_ADDR(0) +#define B100_REG_DSP_RX_SCALE_IQ B100_REG_DSP_RX_ADDR(1) // {scale_i,scale_q} +#define B100_REG_DSP_RX_DECIM_RATE B100_REG_DSP_RX_ADDR(2) // hb and decim rate +#define B100_REG_DSP_RX_DCOFFSET_I B100_REG_DSP_RX_ADDR(3) // Bit 31 high sets fixed offset mode, using lower 14 bits, // otherwise it is automatic +#define B100_REG_DSP_RX_DCOFFSET_Q B100_REG_DSP_RX_ADDR(4) // Bit 31 high sets fixed offset mode, using lower 14 bits +#define B100_REG_DSP_RX_MUX B100_REG_DSP_RX_ADDR(5) + +/////////////////////////////////////////////////// +// VITA RX CTRL regs +/////////////////////////////////////////////////// +// The following 3 are logically a single command register. +// They are clocked into the underlying fifo when time_ticks is written. +#define B100_REG_CTRL_RX_ADDR(n) (B100_REG_SETTINGS_BASE_ADDR(0) + (4*(n))) +#define B100_REG_CTRL_RX_STREAM_CMD B100_REG_CTRL_RX_ADDR(0) // {now, chain, num_samples(30) +#define B100_REG_CTRL_RX_TIME_SECS B100_REG_CTRL_RX_ADDR(1) +#define B100_REG_CTRL_RX_TIME_TICKS B100_REG_CTRL_RX_ADDR(2) +#define B100_REG_CTRL_RX_CLEAR_OVERRUN B100_REG_CTRL_RX_ADDR(3) // write anything to clear overrun +#define B100_REG_CTRL_RX_VRT_HEADER B100_REG_CTRL_RX_ADDR(4) // word 0 of packet. FPGA fills in packet counter +#define B100_REG_CTRL_RX_VRT_STREAM_ID B100_REG_CTRL_RX_ADDR(5) // word 1 of packet. +#define B100_REG_CTRL_RX_VRT_TRAILER B100_REG_CTRL_RX_ADDR(6) +#define B100_REG_CTRL_RX_NSAMPS_PER_PKT B100_REG_CTRL_RX_ADDR(7) +#define B100_REG_CTRL_RX_NCHANNELS B100_REG_CTRL_RX_ADDR(8) // 1 in basic case, up to 4 for vector sources + +///////////////////////////////////////////////// +// DSP TX Regs +//////////////////////////////////////////////// +#define B100_REG_DSP_TX_ADDR(n) (B100_REG_SETTINGS_BASE_ADDR(32) + (4*(n))) +#define B100_REG_DSP_TX_FREQ B100_REG_DSP_TX_ADDR(0) +#define B100_REG_DSP_TX_SCALE_IQ B100_REG_DSP_TX_ADDR(1) // {scale_i,scale_q} +#define B100_REG_DSP_TX_INTERP_RATE B100_REG_DSP_TX_ADDR(2) +#define B100_REG_DSP_TX_UNUSED B100_REG_DSP_TX_ADDR(3) +#define B100_REG_DSP_TX_MUX B100_REG_DSP_TX_ADDR(4) + +///////////////////////////////////////////////// +// VITA TX CTRL regs +//////////////////////////////////////////////// +#define B100_REG_CTRL_TX_ADDR(n) (B100_REG_SETTINGS_BASE_ADDR(24) + (4*(n))) +#define B100_REG_CTRL_TX_NCHANNELS B100_REG_CTRL_TX_ADDR(0) +#define B100_REG_CTRL_TX_CLEAR_UNDERRUN B100_REG_CTRL_TX_ADDR(1) +#define B100_REG_CTRL_TX_REPORT_SID B100_REG_CTRL_TX_ADDR(2) +#define B100_REG_CTRL_TX_POLICY B100_REG_CTRL_TX_ADDR(3) + +#define B100_FLAG_CTRL_TX_POLICY_WAIT (0x1 << 0) +#define B100_FLAG_CTRL_TX_POLICY_NEXT_PACKET (0x1 << 1) +#define B100_FLAG_CTRL_TX_POLICY_NEXT_BURST (0x1 << 2) + +///////////////////////////////////////////////// +// VITA49 64 bit time (write only) +//////////////////////////////////////////////// + /*! + * \brief Time 64 flags + * + * 
+   *
+   *    3                   2                   1
+   *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   * +-----------------------------------------------------------+-+-+
+   * |                                                           |S|P|
+   * +-----------------------------------------------------------+-+-+
+   *
+   * P - PPS edge selection (0=negedge, 1=posedge, default=0)
+   * S - Source (0=sma, 1=mimo, 0=default)
+   *
+   *
+ */ +#define B100_REG_TIME64_ADDR(n) (B100_REG_SETTINGS_BASE_ADDR(40) + (4*(n))) +#define B100_REG_TIME64_SECS B100_REG_TIME64_ADDR(0) // value to set absolute secs to on next PPS +#define B100_REG_TIME64_TICKS B100_REG_TIME64_ADDR(1) // value to set absolute ticks to on next PPS +#define B100_REG_TIME64_FLAGS B100_REG_TIME64_ADDR(2) // flags - see chart above +#define B100_REG_TIME64_IMM B100_REG_TIME64_ADDR(3) // set immediate (0=latch on next pps, 1=latch immediate, default=0) +#define B100_REG_TIME64_TPS B100_REG_TIME64_ADDR(4) // clock ticks per second (counter rollover) + +//pps flags (see above) +#define B100_FLAG_TIME64_PPS_NEGEDGE (0 << 0) +#define B100_FLAG_TIME64_PPS_POSEDGE (1 << 0) +#define B100_FLAG_TIME64_PPS_SMA (0 << 1) +#define B100_FLAG_TIME64_PPS_MIMO (1 << 1) + +#define B100_FLAG_TIME64_LATCH_NOW 1 +#define B100_FLAG_TIME64_LATCH_NEXT_PPS 0 + +#define B100_REG_CLEAR_RX_FIFO B100_REG_SETTINGS_BASE_ADDR(48) +#define B100_REG_CLEAR_TX_FIFO B100_REG_SETTINGS_BASE_ADDR(49) + +#define B100_REG_GLOBAL_RESET B100_REG_SETTINGS_BASE_ADDR(50) +#define B100_REG_TEST32 B100_REG_SETTINGS_BASE_ADDR(52) + +#endif + diff --git a/host/lib/usrp/usrp_b100/clock_ctrl.cpp b/host/lib/usrp/usrp_b100/clock_ctrl.cpp new file mode 100644 index 000000000..e138242d1 --- /dev/null +++ b/host/lib/usrp/usrp_b100/clock_ctrl.cpp @@ -0,0 +1,525 @@ +// +// Copyright 2010-2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "clock_ctrl.hpp" +#include "ad9522_regs.hpp" +#include +#include +#include +#include +#include +#include +#include "b100_regs.hpp" //spi slave constants +#include +#include +#include +#include +#include //gcd +#include +#include + +using namespace uhd; + +/*********************************************************************** + * Constants + **********************************************************************/ +static const bool ENABLE_THE_TEST_OUT = true; +static const double REFERENCE_INPUT_RATE = 10e6; + +/*********************************************************************** + * Helpers + **********************************************************************/ +template static void set_clock_divider( + size_t divider, div_type &low, div_type &high, bypass_type &bypass +){ + high = divider/2 - 1; + low = divider - high - 2; + bypass = (divider == 1)? 1 : 0; +} + +/*********************************************************************** + * Clock rate calculation stuff: + * Using the internal VCO between 1400 and 1800 MHz + **********************************************************************/ +struct clock_settings_type{ + size_t ref_clock_doubler, r_counter, a_counter, b_counter, prescaler, vco_divider, chan_divider; + size_t get_n_counter(void) const{return prescaler * b_counter + a_counter;} + double get_ref_rate(void) const{return REFERENCE_INPUT_RATE * ref_clock_doubler;} + double get_vco_rate(void) const{return get_ref_rate()/r_counter * get_n_counter();} + double get_chan_rate(void) const{return get_vco_rate()/vco_divider;} + double get_out_rate(void) const{return get_chan_rate()/chan_divider;} + std::string to_pp_string(void) const{ + return str(boost::format( + " r_counter: %d\n" + " a_counter: %d\n" + " b_counter: %d\n" + " prescaler: %d\n" + " vco_divider: %d\n" + " chan_divider: %d\n" + " vco_rate: %fMHz\n" + " chan_rate: %fMHz\n" + " out_rate: %fMHz\n" + ) + % r_counter + % a_counter + % b_counter + % prescaler + % vco_divider + % chan_divider + % (get_vco_rate()/1e6) + % (get_chan_rate()/1e6) + % (get_out_rate()/1e6) + ); + } +}; + +//! gives the greatest divisor of num between 1 and max inclusive +template static inline T greatest_divisor(T num, T max){ + for (T i = max; i > 1; i--) if (num%i == 0) return i; return 1; +} + +//! gives the least divisor of num between min and num exclusive +template static inline T least_divisor(T num, T min){ + for (T i = min; i < num; i++) if (num%i == 0) return i; return 1; +} + +static clock_settings_type get_clock_settings(double rate){ + clock_settings_type cs; + cs.ref_clock_doubler = 2; //always doubling + cs.prescaler = 8; //set to 8 when input is under 2400 MHz + + //basic formulas used below: + //out_rate*X = ref_rate*Y + //X = i*ref_rate/gcd + //Y = i*out_rate/gcd + //X = chan_div * vco_div * R + //Y = P*B + A + + const boost::uint64_t out_rate = boost::uint64_t(rate); + const boost::uint64_t ref_rate = boost::uint64_t(cs.get_ref_rate()); + const size_t gcd = size_t(boost::math::gcd(ref_rate, out_rate)); + + for (size_t i = 1; i <= 100; i++){ + const size_t X = i*ref_rate/gcd; + const size_t Y = i*out_rate/gcd; + + //determine A and B (P is fixed) + cs.b_counter = Y/cs.prescaler; + cs.a_counter = Y - cs.b_counter*cs.prescaler; + + static const double vco_bound_pad = 100e6; + for ( //calculate an r divider that fits into the bounds of the vco + cs.r_counter = size_t(cs.get_n_counter()*cs.get_ref_rate()/(1800e6 - vco_bound_pad)); + cs.r_counter <= size_t(cs.get_n_counter()*cs.get_ref_rate()/(1400e6 + vco_bound_pad)) + and cs.r_counter > 0; cs.r_counter++ + ){ + + //determine chan_div and vco_div + //and fill in that order of preference + cs.chan_divider = greatest_divisor(X/cs.r_counter, 32); + cs.vco_divider = greatest_divisor(X/cs.chan_divider/cs.r_counter, 6); + + //avoid a vco divider of 1 (if possible) + if (cs.vco_divider == 1){ + cs.vco_divider = least_divisor(cs.chan_divider, 2); + cs.chan_divider /= cs.vco_divider; + } + + UHD_LOGV(always) + << "gcd " << gcd << std::endl + << "X " << X << std::endl + << "Y " << Y << std::endl + << cs.to_pp_string() << std::endl + ; + + //filter limits on the counters + if (cs.vco_divider == 1) continue; + if (cs.r_counter >= (1<<14)) continue; + if (cs.b_counter == 2) continue; + if (cs.b_counter == 1 and cs.a_counter != 0) continue; + if (cs.b_counter >= (1<<13)) continue; + if (cs.a_counter >= (1<<6)) continue; + + UHD_MSG(status) << "USRP-B100 clock control: " << i << std::endl << cs.to_pp_string() << std::endl; + return cs; + } + } + + throw uhd::runtime_error(str(boost::format( + "USRP-B100 clock control: could not calculate settings for clock rate %fMHz" + ) % (rate/1e6))); +} + +/*********************************************************************** + * Clock Control Implementation + **********************************************************************/ +class b100_clock_ctrl_impl : public b100_clock_ctrl{ +public: + b100_clock_ctrl_impl(b100_iface::sptr iface, double master_clock_rate){ + _iface = iface; + _chan_rate = 0.0; + _out_rate = 0.0; + + //init the clock gen registers + _ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO; + _ad9522_regs.enb_stat_eeprom_at_stat_pin = 0; //use status pin + _ad9522_regs.status_pin_control = 0x1; //n divider + _ad9522_regs.ld_pin_control = 0x00; //dld + _ad9522_regs.refmon_pin_control = 0x12; //show ref2 + _ad9522_regs.lock_detect_counter = ad9522_regs_t::LOCK_DETECT_COUNTER_16CYC; + + this->use_internal_ref(); + + this->set_fpga_clock_rate(master_clock_rate); //initialize to something + + this->enable_fpga_clock(true); + this->enable_test_clock(ENABLE_THE_TEST_OUT); + this->enable_rx_dboard_clock(false); + this->enable_tx_dboard_clock(false); + } + + ~b100_clock_ctrl_impl(void){ + UHD_SAFE_CALL( + this->enable_test_clock(ENABLE_THE_TEST_OUT); + this->enable_rx_dboard_clock(false); + this->enable_tx_dboard_clock(false); + //this->enable_fpga_clock(false); //FIXME + ) + } + + /*********************************************************************** + * Clock rate control: + * - set clock rate w/ internal VCO + * - set clock rate w/ external VCXO + **********************************************************************/ + void set_clock_settings_with_internal_vco(double rate){ + const clock_settings_type cs = get_clock_settings(rate); + + //set the rates to private variables so the implementation knows! + _chan_rate = cs.get_chan_rate(); + _out_rate = cs.get_out_rate(); + + _ad9522_regs.enable_clock_doubler = (cs.ref_clock_doubler == 2)? 1 : 0; + + _ad9522_regs.set_r_counter(cs.r_counter); + _ad9522_regs.a_counter = cs.a_counter; + _ad9522_regs.set_b_counter(cs.b_counter); + UHD_ASSERT_THROW(cs.prescaler == 8); //assumes this below: + _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV8_9; + + _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL; + _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA; + + _ad9522_regs.bypass_vco_divider = 0; + switch(cs.vco_divider){ + case 1: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV1; break; + case 2: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV2; break; + case 3: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV3; break; + case 4: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV4; break; + case 5: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5; break; + case 6: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV6; break; + } + _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_VCO; + + //setup fpga master clock + _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; + set_clock_divider(cs.chan_divider, + _ad9522_regs.divider0_low_cycles, + _ad9522_regs.divider0_high_cycles, + _ad9522_regs.divider0_bypass + ); + + //setup codec clock + _ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS; + set_clock_divider(cs.chan_divider, + _ad9522_regs.divider1_low_cycles, + _ad9522_regs.divider1_high_cycles, + _ad9522_regs.divider1_bypass + ); + + this->send_all_regs(); + calibrate_now(); + } + + void set_clock_settings_with_external_vcxo(double rate){ + //set the rates to private variables so the implementation knows! + _chan_rate = rate; + _out_rate = rate; + + _ad9522_regs.enable_clock_doubler = 1; //doubler always on + const double ref_rate = REFERENCE_INPUT_RATE*2; + + //bypass prescaler such that N = B + long gcd = boost::math::gcd(long(ref_rate), long(rate)); + _ad9522_regs.set_r_counter(int(ref_rate/gcd)); + _ad9522_regs.a_counter = 0; + _ad9522_regs.set_b_counter(int(rate/gcd)); + _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV1; + + //setup external vcxo + _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL; + _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA; + _ad9522_regs.bypass_vco_divider = 1; + _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_EXTERNAL; + + //setup fpga master clock + _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; + _ad9522_regs.divider0_bypass = 1; + + //setup codec clock + _ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS; + _ad9522_regs.divider1_bypass = 1; + + this->send_all_regs(); + } + + void set_fpga_clock_rate(double rate){ + if (_out_rate == rate) return; + if (rate == 61.44e6) set_clock_settings_with_external_vcxo(rate); + else set_clock_settings_with_internal_vco(rate); + //clock rate changed! update dboard clocks and FPGA ticks per second + set_rx_dboard_clock_rate(rate); + set_tx_dboard_clock_rate(rate); + _iface->poke32(B100_REG_TIME64_TPS, boost::uint32_t(get_fpga_clock_rate())); + } + + double get_fpga_clock_rate(void){ + return this->_out_rate; + } + + /*********************************************************************** + * FPGA clock enable + **********************************************************************/ + void enable_fpga_clock(bool enb){ + _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; + _ad9522_regs.out0_lvds_power_down = !enb; + this->send_reg(0x0F0); + this->latch_regs(); + } + + /*********************************************************************** + * Special test clock output + **********************************************************************/ + void enable_test_clock(bool enb){ + //setup test clock (same divider as codec clock) + _ad9522_regs.out4_format = ad9522_regs_t::OUT4_FORMAT_CMOS; + _ad9522_regs.out4_cmos_configuration = (enb)? + ad9522_regs_t::OUT4_CMOS_CONFIGURATION_A_ON : + ad9522_regs_t::OUT4_CMOS_CONFIGURATION_OFF; + this->send_reg(0x0F4); + this->latch_regs(); + } + + /*********************************************************************** + * RX Dboard Clock Control (output 9, divider 3) + **********************************************************************/ + void enable_rx_dboard_clock(bool enb){ + _ad9522_regs.out9_format = ad9522_regs_t::OUT9_FORMAT_CMOS; + _ad9522_regs.out9_cmos_configuration = (enb)? + ad9522_regs_t::OUT9_CMOS_CONFIGURATION_B_ON : + ad9522_regs_t::OUT9_CMOS_CONFIGURATION_OFF; + this->send_reg(0x0F9); + this->latch_regs(); + } + + std::vector get_rx_dboard_clock_rates(void){ + std::vector rates; + for(size_t div = 1; div <= 16+16; div++) + rates.push_back(this->_chan_rate/div); + return rates; + } + + void set_rx_dboard_clock_rate(double rate){ + assert_has(get_rx_dboard_clock_rates(), rate, "rx dboard clock rate"); + _rx_clock_rate = rate; + size_t divider = size_t(this->_chan_rate/rate); + //set the divider registers + set_clock_divider(divider, + _ad9522_regs.divider3_low_cycles, + _ad9522_regs.divider3_high_cycles, + _ad9522_regs.divider3_bypass + ); + this->send_reg(0x199); + this->send_reg(0x19a); + this->soft_sync(); + } + + double get_rx_clock_rate(void){ + return _rx_clock_rate; + } + + /*********************************************************************** + * TX Dboard Clock Control (output 6, divider 2) + **********************************************************************/ + void enable_tx_dboard_clock(bool enb){ + _ad9522_regs.out6_format = ad9522_regs_t::OUT6_FORMAT_CMOS; + _ad9522_regs.out6_cmos_configuration = (enb)? + ad9522_regs_t::OUT6_CMOS_CONFIGURATION_B_ON : + ad9522_regs_t::OUT6_CMOS_CONFIGURATION_OFF; + this->send_reg(0x0F6); + this->latch_regs(); + } + + std::vector get_tx_dboard_clock_rates(void){ + return get_rx_dboard_clock_rates(); //same master clock, same dividers... + } + + void set_tx_dboard_clock_rate(double rate){ + assert_has(get_tx_dboard_clock_rates(), rate, "tx dboard clock rate"); + _tx_clock_rate = rate; + size_t divider = size_t(this->_chan_rate/rate); + //set the divider registers + set_clock_divider(divider, + _ad9522_regs.divider2_low_cycles, + _ad9522_regs.divider2_high_cycles, + _ad9522_regs.divider2_bypass + ); + this->send_reg(0x196); + this->send_reg(0x197); + this->soft_sync(); + } + + double get_tx_clock_rate(void){ + return _tx_clock_rate; + } + + /*********************************************************************** + * Clock reference control + **********************************************************************/ + void use_internal_ref(void) { + _ad9522_regs.enable_ref2 = 1; + _ad9522_regs.enable_ref1 = 0; + _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF2; + _ad9522_regs.enb_auto_ref_switchover = ad9522_regs_t::ENB_AUTO_REF_SWITCHOVER_MANUAL; + this->send_reg(0x01C); + this->latch_regs(); + } + + void use_external_ref(void) { + _ad9522_regs.enable_ref2 = 0; + _ad9522_regs.enable_ref1 = 1; + _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF1; + _ad9522_regs.enb_auto_ref_switchover = ad9522_regs_t::ENB_AUTO_REF_SWITCHOVER_MANUAL; + this->send_reg(0x01C); + this->latch_regs(); + } + + void use_auto_ref(void) { + _ad9522_regs.enable_ref2 = 1; + _ad9522_regs.enable_ref1 = 1; + _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF1; + _ad9522_regs.enb_auto_ref_switchover = ad9522_regs_t::ENB_AUTO_REF_SWITCHOVER_AUTO; + this->send_reg(0x01C); + this->latch_regs(); + } + +private: + b100_iface::sptr _iface; + ad9522_regs_t _ad9522_regs; + double _out_rate; //rate at the fpga and codec + double _chan_rate; //rate before final dividers + double _rx_clock_rate, _tx_clock_rate; + + void latch_regs(void){ + _ad9522_regs.io_update = 1; + this->send_reg(0x232); + } + + void send_reg(boost::uint16_t addr){ + boost::uint32_t reg = _ad9522_regs.get_write_reg(addr); + UHD_LOGV(often) << "clock control write reg: " << std::hex << reg << std::endl; + byte_vector_t buf; + buf.push_back(boost::uint8_t(reg >> 16)); + buf.push_back(boost::uint8_t(reg >> 8)); + buf.push_back(boost::uint8_t(reg & 0xff)); + + _iface->get_fx2_i2c_iface().write_i2c(0x5C, buf); + } + + boost::uint8_t read_reg(boost::uint16_t addr){ + byte_vector_t buf; + buf.push_back(boost::uint8_t(addr >> 8)); + buf.push_back(boost::uint8_t(addr & 0xff)); + _iface->get_fx2_i2c_iface().write_i2c(0x5C, buf); + + buf = _iface->get_fx2_i2c_iface().read_i2c(0x5C, 1); + + return boost::uint32_t(buf[0] & 0xFF); + } + + void calibrate_now(void){ + //vco calibration routine: + _ad9522_regs.vco_calibration_now = 0; + this->send_reg(0x18); + this->latch_regs(); + _ad9522_regs.vco_calibration_now = 1; + this->send_reg(0x18); + this->latch_regs(); + //wait for calibration done: + static const boost::uint8_t addr = 0x01F; + for (size_t ms10 = 0; ms10 < 100; ms10++){ + boost::this_thread::sleep(boost::posix_time::milliseconds(10)); + boost::uint32_t reg = read_reg(addr); + _ad9522_regs.set_reg(addr, reg); + if (_ad9522_regs.vco_calibration_finished) goto wait_for_ld; + } + UHD_MSG(error) << "USRP-B100 clock control: VCO calibration timeout" << std::endl; + wait_for_ld: + //wait for digital lock detect: + for (size_t ms10 = 0; ms10 < 100; ms10++){ + boost::this_thread::sleep(boost::posix_time::milliseconds(10)); + boost::uint32_t reg = read_reg(addr); + _ad9522_regs.set_reg(addr, reg); + if (_ad9522_regs.digital_lock_detect) return; + } + UHD_MSG(error) << "USRP-B100 clock control: lock detection timeout" << std::endl; + } + + void soft_sync(void){ + _ad9522_regs.soft_sync = 1; + this->send_reg(0x230); + this->latch_regs(); + _ad9522_regs.soft_sync = 0; + this->send_reg(0x230); + this->latch_regs(); + } + + void send_all_regs(void){ + //setup a list of register ranges to write + typedef std::pair range_t; + static const std::vector ranges = boost::assign::list_of + (range_t(0x000, 0x000)) (range_t(0x010, 0x01F)) + (range_t(0x0F0, 0x0FD)) (range_t(0x190, 0x19B)) + (range_t(0x1E0, 0x1E1)) (range_t(0x230, 0x230)) + ; + + //write initial register values and latch/update + BOOST_FOREACH(const range_t &range, ranges){ + for(boost::uint16_t addr = range.first; addr <= range.second; addr++){ + this->send_reg(addr); + } + } + this->latch_regs(); + } +}; + +/*********************************************************************** + * Clock Control Make + **********************************************************************/ +b100_clock_ctrl::sptr b100_clock_ctrl::make(b100_iface::sptr iface, double master_clock_rate){ + return sptr(new b100_clock_ctrl_impl(iface, master_clock_rate)); +} diff --git a/host/lib/usrp/usrp_b100/clock_ctrl.hpp b/host/lib/usrp/usrp_b100/clock_ctrl.hpp new file mode 100644 index 000000000..2a2e74024 --- /dev/null +++ b/host/lib/usrp/usrp_b100/clock_ctrl.hpp @@ -0,0 +1,118 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_B100_CLOCK_CTRL_HPP +#define INCLUDED_B100_CLOCK_CTRL_HPP + +#include "b100_iface.hpp" +#include +#include +#include + +/*! + * The usrp-e clock control: + * - Setup system clocks. + * - Disable/enable clock lines. + */ +class b100_clock_ctrl : boost::noncopyable{ +public: + typedef boost::shared_ptr sptr; + + /*! + * Make a new clock control object. + * \param iface the b100 iface object + * \param master_clock_rate the master FPGA/sample clock rate + * \return the clock control object + */ + static sptr make(b100_iface::sptr iface, double master_clock_rate); + + /*! + * Set the rate of the fpga clock line. + * Throws if rate is not valid. + * \param rate the new rate in Hz + */ + virtual void set_fpga_clock_rate(double rate) = 0; + + /*! + * Get the rate of the fpga clock line. + * \return the fpga clock rate in Hz + */ + virtual double get_fpga_clock_rate(void) = 0; + + /*! + * Get the possible rates of the rx dboard clock. + * \return a vector of clock rates in Hz + */ + virtual std::vector get_rx_dboard_clock_rates(void) = 0; + + /*! + * Get the possible rates of the tx dboard clock. + * \return a vector of clock rates in Hz + */ + virtual std::vector get_tx_dboard_clock_rates(void) = 0; + + /*! + * Set the rx dboard clock rate to a possible rate. + * \param rate the new clock rate in Hz + * \throw exception when rate cannot be achieved + */ + virtual void set_rx_dboard_clock_rate(double rate) = 0; + + /*! + * Set the tx dboard clock rate to a possible rate. + * \param rate the new clock rate in Hz + * \throw exception when rate cannot be achieved + */ + virtual void set_tx_dboard_clock_rate(double rate) = 0; + + /*! + * Enable/disable the FPGA clock. + * \param enb true to enable + */ + + virtual void enable_fpga_clock(bool enb) = 0; + + /*! + * Enable/disable the rx dboard clock. + * \param enb true to enable + */ + virtual void enable_rx_dboard_clock(bool enb) = 0; + + /*! + * Enable/disable the tx dboard clock. + * \param enb true to enable + */ + virtual void enable_tx_dboard_clock(bool enb) = 0; + + /*! + * Use the internal TCXO reference + */ + virtual void use_internal_ref(void) = 0; + + /*! + * Use the external SMA reference + */ + virtual void use_external_ref(void) = 0; + + /*! + * Use external if available, internal otherwise + */ + virtual void use_auto_ref(void) = 0; + +}; + +#endif /* INCLUDED_B100_CLOCK_CTRL_HPP */ diff --git a/host/lib/usrp/usrp_b100/codec_ctrl.cpp b/host/lib/usrp/usrp_b100/codec_ctrl.cpp new file mode 100644 index 000000000..4d118b68b --- /dev/null +++ b/host/lib/usrp/usrp_b100/codec_ctrl.cpp @@ -0,0 +1,283 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "codec_ctrl.hpp" +#include "ad9862_regs.hpp" +#include +#include +#include +#include +#include +#include +#include +#include +#include "b100_regs.hpp" //spi slave constants +#include + +using namespace uhd; + +const gain_range_t b100_codec_ctrl::tx_pga_gain_range(-20, 0, double(0.1)); +const gain_range_t b100_codec_ctrl::rx_pga_gain_range(0, 20, 1); + +/*********************************************************************** + * Codec Control Implementation + **********************************************************************/ +class b100_codec_ctrl_impl : public b100_codec_ctrl{ +public: + //structors + b100_codec_ctrl_impl(b100_iface::sptr iface); + ~b100_codec_ctrl_impl(void); + + //aux adc and dac control + double read_aux_adc(aux_adc_t which); + void write_aux_dac(aux_dac_t which, double volts); + + //pga gain control + void set_tx_pga_gain(double); + double get_tx_pga_gain(void); + void set_rx_pga_gain(double, char); + double get_rx_pga_gain(char); + +private: + b100_iface::sptr _iface; + ad9862_regs_t _ad9862_regs; + void send_reg(boost::uint8_t addr); + void recv_reg(boost::uint8_t addr); +}; + +/*********************************************************************** + * Codec Control Structors + **********************************************************************/ +b100_codec_ctrl_impl::b100_codec_ctrl_impl(b100_iface::sptr iface){ + _iface = iface; + + //soft reset + _ad9862_regs.soft_reset = 1; + this->send_reg(0); + + //initialize the codec register settings + _ad9862_regs.sdio_bidir = ad9862_regs_t::SDIO_BIDIR_SDIO_SDO; + _ad9862_regs.lsb_first = ad9862_regs_t::LSB_FIRST_MSB; + _ad9862_regs.soft_reset = 0; + + //setup rx side of codec + _ad9862_regs.byp_buffer_a = 1; + _ad9862_regs.byp_buffer_b = 1; + _ad9862_regs.buffer_a_pd = 1; + _ad9862_regs.buffer_b_pd = 1; + _ad9862_regs.mux_out = ad9862_regs_t::MUX_OUT_RX_MUX_MODE; //B100 uses interleaved RX->FPGA + _ad9862_regs.rx_pga_a = 0;//0x1f; //TODO bring under api control + _ad9862_regs.rx_pga_b = 0;//0x1f; //TODO bring under api control + _ad9862_regs.rx_twos_comp = 1; + _ad9862_regs.rx_hilbert = ad9862_regs_t::RX_HILBERT_DIS; + + //setup tx side of codec + _ad9862_regs.two_data_paths = ad9862_regs_t::TWO_DATA_PATHS_BOTH; + _ad9862_regs.interleaved = ad9862_regs_t::INTERLEAVED_INTERLEAVED; + _ad9862_regs.tx_retime = ad9862_regs_t::TX_RETIME_CLKOUT2; + _ad9862_regs.tx_pga_gain = 199; //TODO bring under api control + _ad9862_regs.tx_hilbert = ad9862_regs_t::TX_HILBERT_DIS; + _ad9862_regs.interp = ad9862_regs_t::INTERP_2; + _ad9862_regs.tx_twos_comp = 1; + _ad9862_regs.fine_mode = ad9862_regs_t::FINE_MODE_BYPASS; + _ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_BYPASS; + _ad9862_regs.dac_a_coarse_gain = 0x3; + _ad9862_regs.dac_b_coarse_gain = 0x3; + _ad9862_regs.edges = ad9862_regs_t::EDGES_NORMAL; + + //setup the dll + _ad9862_regs.input_clk_ctrl = ad9862_regs_t::INPUT_CLK_CTRL_EXTERNAL; + _ad9862_regs.dll_mult = ad9862_regs_t::DLL_MULT_2; + _ad9862_regs.dll_mode = ad9862_regs_t::DLL_MODE_FAST; + + //write the register settings to the codec + for (uint8_t addr = 0; addr <= 25; addr++){ + this->send_reg(addr); + } + + //always start conversions for aux ADC + _ad9862_regs.start_a = 1; + _ad9862_regs.start_b = 1; + + //aux adc clock + _ad9862_regs.clk_4 = ad9862_regs_t::CLK_4_1_4; + this->send_reg(34); +} + +b100_codec_ctrl_impl::~b100_codec_ctrl_impl(void){ + UHD_SAFE_CALL( + //set aux dacs to zero + this->write_aux_dac(AUX_DAC_A, 0); + this->write_aux_dac(AUX_DAC_B, 0); + this->write_aux_dac(AUX_DAC_C, 0); + this->write_aux_dac(AUX_DAC_D, 0); + + //power down + _ad9862_regs.all_rx_pd = 1; + this->send_reg(1); + _ad9862_regs.tx_digital_pd = 1; + _ad9862_regs.tx_analog_pd = ad9862_regs_t::TX_ANALOG_PD_BOTH; + this->send_reg(8); + ) +} + +/*********************************************************************** + * Codec Control Gain Control Methods + **********************************************************************/ +static const int mtpgw = 255; //maximum tx pga gain word + +void b100_codec_ctrl_impl::set_tx_pga_gain(double gain){ + int gain_word = int(mtpgw*(gain - tx_pga_gain_range.start())/(tx_pga_gain_range.stop() - tx_pga_gain_range.start())); + _ad9862_regs.tx_pga_gain = uhd::clip(gain_word, 0, mtpgw); + this->send_reg(16); +} + +double b100_codec_ctrl_impl::get_tx_pga_gain(void){ + return (_ad9862_regs.tx_pga_gain*(tx_pga_gain_range.stop() - tx_pga_gain_range.start())/mtpgw) + tx_pga_gain_range.start(); +} + +static const int mrpgw = 0x14; //maximum rx pga gain word + +void b100_codec_ctrl_impl::set_rx_pga_gain(double gain, char which){ + int gain_word = int(mrpgw*(gain - rx_pga_gain_range.start())/(rx_pga_gain_range.stop() - rx_pga_gain_range.start())); + gain_word = uhd::clip(gain_word, 0, mrpgw); + switch(which){ + case 'A': + _ad9862_regs.rx_pga_a = gain_word; + this->send_reg(2); + return; + case 'B': + _ad9862_regs.rx_pga_b = gain_word; + this->send_reg(3); + return; + default: UHD_THROW_INVALID_CODE_PATH(); + } +} + +double b100_codec_ctrl_impl::get_rx_pga_gain(char which){ + int gain_word; + switch(which){ + case 'A': gain_word = _ad9862_regs.rx_pga_a; break; + case 'B': gain_word = _ad9862_regs.rx_pga_b; break; + default: UHD_THROW_INVALID_CODE_PATH(); + } + return (gain_word*(rx_pga_gain_range.stop() - rx_pga_gain_range.start())/mrpgw) + rx_pga_gain_range.start(); +} + +/*********************************************************************** + * Codec Control AUX ADC Methods + **********************************************************************/ +static double aux_adc_to_volts(boost::uint8_t high, boost::uint8_t low){ + return double((boost::uint16_t(high) << 2) | low)*3.3/0x3ff; +} + +double b100_codec_ctrl_impl::read_aux_adc(aux_adc_t which){ + switch(which){ + + case AUX_ADC_A1: + _ad9862_regs.select_a = ad9862_regs_t::SELECT_A_AUX_ADC1; + this->send_reg(34); //start conversion and select mux + this->recv_reg(28); //read the value (2 bytes, 2 reads) + this->recv_reg(29); + return aux_adc_to_volts(_ad9862_regs.aux_adc_a1_9_2, _ad9862_regs.aux_adc_a1_1_0); + case AUX_ADC_A2: + _ad9862_regs.select_a = ad9862_regs_t::SELECT_A_AUX_ADC2; + this->send_reg(34); //start conversion and select mux + this->recv_reg(26); //read the value (2 bytes, 2 reads) + this->recv_reg(27); + return aux_adc_to_volts(_ad9862_regs.aux_adc_a2_9_2, _ad9862_regs.aux_adc_a2_1_0); + + case AUX_ADC_B1: + _ad9862_regs.select_b = ad9862_regs_t::SELECT_B_AUX_ADC1; + this->send_reg(34); //start conversion and select mux + this->recv_reg(32); //read the value (2 bytes, 2 reads) + this->recv_reg(33); + return aux_adc_to_volts(_ad9862_regs.aux_adc_b1_9_2, _ad9862_regs.aux_adc_b1_1_0); + case AUX_ADC_B2: + _ad9862_regs.select_b = ad9862_regs_t::SELECT_B_AUX_ADC2; + this->send_reg(34); //start conversion and select mux + this->recv_reg(30); //read the value (2 bytes, 2 reads) + this->recv_reg(31); + return aux_adc_to_volts(_ad9862_regs.aux_adc_b2_9_2, _ad9862_regs.aux_adc_b2_1_0); + } + UHD_THROW_INVALID_CODE_PATH(); +} + +/*********************************************************************** + * Codec Control AUX DAC Methods + **********************************************************************/ +void b100_codec_ctrl_impl::write_aux_dac(aux_dac_t which, double volts){ + //special case for aux dac d (aka sigma delta word) + if (which == AUX_DAC_D){ + boost::uint16_t dac_word = uhd::clip(boost::math::iround(volts*0xfff/3.3), 0, 0xfff); + _ad9862_regs.sig_delt_11_4 = boost::uint8_t(dac_word >> 4); + _ad9862_regs.sig_delt_3_0 = boost::uint8_t(dac_word & 0xf); + this->send_reg(42); + this->send_reg(43); + return; + } + + //calculate the dac word for aux dac a, b, c + boost::uint8_t dac_word = uhd::clip(boost::math::iround(volts*0xff/3.3), 0, 0xff); + + //setup a lookup table for the aux dac params (reg ref, reg addr) + typedef boost::tuple dac_params_t; + uhd::dict aux_dac_to_params = boost::assign::map_list_of + (AUX_DAC_A, dac_params_t(&_ad9862_regs.aux_dac_a, 36)) + (AUX_DAC_B, dac_params_t(&_ad9862_regs.aux_dac_b, 37)) + (AUX_DAC_C, dac_params_t(&_ad9862_regs.aux_dac_c, 38)) + ; + + //set the aux dac register + UHD_ASSERT_THROW(aux_dac_to_params.has_key(which)); + boost::uint8_t *reg_ref, reg_addr; + boost::tie(reg_ref, reg_addr) = aux_dac_to_params[which]; + *reg_ref = dac_word; + this->send_reg(reg_addr); +} + +/*********************************************************************** + * Codec Control SPI Methods + **********************************************************************/ +void b100_codec_ctrl_impl::send_reg(boost::uint8_t addr){ + boost::uint32_t reg = _ad9862_regs.get_write_reg(addr); + UHD_LOGV(rarely) << "codec control write reg: " << std::hex << reg << std::endl; + _iface->transact_spi( + B100_SPI_SS_AD9862, + spi_config_t::EDGE_RISE, + reg, 16, false /*no rb*/ + ); +} + +void b100_codec_ctrl_impl::recv_reg(boost::uint8_t addr){ + boost::uint32_t reg = _ad9862_regs.get_read_reg(addr); + UHD_LOGV(rarely) << "codec control read reg: " << std::hex << reg << std::endl; + boost::uint32_t ret = _iface->transact_spi( + B100_SPI_SS_AD9862, + spi_config_t::EDGE_RISE, + reg, 16, true /*rb*/ + ); + UHD_LOGV(rarely) << "codec control read ret: " << std::hex << boost::uint16_t(ret & 0xFF) << std::endl; + _ad9862_regs.set_reg(addr, boost::uint8_t(ret&0xff)); +} + +/*********************************************************************** + * Codec Control Make + **********************************************************************/ +b100_codec_ctrl::sptr b100_codec_ctrl::make(b100_iface::sptr iface){ + return sptr(new b100_codec_ctrl_impl(iface)); +} diff --git a/host/lib/usrp/usrp_b100/codec_ctrl.hpp b/host/lib/usrp/usrp_b100/codec_ctrl.hpp new file mode 100644 index 000000000..1bd579190 --- /dev/null +++ b/host/lib/usrp/usrp_b100/codec_ctrl.hpp @@ -0,0 +1,90 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_B100_CODEC_CTRL_HPP +#define INCLUDED_B100_CODEC_CTRL_HPP + +#include "b100_iface.hpp" +#include +#include +#include + +/*! + * The usrp-e codec control: + * - Init/power down codec. + * - Read aux adc, write aux dac. + */ +class b100_codec_ctrl : boost::noncopyable{ +public: + typedef boost::shared_ptr sptr; + + static const uhd::gain_range_t tx_pga_gain_range; + static const uhd::gain_range_t rx_pga_gain_range; + + /*! + * Make a new codec control object. + * \param iface the usrp_e iface object + * \return the codec control object + */ + static sptr make(b100_iface::sptr iface); + + //! aux adc identifier constants + enum aux_adc_t{ + AUX_ADC_A2 = 0xA2, + AUX_ADC_A1 = 0xA1, + AUX_ADC_B2 = 0xB2, + AUX_ADC_B1 = 0xB1 + }; + + /*! + * Read an auxiliary adc: + * The internals remember which aux adc was read last. + * Therefore, the aux adc switch is only changed as needed. + * \param which which of the 4 adcs + * \return a value in volts + */ + virtual double read_aux_adc(aux_adc_t which) = 0; + + //! aux dac identifier constants + enum aux_dac_t{ + AUX_DAC_A = 0xA, + AUX_DAC_B = 0xB, + AUX_DAC_C = 0xC, + AUX_DAC_D = 0xD //really the sigma delta output + }; + + /*! + * Write an auxiliary dac. + * \param which which of the 4 dacs + * \param volts the level in in volts + */ + virtual void write_aux_dac(aux_dac_t which, double volts) = 0; + + //! Set the TX PGA gain + virtual void set_tx_pga_gain(double gain) = 0; + + //! Get the TX PGA gain + virtual double get_tx_pga_gain(void) = 0; + + //! Set the RX PGA gain ('A' or 'B') + virtual void set_rx_pga_gain(double gain, char which) = 0; + + //! Get the RX PGA gain ('A' or 'B') + virtual double get_rx_pga_gain(char which) = 0; +}; + +#endif /* INCLUDED_B100_CODEC_CTRL_HPP */ diff --git a/host/lib/usrp/usrp_b100/codec_impl.cpp b/host/lib/usrp/usrp_b100/codec_impl.cpp new file mode 100644 index 000000000..de3ca3a66 --- /dev/null +++ b/host/lib/usrp/usrp_b100/codec_impl.cpp @@ -0,0 +1,149 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "b100_impl.hpp" +#include +#include +#include + +using namespace uhd; +using namespace uhd::usrp; + +/*********************************************************************** + * Helper Methods + **********************************************************************/ +void b100_impl::codec_init(void){ + //make proxies + _rx_codec_proxy = wax_obj_proxy::make( + boost::bind(&b100_impl::rx_codec_get, this, _1, _2), + boost::bind(&b100_impl::rx_codec_set, this, _1, _2) + ); + _tx_codec_proxy = wax_obj_proxy::make( + boost::bind(&b100_impl::tx_codec_get, this, _1, _2), + boost::bind(&b100_impl::tx_codec_set, this, _1, _2) + ); +} + +/*********************************************************************** + * RX Codec Properties + **********************************************************************/ +static const std::string ad9862_pga_gain_name = "ad9862 pga"; + +void b100_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case CODEC_PROP_NAME: + val = std::string("b100 adc - ad9522"); + return; + + case CODEC_PROP_OTHERS: + val = prop_names_t(); + return; + + case CODEC_PROP_GAIN_NAMES: + val = prop_names_t(1, ad9862_pga_gain_name); + return; + + case CODEC_PROP_GAIN_RANGE: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + val = b100_codec_ctrl::rx_pga_gain_range; + return; + + case CODEC_PROP_GAIN_I: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + val = _codec_ctrl->get_rx_pga_gain('A'); + return; + + case CODEC_PROP_GAIN_Q: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + val = _codec_ctrl->get_rx_pga_gain('B'); + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +void b100_impl::rx_codec_set(const wax::obj &key_, const wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the set request conditioned on the key + switch(key.as()){ + case CODEC_PROP_GAIN_I: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + _codec_ctrl->set_rx_pga_gain(val.as(), 'A'); + return; + + case CODEC_PROP_GAIN_Q: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + _codec_ctrl->set_rx_pga_gain(val.as(), 'B'); + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } +} + +/*********************************************************************** + * TX Codec Properties + **********************************************************************/ +void b100_impl::tx_codec_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case CODEC_PROP_NAME: + val = std::string("b100 dac - ad9522"); + return; + + case CODEC_PROP_OTHERS: + val = prop_names_t(); + return; + + case CODEC_PROP_GAIN_NAMES: + val = prop_names_t(1, ad9862_pga_gain_name); + return; + + case CODEC_PROP_GAIN_RANGE: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + val = b100_codec_ctrl::tx_pga_gain_range; + return; + + case CODEC_PROP_GAIN_I: //only one gain for I and Q + case CODEC_PROP_GAIN_Q: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + val = _codec_ctrl->get_tx_pga_gain(); + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +void b100_impl::tx_codec_set(const wax::obj &key_, const wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the set request conditioned on the key + switch(key.as()){ + case CODEC_PROP_GAIN_I: //only one gain for I and Q + case CODEC_PROP_GAIN_Q: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + _codec_ctrl->set_tx_pga_gain(val.as()); + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } +} diff --git a/host/lib/usrp/usrp_b100/ctrl_packet.hpp b/host/lib/usrp/usrp_b100/ctrl_packet.hpp new file mode 100644 index 000000000..f504fc5aa --- /dev/null +++ b/host/lib/usrp/usrp_b100/ctrl_packet.hpp @@ -0,0 +1,75 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_CTRL_PACKET_HPP +#define INCLUDED_CTRL_PACKET_HPP + +#include +#include +#include + +typedef std::vector ctrl_data_t; + +/*! + * Control packet operation type + */ +enum ctrl_pkt_op_t { + CTRL_PKT_OP_WRITE = 1, + CTRL_PKT_OP_READ = 2, + CTRL_PKT_OP_READBACK = 3 +}; + +/*! + * Control packet transaction length + */ +const size_t CTRL_PACKET_LENGTH = 32; +const size_t CTRL_PACKET_HEADER_LENGTH = 8; +const size_t CTRL_PACKET_DATA_LENGTH = 24; //=length-header + +/*! + * Control packet header magic value + */ +const boost::uint8_t CTRL_PACKET_HEADER_MAGIC = 0xAA; + +/*! + * Callback triggers for readback operation + */ +//FIXME: these are not real numbers, callbacks aren't implemented yet +const boost::uint16_t CTRL_PACKET_CALLBACK_SPI = 0x0001; +const boost::uint16_t CTRL_PACKET_CALLBACK_I2C = 0x0002; +//and so on + +/*! + * Metadata structure to describe a control packet + */ +struct UHD_API ctrl_pkt_meta_t { + ctrl_pkt_op_t op; + boost::uint8_t callbacks; + boost::uint8_t seq; + boost::uint16_t len; + boost::uint32_t addr; +}; + +/*! + * Full control packet structure + */ +struct UHD_API ctrl_pkt_t { + ctrl_pkt_meta_t pkt_meta; + ctrl_data_t data; +}; + +#endif /* INCLUDED_CTRL_PACKET_HPP */ diff --git a/host/lib/usrp/usrp_b100/dboard_iface.cpp b/host/lib/usrp/usrp_b100/dboard_iface.cpp new file mode 100644 index 000000000..ec3da6220 --- /dev/null +++ b/host/lib/usrp/usrp_b100/dboard_iface.cpp @@ -0,0 +1,298 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "b100_iface.hpp" +#include "b100_regs.hpp" +#include "clock_ctrl.hpp" +#include "codec_ctrl.hpp" +#include +#include +#include +#include + + +using namespace uhd; +using namespace uhd::usrp; +using namespace boost::assign; + +class b100_dboard_iface : public dboard_iface{ +public: + + b100_dboard_iface( + b100_iface::sptr iface, + b100_clock_ctrl::sptr clock, + b100_codec_ctrl::sptr codec + ){ + _iface = iface; + _clock = clock; + _codec = codec; + + //init the clock rate shadows + this->set_clock_rate(UNIT_RX, _clock->get_fpga_clock_rate()); + this->set_clock_rate(UNIT_TX, _clock->get_fpga_clock_rate()); + + _iface->poke16(B100_REG_GPIO_RX_DBG, 0); + _iface->poke16(B100_REG_GPIO_TX_DBG, 0); + } + + ~b100_dboard_iface(void){ + /* NOP */ + } + + special_props_t get_special_props(void){ + special_props_t props; + props.soft_clock_divider = false; + props.mangle_i2c_addrs = false; + return props; + } + + void write_aux_dac(unit_t, aux_dac_t, double); + double read_aux_adc(unit_t, aux_adc_t); + + void _set_pin_ctrl(unit_t, boost::uint16_t); + void _set_atr_reg(unit_t, atr_reg_t, boost::uint16_t); + void _set_gpio_ddr(unit_t, boost::uint16_t); + void _set_gpio_out(unit_t, boost::uint16_t); + void set_gpio_debug(unit_t, int); + boost::uint16_t read_gpio(unit_t); + + void write_i2c(boost::uint8_t, const byte_vector_t &); + byte_vector_t read_i2c(boost::uint8_t, size_t); + + void write_spi( + unit_t unit, + const spi_config_t &config, + boost::uint32_t data, + size_t num_bits + ); + + boost::uint32_t read_write_spi( + unit_t unit, + const spi_config_t &config, + boost::uint32_t data, + size_t num_bits + ); + + void set_clock_rate(unit_t, double); + std::vector get_clock_rates(unit_t); + double get_clock_rate(unit_t); + void set_clock_enabled(unit_t, bool); + double get_codec_rate(unit_t); + +private: + b100_iface::sptr _iface; + b100_clock_ctrl::sptr _clock; + b100_codec_ctrl::sptr _codec; + uhd::dict _clock_rates; +}; + +/*********************************************************************** + * Make Function + **********************************************************************/ +dboard_iface::sptr make_b100_dboard_iface( + b100_iface::sptr iface, + b100_clock_ctrl::sptr clock, + b100_codec_ctrl::sptr codec +){ + return dboard_iface::sptr(new b100_dboard_iface(iface, clock, codec)); +} + +/*********************************************************************** + * Clock Rates + **********************************************************************/ +void b100_dboard_iface::set_clock_rate(unit_t unit, double rate){ + _clock_rates[unit] = rate; + switch(unit){ + case UNIT_RX: return _clock->set_rx_dboard_clock_rate(rate); + case UNIT_TX: return _clock->set_tx_dboard_clock_rate(rate); + } +} + +std::vector b100_dboard_iface::get_clock_rates(unit_t unit){ + switch(unit){ + case UNIT_RX: return _clock->get_rx_dboard_clock_rates(); + case UNIT_TX: return _clock->get_tx_dboard_clock_rates(); + default: UHD_THROW_INVALID_CODE_PATH(); + } +} + +double b100_dboard_iface::get_clock_rate(unit_t unit){ + return _clock_rates[unit]; +} + +void b100_dboard_iface::set_clock_enabled(unit_t unit, bool enb){ + switch(unit){ + case UNIT_RX: return _clock->enable_rx_dboard_clock(enb); + case UNIT_TX: return _clock->enable_tx_dboard_clock(enb); + } +} + +double b100_dboard_iface::get_codec_rate(unit_t){ + return _clock->get_fpga_clock_rate(); +} + +/*********************************************************************** + * GPIO + **********************************************************************/ +void b100_dboard_iface::_set_pin_ctrl(unit_t unit, boost::uint16_t value){ + UHD_ASSERT_THROW(GPIO_SEL_ATR == 1); //make this assumption + switch(unit){ + case UNIT_RX: _iface->poke16(B100_REG_GPIO_RX_SEL, value); return; + case UNIT_TX: _iface->poke16(B100_REG_GPIO_TX_SEL, value); return; + } +} + +void b100_dboard_iface::_set_gpio_ddr(unit_t unit, boost::uint16_t value){ + switch(unit){ + case UNIT_RX: _iface->poke16(B100_REG_GPIO_RX_DDR, value); return; + case UNIT_TX: _iface->poke16(B100_REG_GPIO_TX_DDR, value); return; + } +} + +void b100_dboard_iface::_set_gpio_out(unit_t unit, boost::uint16_t value){ + switch(unit){ + case UNIT_RX: _iface->poke16(B100_REG_GPIO_RX_IO, value); return; + case UNIT_TX: _iface->poke16(B100_REG_GPIO_TX_IO, value); return; + } +} + +boost::uint16_t b100_dboard_iface::read_gpio(unit_t unit){ + switch(unit){ + case UNIT_RX: return _iface->peek16(B100_REG_GPIO_RX_IO); + case UNIT_TX: return _iface->peek16(B100_REG_GPIO_TX_IO); + default: UHD_THROW_INVALID_CODE_PATH(); + } +} + +void b100_dboard_iface::_set_atr_reg(unit_t unit, atr_reg_t atr, boost::uint16_t value){ + //define mapping of unit to atr regs to register address + static const uhd::dict< + unit_t, uhd::dict + > unit_to_atr_to_addr = map_list_of + (UNIT_RX, map_list_of + (ATR_REG_IDLE, B100_REG_ATR_IDLE_RXSIDE) + (ATR_REG_TX_ONLY, B100_REG_ATR_INTX_RXSIDE) + (ATR_REG_RX_ONLY, B100_REG_ATR_INRX_RXSIDE) + (ATR_REG_FULL_DUPLEX, B100_REG_ATR_FULL_RXSIDE) + ) + (UNIT_TX, map_list_of + (ATR_REG_IDLE, B100_REG_ATR_IDLE_TXSIDE) + (ATR_REG_TX_ONLY, B100_REG_ATR_INTX_TXSIDE) + (ATR_REG_RX_ONLY, B100_REG_ATR_INRX_TXSIDE) + (ATR_REG_FULL_DUPLEX, B100_REG_ATR_FULL_TXSIDE) + ) + ; + _iface->poke16(unit_to_atr_to_addr[unit][atr], value); +} + +void b100_dboard_iface::set_gpio_debug(unit_t unit, int which){ + //set this unit to all outputs + this->set_gpio_ddr(unit, 0xffff); + + //calculate the debug selections + boost::uint32_t dbg_sels = 0x0; + int sel = (which == 0)? GPIO_SEL_DEBUG_0 : GPIO_SEL_DEBUG_1; + for(size_t i = 0; i < 16; i++) dbg_sels |= sel << i; + + //set the debug on and which debug selection + switch(unit){ + case UNIT_RX: + _iface->poke16(B100_REG_GPIO_RX_DBG, 0xffff); + _iface->poke16(B100_REG_GPIO_RX_SEL, dbg_sels); + return; + + case UNIT_TX: + _iface->poke16(B100_REG_GPIO_TX_DBG, 0xffff); + _iface->poke16(B100_REG_GPIO_TX_SEL, dbg_sels); + return; + } +} + +/*********************************************************************** + * SPI + **********************************************************************/ +/*! + * Static function to convert a unit type to a spi slave device number. + * \param unit the dboard interface unit type enum + * \return the slave device number + */ +static boost::uint32_t unit_to_otw_spi_dev(dboard_iface::unit_t unit){ + switch(unit){ + case dboard_iface::UNIT_TX: return B100_SPI_SS_TX_DB; + case dboard_iface::UNIT_RX: return B100_SPI_SS_RX_DB; + } + throw std::invalid_argument("unknown unit type"); +} + +void b100_dboard_iface::write_spi( + unit_t unit, + const spi_config_t &config, + boost::uint32_t data, + size_t num_bits +){ + _iface->transact_spi(unit_to_otw_spi_dev(unit), config, data, num_bits, false /*no rb*/); +} + +boost::uint32_t b100_dboard_iface::read_write_spi( + unit_t unit, + const spi_config_t &config, + boost::uint32_t data, + size_t num_bits +){ + return _iface->transact_spi(unit_to_otw_spi_dev(unit), config, data, num_bits, true /*rb*/); +} + +/*********************************************************************** + * I2C + **********************************************************************/ +void b100_dboard_iface::write_i2c(boost::uint8_t addr, const byte_vector_t &bytes){ + return _iface->write_i2c(addr, bytes); +} + +byte_vector_t b100_dboard_iface::read_i2c(boost::uint8_t addr, size_t num_bytes){ + return _iface->read_i2c(addr, num_bytes); +} + +/*********************************************************************** + * Aux DAX/ADC + **********************************************************************/ +void b100_dboard_iface::write_aux_dac(dboard_iface::unit_t, aux_dac_t which, double value){ + //same aux dacs for each unit + static const uhd::dict which_to_aux_dac = map_list_of + (AUX_DAC_A, b100_codec_ctrl::AUX_DAC_A) + (AUX_DAC_B, b100_codec_ctrl::AUX_DAC_B) + (AUX_DAC_C, b100_codec_ctrl::AUX_DAC_C) + (AUX_DAC_D, b100_codec_ctrl::AUX_DAC_D) + ; + _codec->write_aux_dac(which_to_aux_dac[which], value); +} + +double b100_dboard_iface::read_aux_adc(dboard_iface::unit_t unit, aux_adc_t which){ + static const uhd::dict< + unit_t, uhd::dict + > unit_to_which_to_aux_adc = map_list_of + (UNIT_RX, map_list_of + (AUX_ADC_A, b100_codec_ctrl::AUX_ADC_A1) + (AUX_ADC_B, b100_codec_ctrl::AUX_ADC_B1) + ) + (UNIT_TX, map_list_of + (AUX_ADC_A, b100_codec_ctrl::AUX_ADC_A2) + (AUX_ADC_B, b100_codec_ctrl::AUX_ADC_B2) + ) + ; + return _codec->read_aux_adc(unit_to_which_to_aux_adc[unit][which]); +} diff --git a/host/lib/usrp/usrp_b100/dboard_impl.cpp b/host/lib/usrp/usrp_b100/dboard_impl.cpp new file mode 100644 index 000000000..ba3776728 --- /dev/null +++ b/host/lib/usrp/usrp_b100/dboard_impl.cpp @@ -0,0 +1,185 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "b100_impl.hpp" +#include "b100_regs.hpp" +#include +#include +#include +#include +#include +#include "usrp_i2c_addr.h" + +using namespace uhd; +using namespace uhd::usrp; + +/*********************************************************************** + * Dboard Initialization + **********************************************************************/ +void b100_impl::dboard_init(void){ + //read the tx and rx dboard eeproms + _rx_db_eeprom.load(*_iface, I2C_ADDR_RX_A); + _tx_db_eeprom.load(*_iface, I2C_ADDR_TX_A); + _gdb_eeprom.load(*_iface, I2C_ADDR_TX_A ^ 5); + + //create a new dboard interface and manager + _dboard_iface = make_b100_dboard_iface( + _iface, _clock_ctrl, _codec_ctrl + ); + _dboard_manager = dboard_manager::make( + _rx_db_eeprom.id, + ((_gdb_eeprom.id == dboard_id_t::none())? _tx_db_eeprom : _gdb_eeprom).id, + _dboard_iface + ); + + //setup the dboard proxies + _rx_dboard_proxy = wax_obj_proxy::make( + boost::bind(&b100_impl::rx_dboard_get, this, _1, _2), + boost::bind(&b100_impl::rx_dboard_set, this, _1, _2) + ); + _tx_dboard_proxy = wax_obj_proxy::make( + boost::bind(&b100_impl::tx_dboard_get, this, _1, _2), + boost::bind(&b100_impl::tx_dboard_set, this, _1, _2) + ); +} + +/*********************************************************************** + * RX Dboard Get + **********************************************************************/ +void b100_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case DBOARD_PROP_NAME: + val = std::string("b100 dboard (rx unit)"); + return; + + case DBOARD_PROP_SUBDEV: + val = _dboard_manager->get_rx_subdev(key.name); + return; + + case DBOARD_PROP_SUBDEV_NAMES: + val = _dboard_manager->get_rx_subdev_names(); + return; + + case DBOARD_PROP_DBOARD_EEPROM: + val = _rx_db_eeprom; + return; + + case DBOARD_PROP_DBOARD_IFACE: + val = _dboard_iface; + return; + + case DBOARD_PROP_CODEC: + val = _rx_codec_proxy->get_link(); + return; + + case DBOARD_PROP_GAIN_GROUP: + val = make_gain_group( + _rx_db_eeprom.id, + _dboard_manager->get_rx_subdev(key.name), + _rx_codec_proxy->get_link(), + GAIN_GROUP_POLICY_RX + ); + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +/*********************************************************************** + * RX Dboard Set + **********************************************************************/ +void b100_impl::rx_dboard_set(const wax::obj &key, const wax::obj &val){ + switch(key.as()){ + case DBOARD_PROP_DBOARD_EEPROM: + _rx_db_eeprom = val.as(); + _rx_db_eeprom.store(*_iface, I2C_ADDR_RX_A); + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } +} + +/*********************************************************************** + * TX Dboard Get + **********************************************************************/ +void b100_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case DBOARD_PROP_NAME: + val = std::string("b100 dboard (tx unit)"); + return; + + case DBOARD_PROP_SUBDEV: + val = _dboard_manager->get_tx_subdev(key.name); + return; + + case DBOARD_PROP_SUBDEV_NAMES: + val = _dboard_manager->get_tx_subdev_names(); + return; + + case DBOARD_PROP_DBOARD_EEPROM: + val = _tx_db_eeprom; + return; + + case DBOARD_PROP_GBOARD_EEPROM: + val = _gdb_eeprom; + return; + + case DBOARD_PROP_DBOARD_IFACE: + val = _dboard_iface; + return; + + case DBOARD_PROP_CODEC: + val = _tx_codec_proxy->get_link(); + return; + + case DBOARD_PROP_GAIN_GROUP: + val = make_gain_group( + _tx_db_eeprom.id, + _dboard_manager->get_tx_subdev(key.name), + _tx_codec_proxy->get_link(), + GAIN_GROUP_POLICY_TX + ); + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +/*********************************************************************** + * TX Dboard Set + **********************************************************************/ +void b100_impl::tx_dboard_set(const wax::obj &key, const wax::obj &val){ + switch(key.as()){ + case DBOARD_PROP_DBOARD_EEPROM: + _tx_db_eeprom = val.as(); + _tx_db_eeprom.store(*_iface, I2C_ADDR_TX_A); + return; + + case DBOARD_PROP_GBOARD_EEPROM: + _gdb_eeprom = val.as(); + _gdb_eeprom.store(*_iface, I2C_ADDR_TX_A ^ 5); + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } +} diff --git a/host/lib/usrp/usrp_b100/dsp_impl.cpp b/host/lib/usrp/usrp_b100/dsp_impl.cpp new file mode 100644 index 000000000..c1bf6bedd --- /dev/null +++ b/host/lib/usrp/usrp_b100/dsp_impl.cpp @@ -0,0 +1,189 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "b100_impl.hpp" +#include "b100_regs.hpp" +#include +#include +#include +#include + +#define rint boost::math::iround + +using namespace uhd; +using namespace uhd::usrp; + +static const double MASTER_CLOCK_RATE = 64e6; //TODO get from clock control + +/*********************************************************************** + * RX DDC Initialization + **********************************************************************/ +void b100_impl::rx_ddc_init(void){ + _rx_ddc_proxy = wax_obj_proxy::make( + boost::bind(&b100_impl::rx_ddc_get, this, _1, _2), + boost::bind(&b100_impl::rx_ddc_set, this, _1, _2) + ); + + //initial config and update + rx_ddc_set(DSP_PROP_FREQ_SHIFT, double(0)); + rx_ddc_set(DSP_PROP_HOST_RATE, double(16e6)); +} + +/*********************************************************************** + * RX DDC Get + **********************************************************************/ +void b100_impl::rx_ddc_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + switch(key.as()){ + case DSP_PROP_NAME: + val = std::string("USRP-B100 RX DSP"); + return; + + case DSP_PROP_OTHERS: + val = prop_names_t(); //empty + return; + + case DSP_PROP_FREQ_SHIFT: + val = _ddc_freq; + return; + + case DSP_PROP_CODEC_RATE: + val = _clock_ctrl->get_fpga_clock_rate(); + return; + + case DSP_PROP_HOST_RATE: + val = _clock_ctrl->get_fpga_clock_rate()/_ddc_decim; + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +/*********************************************************************** + * RX DDC Set + **********************************************************************/ +void b100_impl::rx_ddc_set(const wax::obj &key_, const wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + switch(key.as()){ + case DSP_PROP_STREAM_CMD: + issue_stream_cmd(val.as()); + return; + + case DSP_PROP_FREQ_SHIFT:{ + double new_freq = val.as(); + _iface->poke32(B100_REG_DSP_RX_FREQ, + dsp_type1::calc_cordic_word_and_update(new_freq, _clock_ctrl->get_fpga_clock_rate()) + ); + _ddc_freq = new_freq; //shadow + } + return; + + case DSP_PROP_HOST_RATE:{ + //set the decimation + _ddc_decim = rint(_clock_ctrl->get_fpga_clock_rate()/val.as()); + _iface->poke32(B100_REG_DSP_RX_DECIM_RATE, dsp_type1::calc_cic_filter_word(_ddc_decim)); + + //set the scaling + static const boost::int16_t default_rx_scale_iq = 1024; + _iface->poke32(B100_REG_DSP_RX_SCALE_IQ, + dsp_type1::calc_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq) + ); + } + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } +} + +/*********************************************************************** + * TX DUC Initialization + **********************************************************************/ +void b100_impl::tx_duc_init(void){ + _tx_duc_proxy = wax_obj_proxy::make( + boost::bind(&b100_impl::tx_duc_get, this, _1, _2), + boost::bind(&b100_impl::tx_duc_set, this, _1, _2) + ); + + //initial config and update + tx_duc_set(DSP_PROP_FREQ_SHIFT, double(0)); + tx_duc_set(DSP_PROP_HOST_RATE, double(16e6)); +} + +/*********************************************************************** + * TX DUC Get + **********************************************************************/ +void b100_impl::tx_duc_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + switch(key.as()){ + case DSP_PROP_NAME: + val = std::string("USRP-B100 TX DSP"); + return; + + case DSP_PROP_OTHERS: + val = prop_names_t(); //empty + return; + + case DSP_PROP_FREQ_SHIFT: + val = _duc_freq; + return; + + case DSP_PROP_CODEC_RATE: + val = _clock_ctrl->get_fpga_clock_rate(); + return; + + case DSP_PROP_HOST_RATE: + val = _clock_ctrl->get_fpga_clock_rate()/_duc_interp; + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +/*********************************************************************** + * TX DUC Set + **********************************************************************/ +void b100_impl::tx_duc_set(const wax::obj &key_, const wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + switch(key.as()){ + + case DSP_PROP_FREQ_SHIFT:{ + double new_freq = val.as(); + _iface->poke32(B100_REG_DSP_TX_FREQ, + dsp_type1::calc_cordic_word_and_update(new_freq, _clock_ctrl->get_fpga_clock_rate()) + ); + _duc_freq = new_freq; //shadow + } + return; + + case DSP_PROP_HOST_RATE:{ + _duc_interp = rint(_clock_ctrl->get_fpga_clock_rate()/val.as()); + + //set the interpolation + _iface->poke32(B100_REG_DSP_TX_INTERP_RATE, dsp_type1::calc_cic_filter_word(_duc_interp)); + + //set the scaling + _iface->poke32(B100_REG_DSP_TX_SCALE_IQ, dsp_type1::calc_iq_scale_word(_duc_interp)); + } + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } +} diff --git a/host/lib/usrp/usrp_b100/io_impl.cpp b/host/lib/usrp/usrp_b100/io_impl.cpp new file mode 100644 index 000000000..3978bea75 --- /dev/null +++ b/host/lib/usrp/usrp_b100/io_impl.cpp @@ -0,0 +1,210 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "../../transport/super_recv_packet_handler.hpp" +#include "../../transport/super_send_packet_handler.hpp" +#include "usrp_commands.h" +#include "b100_impl.hpp" +#include "b100_regs.hpp" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +using namespace uhd; +using namespace uhd::usrp; +using namespace uhd::transport; +namespace asio = boost::asio; + +/*********************************************************************** + * IO Implementation Details + **********************************************************************/ +struct b100_impl::io_impl{ + io_impl(zero_copy_if::sptr data_transport): + data_transport(data_transport) + { + /* NOP */ + } + + ~io_impl(void){ + //drain the rx buffs + //while(data_transport->get_recv_buff().get() != NULL){ + /* NOP */ + //} + } + + zero_copy_if::sptr &data_transport; + + sph::recv_packet_handler recv_handler; + sph::send_packet_handler send_handler; + bool continuous_streaming; +}; + +/*********************************************************************** + * Initialize internals within this file + **********************************************************************/ +void b100_impl::io_init(void){ + _recv_otw_type.width = 16; + _recv_otw_type.shift = 0; + _recv_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN; + + _send_otw_type.width = 16; + _send_otw_type.shift = 0; + _send_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN; + + _iface->reset_gpif(6); + + //reset state machines + _iface->poke32(B100_REG_CTRL_TX_CLEAR_UNDERRUN, 0); + _iface->poke32(B100_REG_CTRL_RX_CLEAR_OVERRUN, 0); + + _io_impl = UHD_PIMPL_MAKE(io_impl, (_data_transport)); + + //setup rx data path + _iface->poke32(B100_REG_CTRL_RX_NSAMPS_PER_PKT, get_max_recv_samps_per_packet()); + UHD_LOGV(always) << "IO: Using " << get_max_recv_samps_per_packet() << " samples per packet" << std::endl; + _iface->poke32(B100_REG_CTRL_RX_NCHANNELS, 1); + _iface->poke32(B100_REG_CTRL_RX_VRT_HEADER, 0 + | (0x1 << 28) //if data with stream id + | (0x1 << 26) //has trailer + | (0x3 << 22) //integer time other + | (0x1 << 20) //fractional time sample count + ); + _iface->poke32(B100_REG_CTRL_RX_VRT_TRAILER, 0); + + //set the streamid to reset the seq num + _iface->poke32(B100_REG_CTRL_TX_REPORT_SID, 0); + //setup the tx policy + _iface->poke32(B100_REG_CTRL_TX_POLICY, B100_FLAG_CTRL_TX_POLICY_NEXT_PACKET); + + //set the expected packet size in USB frames + _iface->poke32(B100_REG_MISC_RX_LEN, 4); + + update_transport_channel_mapping(); +} + +void b100_impl::update_transport_channel_mapping(void){ + if (_io_impl.get() == NULL) return; //not inited yet + + //set all of the relevant properties on the handler + boost::mutex::scoped_lock recv_lock = _io_impl->recv_handler.get_scoped_lock(); + _io_impl->recv_handler.resize(_rx_subdev_spec.size()); + _io_impl->recv_handler.set_vrt_unpacker(&vrt::if_hdr_unpack_le); + _io_impl->recv_handler.set_tick_rate(_clock_ctrl->get_fpga_clock_rate()); + _io_impl->recv_handler.set_samp_rate(_rx_ddc_proxy->get_link()[DSP_PROP_HOST_RATE].as()); + for (size_t chan = 0; chan < _io_impl->recv_handler.size(); chan++){ + _io_impl->recv_handler.set_xport_chan_get_buff(chan, boost::bind( + &uhd::transport::zero_copy_if::get_recv_buff, _io_impl->data_transport, _1 + )); + _io_impl->recv_handler.set_overflow_handler(chan, boost::bind( + &b100_impl::handle_overrun, this, chan + )); + } + _io_impl->recv_handler.set_converter(_recv_otw_type); + + //set all of the relevant properties on the handler + boost::mutex::scoped_lock send_lock = _io_impl->send_handler.get_scoped_lock(); + _io_impl->send_handler.resize(_tx_subdev_spec.size()); + _io_impl->send_handler.set_vrt_packer(&vrt::if_hdr_pack_le); + _io_impl->send_handler.set_tick_rate(_clock_ctrl->get_fpga_clock_rate()); + _io_impl->send_handler.set_samp_rate(_tx_duc_proxy->get_link()[DSP_PROP_HOST_RATE].as()); + for (size_t chan = 0; chan < _io_impl->send_handler.size(); chan++){ + _io_impl->send_handler.set_xport_chan_get_buff(chan, boost::bind( + &uhd::transport::zero_copy_if::get_send_buff, _io_impl->data_transport, _1 + )); + } + _io_impl->send_handler.set_converter(_send_otw_type); + _io_impl->send_handler.set_max_samples_per_packet(get_max_send_samps_per_packet()); +} + +/*********************************************************************** + * Data send + helper functions + **********************************************************************/ +size_t b100_impl::get_max_send_samps_per_packet(void) const { + static const size_t hdr_size = 0 + + vrt::max_if_hdr_words32*sizeof(boost::uint32_t) + - sizeof(vrt::if_packet_info_t().cid) //no class id ever used + ; + static const size_t bpp = 2048 - hdr_size; + return bpp / _send_otw_type.get_sample_size(); +} + +size_t b100_impl::send( + const send_buffs_type &buffs, size_t nsamps_per_buff, + const tx_metadata_t &metadata, const io_type_t &io_type, + send_mode_t send_mode, double timeout +){ + return _io_impl->send_handler.send( + buffs, nsamps_per_buff, + metadata, io_type, + send_mode, timeout + ); +} + +/*********************************************************************** + * Data recv + helper functions + **********************************************************************/ + +size_t b100_impl::get_max_recv_samps_per_packet(void) const { + static const size_t hdr_size = 0 + + vrt::max_if_hdr_words32*sizeof(boost::uint32_t) + + sizeof(vrt::if_packet_info_t().tlr) //forced to have trailer + - sizeof(vrt::if_packet_info_t().cid) //no class id ever used + ; + size_t bpp = 2048 - hdr_size; //limited by FPGA pkt buffer size + return bpp/_recv_otw_type.get_sample_size(); +} + +size_t b100_impl::recv( + const recv_buffs_type &buffs, size_t nsamps_per_buff, + rx_metadata_t &metadata, const io_type_t &io_type, + recv_mode_t recv_mode, double timeout +){ + return _io_impl->recv_handler.recv( + buffs, nsamps_per_buff, + metadata, io_type, + recv_mode, timeout + ); +} + +void b100_impl::issue_stream_cmd(const stream_cmd_t &stream_cmd) +{ + _io_impl->continuous_streaming = (stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_START_CONTINUOUS); + _iface->poke32(B100_REG_CTRL_RX_STREAM_CMD, dsp_type1::calc_stream_cmd_word(stream_cmd)); + _iface->poke32(B100_REG_CTRL_RX_TIME_SECS, boost::uint32_t(stream_cmd.time_spec.get_full_secs())); + _iface->poke32(B100_REG_CTRL_RX_TIME_TICKS, stream_cmd.time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate())); + + if (stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS) { + while(_io_impl->data_transport->get_recv_buff().get() != NULL){ + /* NOP */ + } + } +} + +void b100_impl::handle_overrun(size_t){ + if (_io_impl->continuous_streaming){ + this->issue_stream_cmd(stream_cmd_t::STREAM_MODE_START_CONTINUOUS); + } +} diff --git a/host/lib/usrp/usrp_b100/mboard_impl.cpp b/host/lib/usrp/usrp_b100/mboard_impl.cpp new file mode 100644 index 000000000..c651ff2a2 --- /dev/null +++ b/host/lib/usrp/usrp_b100/mboard_impl.cpp @@ -0,0 +1,246 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "b100_impl.hpp" +#include "usrp_commands.h" +#include "fpga_regs_standard.h" +#include "fpga_regs_common.h" +#include "b100_regs.hpp" +#include "usrp_i2c_addr.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +using namespace uhd; +using namespace uhd::usrp; + +static const bool b100_mboard_verbose = true; + +/*********************************************************************** + * Mboard Initialization + **********************************************************************/ +void b100_impl::mboard_init(void) +{ + _mboard_proxy = wax_obj_proxy::make( + boost::bind(&b100_impl::mboard_get, this, _1, _2), + boost::bind(&b100_impl::mboard_set, this, _1, _2)); + + //set the ticks per seconds into the vita time control + _iface->poke32(B100_REG_TIME64_TPS, + boost::uint32_t(_clock_ctrl->get_fpga_clock_rate()) + ); + + //init the clock config + _clock_config = clock_config_t::internal(); + update_clock_config(); +} + +void b100_impl::update_clock_config(void){ + boost::uint32_t pps_flags = 0; + + //translate pps polarity enums + switch(_clock_config.pps_polarity){ + case clock_config_t::PPS_POS: pps_flags |= B100_FLAG_TIME64_PPS_POSEDGE; break; + case clock_config_t::PPS_NEG: pps_flags |= B100_FLAG_TIME64_PPS_NEGEDGE; break; + default: throw uhd::runtime_error("unhandled clock configuration pps polarity"); + } + + //set the pps flags + _iface->poke32(B100_REG_TIME64_FLAGS, pps_flags); + + //clock source ref 10mhz + switch(_clock_config.ref_source){ + case clock_config_t::REF_AUTO: _clock_ctrl->use_auto_ref(); break; + case clock_config_t::REF_INT: _clock_ctrl->use_internal_ref(); break; + case clock_config_t::REF_SMA: _clock_ctrl->use_auto_ref(); break; + default: throw uhd::runtime_error("unhandled clock configuration ref source"); + } +} + +/*********************************************************************** + * Mboard Get + **********************************************************************/ +void b100_impl::mboard_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case MBOARD_PROP_NAME: + val = std::string("USRP-B100 mboard"); + return; + + case MBOARD_PROP_OTHERS: + val = prop_names_t(); + return; + + case MBOARD_PROP_RX_DBOARD: + UHD_ASSERT_THROW(key.name == ""); + val = _rx_dboard_proxy->get_link(); + return; + + case MBOARD_PROP_RX_DBOARD_NAMES: + val = prop_names_t(1, ""); //vector of size 1 with empty string + return; + + case MBOARD_PROP_TX_DBOARD: + UHD_ASSERT_THROW(key.name == ""); + val = _tx_dboard_proxy->get_link(); + return; + + case MBOARD_PROP_TX_DBOARD_NAMES: + val = prop_names_t(1, ""); //vector of size 1 with empty string + return; + + case MBOARD_PROP_RX_DSP: + UHD_ASSERT_THROW(key.name == ""); + val = _rx_ddc_proxy->get_link(); + return; + + case MBOARD_PROP_RX_DSP_NAMES: + val = prop_names_t(1, ""); + return; + + case MBOARD_PROP_TX_DSP: + UHD_ASSERT_THROW(key.name == ""); + val = _tx_duc_proxy->get_link(); + return; + + case MBOARD_PROP_TX_DSP_NAMES: + val = prop_names_t(1, ""); + return; + + case MBOARD_PROP_CLOCK_CONFIG: + val = _clock_config; + return; + + case MBOARD_PROP_RX_SUBDEV_SPEC: + val = _rx_subdev_spec; + return; + + case MBOARD_PROP_TX_SUBDEV_SPEC: + val = _tx_subdev_spec; + return; + + case MBOARD_PROP_EEPROM_MAP: + val = _iface->mb_eeprom; + return; + + case MBOARD_PROP_TIME_NOW:while(true){ + uint32_t secs = _iface->peek32(B100_REG_RB_TIME_NOW_SECS); + uint32_t ticks = _iface->peek32(B100_REG_RB_TIME_NOW_TICKS); + if (secs != _iface->peek32(B100_REG_RB_TIME_NOW_SECS)) continue; + val = time_spec_t(secs, ticks, _clock_ctrl->get_fpga_clock_rate()); + return; + } + + case MBOARD_PROP_TIME_PPS: while(true){ + uint32_t secs = _iface->peek32(B100_REG_RB_TIME_PPS_SECS); + uint32_t ticks = _iface->peek32(B100_REG_RB_TIME_PPS_TICKS); + if (secs != _iface->peek32(B100_REG_RB_TIME_PPS_SECS)) continue; + val = time_spec_t(secs, ticks, _clock_ctrl->get_fpga_clock_rate()); + return; + } + + case MBOARD_PROP_CLOCK_RATE: + val = _clock_ctrl->get_fpga_clock_rate(); + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +/*********************************************************************** + * Mboard Set + **********************************************************************/ +void b100_impl::mboard_set(const wax::obj &key, const wax::obj &val) +{ + if(key.type() == typeid(std::string)) { + if(key.as() == "load_eeprom") { + std::string b100_eeprom_image = val.as(); + UHD_MSG(status) << "B100 EEPROM image: " << b100_eeprom_image << std::endl; + _fx2_ctrl->usrp_load_eeprom(val.as()); + } + return; + } + + //handle the get request conditioned on the key + switch(key.as()){ + case MBOARD_PROP_TIME_NOW: + case MBOARD_PROP_TIME_PPS:{ + time_spec_t time_spec = val.as(); + _iface->poke32(B100_REG_TIME64_TICKS, time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate())); + boost::uint32_t imm_flags = (key.as() == MBOARD_PROP_TIME_NOW)? 1 : 0; + _iface->poke32(B100_REG_TIME64_IMM, imm_flags); + _iface->poke32(B100_REG_TIME64_SECS, boost::uint32_t(time_spec.get_full_secs())); + } + return; + + case MBOARD_PROP_RX_SUBDEV_SPEC: + _rx_subdev_spec = val.as(); + verify_rx_subdev_spec(_rx_subdev_spec, _mboard_proxy->get_link()); + UHD_ASSERT_THROW(_rx_subdev_spec.size() == 1); + //set the mux + _iface->poke32(B100_REG_DSP_RX_MUX, dsp_type1::calc_rx_mux_word( + _dboard_manager->get_rx_subdev(_rx_subdev_spec.front().sd_name)[SUBDEV_PROP_CONNECTION].as() + )); + return; + + case MBOARD_PROP_TX_SUBDEV_SPEC: + _tx_subdev_spec = val.as(); + verify_tx_subdev_spec(_tx_subdev_spec, _mboard_proxy->get_link()); + UHD_ASSERT_THROW(_tx_subdev_spec.size() == 1); + //set the mux and set the number of tx channels + _iface->poke32(B100_REG_DSP_TX_MUX, dsp_type1::calc_tx_mux_word( + _dboard_manager->get_tx_subdev(_tx_subdev_spec.front().sd_name)[SUBDEV_PROP_CONNECTION].as() + )); + return; + + case MBOARD_PROP_EEPROM_MAP: + // Step1: commit the map, writing only those values set. + // Step2: readback the entire eeprom map into the iface. + val.as().commit(*_iface, mboard_eeprom_t::MAP_B000); + _iface->mb_eeprom = mboard_eeprom_t(*_iface, mboard_eeprom_t::MAP_B000); + return; + + case MBOARD_PROP_CLOCK_CONFIG: + _clock_config = val.as(); + update_clock_config(); + return; + + case MBOARD_PROP_CLOCK_RATE: + UHD_MSG(warning) + << "You are setting the master clock rate from the API.\n" + << "You may want to pass this into the device address as master_clock_rate=.\n" + << "This way, the clock rate is guaranteed to be initialized first.\n" + << "See the application notes for USRP-B100 for further instructions.\n" + ; + _clock_ctrl->set_fpga_clock_rate(val.as()); + update_transport_channel_mapping(); + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } +} diff --git a/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp b/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp index 01a49c129..5b039aafc 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp @@ -39,7 +39,7 @@ static device_addrs_t usrp_e100_find(const device_addr_t &hint){ device_addrs_t usrp_e100_addrs; //return an empty list of addresses when type is set to non-usrp-e - if (hint.has_key("type") and hint["type"] != "usrp-e") return usrp_e100_addrs; + if (hint.has_key("type") and hint["type"] != "e100") return usrp_e100_addrs; //device node not provided, assume its 0 if (not hint.has_key("node")){ diff --git a/host/utils/usrp1p_gpif_loopback.cpp b/host/utils/usrp1p_gpif_loopback.cpp new file mode 100644 index 000000000..3b9da4304 --- /dev/null +++ b/host/utils/usrp1p_gpif_loopback.cpp @@ -0,0 +1,111 @@ +//USB->GPIF->FPGA loopback test for USRP1P +//uses UHD libusb transport + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +//so the goal is to open a USB device to endpoints (2,6), submit a buffer, receive a reply, and compare them. +//use usb_zero_copy::make() to get a usb_zero_copy object and then start submitting. +//need to get a usb dev handle to pass to make +//use static std::vector get_device_list(boost::uint16_t vid, boost::uint16_t pid) to get a device handle +//then get_send_buffer, send, etc. +using namespace uhd; +using namespace uhd::transport; + +const boost::uint16_t data_xfer_size = 32; +const boost::uint16_t ctrl_xfer_size = 32; + +int main(int argc, char *argv[]) { + std::cout << "USRP1+ GPIF loopback test" << std::endl; + //step 1: get a handle on it + std::vector handles = usb_device_handle::get_device_list(0xfffe, 0x0003); + if(handles.size() == 0) { + std::cout << "No USRP1+ found." << std::endl; + return ~0; + } + + bool verbose = false; + if(argc > 1) if(std::string(argv[1]) == "-v") verbose = true; + + usb_device_handle::sptr handle = handles.front(); + + usb_zero_copy::sptr data_transport; + usb_control::sptr ctrl_transport = usb_control::make(handle); //just in case + + data_transport = usb_zero_copy::make( + handle, // identifier + 8, // IN endpoint + 4, // OUT endpoint + uhd::device_addr_t("recv_frame_size=32, num_recv_frames=1, send_frame_size=32, num_send_frames=1") //args + ); + + if(verbose) std::cout << "Made." << std::endl; + + //ok now we're made. time to get a buffer and start sending data. + + boost::uint8_t localbuf[data_xfer_size]; + + managed_send_buffer::sptr sbuf; + managed_recv_buffer::sptr rbuf; + size_t xfercount = 0; + + srand(time(0)); + while(1) { + + if(verbose) std::cout << "Getting send buffer." << std::endl; + sbuf = data_transport->get_send_buff(); + if(sbuf == 0) { + std::cout << "Failed to get a send buffer." << std::endl; + return ~0; + } + for(int i = 0; i < data_xfer_size; i++) { + boost::uint8_t x = rand(); + sbuf->cast()[i] = x; + localbuf[i] = x; + } + + if(verbose) std::cout << "Buffer loaded" << std::endl; + + sbuf->commit(data_xfer_size); + if(verbose) std::cout << "Committed." << std::endl; + + rbuf = data_transport->get_recv_buff(0.3); //timeout + + if(rbuf == 0) { + std::cout << "Failed to get receive buffer (timeout?)" << std::endl; + return ~0; + } + + if(verbose) std::cout << "# " << xfercount << std::endl; + + if(!memcmp(rbuf->cast(), localbuf, data_xfer_size)) { + std::cout << "."; + } else { + if(verbose) { + int i = 0; + for(int j = 0; j < 32; j++) { + std::cout << boost::format("%02X ") % int(rbuf->cast()[i*32+j]); + } + std::cout << std::endl; + } + else std::cout << "x"; + + } + sbuf.reset(); + rbuf.reset(); + xfercount++; + //if(verbose) std::cout << "sptrs reset" << std::endl; + } + + return 0; +} diff --git a/host/utils/usrp1p_poketest.cpp b/host/utils/usrp1p_poketest.cpp new file mode 100644 index 000000000..ca7628e01 --- /dev/null +++ b/host/utils/usrp1p_poketest.cpp @@ -0,0 +1,134 @@ +//FPGA register poke test for USRP1P +//uses UHD libusb transport + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../lib/usrp/usrp1p/ctrl_packet.hpp" + +//so the goal is to open a USB device to endpoints (2,6), submit a buffer, receive a reply, and compare them. +//use usb_zero_copy::make() to get a usb_zero_copy object and then start submitting. +//need to get a usb dev handle to pass to make +//use static std::vector get_device_list(boost::uint16_t vid, boost::uint16_t pid) to get a device handle +//then get_send_buffer, send, etc. +using namespace uhd; +using namespace uhd::transport; + +const boost::uint16_t ctrl_xfer_size = 32; + +int main(int argc, char *argv[]) { + std::cout << "USRP1+ GPIF poke test" << std::endl; + //step 1: get a handle on it + std::vector handles = usb_device_handle::get_device_list(0xfffe, 0x0003); + if(handles.size() == 0) { + std::cout << "No USRP1+ found." << std::endl; + return ~0; + } + + bool verbose = false; + if(argc > 1) if(std::string(argv[1]) == "-v") verbose = true; + + usb_device_handle::sptr handle = handles.front(); + + usb_zero_copy::sptr data_transport; + usb_control::sptr ctrl_transport = usb_control::make(handle); //just in case + + data_transport = usb_zero_copy::make( + handle, // identifier + 8, // IN endpoint + 4, // OUT endpoint + uhd::device_addr_t("recv_frame_size=32, num_recv_frames=1, send_frame_size=32, num_send_frames=1") //args + ); + + if(verbose) std::cout << "Made." << std::endl; + + //ok now we're made. time to get a buffer and start sending data. + + managed_send_buffer::sptr sbuf; + managed_recv_buffer::sptr rbuf; + size_t xfercount = 0; + + static uint8_t sequence = 0; + //uhd::usrp::ctrl_packet_out_t outpkt; + //memset(outpkt.data, 0x00, sizeof(outpkt.data)); +// outpkt.op = uhd::usrp::CTRL_PACKET_WRITE; +// outpkt.callbacks = 0; +// outpkt.seq = sequence++; +// outpkt.len = 4; +// outpkt.addr = 0x00000000; +// outpkt.data[0] = 0xff; +// outpkt.data[1] = 0xfe; +// outpkt.data[2] = 0xfd; +// outpkt.data[3] = 0xfc; + + boost::uint16_t outpkt[16]; + /* Packet format: + * Command: 2 bits + * Callbacks: 6 bits + * Seq num: 8 bits + * Length: 16 bits + * Addr LSW: 16 bits + * Addr MSW: 16 bits + * Data: 24 bytes/12 words + * Lengths are in lines + * + * readback: + * AA00 LEN(16) SEQ(16) ADDR(32) DATA(16bx12B) + */ + memset(outpkt, 0x00, sizeof(outpkt)); + outpkt[0] = 0x8000; //read cmd + callbacks (0) + seq + outpkt[1] = 0x0001; //len + outpkt[2] = 0x0000; //addr LSW + outpkt[3] = 0x0000; //addr MSW + outpkt[4] = 0x0A0A; //data + outpkt[5] = 0xFFFF; + + + srand(time(0)); +// while(1) { + + if(verbose) std::cout << "Getting send buffer." << std::endl; + sbuf = data_transport->get_send_buff(); + if(sbuf == 0) { + std::cout << "Failed to get a send buffer." << std::endl; + return ~0; + } + + for(int i = 0; i < ctrl_xfer_size; i++) { + sbuf->cast()[i] = ((boost::uint8_t *)&outpkt)[i]; + } + + if(verbose) std::cout << "Buffer loaded" << std::endl; + + sbuf->commit(ctrl_xfer_size); + if(verbose) std::cout << "Committed." << std::endl; + + rbuf = data_transport->get_recv_buff(0.3); //timeout + + if(rbuf == 0) { + std::cout << "Failed to get receive buffer (timeout?)" << std::endl; + return ~0; + } + + for(int j = 0; j < 32; j++) { + std::cout << boost::format("%02X ") % int(rbuf->cast()[j]); + } + std::cout << std::endl; + + sbuf.reset(); + rbuf.reset(); + xfercount++; + //if(verbose) std::cout << "sptrs reset" << std::endl; +// } + + return 0; +} -- cgit v1.2.3 From 3d771334a820cb54870cbca23eab49bb84571905 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 14 Jun 2011 19:08:26 -0700 Subject: b100: added images to Makefile --- host/lib/usrp/usrp_b100/b100_impl.cpp | 4 ++-- images/Makefile | 24 ++++++++++++++++++++++-- 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/host/lib/usrp/usrp_b100/b100_impl.cpp b/host/lib/usrp/usrp_b100/b100_impl.cpp index 066831a92..772da8f42 100644 --- a/host/lib/usrp/usrp_b100/b100_impl.cpp +++ b/host/lib/usrp/usrp_b100/b100_impl.cpp @@ -58,7 +58,7 @@ static device_addrs_t b100_find(const device_addr_t &hint) std::string b100_fw_image; try{ b100_fw_image = find_image_path( - hint.has_key("fw")? hint["fw"] : "usrp_b100_fw_c2.ihx" + hint.has_key("fw")? hint["fw"] : "usrp_b100_fw.ihx" ); } catch(...){ @@ -129,7 +129,7 @@ static device::sptr b100_make(const device_addr_t &device_addr){ //extract the FPGA path for the B100 std::string b100_fpga_image = find_image_path( - device_addr.has_key("fpga")? device_addr["fpga"] : "usrp_b100_fpga_c3.bin" + device_addr.has_key("fpga")? device_addr["fpga"] : "usrp_b100_fpga.bin" ); //try to match the given device address with something on the USB bus diff --git a/images/Makefile b/images/Makefile index f2ba21bdc..4b0034bf0 100644 --- a/images/Makefile +++ b/images/Makefile @@ -52,13 +52,14 @@ ifeq ($(shell xtclsh -h > /dev/null 2>&1 && echo $$?),0) endif ######################################################################## -# USRP1 firmware +# USRP1 and B100 firmware ######################################################################## ifdef HAS_SDCC _usrp1_fw_dir = $(TOP_FW_DIR)/fx2 _usrp1_fw_ihx = $(BUILT_IMAGES_DIR)/usrp1_fw.ihx -IMAGES_LIST += $(_usrp1_fw_ihx) +_usrp_b100_fw_ihx = $(BUILT_IMAGES_DIR)/usrp_b100_fw.ihx +IMAGES_LIST += $(_usrp1_fw_ihx) $(_usrp_b100_fw_ihx) $(_usrp1_fw_ihx): $(GLOBAL_DEPS) cd $(_usrp1_fw_dir) && rm -rf build @@ -67,6 +68,9 @@ $(_usrp1_fw_ihx): $(GLOBAL_DEPS) cd $(_usrp1_fw_dir)/build && make cp $(_usrp1_fw_dir)/build/usrp1/usrp1_fw.ihx $@ +$(_usrp_b100_fw_ihx): $(_usrp1_fw_ihx) + cp $(_usrp1_fw_dir)/build/b100/b100_fw.ihx $(_usrp_b100_fw_ihx) + endif ######################################################################## @@ -83,6 +87,22 @@ $(_usrp1_fpga_rbf): $(GLOBAL_DEPS) $(_usrp1_fpga_4rx_rbf): $(GLOBAL_DEPS) cp $(_usrp1_fpga_dir)/std_4rx_0tx.rbf $@ +######################################################################## +# USRP-B100 fpga +######################################################################## +ifdef HAS_XTCLSH + +_usrp_b100_fpga_dir = $(TOP_FPGA_DIR)/usrp2/top/B100 +_usrp_b100_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_b100_fpga.bin +IMAGES_LIST += $(_usrp_b100_fpga_bin) + +$(_usrp_b100_fpga_bin): $(GLOBAL_DEPS) + cd $(_usrp_b100_fpga_dir) && make clean + cd $(_usrp_b100_fpga_dir) && make bin + cp $(_usrp_b100_fpga_dir)/build/u1plus.bin $@ + +endif + ######################################################################## # USRP2 and N Series firmware ######################################################################## -- cgit v1.2.3 From 522677b38cf06eea61ceb724d099fc901dc1c4b5 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 14 Jun 2011 19:15:46 -0700 Subject: n2xx: makefile typo fixes --- images/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/images/Makefile b/images/Makefile index 4b0034bf0..10e3eb7ba 100644 --- a/images/Makefile +++ b/images/Makefile @@ -201,7 +201,7 @@ IMAGES_LIST += $(_usrp_n200_r4_fpga_bin) $(_usrp_n200_r4_fpga_bin): $(GLOBAL_DEPS) cd $(_usrp_n200_r4_fpga_dir) && make -f Makefile.N200R4 clean cd $(_usrp_n200_r4_fpga_dir) && make -f Makefile.N200R4 bin - cp $(_usrp_n200_r4_fpga_dir)/build-N200r4/u2plus.bin $@ + cp $(_usrp_n200_r4_fpga_dir)/build-N200R4/u2plus.bin $@ endif @@ -217,7 +217,7 @@ IMAGES_LIST += $(_usrp_n210_r4_fpga_bin) $(_usrp_n210_r4_fpga_bin): $(GLOBAL_DEPS) cd $(_usrp_n210_r4_fpga_dir) && make -f Makefile.N210R4 clean cd $(_usrp_n210_r4_fpga_dir) && make -f Makefile.N210R4 bin - cp $(_usrp_n210_r4_fpga_dir)/build-N210r4/u2plus.bin $@ + cp $(_usrp_n210_r4_fpga_dir)/build-N210R4/u2plus.bin $@ endif -- cgit v1.2.3 From ed3439eebb51ab5ef8f184624212ded30a8544bb Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 14 Jun 2011 23:58:06 -0700 Subject: b100: fix fx2_ctrl include to use relative path --- host/lib/usrp/usrp_b100/b100_iface.hpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/host/lib/usrp/usrp_b100/b100_iface.hpp b/host/lib/usrp/usrp_b100/b100_iface.hpp index 4da43681d..57ed6a45c 100644 --- a/host/lib/usrp/usrp_b100/b100_iface.hpp +++ b/host/lib/usrp/usrp_b100/b100_iface.hpp @@ -23,7 +23,7 @@ #include #include #include -#include "fx2_ctrl.hpp" +#include "../fx2/fx2_ctrl.hpp" #include "b100_ctrl.hpp" /*! -- cgit v1.2.3 From 1bfb999b0a322ca6dae302c8808749bfb5f6fcb6 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 15 Jun 2011 11:34:25 -0700 Subject: b100: removed usrp prefix from files --- host/lib/usrp/CMakeLists.txt | 2 +- host/lib/usrp/b100/CMakeLists.txt | 47 +++ host/lib/usrp/b100/b100_ctrl.cpp | 245 +++++++++++++++ host/lib/usrp/b100/b100_ctrl.hpp | 69 ++++ host/lib/usrp/b100/b100_iface.cpp | 336 ++++++++++++++++++++ host/lib/usrp/b100/b100_iface.hpp | 73 +++++ host/lib/usrp/b100/b100_impl.cpp | 277 ++++++++++++++++ host/lib/usrp/b100/b100_impl.hpp | 204 ++++++++++++ host/lib/usrp/b100/b100_regs.hpp | 264 ++++++++++++++++ host/lib/usrp/b100/clock_ctrl.cpp | 525 +++++++++++++++++++++++++++++++ host/lib/usrp/b100/clock_ctrl.hpp | 118 +++++++ host/lib/usrp/b100/codec_ctrl.cpp | 283 +++++++++++++++++ host/lib/usrp/b100/codec_ctrl.hpp | 90 ++++++ host/lib/usrp/b100/codec_impl.cpp | 149 +++++++++ host/lib/usrp/b100/ctrl_packet.hpp | 75 +++++ host/lib/usrp/b100/dboard_iface.cpp | 298 ++++++++++++++++++ host/lib/usrp/b100/dboard_impl.cpp | 185 +++++++++++ host/lib/usrp/b100/dsp_impl.cpp | 189 +++++++++++ host/lib/usrp/b100/io_impl.cpp | 210 +++++++++++++ host/lib/usrp/b100/mboard_impl.cpp | 246 +++++++++++++++ host/lib/usrp/usrp_b100/CMakeLists.txt | 47 --- host/lib/usrp/usrp_b100/b100_ctrl.cpp | 245 --------------- host/lib/usrp/usrp_b100/b100_ctrl.hpp | 69 ---- host/lib/usrp/usrp_b100/b100_iface.cpp | 336 -------------------- host/lib/usrp/usrp_b100/b100_iface.hpp | 73 ----- host/lib/usrp/usrp_b100/b100_impl.cpp | 277 ---------------- host/lib/usrp/usrp_b100/b100_impl.hpp | 204 ------------ host/lib/usrp/usrp_b100/b100_regs.hpp | 264 ---------------- host/lib/usrp/usrp_b100/clock_ctrl.cpp | 525 ------------------------------- host/lib/usrp/usrp_b100/clock_ctrl.hpp | 118 ------- host/lib/usrp/usrp_b100/codec_ctrl.cpp | 283 ----------------- host/lib/usrp/usrp_b100/codec_ctrl.hpp | 90 ------ host/lib/usrp/usrp_b100/codec_impl.cpp | 149 --------- host/lib/usrp/usrp_b100/ctrl_packet.hpp | 75 ----- host/lib/usrp/usrp_b100/dboard_iface.cpp | 298 ------------------ host/lib/usrp/usrp_b100/dboard_impl.cpp | 185 ----------- host/lib/usrp/usrp_b100/dsp_impl.cpp | 189 ----------- host/lib/usrp/usrp_b100/io_impl.cpp | 210 ------------- host/lib/usrp/usrp_b100/mboard_impl.cpp | 246 --------------- 39 files changed, 3884 insertions(+), 3884 deletions(-) create mode 100644 host/lib/usrp/b100/CMakeLists.txt create mode 100644 host/lib/usrp/b100/b100_ctrl.cpp create mode 100644 host/lib/usrp/b100/b100_ctrl.hpp create mode 100644 host/lib/usrp/b100/b100_iface.cpp create mode 100644 host/lib/usrp/b100/b100_iface.hpp create mode 100644 host/lib/usrp/b100/b100_impl.cpp create mode 100644 host/lib/usrp/b100/b100_impl.hpp create mode 100644 host/lib/usrp/b100/b100_regs.hpp create mode 100644 host/lib/usrp/b100/clock_ctrl.cpp create mode 100644 host/lib/usrp/b100/clock_ctrl.hpp create mode 100644 host/lib/usrp/b100/codec_ctrl.cpp create mode 100644 host/lib/usrp/b100/codec_ctrl.hpp create mode 100644 host/lib/usrp/b100/codec_impl.cpp create mode 100644 host/lib/usrp/b100/ctrl_packet.hpp create mode 100644 host/lib/usrp/b100/dboard_iface.cpp create mode 100644 host/lib/usrp/b100/dboard_impl.cpp create mode 100644 host/lib/usrp/b100/dsp_impl.cpp create mode 100644 host/lib/usrp/b100/io_impl.cpp create mode 100644 host/lib/usrp/b100/mboard_impl.cpp delete mode 100644 host/lib/usrp/usrp_b100/CMakeLists.txt delete mode 100644 host/lib/usrp/usrp_b100/b100_ctrl.cpp delete mode 100644 host/lib/usrp/usrp_b100/b100_ctrl.hpp delete mode 100644 host/lib/usrp/usrp_b100/b100_iface.cpp delete mode 100644 host/lib/usrp/usrp_b100/b100_iface.hpp delete mode 100644 host/lib/usrp/usrp_b100/b100_impl.cpp delete mode 100644 host/lib/usrp/usrp_b100/b100_impl.hpp delete mode 100644 host/lib/usrp/usrp_b100/b100_regs.hpp delete mode 100644 host/lib/usrp/usrp_b100/clock_ctrl.cpp delete mode 100644 host/lib/usrp/usrp_b100/clock_ctrl.hpp delete mode 100644 host/lib/usrp/usrp_b100/codec_ctrl.cpp delete mode 100644 host/lib/usrp/usrp_b100/codec_ctrl.hpp delete mode 100644 host/lib/usrp/usrp_b100/codec_impl.cpp delete mode 100644 host/lib/usrp/usrp_b100/ctrl_packet.hpp delete mode 100644 host/lib/usrp/usrp_b100/dboard_iface.cpp delete mode 100644 host/lib/usrp/usrp_b100/dboard_impl.cpp delete mode 100644 host/lib/usrp/usrp_b100/dsp_impl.cpp delete mode 100644 host/lib/usrp/usrp_b100/io_impl.cpp delete mode 100644 host/lib/usrp/usrp_b100/mboard_impl.cpp diff --git a/host/lib/usrp/CMakeLists.txt b/host/lib/usrp/CMakeLists.txt index a30a45977..80f4bf45e 100644 --- a/host/lib/usrp/CMakeLists.txt +++ b/host/lib/usrp/CMakeLists.txt @@ -37,5 +37,5 @@ INCLUDE_SUBDIRECTORY(dboard) INCLUDE_SUBDIRECTORY(fx2) INCLUDE_SUBDIRECTORY(usrp1) INCLUDE_SUBDIRECTORY(usrp2) -INCLUDE_SUBDIRECTORY(usrp_b100) +INCLUDE_SUBDIRECTORY(b100) INCLUDE_SUBDIRECTORY(usrp_e100) diff --git a/host/lib/usrp/b100/CMakeLists.txt b/host/lib/usrp/b100/CMakeLists.txt new file mode 100644 index 000000000..e1618a49c --- /dev/null +++ b/host/lib/usrp/b100/CMakeLists.txt @@ -0,0 +1,47 @@ +# +# Copyright 2010-2011 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + +######################################################################## +# This file included, use CMake directory variables +######################################################################## + +######################################################################## +# Conditionally configure the B100 support +######################################################################## +LIBUHD_REGISTER_COMPONENT("B100" ENABLE_B100 ON "ENABLE_LIBUHD;ENABLE_USB" OFF) + +IF(ENABLE_B100) + LIBUHD_APPEND_SOURCES( + ${CMAKE_CURRENT_SOURCE_DIR}/clock_ctrl.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/clock_ctrl.hpp + ${CMAKE_CURRENT_SOURCE_DIR}/codec_ctrl.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/codec_ctrl.hpp + ${CMAKE_CURRENT_SOURCE_DIR}/codec_impl.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/ctrl_packet.hpp + ${CMAKE_CURRENT_SOURCE_DIR}/dboard_impl.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/dboard_iface.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/dsp_impl.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/io_impl.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/mboard_impl.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/b100_ctrl.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/b100_ctrl.hpp + ${CMAKE_CURRENT_SOURCE_DIR}/b100_iface.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/b100_iface.hpp + ${CMAKE_CURRENT_SOURCE_DIR}/b100_impl.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/b100_impl.hpp + ) +ENDIF(ENABLE_B100) diff --git a/host/lib/usrp/b100/b100_ctrl.cpp b/host/lib/usrp/b100/b100_ctrl.cpp new file mode 100644 index 000000000..4d4520e1e --- /dev/null +++ b/host/lib/usrp/b100/b100_ctrl.cpp @@ -0,0 +1,245 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "../../transport/super_recv_packet_handler.hpp" +#include "b100_ctrl.hpp" +#include "b100_impl.hpp" +#include +#include +#include +#include +#include +#include +#include +#include "ctrl_packet.hpp" +#include +#include + +using namespace uhd::transport; +using namespace uhd; + +bool b100_ctrl_debug = false; + +class b100_ctrl_impl : public b100_ctrl { +public: + b100_ctrl_impl(uhd::transport::usb_zero_copy::sptr ctrl_transport) : + sync_ctrl_fifo(2), + async_msg_fifo(100), + _ctrl_transport(ctrl_transport), + _seq(0) + { + boost::barrier spawn_barrier(2); + viking_marauders.create_thread(boost::bind(&b100_ctrl_impl::viking_marauder_loop, this, boost::ref(spawn_barrier))); + spawn_barrier.wait(); + } + + int write(boost::uint32_t addr, const ctrl_data_t &data); + ctrl_data_t read(boost::uint32_t addr, size_t len); + + ~b100_ctrl_impl(void) { + bbl_out_marauding = false; + viking_marauders.interrupt_all(); + viking_marauders.join_all(); + } + + bool get_ctrl_data(ctrl_data_t &pkt_data, double timeout); + bool recv_async_msg(uhd::async_metadata_t &async_metadata, double timeout); + +private: + int send_pkt(boost::uint16_t *cmd); + + //änd hërë wë gö ä-Vïkïng för äsynchronous control packets + void viking_marauder_loop(boost::barrier &); + bounded_buffer sync_ctrl_fifo; + bounded_buffer async_msg_fifo; + boost::thread_group viking_marauders; + bool bbl_out_marauding; + + uhd::transport::usb_zero_copy::sptr _ctrl_transport; + boost::uint8_t _seq; +}; + +/*********************************************************************** + * helper functions for packing/unpacking control packets + **********************************************************************/ +void pack_ctrl_pkt(boost::uint16_t *pkt_buff, + const ctrl_pkt_t &pkt){ + //first two bits are OP + //next six bits are CALLBACKS + //next 8 bits are SEQUENCE + //next 16 bits are LENGTH (16-bit word) + //next 32 bits are ADDRESS (16-bit word LSW) + //then DATA (28 16-bit words) + pkt_buff[0] = (boost::uint16_t(pkt.pkt_meta.op) << 14) | (boost::uint16_t(pkt.pkt_meta.callbacks) << 8) | pkt.pkt_meta.seq; + pkt_buff[1] = pkt.pkt_meta.len; + pkt_buff[2] = (pkt.pkt_meta.addr & 0x00000FFF); + pkt_buff[3] = 0x0000; //address high bits always 0 on this device + + for(size_t i = 0; i < pkt.data.size(); i++) { + pkt_buff[4+i] = pkt.data[i]; + } +} + +void unpack_ctrl_pkt(const boost::uint16_t *pkt_buff, + ctrl_pkt_t &pkt){ + pkt.pkt_meta.seq = pkt_buff[0] & 0xFF; + pkt.pkt_meta.op = CTRL_PKT_OP_READ; //really this is useless + pkt.pkt_meta.len = pkt_buff[1]; + pkt.pkt_meta.callbacks = 0; //callbacks aren't implemented yet + pkt.pkt_meta.addr = pkt_buff[2] | boost::uint32_t(pkt_buff[3] << 16); + + //let's check this so we don't go pushing 64K of crap onto the pkt + if(pkt.pkt_meta.len > CTRL_PACKET_DATA_LENGTH) { + throw uhd::runtime_error("Received control packet too long"); + } + + for(int i = 4; i < 4+pkt.pkt_meta.len; i++) pkt.data.push_back(pkt_buff[i]); +} + +int b100_ctrl_impl::send_pkt(boost::uint16_t *cmd) { + managed_send_buffer::sptr sbuf = _ctrl_transport->get_send_buff(); + if(!sbuf.get()) { + throw uhd::runtime_error("Control channel send error"); + } + + //FIXME there's a better way to do this + for(size_t i = 0; i < (CTRL_PACKET_LENGTH / sizeof(boost::uint16_t)); i++) { + sbuf->cast()[i] = cmd[i]; + } + sbuf->commit(CTRL_PACKET_LENGTH); //fixed size transaction + return 0; +} + +int b100_ctrl_impl::write(boost::uint32_t addr, const ctrl_data_t &data) { + UHD_ASSERT_THROW(data.size() <= (CTRL_PACKET_DATA_LENGTH / sizeof(boost::uint16_t))); + ctrl_pkt_t pkt; + pkt.data = data; + pkt.pkt_meta.op = CTRL_PKT_OP_WRITE; + pkt.pkt_meta.callbacks = 0; + pkt.pkt_meta.seq = _seq++; + pkt.pkt_meta.len = pkt.data.size(); + pkt.pkt_meta.addr = addr; + boost::uint16_t pkt_buff[CTRL_PACKET_LENGTH / sizeof(boost::uint16_t)]; + + pack_ctrl_pkt(pkt_buff, pkt); + size_t result = send_pkt(pkt_buff); + return result; +} + +ctrl_data_t b100_ctrl_impl::read(boost::uint32_t addr, size_t len) { + UHD_ASSERT_THROW(len <= (CTRL_PACKET_DATA_LENGTH / sizeof(boost::uint16_t))); + + ctrl_pkt_t pkt; + pkt.pkt_meta.op = CTRL_PKT_OP_READ; + pkt.pkt_meta.callbacks = 0; + pkt.pkt_meta.seq = _seq++; + pkt.pkt_meta.len = len; + pkt.pkt_meta.addr = addr; + boost::uint16_t pkt_buff[CTRL_PACKET_LENGTH / sizeof(boost::uint16_t)]; + + pack_ctrl_pkt(pkt_buff, pkt); + send_pkt(pkt_buff); + + //loop around waiting for the response to appear + while(!get_ctrl_data(pkt.data, 0.05)); + + return pkt.data; +} + +/*********************************************************************** + * Viking marauders go pillaging for asynchronous control packets in the + * control response endpoint. Sync packets go in sync_ctrl_fifo, + * async TX error messages go in async_msg_fifo. sync_ctrl_fifo should + * never have more than 1 message in it, since it's expected that we'll + * wait for a control operation to finish before starting another one. + **********************************************************************/ +void b100_ctrl_impl::viking_marauder_loop(boost::barrier &spawn_barrier) { + bbl_out_marauding = true; + spawn_barrier.wait(); + set_thread_priority_safe(); + + while(bbl_out_marauding){ + managed_recv_buffer::sptr rbuf = _ctrl_transport->get_recv_buff(); + if(!rbuf.get()) continue; //that's ok, there are plenty of villages to pillage! + const boost::uint16_t *pkt_buf = rbuf->cast(); + + if(pkt_buf[0] >> 8 == CTRL_PACKET_HEADER_MAGIC) { + //so it's got a control packet header, let's parse it. + ctrl_pkt_t pkt; + unpack_ctrl_pkt(pkt_buf, pkt); + + if(pkt.pkt_meta.seq != boost::uint8_t(_seq - 1)) { + throw uhd::runtime_error("Sequence error on control channel"); + } + if(pkt.pkt_meta.len > (CTRL_PACKET_LENGTH - CTRL_PACKET_HEADER_LENGTH)) { + throw uhd::runtime_error("Control channel packet length too long"); + } + + //push it onto the queue + sync_ctrl_fifo.push_with_wait(pkt.data); + } else { //it's an async status pkt + //extract the vrt header packet info + vrt::if_packet_info_t if_packet_info; + if_packet_info.num_packet_words32 = rbuf->size()/sizeof(boost::uint32_t); + const boost::uint32_t *vrt_hdr = rbuf->cast(); + vrt::if_hdr_unpack_le(vrt_hdr, if_packet_info); + + if( if_packet_info.sid == 0 + and if_packet_info.packet_type != vrt::if_packet_info_t::PACKET_TYPE_DATA){ + //fill in the async metadata + async_metadata_t metadata; + metadata.channel = 0; + metadata.has_time_spec = if_packet_info.has_tsi and if_packet_info.has_tsf; + metadata.time_spec = time_spec_t( + time_t(if_packet_info.tsi), size_t(if_packet_info.tsf), 64e6 //FIXME get from clock_ctrl + ); + metadata.event_code = async_metadata_t::event_code_t(sph::get_context_code(vrt_hdr, if_packet_info)); + //print the famous U, and push the metadata into the message queue + if (metadata.event_code & + ( async_metadata_t::EVENT_CODE_UNDERFLOW + | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET) ) + UHD_MSG(fastpath) << "U"; + + if (metadata.event_code & + ( async_metadata_t::EVENT_CODE_SEQ_ERROR + | async_metadata_t::EVENT_CODE_SEQ_ERROR_IN_BURST) ) + UHD_MSG(fastpath) << "S"; + + async_msg_fifo.push_with_pop_on_full(metadata); + continue; + } + throw uhd::runtime_error("Control: unknown async response"); + } + } +} + +bool b100_ctrl_impl::get_ctrl_data(ctrl_data_t &pkt_data, double timeout){ + boost::this_thread::disable_interruption di; //disable because the wait can throw + return sync_ctrl_fifo.pop_with_timed_wait(pkt_data, timeout); +} + +bool b100_ctrl_impl::recv_async_msg(uhd::async_metadata_t &async_metadata, double timeout) { + boost::this_thread::disable_interruption di; //disable because the wait can throw + return async_msg_fifo.pop_with_timed_wait(async_metadata, timeout); +} + +/*********************************************************************** + * Public make function for b100_ctrl interface + **********************************************************************/ +b100_ctrl::sptr b100_ctrl::make(uhd::transport::usb_zero_copy::sptr ctrl_transport){ + return sptr(new b100_ctrl_impl(ctrl_transport)); +} diff --git a/host/lib/usrp/b100/b100_ctrl.hpp b/host/lib/usrp/b100/b100_ctrl.hpp new file mode 100644 index 000000000..ae706dbb4 --- /dev/null +++ b/host/lib/usrp/b100/b100_ctrl.hpp @@ -0,0 +1,69 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_B100_CTRL_HPP +#define INCLUDED_B100_CTRL_HPP + +#include +#include +#include +#include +#include +#include +#include "ctrl_packet.hpp" +#include + +class b100_ctrl : boost::noncopyable{ +public: + typedef boost::shared_ptr sptr; + + /*! + * Make a USRP control object from a data transport + * \param ctrl_transport a USB data transport + * \return a new b100 control object + */ + static sptr make(uhd::transport::usb_zero_copy::sptr ctrl_transport); + + /*! + * Write a byte vector to an FPGA register + * \param addr the FPGA register address + * \param bytes the data to write + * \return 0 on success, error code on failure + */ + virtual int write(boost::uint32_t addr, const ctrl_data_t &data) = 0; + + /*! + * Read a byte vector from an FPGA register (blocking read) + * \param addr the FPGA register address + * \param len the length of the read + * \return a vector of bytes from the register(s) in question + */ + virtual ctrl_data_t read(boost::uint32_t addr, size_t len) = 0; + + /*! + * Get a sync ctrl packet (blocking) + * \param the packet data buffer + * \param the timeout value + * \return true if it got something + */ + virtual bool get_ctrl_data(ctrl_data_t &pkt_data, double timeout) = 0; + + virtual bool recv_async_msg(uhd::async_metadata_t &async_metadata, double timeout) = 0; + +}; + +#endif /* INCLUDED_B100_CTRL_HPP */ diff --git a/host/lib/usrp/b100/b100_iface.cpp b/host/lib/usrp/b100/b100_iface.cpp new file mode 100644 index 000000000..17ea2e6ad --- /dev/null +++ b/host/lib/usrp/b100/b100_iface.cpp @@ -0,0 +1,336 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "b100_iface.hpp" +#include "usrp_commands.h" +#include +#include +#include +#include +#include +#include +#include + +//FOR TESTING ONLY +#include "b100_regs.hpp" +#include +#include "usrp_i2c_addr.h" + +using namespace uhd; +using namespace uhd::usrp; +using namespace uhd::transport; + +/*********************************************************************** + * Constants + **********************************************************************/ +static const bool iface_debug = true; +static const boost::uint16_t USRP_B_FW_COMPAT_NUM = 0x02; +static const boost::uint16_t USRP_B_FPGA_COMPAT_NUM = 0x03; + +/*********************************************************************** + * I2C + FX2 implementation wrapper + **********************************************************************/ +class b100_i2c_fx2_iface : public i2c_iface{ +public: + b100_i2c_fx2_iface(uhd::usrp::fx2_ctrl::sptr fx2_ctrl){ + _fx2_ctrl = fx2_ctrl; + } + + void write_i2c(boost::uint8_t addr, const byte_vector_t &bytes) + { + UHD_ASSERT_THROW(bytes.size() < max_i2c_data_bytes); + + unsigned char buff[max_i2c_data_bytes]; + std::copy(bytes.begin(), bytes.end(), buff); + + int ret = _fx2_ctrl->usrp_i2c_write(addr & 0xff, + buff, + bytes.size()); + + if (iface_debug && (ret < 0)) + uhd::runtime_error("USRP: failed i2c write"); + } + + byte_vector_t read_i2c(boost::uint8_t addr, size_t num_bytes) + { + UHD_ASSERT_THROW(num_bytes < max_i2c_data_bytes); + + unsigned char buff[max_i2c_data_bytes]; + int ret = _fx2_ctrl->usrp_i2c_read(addr & 0xff, + buff, + num_bytes); + + if (iface_debug && ((ret < 0) || (unsigned)ret < (num_bytes))) + uhd::runtime_error("USRP: failed i2c read"); + + byte_vector_t out_bytes; + for (size_t i = 0; i < num_bytes; i++) + out_bytes.push_back(buff[i]); + + return out_bytes; + } + +private: + static const size_t max_i2c_data_bytes = 64; + uhd::usrp::fx2_ctrl::sptr _fx2_ctrl; +}; + +/*********************************************************************** + * USRP-E100 interface implementation + **********************************************************************/ +class b100_iface_impl : public b100_iface{ +public: + /******************************************************************* + * Structors + ******************************************************************/ + b100_iface_impl(uhd::usrp::fx2_ctrl::sptr fx2_ctrl, + b100_ctrl::sptr fpga_ctrl) : + _fx2_i2c_iface(fx2_ctrl), + _fx2_ctrl(fx2_ctrl), + _fpga_ctrl(fpga_ctrl) + { + this->check_fw_compat(); + if (fpga_ctrl.get() != NULL){ + enable_gpif(1); + i2c_init(); + this->check_fpga_compat(); + } + mb_eeprom = mboard_eeprom_t(get_fx2_i2c_iface(), mboard_eeprom_t::MAP_B000); + } + + void check_fw_compat(void){ + unsigned char data[4]; //useless data buffer + const boost::uint16_t fw_compat_num = _fx2_ctrl->usrp_control_read( + VRQ_FW_COMPAT, 0, 0, data, sizeof(data) + ); + if (fw_compat_num != USRP_B_FW_COMPAT_NUM){ + throw uhd::runtime_error(str(boost::format( + "Expected firmware compatibility number 0x%x, but got 0x%x:\n" + "The firmware build is not compatible with the host code build." + ) % USRP_B_FW_COMPAT_NUM % fw_compat_num)); + } + } + + void check_fpga_compat(void){ + const boost::uint16_t fpga_compat_num = this->peek16(B100_REG_MISC_COMPAT); + if (fpga_compat_num != USRP_B_FPGA_COMPAT_NUM){ + throw uhd::runtime_error(str(boost::format( + "Expected FPGA compatibility number 0x%x, but got 0x%x:\n" + "The FPGA build is not compatible with the host code build." + ) % USRP_B_FPGA_COMPAT_NUM % fpga_compat_num)); + } + } + + ~b100_iface_impl(void) + { + /* NOP */ + } + + /******************************************************************* + * Peek and Poke + ******************************************************************/ + + void poke(boost::uint32_t addr, const ctrl_data_t &data) { + boost::mutex::scoped_lock lock(_ctrl_mutex); + _fpga_ctrl->write(addr, data); + } + + ctrl_data_t peek(boost::uint32_t addr, size_t len) { + boost::mutex::scoped_lock lock(_ctrl_mutex); + return _fpga_ctrl->read(addr, len); + } + + void poke16(boost::uint32_t addr, boost::uint16_t value) + { + ctrl_data_t words(1); + words[0] = value; + poke(addr, words); + } + + void poke32(boost::uint32_t addr, boost::uint32_t value) + { + //just a subset of poke() to maintain compatibility + ctrl_data_t words(2); + words[0] = value & 0x0000FFFF; + words[1] = value >> 16; + poke(addr, words); + } + + boost::uint32_t peek32(boost::uint32_t addr) + { + ctrl_data_t words = peek(addr, 2); + return boost::uint32_t((boost::uint32_t(words[1]) << 16) | words[0]); + } + + boost::uint16_t peek16(boost::uint32_t addr) + { + ctrl_data_t words = peek(addr, 1); + return boost::uint16_t(words[0]); + } + + /******************************************************************* + * I2C + ******************************************************************/ + static const boost::uint32_t i2c_datarate = 400000; + static const boost::uint32_t wishbone_clk = 64000000; //FIXME should go somewhere else + + void i2c_init(void) { + //init I2C FPGA interface. + poke16(B100_REG_I2C_CTRL, 0x0000); + //set prescalers to operate at 400kHz: WB_CLK is 64MHz... + boost::uint16_t prescaler = wishbone_clk / (i2c_datarate*5) - 1; + poke16(B100_REG_I2C_PRESCALER_LO, prescaler & 0xFF); + poke16(B100_REG_I2C_PRESCALER_HI, (prescaler >> 8) & 0xFF); + poke16(B100_REG_I2C_CTRL, I2C_CTRL_EN); //enable I2C core + } + + static const size_t max_i2c_data_bytes = 64; + + void i2c_wait_for_xfer(void) + { + while(this->peek16(B100_REG_I2C_CMD_STATUS) & I2C_ST_TIP) + boost::this_thread::sleep(boost::posix_time::milliseconds(10)); + } + + bool wait_chk_ack(void) { + i2c_wait_for_xfer(); + return (this->peek16(B100_REG_I2C_CMD_STATUS) & I2C_ST_RXACK) == 0; + } + + void write_i2c(boost::uint8_t addr, const byte_vector_t &bytes) + { + poke16(B100_REG_I2C_DATA, (addr << 1) | 0); //addr and read bit (0) + poke16(B100_REG_I2C_CMD_STATUS, I2C_CMD_WR | I2C_CMD_START | (bytes.size() == 0 ? I2C_CMD_STOP : 0)); + + //wait for previous transfer to complete + if(!wait_chk_ack()) { + poke16(B100_REG_I2C_CMD_STATUS, I2C_CMD_STOP); + return; + } + + for(size_t i = 0; i < bytes.size(); i++) { + poke16(B100_REG_I2C_DATA, bytes[i]); + poke16(B100_REG_I2C_CMD_STATUS, I2C_CMD_WR | ((i == (bytes.size() - 1)) ? I2C_CMD_STOP : 0)); + if(!wait_chk_ack()) { + poke16(B100_REG_I2C_CMD_STATUS, I2C_CMD_STOP); + return; + } + } + } + + byte_vector_t read_i2c(boost::uint8_t addr, size_t num_bytes) + { + byte_vector_t bytes; + if(num_bytes == 0) return bytes; + + while (peek16(B100_REG_I2C_CMD_STATUS) & I2C_ST_BUSY); + + poke16(B100_REG_I2C_DATA, (addr << 1) | 1); //addr and read bit (1) + poke16(B100_REG_I2C_CMD_STATUS, I2C_CMD_WR | I2C_CMD_START); + //wait for previous transfer to complete + if(!wait_chk_ack()) { + poke16(B100_REG_I2C_CMD_STATUS, I2C_CMD_STOP); + } + + for(; num_bytes > 0; num_bytes--) { + poke16(B100_REG_I2C_CMD_STATUS, I2C_CMD_RD | ((num_bytes == 1) ? (I2C_CMD_STOP | I2C_CMD_NACK) : 0)); + i2c_wait_for_xfer(); + boost::uint8_t readback = peek16(B100_REG_I2C_DATA) & 0xFF; + bytes.push_back(readback); + } + return bytes; + } + + i2c_iface &get_fx2_i2c_iface(void){ + return _fx2_i2c_iface; + } + + /******************************************************************* + * SPI interface + * Eventually this will be replaced with a control-channel system + * to let the firmware do the actual write/readback cycles. + * This keeps the bandwidth on the control channel down. + ******************************************************************/ + + void spi_wait(void) { + while(peek32(B100_REG_SPI_CTRL) & SPI_CTRL_GO_BSY); + } + + boost::uint32_t transact_spi(int which_slave, + const spi_config_t &config, + boost::uint32_t bits, + size_t num_bits, + bool readback) + { + UHD_ASSERT_THROW((num_bits <= 32) && !(num_bits % 8)); + + int edge_flags = ((config.miso_edge==spi_config_t::EDGE_FALL) ? SPI_CTRL_RXNEG : 0) | + ((config.mosi_edge==spi_config_t::EDGE_FALL) ? 0 : SPI_CTRL_TXNEG) + ; + + boost::uint16_t ctrl = SPI_CTRL_ASS | (SPI_CTRL_CHAR_LEN_MASK & num_bits) | edge_flags; + + poke16(B100_REG_SPI_DIV, 0x0001); // = fpga_clk / 4 + poke32(B100_REG_SPI_SS, which_slave & 0xFFFF); + poke32(B100_REG_SPI_TXRX0, bits); + poke16(B100_REG_SPI_CTRL, ctrl); + + poke16(B100_REG_SPI_CTRL, ctrl | SPI_CTRL_GO_BSY); + if(readback) { + spi_wait(); + return peek32(B100_REG_SPI_TXRX0); + } + else { + return 0; + } + } + + void reset_gpif(boost::uint16_t ep) { + _fx2_ctrl->usrp_control_write(VRQ_RESET_GPIF, ep, ep, 0, 0); + } + + void enable_gpif(bool en) { + _fx2_ctrl->usrp_control_write(VRQ_ENABLE_GPIF, en ? 1 : 0, 0, 0, 0); + } + + void clear_fpga_fifo(void) { + _fx2_ctrl->usrp_control_write(VRQ_CLEAR_FPGA_FIFO, 0, 0, 0, 0); + } + + void write_uart(boost::uint8_t, const std::string &) { + throw uhd::not_implemented_error("Unhandled command write_uart()"); + } + + std::string read_uart(boost::uint8_t) { + throw uhd::not_implemented_error("Unhandled command read_uart()"); + } + +private: + b100_i2c_fx2_iface _fx2_i2c_iface; + uhd::usrp::fx2_ctrl::sptr _fx2_ctrl; + b100_ctrl::sptr _fpga_ctrl; + boost::mutex _ctrl_mutex; +}; + +/*********************************************************************** + * Public Make Function + **********************************************************************/ +b100_iface::sptr b100_iface::make(uhd::usrp::fx2_ctrl::sptr fx2_ctrl, + b100_ctrl::sptr fpga_ctrl) +{ + return b100_iface::sptr(new b100_iface_impl(fx2_ctrl, fpga_ctrl)); +} diff --git a/host/lib/usrp/b100/b100_iface.hpp b/host/lib/usrp/b100/b100_iface.hpp new file mode 100644 index 000000000..57ed6a45c --- /dev/null +++ b/host/lib/usrp/b100/b100_iface.hpp @@ -0,0 +1,73 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_B100_IFACE_HPP +#define INCLUDED_B100_IFACE_HPP + +#include +#include +#include +#include +#include +#include "../fx2/fx2_ctrl.hpp" +#include "b100_ctrl.hpp" + +/*! + * The usrp1 interface class: + * Provides a set of functions to implementation layer. + * Including spi, peek, poke, control... + */ +class b100_iface : boost::noncopyable, public uhd::usrp::mboard_iface{ +public: + typedef boost::shared_ptr sptr; + + /*! + * Make a new b100 interface with the control transport. + * \param fx2_ctrl the usrp control object + * \param fpga_ctrl the FPGA interface control object + * \return a new usrp1 interface object + */ + static sptr make(uhd::usrp::fx2_ctrl::sptr fx2_ctrl, + b100_ctrl::sptr fpga_ctrl = b100_ctrl::sptr() + ); + + /*! + * Reset the GPIF interface on the FX2 + * \param which endpoint to reset + * \return + */ + virtual void reset_gpif(boost::uint16_t ep) = 0; + + /*! + * Clear the GPIF FIFOs on the FPGA + * \return + */ + virtual void clear_fpga_fifo(void) = 0; + + /*! + * Enable/disable the GPIF interfaces on the FX2 + * \return + */ + virtual void enable_gpif(bool en) = 0; + + //! Get access to the FX2 I2C interface + virtual uhd::i2c_iface &get_fx2_i2c_iface(void) = 0; + + uhd::usrp::mboard_eeprom_t mb_eeprom; +}; + +#endif /* INCLUDED_USRP1_IFACE_HPP */ diff --git a/host/lib/usrp/b100/b100_impl.cpp b/host/lib/usrp/b100/b100_impl.cpp new file mode 100644 index 000000000..772da8f42 --- /dev/null +++ b/host/lib/usrp/b100/b100_impl.cpp @@ -0,0 +1,277 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "b100_impl.hpp" +#include "b100_ctrl.hpp" +#include "fpga_regs_standard.h" +#include "usrp_spi_defs.h" +#include +#include "ctrl_packet.hpp" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "b100_regs.hpp" + +using namespace uhd; +using namespace uhd::usrp; +using namespace uhd::transport; + +const boost::uint16_t B100_VENDOR_ID = 0x2500; +const boost::uint16_t B100_PRODUCT_ID = 0x0001; +const boost::uint16_t FX2_VENDOR_ID = 0x04b4; +const boost::uint16_t FX2_PRODUCT_ID = 0x8613; + +/*********************************************************************** + * Discovery + **********************************************************************/ +static device_addrs_t b100_find(const device_addr_t &hint) +{ + device_addrs_t b100_addrs; + + //return an empty list of addresses when type is set to non-b100 + if (hint.has_key("type") and hint["type"] != "b100") return b100_addrs; + + //extract the firmware path for the b100 + std::string b100_fw_image; + try{ + b100_fw_image = find_image_path( + hint.has_key("fw")? hint["fw"] : "usrp_b100_fw.ihx" + ); + } + catch(...){ + UHD_MSG(warning) << boost::format( + "Could not locate B100 firmware.\n" + "Please install the images package.\n" + ); + return b100_addrs; + } + + boost::uint16_t vid = hint.has_key("uninit") ? FX2_VENDOR_ID : B100_VENDOR_ID; + boost::uint16_t pid = hint.has_key("uninit") ? FX2_PRODUCT_ID : B100_PRODUCT_ID; + + // Important note: + // The get device list calls are nested inside the for loop. + // This allows the usb guts to decontruct when not in use, + // so that re-enumeration after fw load can occur successfully. + // This requirement is a courtesy of libusb1.0 on windows. + + //find the usrps and load firmware + BOOST_FOREACH(usb_device_handle::sptr handle, usb_device_handle::get_device_list(vid, pid)) { + try { + fx2_ctrl::make(usb_control::make(handle))->usrp_load_firmware(b100_fw_image); + } catch (...) { + UHD_MSG(status) << "Interface claimed, ignoring device" << std::endl; + } + } + + //get descriptors again with serial number, but using the initialized VID/PID now since we have firmware + vid = B100_VENDOR_ID; + pid = B100_PRODUCT_ID; + + BOOST_FOREACH(usb_device_handle::sptr handle, usb_device_handle::get_device_list(vid, pid)) { + device_addr_t new_addr; + new_addr["type"] = "b100"; + + //Attempt to read the name from the EEPROM and perform filtering. + //This operation can throw due to compatibility mismatch. + try{ + usb_control::sptr control = usb_control::make(handle); + b100_iface::sptr iface = b100_iface::make(fx2_ctrl::make(control)); + new_addr["name"] = iface->mb_eeprom["name"]; + new_addr["serial"] = handle->get_serial(); + } + catch(const uhd::exception &){ + //set these values as empty string so the device may still be found + //and the filter's below can still operate on the discovered device + new_addr["name"] = ""; + new_addr["serial"] = ""; + } + + //this is a found b100 when the hint serial and name match or blank + if ( + (not hint.has_key("name") or hint["name"] == new_addr["name"]) and + (not hint.has_key("serial") or hint["serial"] == new_addr["serial"]) + ){ + b100_addrs.push_back(new_addr); + } + } + + return b100_addrs; +} + +/*********************************************************************** + * Make + **********************************************************************/ +static device::sptr b100_make(const device_addr_t &device_addr){ + + //extract the FPGA path for the B100 + std::string b100_fpga_image = find_image_path( + device_addr.has_key("fpga")? device_addr["fpga"] : "usrp_b100_fpga.bin" + ); + + //try to match the given device address with something on the USB bus + std::vector device_list = + usb_device_handle::get_device_list(B100_VENDOR_ID, B100_PRODUCT_ID); + + //locate the matching handle in the device list + usb_device_handle::sptr handle; + BOOST_FOREACH(usb_device_handle::sptr dev_handle, device_list) { + if (dev_handle->get_serial() == device_addr["serial"]){ + handle = dev_handle; + break; + } + } + UHD_ASSERT_THROW(handle.get() != NULL); //better be found + + //create control objects and a data transport + usb_control::sptr fx2_transport = usb_control::make(handle); + fx2_ctrl::sptr fx2_ctrl = fx2_ctrl::make(fx2_transport); + fx2_ctrl->usrp_load_fpga(b100_fpga_image); + + device_addr_t data_xport_args; + data_xport_args["recv_frame_size"] = device_addr.get("recv_frame_size", "16384"); + data_xport_args["num_recv_frames"] = device_addr.get("num_recv_frames", "16"); + data_xport_args["send_frame_size"] = device_addr.get("send_frame_size", "16384"); + data_xport_args["num_send_frames"] = device_addr.get("num_send_frames", "16"); + + usb_zero_copy::sptr data_transport = usb_zero_copy::make_wrapper( + usb_zero_copy::make( + handle, // identifier + 6, // IN endpoint + 2, // OUT endpoint + data_xport_args // param hints + ) + ); + + //create the control transport + device_addr_t ctrl_xport_args; + ctrl_xport_args["recv_frame_size"] = boost::lexical_cast(CTRL_PACKET_LENGTH); + ctrl_xport_args["num_recv_frames"] = "16"; + ctrl_xport_args["send_frame_size"] = boost::lexical_cast(CTRL_PACKET_LENGTH); + ctrl_xport_args["num_send_frames"] = "4"; + + usb_zero_copy::sptr ctrl_transport = usb_zero_copy::make( + handle, + 8, + 4, + ctrl_xport_args + ); + + const double master_clock_rate = device_addr.cast("master_clock_rate", 64e6); + + + //create the b100 implementation guts + return device::sptr(new b100_impl(data_transport, ctrl_transport, fx2_ctrl, master_clock_rate)); +} + +UHD_STATIC_BLOCK(register_b100_device){ + device::register_device(&b100_find, &b100_make); +} + +/*********************************************************************** + * Structors + **********************************************************************/ +b100_impl::b100_impl(uhd::transport::usb_zero_copy::sptr data_transport, + uhd::transport::usb_zero_copy::sptr ctrl_transport, + uhd::usrp::fx2_ctrl::sptr fx2_ctrl, + const double master_clock_rate) + : _data_transport(data_transport), _fx2_ctrl(fx2_ctrl) +{ + //this is the handler object for FPGA control packets + _fpga_ctrl = b100_ctrl::make(ctrl_transport); + + _iface = b100_iface::make(_fx2_ctrl, _fpga_ctrl); + + //create clock interface + _clock_ctrl = b100_clock_ctrl::make(_iface, master_clock_rate); + + //create codec interface + _codec_ctrl = b100_codec_ctrl::make(_iface); + + //initialize the codecs + codec_init(); + + //initialize the mboard + mboard_init(); + + //initialize the dboards + dboard_init(); + + //initialize the dsps + rx_ddc_init(); + + //initialize the dsps + tx_duc_init(); + + //init the subdev specs + this->mboard_set(MBOARD_PROP_RX_SUBDEV_SPEC, subdev_spec_t()); + this->mboard_set(MBOARD_PROP_TX_SUBDEV_SPEC, subdev_spec_t()); + + //initialize the send/recv buffs + io_init(); +} + +b100_impl::~b100_impl(void){ + /* NOP */ +} + +bool b100_impl::recv_async_msg(uhd::async_metadata_t &md, double timeout){ + return _fpga_ctrl->recv_async_msg(md, timeout); +} + +/*********************************************************************** + * Device Get + **********************************************************************/ +void b100_impl::get(const wax::obj &key_, wax::obj &val) +{ + named_prop_t key = named_prop_t::extract(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case DEVICE_PROP_NAME: + val = std::string("USRP-B100 device"); + return; + + case DEVICE_PROP_MBOARD: + UHD_ASSERT_THROW(key.name == ""); + val = _mboard_proxy->get_link(); + return; + + case DEVICE_PROP_MBOARD_NAMES: + val = prop_names_t(1, ""); //vector of size 1 with empty string + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +/*********************************************************************** + * Device Set + **********************************************************************/ +void b100_impl::set(const wax::obj &, const wax::obj &) +{ + UHD_THROW_PROP_SET_ERROR(); +} diff --git a/host/lib/usrp/b100/b100_impl.hpp b/host/lib/usrp/b100/b100_impl.hpp new file mode 100644 index 000000000..daec70bca --- /dev/null +++ b/host/lib/usrp/b100/b100_impl.hpp @@ -0,0 +1,204 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "b100_iface.hpp" +#include "b100_ctrl.hpp" +#include "clock_ctrl.hpp" +#include "codec_ctrl.hpp" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef INCLUDED_B100_IMPL_HPP +#define INCLUDED_B100_IMPL_HPP + +/*! + * Make a b100 dboard interface. + * \param iface the b100 interface object + * \param clock the clock control interface + * \param codec the codec control interface + * \return a sptr to a new dboard interface + */ +uhd::usrp::dboard_iface::sptr make_b100_dboard_iface( + b100_iface::sptr iface, + b100_clock_ctrl::sptr clock, + b100_codec_ctrl::sptr codec +); + +/*! + * Simple wax obj proxy class: + * Provides a wax obj interface for a set and a get function. + * This allows us to create nested properties structures + * while maintaining flattened code within the implementation. + */ +class wax_obj_proxy : public wax::obj { +public: + typedef boost::function get_t; + typedef boost::function set_t; + typedef boost::shared_ptr sptr; + + static sptr make(const get_t &get, const set_t &set){ + return sptr(new wax_obj_proxy(get, set)); + } + +private: + get_t _get; set_t _set; + wax_obj_proxy(const get_t &get, const set_t &set): _get(get), _set(set) {}; + void get(const wax::obj &key, wax::obj &val) {return _get(key, val);} + void set(const wax::obj &key, const wax::obj &val) {return _set(key, val);} +}; + +/*! + * USRP1 implementation guts: + * The implementation details are encapsulated here. + * Handles properties on the mboard, dboard, dsps... + */ +class b100_impl : public uhd::device { +public: + //structors + b100_impl(uhd::transport::usb_zero_copy::sptr data_transport, + uhd::transport::usb_zero_copy::sptr ctrl_transport, + uhd::usrp::fx2_ctrl::sptr fx2_ctrl, + double master_clock_rate); + + ~b100_impl(void); + + //the io interface + size_t send(const send_buffs_type &, + size_t, + const uhd::tx_metadata_t &, + const uhd::io_type_t &, + send_mode_t, double); + + size_t recv(const recv_buffs_type &, + size_t, uhd::rx_metadata_t &, + const uhd::io_type_t &, + recv_mode_t, double); + + size_t get_max_send_samps_per_packet(void) const; + + size_t get_max_recv_samps_per_packet(void) const; + + bool recv_async_msg(uhd::async_metadata_t &, double); + +private: + //clock control + b100_clock_ctrl::sptr _clock_ctrl; + + //interface to ioctls and file descriptor + b100_iface::sptr _iface; + + //handle io stuff + uhd::transport::zero_copy_if::sptr _data_transport; + UHD_PIMPL_DECL(io_impl) _io_impl; + void update_transport_channel_mapping(void); + void io_init(void); + void issue_stream_cmd(const uhd::stream_cmd_t &stream_cmd); + void handle_overrun(size_t); + + //otw types + uhd::otw_type_t _recv_otw_type; + uhd::otw_type_t _send_otw_type; + + //configuration shadows + uhd::clock_config_t _clock_config; + uhd::usrp::subdev_spec_t _rx_subdev_spec, _tx_subdev_spec; + + //ad9862 codec control interface + b100_codec_ctrl::sptr _codec_ctrl; + + //codec properties interfaces + void codec_init(void); + void rx_codec_get(const wax::obj &, wax::obj &); + void rx_codec_set(const wax::obj &, const wax::obj &); + void tx_codec_get(const wax::obj &, wax::obj &); + void tx_codec_set(const wax::obj &, const wax::obj &); + wax_obj_proxy::sptr _rx_codec_proxy, _tx_codec_proxy; + + //device functions and settings + void get(const wax::obj &, wax::obj &); + void set(const wax::obj &, const wax::obj &); + + //mboard functions and settings + void mboard_init(void); + void mboard_get(const wax::obj &, wax::obj &); + void mboard_set(const wax::obj &, const wax::obj &); + void update_clock_config(void); + wax_obj_proxy::sptr _mboard_proxy; + + /*! + * Make a usrp1 dboard interface. + * \param iface the usrp1 interface object + * \param clock the clock control interface + * \param codec the codec control interface + * \param dboard_slot the slot identifier + * \param rx_dboard_id the db id for the rx board (used for evil dbsrx purposes) + * \return a sptr to a new dboard interface + */ + static uhd::usrp::dboard_iface::sptr make_dboard_iface( + b100_iface::sptr iface, + b100_clock_ctrl::sptr clock, + b100_codec_ctrl::sptr codec, + const uhd::usrp::dboard_id_t &rx_dboard_id + ); + + //xx dboard functions and settings + void dboard_init(void); + uhd::usrp::dboard_manager::sptr _dboard_manager; + uhd::usrp::dboard_iface::sptr _dboard_iface; + + //rx dboard functions and settings + uhd::usrp::dboard_eeprom_t _rx_db_eeprom; + void rx_dboard_get(const wax::obj &, wax::obj &); + void rx_dboard_set(const wax::obj &, const wax::obj &); + wax_obj_proxy::sptr _rx_dboard_proxy; + + //tx dboard functions and settings + uhd::usrp::dboard_eeprom_t _tx_db_eeprom, _gdb_eeprom; + void tx_dboard_get(const wax::obj &, wax::obj &); + void tx_dboard_set(const wax::obj &, const wax::obj &); + wax_obj_proxy::sptr _tx_dboard_proxy; + + //rx ddc functions and settings + void rx_ddc_init(void); + void rx_ddc_get(const wax::obj &, wax::obj &); + void rx_ddc_set(const wax::obj &, const wax::obj &); + double _ddc_freq; size_t _ddc_decim; + wax_obj_proxy::sptr _rx_ddc_proxy; + + //tx duc functions and settings + void tx_duc_init(void); + void tx_duc_get(const wax::obj &, wax::obj &); + void tx_duc_set(const wax::obj &, const wax::obj &); + double _duc_freq; size_t _duc_interp; + wax_obj_proxy::sptr _tx_duc_proxy; + + //transports + b100_ctrl::sptr _fpga_ctrl; + uhd::usrp::fx2_ctrl::sptr _fx2_ctrl; + +}; + +#endif /* INCLUDED_b100_IMPL_HPP */ diff --git a/host/lib/usrp/b100/b100_regs.hpp b/host/lib/usrp/b100/b100_regs.hpp new file mode 100644 index 000000000..010df283e --- /dev/null +++ b/host/lib/usrp/b100/b100_regs.hpp @@ -0,0 +1,264 @@ + + +//////////////////////////////////////////////////////////////// +// +// Memory map for wishbone bus +// +//////////////////////////////////////////////////////////////// + +// All addresses are byte addresses. All accesses are word (16-bit) accesses. +// This means that address bit 0 is usually 0. +// There are 11 bits of address for the control. + +#ifndef __B100_REGS_H +#define __B100_REGS_H + +///////////////////////////////////////////////////// +// Slave pointers + +#define B100_REG_SLAVE(n) ((n)<<7) +#define B100_REG_SR_ADDR(n) ((B100_REG_SETTINGS_BASE) + (4*(n))) + +///////////////////////////////////////////////////// +// Slave 0 -- Misc Regs + +#define B100_REG_MISC_BASE B100_REG_SLAVE(0) + +#define B100_REG_MISC_LED B100_REG_MISC_BASE + 0 +#define B100_REG_MISC_SW B100_REG_MISC_BASE + 2 +#define B100_REG_MISC_CGEN_CTRL B100_REG_MISC_BASE + 4 +#define B100_REG_MISC_CGEN_ST B100_REG_MISC_BASE + 6 +#define B100_REG_MISC_TEST B100_REG_MISC_BASE + 8 +#define B100_REG_MISC_RX_LEN B100_REG_MISC_BASE + 10 +#define B100_REG_MISC_TX_LEN B100_REG_MISC_BASE + 12 +#define B100_REG_MISC_XFER_RATE B100_REG_MISC_BASE + 14 +#define B100_REG_MISC_COMPAT B100_REG_MISC_BASE + 16 + +///////////////////////////////////////////////////// +// Slave 1 -- UART +// CLKDIV is 16 bits, others are only 8 + +#define B100_REG_UART_BASE B100_REG_SLAVE(1) + +#define B100_REG_UART_CLKDIV B100_REG_UART_BASE + 0 +#define B100_REG_UART_TXLEVEL B100_REG_UART_BASE + 2 +#define B100_REG_UART_RXLEVEL B100_REG_UART_BASE + 4 +#define B100_REG_UART_TXCHAR B100_REG_UART_BASE + 6 +#define B100_REG_UART_RXCHAR B100_REG_UART_BASE + 8 + +///////////////////////////////////////////////////// +// Slave 2 -- SPI Core +//these are 32-bit registers mapped onto the 16-bit Wishbone bus. +//Using peek32/poke32 should allow transparent use of these registers. +#define B100_REG_SPI_BASE B100_REG_SLAVE(2) +#define B100_REG_SPI_TXRX0 B100_REG_SPI_BASE + 0 +#define B100_REG_SPI_TXRX1 B100_REG_SPI_BASE + 4 +#define B100_REG_SPI_TXRX2 B100_REG_SPI_BASE + 8 +#define B100_REG_SPI_TXRX3 B100_REG_SPI_BASE + 12 +#define B100_REG_SPI_CTRL B100_REG_SPI_BASE + 16 +#define B100_REG_SPI_DIV B100_REG_SPI_BASE + 20 +#define B100_REG_SPI_SS B100_REG_SPI_BASE + 24 + +//spi slave constants +#define B100_SPI_SS_AD9862 (1 << 2) +#define B100_SPI_SS_TX_DB (1 << 1) +#define B100_SPI_SS_RX_DB (1 << 0) + +//spi ctrl register bit definitions +#define SPI_CTRL_ASS (1<<13) +#define SPI_CTRL_IE (1<<12) +#define SPI_CTRL_LSB (1<<11) +#define SPI_CTRL_TXNEG (1<<10) //mosi edge, push on falling edge when 1 +#define SPI_CTRL_RXNEG (1<< 9) //miso edge, latch on falling edge when 1 +#define SPI_CTRL_GO_BSY (1<< 8) +#define SPI_CTRL_CHAR_LEN_MASK 0x7F + +//////////////////////////////////////////////// +// Slave 3 -- I2C Core + +#define B100_REG_I2C_BASE B100_REG_SLAVE(3) +#define B100_REG_I2C_PRESCALER_LO B100_REG_I2C_BASE + 0 +#define B100_REG_I2C_PRESCALER_HI B100_REG_I2C_BASE + 2 +#define B100_REG_I2C_CTRL B100_REG_I2C_BASE + 4 +#define B100_REG_I2C_DATA B100_REG_I2C_BASE + 6 +#define B100_REG_I2C_CMD_STATUS B100_REG_I2C_BASE + 8 + +//and while we're here... + +// +// STA, STO, RD, WR, and IACK bits are cleared automatically +// + +#define I2C_CTRL_EN (1 << 7) // core enable +#define I2C_CTRL_IE (1 << 6) // interrupt enable + +#define I2C_CMD_START (1 << 7) // generate (repeated) start condition +#define I2C_CMD_STOP (1 << 6) // generate stop condition +#define I2C_CMD_RD (1 << 5) // read from slave +#define I2C_CMD_WR (1 << 4) // write to slave +#define I2C_CMD_NACK (1 << 3) // when a rcvr, send ACK (ACK=0) or NACK (ACK=1) +#define I2C_CMD_RSVD_2 (1 << 2) // reserved +#define I2C_CMD_RSVD_1 (1 << 1) // reserved +#define I2C_CMD_IACK (1 << 0) // set to clear pending interrupt + +#define I2C_ST_RXACK (1 << 7) // Received acknowledgement from slave (1 = NAK, 0 = ACK) +#define I2C_ST_BUSY (1 << 6) // 1 after START signal detected; 0 after STOP signal detected +#define I2C_ST_AL (1 << 5) // Arbitration lost. 1 when core lost arbitration +#define I2C_ST_RSVD_4 (1 << 4) // reserved +#define I2C_ST_RSVD_3 (1 << 3) // reserved +#define I2C_ST_RSVD_2 (1 << 2) // reserved +#define I2C_ST_TIP (1 << 1) // Transfer-in-progress +#define I2C_ST_IP (1 << 0) // Interrupt pending + +//////////////////////////////////////////////// +// Slave 4 -- GPIO + +#define B100_REG_GPIO_BASE B100_REG_SLAVE(4) + +#define B100_REG_GPIO_RX_IO B100_REG_GPIO_BASE + 0 +#define B100_REG_GPIO_TX_IO B100_REG_GPIO_BASE + 2 +#define B100_REG_GPIO_RX_DDR B100_REG_GPIO_BASE + 4 +#define B100_REG_GPIO_TX_DDR B100_REG_GPIO_BASE + 6 +#define B100_REG_GPIO_RX_SEL B100_REG_GPIO_BASE + 8 +#define B100_REG_GPIO_TX_SEL B100_REG_GPIO_BASE + 10 +#define B100_REG_GPIO_RX_DBG B100_REG_GPIO_BASE + 12 +#define B100_REG_GPIO_TX_DBG B100_REG_GPIO_BASE + 14 + +//possible bit values for sel when dbg is 0: +#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg +#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic + +//possible bit values for sel when dbg is 1: +#define GPIO_SEL_DEBUG_0 0 // if pin is an output, debug lines from FPGA fabric +#define GPIO_SEL_DEBUG_1 1 // if pin is an output, debug lines from FPGA fabric + +/////////////////////////////////////////////////// +// Slave 6 -- ATR Controller +// 16 regs + +#define B100_REG_ATR_BASE B100_REG_SLAVE(6) + +#define B100_REG_ATR_IDLE_RXSIDE B100_REG_ATR_BASE + 0 +#define B100_REG_ATR_IDLE_TXSIDE B100_REG_ATR_BASE + 2 +#define B100_REG_ATR_INTX_RXSIDE B100_REG_ATR_BASE + 4 +#define B100_REG_ATR_INTX_TXSIDE B100_REG_ATR_BASE + 6 +#define B100_REG_ATR_INRX_RXSIDE B100_REG_ATR_BASE + 8 +#define B100_REG_ATR_INRX_TXSIDE B100_REG_ATR_BASE + 10 +#define B100_REG_ATR_FULL_RXSIDE B100_REG_ATR_BASE + 12 +#define B100_REG_ATR_FULL_TXSIDE B100_REG_ATR_BASE + 14 + +/////////////////////////////////////////////////// +// Slave 7 -- Readback Mux 32 + +#define B100_REG_RB_MUX_32_BASE B100_REG_SLAVE(7) + +#define B100_REG_RB_TIME_NOW_SECS B100_REG_RB_MUX_32_BASE + 0 +#define B100_REG_RB_TIME_NOW_TICKS B100_REG_RB_MUX_32_BASE + 4 +#define B100_REG_RB_TIME_PPS_SECS B100_REG_RB_MUX_32_BASE + 8 +#define B100_REG_RB_TIME_PPS_TICKS B100_REG_RB_MUX_32_BASE + 12 +#define B100_REG_RB_MISC_TEST32 B100_REG_RB_MUX_32_BASE + 16 + +//////////////////////////////////////////////////// +// Slaves 8 & 9 -- Settings Bus +// +// Output-only, no readback, 64 registers total +// Each register must be written 32 bits at a time +// First the address xxx_xx00 and then xxx_xx10 + +#define B100_REG_SETTINGS_BASE_ADDR(n) (B100_REG_SLAVE(8) + (4*(n))) + +#define B100_REG_SR_MISC_TEST32 B100_REG_SETTINGS_BASE_ADDR(52) + +///////////////////////////////////////////////// +// DSP RX Regs +//////////////////////////////////////////////// +#define B100_REG_DSP_RX_ADDR(n) (B100_REG_SETTINGS_BASE_ADDR(16) + (4*(n))) +#define B100_REG_DSP_RX_FREQ B100_REG_DSP_RX_ADDR(0) +#define B100_REG_DSP_RX_SCALE_IQ B100_REG_DSP_RX_ADDR(1) // {scale_i,scale_q} +#define B100_REG_DSP_RX_DECIM_RATE B100_REG_DSP_RX_ADDR(2) // hb and decim rate +#define B100_REG_DSP_RX_DCOFFSET_I B100_REG_DSP_RX_ADDR(3) // Bit 31 high sets fixed offset mode, using lower 14 bits, // otherwise it is automatic +#define B100_REG_DSP_RX_DCOFFSET_Q B100_REG_DSP_RX_ADDR(4) // Bit 31 high sets fixed offset mode, using lower 14 bits +#define B100_REG_DSP_RX_MUX B100_REG_DSP_RX_ADDR(5) + +/////////////////////////////////////////////////// +// VITA RX CTRL regs +/////////////////////////////////////////////////// +// The following 3 are logically a single command register. +// They are clocked into the underlying fifo when time_ticks is written. +#define B100_REG_CTRL_RX_ADDR(n) (B100_REG_SETTINGS_BASE_ADDR(0) + (4*(n))) +#define B100_REG_CTRL_RX_STREAM_CMD B100_REG_CTRL_RX_ADDR(0) // {now, chain, num_samples(30) +#define B100_REG_CTRL_RX_TIME_SECS B100_REG_CTRL_RX_ADDR(1) +#define B100_REG_CTRL_RX_TIME_TICKS B100_REG_CTRL_RX_ADDR(2) +#define B100_REG_CTRL_RX_CLEAR_OVERRUN B100_REG_CTRL_RX_ADDR(3) // write anything to clear overrun +#define B100_REG_CTRL_RX_VRT_HEADER B100_REG_CTRL_RX_ADDR(4) // word 0 of packet. FPGA fills in packet counter +#define B100_REG_CTRL_RX_VRT_STREAM_ID B100_REG_CTRL_RX_ADDR(5) // word 1 of packet. +#define B100_REG_CTRL_RX_VRT_TRAILER B100_REG_CTRL_RX_ADDR(6) +#define B100_REG_CTRL_RX_NSAMPS_PER_PKT B100_REG_CTRL_RX_ADDR(7) +#define B100_REG_CTRL_RX_NCHANNELS B100_REG_CTRL_RX_ADDR(8) // 1 in basic case, up to 4 for vector sources + +///////////////////////////////////////////////// +// DSP TX Regs +//////////////////////////////////////////////// +#define B100_REG_DSP_TX_ADDR(n) (B100_REG_SETTINGS_BASE_ADDR(32) + (4*(n))) +#define B100_REG_DSP_TX_FREQ B100_REG_DSP_TX_ADDR(0) +#define B100_REG_DSP_TX_SCALE_IQ B100_REG_DSP_TX_ADDR(1) // {scale_i,scale_q} +#define B100_REG_DSP_TX_INTERP_RATE B100_REG_DSP_TX_ADDR(2) +#define B100_REG_DSP_TX_UNUSED B100_REG_DSP_TX_ADDR(3) +#define B100_REG_DSP_TX_MUX B100_REG_DSP_TX_ADDR(4) + +///////////////////////////////////////////////// +// VITA TX CTRL regs +//////////////////////////////////////////////// +#define B100_REG_CTRL_TX_ADDR(n) (B100_REG_SETTINGS_BASE_ADDR(24) + (4*(n))) +#define B100_REG_CTRL_TX_NCHANNELS B100_REG_CTRL_TX_ADDR(0) +#define B100_REG_CTRL_TX_CLEAR_UNDERRUN B100_REG_CTRL_TX_ADDR(1) +#define B100_REG_CTRL_TX_REPORT_SID B100_REG_CTRL_TX_ADDR(2) +#define B100_REG_CTRL_TX_POLICY B100_REG_CTRL_TX_ADDR(3) + +#define B100_FLAG_CTRL_TX_POLICY_WAIT (0x1 << 0) +#define B100_FLAG_CTRL_TX_POLICY_NEXT_PACKET (0x1 << 1) +#define B100_FLAG_CTRL_TX_POLICY_NEXT_BURST (0x1 << 2) + +///////////////////////////////////////////////// +// VITA49 64 bit time (write only) +//////////////////////////////////////////////// + /*! + * \brief Time 64 flags + * + * 
+   *
+   *    3                   2                   1
+   *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   * +-----------------------------------------------------------+-+-+
+   * |                                                           |S|P|
+   * +-----------------------------------------------------------+-+-+
+   *
+   * P - PPS edge selection (0=negedge, 1=posedge, default=0)
+   * S - Source (0=sma, 1=mimo, 0=default)
+   *
+   *
+ */ +#define B100_REG_TIME64_ADDR(n) (B100_REG_SETTINGS_BASE_ADDR(40) + (4*(n))) +#define B100_REG_TIME64_SECS B100_REG_TIME64_ADDR(0) // value to set absolute secs to on next PPS +#define B100_REG_TIME64_TICKS B100_REG_TIME64_ADDR(1) // value to set absolute ticks to on next PPS +#define B100_REG_TIME64_FLAGS B100_REG_TIME64_ADDR(2) // flags - see chart above +#define B100_REG_TIME64_IMM B100_REG_TIME64_ADDR(3) // set immediate (0=latch on next pps, 1=latch immediate, default=0) +#define B100_REG_TIME64_TPS B100_REG_TIME64_ADDR(4) // clock ticks per second (counter rollover) + +//pps flags (see above) +#define B100_FLAG_TIME64_PPS_NEGEDGE (0 << 0) +#define B100_FLAG_TIME64_PPS_POSEDGE (1 << 0) +#define B100_FLAG_TIME64_PPS_SMA (0 << 1) +#define B100_FLAG_TIME64_PPS_MIMO (1 << 1) + +#define B100_FLAG_TIME64_LATCH_NOW 1 +#define B100_FLAG_TIME64_LATCH_NEXT_PPS 0 + +#define B100_REG_CLEAR_RX_FIFO B100_REG_SETTINGS_BASE_ADDR(48) +#define B100_REG_CLEAR_TX_FIFO B100_REG_SETTINGS_BASE_ADDR(49) + +#define B100_REG_GLOBAL_RESET B100_REG_SETTINGS_BASE_ADDR(50) +#define B100_REG_TEST32 B100_REG_SETTINGS_BASE_ADDR(52) + +#endif + diff --git a/host/lib/usrp/b100/clock_ctrl.cpp b/host/lib/usrp/b100/clock_ctrl.cpp new file mode 100644 index 000000000..e138242d1 --- /dev/null +++ b/host/lib/usrp/b100/clock_ctrl.cpp @@ -0,0 +1,525 @@ +// +// Copyright 2010-2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "clock_ctrl.hpp" +#include "ad9522_regs.hpp" +#include +#include +#include +#include +#include +#include +#include "b100_regs.hpp" //spi slave constants +#include +#include +#include +#include +#include //gcd +#include +#include + +using namespace uhd; + +/*********************************************************************** + * Constants + **********************************************************************/ +static const bool ENABLE_THE_TEST_OUT = true; +static const double REFERENCE_INPUT_RATE = 10e6; + +/*********************************************************************** + * Helpers + **********************************************************************/ +template static void set_clock_divider( + size_t divider, div_type &low, div_type &high, bypass_type &bypass +){ + high = divider/2 - 1; + low = divider - high - 2; + bypass = (divider == 1)? 1 : 0; +} + +/*********************************************************************** + * Clock rate calculation stuff: + * Using the internal VCO between 1400 and 1800 MHz + **********************************************************************/ +struct clock_settings_type{ + size_t ref_clock_doubler, r_counter, a_counter, b_counter, prescaler, vco_divider, chan_divider; + size_t get_n_counter(void) const{return prescaler * b_counter + a_counter;} + double get_ref_rate(void) const{return REFERENCE_INPUT_RATE * ref_clock_doubler;} + double get_vco_rate(void) const{return get_ref_rate()/r_counter * get_n_counter();} + double get_chan_rate(void) const{return get_vco_rate()/vco_divider;} + double get_out_rate(void) const{return get_chan_rate()/chan_divider;} + std::string to_pp_string(void) const{ + return str(boost::format( + " r_counter: %d\n" + " a_counter: %d\n" + " b_counter: %d\n" + " prescaler: %d\n" + " vco_divider: %d\n" + " chan_divider: %d\n" + " vco_rate: %fMHz\n" + " chan_rate: %fMHz\n" + " out_rate: %fMHz\n" + ) + % r_counter + % a_counter + % b_counter + % prescaler + % vco_divider + % chan_divider + % (get_vco_rate()/1e6) + % (get_chan_rate()/1e6) + % (get_out_rate()/1e6) + ); + } +}; + +//! gives the greatest divisor of num between 1 and max inclusive +template static inline T greatest_divisor(T num, T max){ + for (T i = max; i > 1; i--) if (num%i == 0) return i; return 1; +} + +//! gives the least divisor of num between min and num exclusive +template static inline T least_divisor(T num, T min){ + for (T i = min; i < num; i++) if (num%i == 0) return i; return 1; +} + +static clock_settings_type get_clock_settings(double rate){ + clock_settings_type cs; + cs.ref_clock_doubler = 2; //always doubling + cs.prescaler = 8; //set to 8 when input is under 2400 MHz + + //basic formulas used below: + //out_rate*X = ref_rate*Y + //X = i*ref_rate/gcd + //Y = i*out_rate/gcd + //X = chan_div * vco_div * R + //Y = P*B + A + + const boost::uint64_t out_rate = boost::uint64_t(rate); + const boost::uint64_t ref_rate = boost::uint64_t(cs.get_ref_rate()); + const size_t gcd = size_t(boost::math::gcd(ref_rate, out_rate)); + + for (size_t i = 1; i <= 100; i++){ + const size_t X = i*ref_rate/gcd; + const size_t Y = i*out_rate/gcd; + + //determine A and B (P is fixed) + cs.b_counter = Y/cs.prescaler; + cs.a_counter = Y - cs.b_counter*cs.prescaler; + + static const double vco_bound_pad = 100e6; + for ( //calculate an r divider that fits into the bounds of the vco + cs.r_counter = size_t(cs.get_n_counter()*cs.get_ref_rate()/(1800e6 - vco_bound_pad)); + cs.r_counter <= size_t(cs.get_n_counter()*cs.get_ref_rate()/(1400e6 + vco_bound_pad)) + and cs.r_counter > 0; cs.r_counter++ + ){ + + //determine chan_div and vco_div + //and fill in that order of preference + cs.chan_divider = greatest_divisor(X/cs.r_counter, 32); + cs.vco_divider = greatest_divisor(X/cs.chan_divider/cs.r_counter, 6); + + //avoid a vco divider of 1 (if possible) + if (cs.vco_divider == 1){ + cs.vco_divider = least_divisor(cs.chan_divider, 2); + cs.chan_divider /= cs.vco_divider; + } + + UHD_LOGV(always) + << "gcd " << gcd << std::endl + << "X " << X << std::endl + << "Y " << Y << std::endl + << cs.to_pp_string() << std::endl + ; + + //filter limits on the counters + if (cs.vco_divider == 1) continue; + if (cs.r_counter >= (1<<14)) continue; + if (cs.b_counter == 2) continue; + if (cs.b_counter == 1 and cs.a_counter != 0) continue; + if (cs.b_counter >= (1<<13)) continue; + if (cs.a_counter >= (1<<6)) continue; + + UHD_MSG(status) << "USRP-B100 clock control: " << i << std::endl << cs.to_pp_string() << std::endl; + return cs; + } + } + + throw uhd::runtime_error(str(boost::format( + "USRP-B100 clock control: could not calculate settings for clock rate %fMHz" + ) % (rate/1e6))); +} + +/*********************************************************************** + * Clock Control Implementation + **********************************************************************/ +class b100_clock_ctrl_impl : public b100_clock_ctrl{ +public: + b100_clock_ctrl_impl(b100_iface::sptr iface, double master_clock_rate){ + _iface = iface; + _chan_rate = 0.0; + _out_rate = 0.0; + + //init the clock gen registers + _ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO; + _ad9522_regs.enb_stat_eeprom_at_stat_pin = 0; //use status pin + _ad9522_regs.status_pin_control = 0x1; //n divider + _ad9522_regs.ld_pin_control = 0x00; //dld + _ad9522_regs.refmon_pin_control = 0x12; //show ref2 + _ad9522_regs.lock_detect_counter = ad9522_regs_t::LOCK_DETECT_COUNTER_16CYC; + + this->use_internal_ref(); + + this->set_fpga_clock_rate(master_clock_rate); //initialize to something + + this->enable_fpga_clock(true); + this->enable_test_clock(ENABLE_THE_TEST_OUT); + this->enable_rx_dboard_clock(false); + this->enable_tx_dboard_clock(false); + } + + ~b100_clock_ctrl_impl(void){ + UHD_SAFE_CALL( + this->enable_test_clock(ENABLE_THE_TEST_OUT); + this->enable_rx_dboard_clock(false); + this->enable_tx_dboard_clock(false); + //this->enable_fpga_clock(false); //FIXME + ) + } + + /*********************************************************************** + * Clock rate control: + * - set clock rate w/ internal VCO + * - set clock rate w/ external VCXO + **********************************************************************/ + void set_clock_settings_with_internal_vco(double rate){ + const clock_settings_type cs = get_clock_settings(rate); + + //set the rates to private variables so the implementation knows! + _chan_rate = cs.get_chan_rate(); + _out_rate = cs.get_out_rate(); + + _ad9522_regs.enable_clock_doubler = (cs.ref_clock_doubler == 2)? 1 : 0; + + _ad9522_regs.set_r_counter(cs.r_counter); + _ad9522_regs.a_counter = cs.a_counter; + _ad9522_regs.set_b_counter(cs.b_counter); + UHD_ASSERT_THROW(cs.prescaler == 8); //assumes this below: + _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV8_9; + + _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL; + _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA; + + _ad9522_regs.bypass_vco_divider = 0; + switch(cs.vco_divider){ + case 1: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV1; break; + case 2: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV2; break; + case 3: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV3; break; + case 4: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV4; break; + case 5: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5; break; + case 6: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV6; break; + } + _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_VCO; + + //setup fpga master clock + _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; + set_clock_divider(cs.chan_divider, + _ad9522_regs.divider0_low_cycles, + _ad9522_regs.divider0_high_cycles, + _ad9522_regs.divider0_bypass + ); + + //setup codec clock + _ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS; + set_clock_divider(cs.chan_divider, + _ad9522_regs.divider1_low_cycles, + _ad9522_regs.divider1_high_cycles, + _ad9522_regs.divider1_bypass + ); + + this->send_all_regs(); + calibrate_now(); + } + + void set_clock_settings_with_external_vcxo(double rate){ + //set the rates to private variables so the implementation knows! + _chan_rate = rate; + _out_rate = rate; + + _ad9522_regs.enable_clock_doubler = 1; //doubler always on + const double ref_rate = REFERENCE_INPUT_RATE*2; + + //bypass prescaler such that N = B + long gcd = boost::math::gcd(long(ref_rate), long(rate)); + _ad9522_regs.set_r_counter(int(ref_rate/gcd)); + _ad9522_regs.a_counter = 0; + _ad9522_regs.set_b_counter(int(rate/gcd)); + _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV1; + + //setup external vcxo + _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL; + _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA; + _ad9522_regs.bypass_vco_divider = 1; + _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_EXTERNAL; + + //setup fpga master clock + _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; + _ad9522_regs.divider0_bypass = 1; + + //setup codec clock + _ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS; + _ad9522_regs.divider1_bypass = 1; + + this->send_all_regs(); + } + + void set_fpga_clock_rate(double rate){ + if (_out_rate == rate) return; + if (rate == 61.44e6) set_clock_settings_with_external_vcxo(rate); + else set_clock_settings_with_internal_vco(rate); + //clock rate changed! update dboard clocks and FPGA ticks per second + set_rx_dboard_clock_rate(rate); + set_tx_dboard_clock_rate(rate); + _iface->poke32(B100_REG_TIME64_TPS, boost::uint32_t(get_fpga_clock_rate())); + } + + double get_fpga_clock_rate(void){ + return this->_out_rate; + } + + /*********************************************************************** + * FPGA clock enable + **********************************************************************/ + void enable_fpga_clock(bool enb){ + _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; + _ad9522_regs.out0_lvds_power_down = !enb; + this->send_reg(0x0F0); + this->latch_regs(); + } + + /*********************************************************************** + * Special test clock output + **********************************************************************/ + void enable_test_clock(bool enb){ + //setup test clock (same divider as codec clock) + _ad9522_regs.out4_format = ad9522_regs_t::OUT4_FORMAT_CMOS; + _ad9522_regs.out4_cmos_configuration = (enb)? + ad9522_regs_t::OUT4_CMOS_CONFIGURATION_A_ON : + ad9522_regs_t::OUT4_CMOS_CONFIGURATION_OFF; + this->send_reg(0x0F4); + this->latch_regs(); + } + + /*********************************************************************** + * RX Dboard Clock Control (output 9, divider 3) + **********************************************************************/ + void enable_rx_dboard_clock(bool enb){ + _ad9522_regs.out9_format = ad9522_regs_t::OUT9_FORMAT_CMOS; + _ad9522_regs.out9_cmos_configuration = (enb)? + ad9522_regs_t::OUT9_CMOS_CONFIGURATION_B_ON : + ad9522_regs_t::OUT9_CMOS_CONFIGURATION_OFF; + this->send_reg(0x0F9); + this->latch_regs(); + } + + std::vector get_rx_dboard_clock_rates(void){ + std::vector rates; + for(size_t div = 1; div <= 16+16; div++) + rates.push_back(this->_chan_rate/div); + return rates; + } + + void set_rx_dboard_clock_rate(double rate){ + assert_has(get_rx_dboard_clock_rates(), rate, "rx dboard clock rate"); + _rx_clock_rate = rate; + size_t divider = size_t(this->_chan_rate/rate); + //set the divider registers + set_clock_divider(divider, + _ad9522_regs.divider3_low_cycles, + _ad9522_regs.divider3_high_cycles, + _ad9522_regs.divider3_bypass + ); + this->send_reg(0x199); + this->send_reg(0x19a); + this->soft_sync(); + } + + double get_rx_clock_rate(void){ + return _rx_clock_rate; + } + + /*********************************************************************** + * TX Dboard Clock Control (output 6, divider 2) + **********************************************************************/ + void enable_tx_dboard_clock(bool enb){ + _ad9522_regs.out6_format = ad9522_regs_t::OUT6_FORMAT_CMOS; + _ad9522_regs.out6_cmos_configuration = (enb)? + ad9522_regs_t::OUT6_CMOS_CONFIGURATION_B_ON : + ad9522_regs_t::OUT6_CMOS_CONFIGURATION_OFF; + this->send_reg(0x0F6); + this->latch_regs(); + } + + std::vector get_tx_dboard_clock_rates(void){ + return get_rx_dboard_clock_rates(); //same master clock, same dividers... + } + + void set_tx_dboard_clock_rate(double rate){ + assert_has(get_tx_dboard_clock_rates(), rate, "tx dboard clock rate"); + _tx_clock_rate = rate; + size_t divider = size_t(this->_chan_rate/rate); + //set the divider registers + set_clock_divider(divider, + _ad9522_regs.divider2_low_cycles, + _ad9522_regs.divider2_high_cycles, + _ad9522_regs.divider2_bypass + ); + this->send_reg(0x196); + this->send_reg(0x197); + this->soft_sync(); + } + + double get_tx_clock_rate(void){ + return _tx_clock_rate; + } + + /*********************************************************************** + * Clock reference control + **********************************************************************/ + void use_internal_ref(void) { + _ad9522_regs.enable_ref2 = 1; + _ad9522_regs.enable_ref1 = 0; + _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF2; + _ad9522_regs.enb_auto_ref_switchover = ad9522_regs_t::ENB_AUTO_REF_SWITCHOVER_MANUAL; + this->send_reg(0x01C); + this->latch_regs(); + } + + void use_external_ref(void) { + _ad9522_regs.enable_ref2 = 0; + _ad9522_regs.enable_ref1 = 1; + _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF1; + _ad9522_regs.enb_auto_ref_switchover = ad9522_regs_t::ENB_AUTO_REF_SWITCHOVER_MANUAL; + this->send_reg(0x01C); + this->latch_regs(); + } + + void use_auto_ref(void) { + _ad9522_regs.enable_ref2 = 1; + _ad9522_regs.enable_ref1 = 1; + _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF1; + _ad9522_regs.enb_auto_ref_switchover = ad9522_regs_t::ENB_AUTO_REF_SWITCHOVER_AUTO; + this->send_reg(0x01C); + this->latch_regs(); + } + +private: + b100_iface::sptr _iface; + ad9522_regs_t _ad9522_regs; + double _out_rate; //rate at the fpga and codec + double _chan_rate; //rate before final dividers + double _rx_clock_rate, _tx_clock_rate; + + void latch_regs(void){ + _ad9522_regs.io_update = 1; + this->send_reg(0x232); + } + + void send_reg(boost::uint16_t addr){ + boost::uint32_t reg = _ad9522_regs.get_write_reg(addr); + UHD_LOGV(often) << "clock control write reg: " << std::hex << reg << std::endl; + byte_vector_t buf; + buf.push_back(boost::uint8_t(reg >> 16)); + buf.push_back(boost::uint8_t(reg >> 8)); + buf.push_back(boost::uint8_t(reg & 0xff)); + + _iface->get_fx2_i2c_iface().write_i2c(0x5C, buf); + } + + boost::uint8_t read_reg(boost::uint16_t addr){ + byte_vector_t buf; + buf.push_back(boost::uint8_t(addr >> 8)); + buf.push_back(boost::uint8_t(addr & 0xff)); + _iface->get_fx2_i2c_iface().write_i2c(0x5C, buf); + + buf = _iface->get_fx2_i2c_iface().read_i2c(0x5C, 1); + + return boost::uint32_t(buf[0] & 0xFF); + } + + void calibrate_now(void){ + //vco calibration routine: + _ad9522_regs.vco_calibration_now = 0; + this->send_reg(0x18); + this->latch_regs(); + _ad9522_regs.vco_calibration_now = 1; + this->send_reg(0x18); + this->latch_regs(); + //wait for calibration done: + static const boost::uint8_t addr = 0x01F; + for (size_t ms10 = 0; ms10 < 100; ms10++){ + boost::this_thread::sleep(boost::posix_time::milliseconds(10)); + boost::uint32_t reg = read_reg(addr); + _ad9522_regs.set_reg(addr, reg); + if (_ad9522_regs.vco_calibration_finished) goto wait_for_ld; + } + UHD_MSG(error) << "USRP-B100 clock control: VCO calibration timeout" << std::endl; + wait_for_ld: + //wait for digital lock detect: + for (size_t ms10 = 0; ms10 < 100; ms10++){ + boost::this_thread::sleep(boost::posix_time::milliseconds(10)); + boost::uint32_t reg = read_reg(addr); + _ad9522_regs.set_reg(addr, reg); + if (_ad9522_regs.digital_lock_detect) return; + } + UHD_MSG(error) << "USRP-B100 clock control: lock detection timeout" << std::endl; + } + + void soft_sync(void){ + _ad9522_regs.soft_sync = 1; + this->send_reg(0x230); + this->latch_regs(); + _ad9522_regs.soft_sync = 0; + this->send_reg(0x230); + this->latch_regs(); + } + + void send_all_regs(void){ + //setup a list of register ranges to write + typedef std::pair range_t; + static const std::vector ranges = boost::assign::list_of + (range_t(0x000, 0x000)) (range_t(0x010, 0x01F)) + (range_t(0x0F0, 0x0FD)) (range_t(0x190, 0x19B)) + (range_t(0x1E0, 0x1E1)) (range_t(0x230, 0x230)) + ; + + //write initial register values and latch/update + BOOST_FOREACH(const range_t &range, ranges){ + for(boost::uint16_t addr = range.first; addr <= range.second; addr++){ + this->send_reg(addr); + } + } + this->latch_regs(); + } +}; + +/*********************************************************************** + * Clock Control Make + **********************************************************************/ +b100_clock_ctrl::sptr b100_clock_ctrl::make(b100_iface::sptr iface, double master_clock_rate){ + return sptr(new b100_clock_ctrl_impl(iface, master_clock_rate)); +} diff --git a/host/lib/usrp/b100/clock_ctrl.hpp b/host/lib/usrp/b100/clock_ctrl.hpp new file mode 100644 index 000000000..2a2e74024 --- /dev/null +++ b/host/lib/usrp/b100/clock_ctrl.hpp @@ -0,0 +1,118 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_B100_CLOCK_CTRL_HPP +#define INCLUDED_B100_CLOCK_CTRL_HPP + +#include "b100_iface.hpp" +#include +#include +#include + +/*! + * The usrp-e clock control: + * - Setup system clocks. + * - Disable/enable clock lines. + */ +class b100_clock_ctrl : boost::noncopyable{ +public: + typedef boost::shared_ptr sptr; + + /*! + * Make a new clock control object. + * \param iface the b100 iface object + * \param master_clock_rate the master FPGA/sample clock rate + * \return the clock control object + */ + static sptr make(b100_iface::sptr iface, double master_clock_rate); + + /*! + * Set the rate of the fpga clock line. + * Throws if rate is not valid. + * \param rate the new rate in Hz + */ + virtual void set_fpga_clock_rate(double rate) = 0; + + /*! + * Get the rate of the fpga clock line. + * \return the fpga clock rate in Hz + */ + virtual double get_fpga_clock_rate(void) = 0; + + /*! + * Get the possible rates of the rx dboard clock. + * \return a vector of clock rates in Hz + */ + virtual std::vector get_rx_dboard_clock_rates(void) = 0; + + /*! + * Get the possible rates of the tx dboard clock. + * \return a vector of clock rates in Hz + */ + virtual std::vector get_tx_dboard_clock_rates(void) = 0; + + /*! + * Set the rx dboard clock rate to a possible rate. + * \param rate the new clock rate in Hz + * \throw exception when rate cannot be achieved + */ + virtual void set_rx_dboard_clock_rate(double rate) = 0; + + /*! + * Set the tx dboard clock rate to a possible rate. + * \param rate the new clock rate in Hz + * \throw exception when rate cannot be achieved + */ + virtual void set_tx_dboard_clock_rate(double rate) = 0; + + /*! + * Enable/disable the FPGA clock. + * \param enb true to enable + */ + + virtual void enable_fpga_clock(bool enb) = 0; + + /*! + * Enable/disable the rx dboard clock. + * \param enb true to enable + */ + virtual void enable_rx_dboard_clock(bool enb) = 0; + + /*! + * Enable/disable the tx dboard clock. + * \param enb true to enable + */ + virtual void enable_tx_dboard_clock(bool enb) = 0; + + /*! + * Use the internal TCXO reference + */ + virtual void use_internal_ref(void) = 0; + + /*! + * Use the external SMA reference + */ + virtual void use_external_ref(void) = 0; + + /*! + * Use external if available, internal otherwise + */ + virtual void use_auto_ref(void) = 0; + +}; + +#endif /* INCLUDED_B100_CLOCK_CTRL_HPP */ diff --git a/host/lib/usrp/b100/codec_ctrl.cpp b/host/lib/usrp/b100/codec_ctrl.cpp new file mode 100644 index 000000000..4d118b68b --- /dev/null +++ b/host/lib/usrp/b100/codec_ctrl.cpp @@ -0,0 +1,283 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "codec_ctrl.hpp" +#include "ad9862_regs.hpp" +#include +#include +#include +#include +#include +#include +#include +#include +#include "b100_regs.hpp" //spi slave constants +#include + +using namespace uhd; + +const gain_range_t b100_codec_ctrl::tx_pga_gain_range(-20, 0, double(0.1)); +const gain_range_t b100_codec_ctrl::rx_pga_gain_range(0, 20, 1); + +/*********************************************************************** + * Codec Control Implementation + **********************************************************************/ +class b100_codec_ctrl_impl : public b100_codec_ctrl{ +public: + //structors + b100_codec_ctrl_impl(b100_iface::sptr iface); + ~b100_codec_ctrl_impl(void); + + //aux adc and dac control + double read_aux_adc(aux_adc_t which); + void write_aux_dac(aux_dac_t which, double volts); + + //pga gain control + void set_tx_pga_gain(double); + double get_tx_pga_gain(void); + void set_rx_pga_gain(double, char); + double get_rx_pga_gain(char); + +private: + b100_iface::sptr _iface; + ad9862_regs_t _ad9862_regs; + void send_reg(boost::uint8_t addr); + void recv_reg(boost::uint8_t addr); +}; + +/*********************************************************************** + * Codec Control Structors + **********************************************************************/ +b100_codec_ctrl_impl::b100_codec_ctrl_impl(b100_iface::sptr iface){ + _iface = iface; + + //soft reset + _ad9862_regs.soft_reset = 1; + this->send_reg(0); + + //initialize the codec register settings + _ad9862_regs.sdio_bidir = ad9862_regs_t::SDIO_BIDIR_SDIO_SDO; + _ad9862_regs.lsb_first = ad9862_regs_t::LSB_FIRST_MSB; + _ad9862_regs.soft_reset = 0; + + //setup rx side of codec + _ad9862_regs.byp_buffer_a = 1; + _ad9862_regs.byp_buffer_b = 1; + _ad9862_regs.buffer_a_pd = 1; + _ad9862_regs.buffer_b_pd = 1; + _ad9862_regs.mux_out = ad9862_regs_t::MUX_OUT_RX_MUX_MODE; //B100 uses interleaved RX->FPGA + _ad9862_regs.rx_pga_a = 0;//0x1f; //TODO bring under api control + _ad9862_regs.rx_pga_b = 0;//0x1f; //TODO bring under api control + _ad9862_regs.rx_twos_comp = 1; + _ad9862_regs.rx_hilbert = ad9862_regs_t::RX_HILBERT_DIS; + + //setup tx side of codec + _ad9862_regs.two_data_paths = ad9862_regs_t::TWO_DATA_PATHS_BOTH; + _ad9862_regs.interleaved = ad9862_regs_t::INTERLEAVED_INTERLEAVED; + _ad9862_regs.tx_retime = ad9862_regs_t::TX_RETIME_CLKOUT2; + _ad9862_regs.tx_pga_gain = 199; //TODO bring under api control + _ad9862_regs.tx_hilbert = ad9862_regs_t::TX_HILBERT_DIS; + _ad9862_regs.interp = ad9862_regs_t::INTERP_2; + _ad9862_regs.tx_twos_comp = 1; + _ad9862_regs.fine_mode = ad9862_regs_t::FINE_MODE_BYPASS; + _ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_BYPASS; + _ad9862_regs.dac_a_coarse_gain = 0x3; + _ad9862_regs.dac_b_coarse_gain = 0x3; + _ad9862_regs.edges = ad9862_regs_t::EDGES_NORMAL; + + //setup the dll + _ad9862_regs.input_clk_ctrl = ad9862_regs_t::INPUT_CLK_CTRL_EXTERNAL; + _ad9862_regs.dll_mult = ad9862_regs_t::DLL_MULT_2; + _ad9862_regs.dll_mode = ad9862_regs_t::DLL_MODE_FAST; + + //write the register settings to the codec + for (uint8_t addr = 0; addr <= 25; addr++){ + this->send_reg(addr); + } + + //always start conversions for aux ADC + _ad9862_regs.start_a = 1; + _ad9862_regs.start_b = 1; + + //aux adc clock + _ad9862_regs.clk_4 = ad9862_regs_t::CLK_4_1_4; + this->send_reg(34); +} + +b100_codec_ctrl_impl::~b100_codec_ctrl_impl(void){ + UHD_SAFE_CALL( + //set aux dacs to zero + this->write_aux_dac(AUX_DAC_A, 0); + this->write_aux_dac(AUX_DAC_B, 0); + this->write_aux_dac(AUX_DAC_C, 0); + this->write_aux_dac(AUX_DAC_D, 0); + + //power down + _ad9862_regs.all_rx_pd = 1; + this->send_reg(1); + _ad9862_regs.tx_digital_pd = 1; + _ad9862_regs.tx_analog_pd = ad9862_regs_t::TX_ANALOG_PD_BOTH; + this->send_reg(8); + ) +} + +/*********************************************************************** + * Codec Control Gain Control Methods + **********************************************************************/ +static const int mtpgw = 255; //maximum tx pga gain word + +void b100_codec_ctrl_impl::set_tx_pga_gain(double gain){ + int gain_word = int(mtpgw*(gain - tx_pga_gain_range.start())/(tx_pga_gain_range.stop() - tx_pga_gain_range.start())); + _ad9862_regs.tx_pga_gain = uhd::clip(gain_word, 0, mtpgw); + this->send_reg(16); +} + +double b100_codec_ctrl_impl::get_tx_pga_gain(void){ + return (_ad9862_regs.tx_pga_gain*(tx_pga_gain_range.stop() - tx_pga_gain_range.start())/mtpgw) + tx_pga_gain_range.start(); +} + +static const int mrpgw = 0x14; //maximum rx pga gain word + +void b100_codec_ctrl_impl::set_rx_pga_gain(double gain, char which){ + int gain_word = int(mrpgw*(gain - rx_pga_gain_range.start())/(rx_pga_gain_range.stop() - rx_pga_gain_range.start())); + gain_word = uhd::clip(gain_word, 0, mrpgw); + switch(which){ + case 'A': + _ad9862_regs.rx_pga_a = gain_word; + this->send_reg(2); + return; + case 'B': + _ad9862_regs.rx_pga_b = gain_word; + this->send_reg(3); + return; + default: UHD_THROW_INVALID_CODE_PATH(); + } +} + +double b100_codec_ctrl_impl::get_rx_pga_gain(char which){ + int gain_word; + switch(which){ + case 'A': gain_word = _ad9862_regs.rx_pga_a; break; + case 'B': gain_word = _ad9862_regs.rx_pga_b; break; + default: UHD_THROW_INVALID_CODE_PATH(); + } + return (gain_word*(rx_pga_gain_range.stop() - rx_pga_gain_range.start())/mrpgw) + rx_pga_gain_range.start(); +} + +/*********************************************************************** + * Codec Control AUX ADC Methods + **********************************************************************/ +static double aux_adc_to_volts(boost::uint8_t high, boost::uint8_t low){ + return double((boost::uint16_t(high) << 2) | low)*3.3/0x3ff; +} + +double b100_codec_ctrl_impl::read_aux_adc(aux_adc_t which){ + switch(which){ + + case AUX_ADC_A1: + _ad9862_regs.select_a = ad9862_regs_t::SELECT_A_AUX_ADC1; + this->send_reg(34); //start conversion and select mux + this->recv_reg(28); //read the value (2 bytes, 2 reads) + this->recv_reg(29); + return aux_adc_to_volts(_ad9862_regs.aux_adc_a1_9_2, _ad9862_regs.aux_adc_a1_1_0); + case AUX_ADC_A2: + _ad9862_regs.select_a = ad9862_regs_t::SELECT_A_AUX_ADC2; + this->send_reg(34); //start conversion and select mux + this->recv_reg(26); //read the value (2 bytes, 2 reads) + this->recv_reg(27); + return aux_adc_to_volts(_ad9862_regs.aux_adc_a2_9_2, _ad9862_regs.aux_adc_a2_1_0); + + case AUX_ADC_B1: + _ad9862_regs.select_b = ad9862_regs_t::SELECT_B_AUX_ADC1; + this->send_reg(34); //start conversion and select mux + this->recv_reg(32); //read the value (2 bytes, 2 reads) + this->recv_reg(33); + return aux_adc_to_volts(_ad9862_regs.aux_adc_b1_9_2, _ad9862_regs.aux_adc_b1_1_0); + case AUX_ADC_B2: + _ad9862_regs.select_b = ad9862_regs_t::SELECT_B_AUX_ADC2; + this->send_reg(34); //start conversion and select mux + this->recv_reg(30); //read the value (2 bytes, 2 reads) + this->recv_reg(31); + return aux_adc_to_volts(_ad9862_regs.aux_adc_b2_9_2, _ad9862_regs.aux_adc_b2_1_0); + } + UHD_THROW_INVALID_CODE_PATH(); +} + +/*********************************************************************** + * Codec Control AUX DAC Methods + **********************************************************************/ +void b100_codec_ctrl_impl::write_aux_dac(aux_dac_t which, double volts){ + //special case for aux dac d (aka sigma delta word) + if (which == AUX_DAC_D){ + boost::uint16_t dac_word = uhd::clip(boost::math::iround(volts*0xfff/3.3), 0, 0xfff); + _ad9862_regs.sig_delt_11_4 = boost::uint8_t(dac_word >> 4); + _ad9862_regs.sig_delt_3_0 = boost::uint8_t(dac_word & 0xf); + this->send_reg(42); + this->send_reg(43); + return; + } + + //calculate the dac word for aux dac a, b, c + boost::uint8_t dac_word = uhd::clip(boost::math::iround(volts*0xff/3.3), 0, 0xff); + + //setup a lookup table for the aux dac params (reg ref, reg addr) + typedef boost::tuple dac_params_t; + uhd::dict aux_dac_to_params = boost::assign::map_list_of + (AUX_DAC_A, dac_params_t(&_ad9862_regs.aux_dac_a, 36)) + (AUX_DAC_B, dac_params_t(&_ad9862_regs.aux_dac_b, 37)) + (AUX_DAC_C, dac_params_t(&_ad9862_regs.aux_dac_c, 38)) + ; + + //set the aux dac register + UHD_ASSERT_THROW(aux_dac_to_params.has_key(which)); + boost::uint8_t *reg_ref, reg_addr; + boost::tie(reg_ref, reg_addr) = aux_dac_to_params[which]; + *reg_ref = dac_word; + this->send_reg(reg_addr); +} + +/*********************************************************************** + * Codec Control SPI Methods + **********************************************************************/ +void b100_codec_ctrl_impl::send_reg(boost::uint8_t addr){ + boost::uint32_t reg = _ad9862_regs.get_write_reg(addr); + UHD_LOGV(rarely) << "codec control write reg: " << std::hex << reg << std::endl; + _iface->transact_spi( + B100_SPI_SS_AD9862, + spi_config_t::EDGE_RISE, + reg, 16, false /*no rb*/ + ); +} + +void b100_codec_ctrl_impl::recv_reg(boost::uint8_t addr){ + boost::uint32_t reg = _ad9862_regs.get_read_reg(addr); + UHD_LOGV(rarely) << "codec control read reg: " << std::hex << reg << std::endl; + boost::uint32_t ret = _iface->transact_spi( + B100_SPI_SS_AD9862, + spi_config_t::EDGE_RISE, + reg, 16, true /*rb*/ + ); + UHD_LOGV(rarely) << "codec control read ret: " << std::hex << boost::uint16_t(ret & 0xFF) << std::endl; + _ad9862_regs.set_reg(addr, boost::uint8_t(ret&0xff)); +} + +/*********************************************************************** + * Codec Control Make + **********************************************************************/ +b100_codec_ctrl::sptr b100_codec_ctrl::make(b100_iface::sptr iface){ + return sptr(new b100_codec_ctrl_impl(iface)); +} diff --git a/host/lib/usrp/b100/codec_ctrl.hpp b/host/lib/usrp/b100/codec_ctrl.hpp new file mode 100644 index 000000000..1bd579190 --- /dev/null +++ b/host/lib/usrp/b100/codec_ctrl.hpp @@ -0,0 +1,90 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_B100_CODEC_CTRL_HPP +#define INCLUDED_B100_CODEC_CTRL_HPP + +#include "b100_iface.hpp" +#include +#include +#include + +/*! + * The usrp-e codec control: + * - Init/power down codec. + * - Read aux adc, write aux dac. + */ +class b100_codec_ctrl : boost::noncopyable{ +public: + typedef boost::shared_ptr sptr; + + static const uhd::gain_range_t tx_pga_gain_range; + static const uhd::gain_range_t rx_pga_gain_range; + + /*! + * Make a new codec control object. + * \param iface the usrp_e iface object + * \return the codec control object + */ + static sptr make(b100_iface::sptr iface); + + //! aux adc identifier constants + enum aux_adc_t{ + AUX_ADC_A2 = 0xA2, + AUX_ADC_A1 = 0xA1, + AUX_ADC_B2 = 0xB2, + AUX_ADC_B1 = 0xB1 + }; + + /*! + * Read an auxiliary adc: + * The internals remember which aux adc was read last. + * Therefore, the aux adc switch is only changed as needed. + * \param which which of the 4 adcs + * \return a value in volts + */ + virtual double read_aux_adc(aux_adc_t which) = 0; + + //! aux dac identifier constants + enum aux_dac_t{ + AUX_DAC_A = 0xA, + AUX_DAC_B = 0xB, + AUX_DAC_C = 0xC, + AUX_DAC_D = 0xD //really the sigma delta output + }; + + /*! + * Write an auxiliary dac. + * \param which which of the 4 dacs + * \param volts the level in in volts + */ + virtual void write_aux_dac(aux_dac_t which, double volts) = 0; + + //! Set the TX PGA gain + virtual void set_tx_pga_gain(double gain) = 0; + + //! Get the TX PGA gain + virtual double get_tx_pga_gain(void) = 0; + + //! Set the RX PGA gain ('A' or 'B') + virtual void set_rx_pga_gain(double gain, char which) = 0; + + //! Get the RX PGA gain ('A' or 'B') + virtual double get_rx_pga_gain(char which) = 0; +}; + +#endif /* INCLUDED_B100_CODEC_CTRL_HPP */ diff --git a/host/lib/usrp/b100/codec_impl.cpp b/host/lib/usrp/b100/codec_impl.cpp new file mode 100644 index 000000000..de3ca3a66 --- /dev/null +++ b/host/lib/usrp/b100/codec_impl.cpp @@ -0,0 +1,149 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "b100_impl.hpp" +#include +#include +#include + +using namespace uhd; +using namespace uhd::usrp; + +/*********************************************************************** + * Helper Methods + **********************************************************************/ +void b100_impl::codec_init(void){ + //make proxies + _rx_codec_proxy = wax_obj_proxy::make( + boost::bind(&b100_impl::rx_codec_get, this, _1, _2), + boost::bind(&b100_impl::rx_codec_set, this, _1, _2) + ); + _tx_codec_proxy = wax_obj_proxy::make( + boost::bind(&b100_impl::tx_codec_get, this, _1, _2), + boost::bind(&b100_impl::tx_codec_set, this, _1, _2) + ); +} + +/*********************************************************************** + * RX Codec Properties + **********************************************************************/ +static const std::string ad9862_pga_gain_name = "ad9862 pga"; + +void b100_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case CODEC_PROP_NAME: + val = std::string("b100 adc - ad9522"); + return; + + case CODEC_PROP_OTHERS: + val = prop_names_t(); + return; + + case CODEC_PROP_GAIN_NAMES: + val = prop_names_t(1, ad9862_pga_gain_name); + return; + + case CODEC_PROP_GAIN_RANGE: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + val = b100_codec_ctrl::rx_pga_gain_range; + return; + + case CODEC_PROP_GAIN_I: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + val = _codec_ctrl->get_rx_pga_gain('A'); + return; + + case CODEC_PROP_GAIN_Q: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + val = _codec_ctrl->get_rx_pga_gain('B'); + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +void b100_impl::rx_codec_set(const wax::obj &key_, const wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the set request conditioned on the key + switch(key.as()){ + case CODEC_PROP_GAIN_I: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + _codec_ctrl->set_rx_pga_gain(val.as(), 'A'); + return; + + case CODEC_PROP_GAIN_Q: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + _codec_ctrl->set_rx_pga_gain(val.as(), 'B'); + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } +} + +/*********************************************************************** + * TX Codec Properties + **********************************************************************/ +void b100_impl::tx_codec_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case CODEC_PROP_NAME: + val = std::string("b100 dac - ad9522"); + return; + + case CODEC_PROP_OTHERS: + val = prop_names_t(); + return; + + case CODEC_PROP_GAIN_NAMES: + val = prop_names_t(1, ad9862_pga_gain_name); + return; + + case CODEC_PROP_GAIN_RANGE: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + val = b100_codec_ctrl::tx_pga_gain_range; + return; + + case CODEC_PROP_GAIN_I: //only one gain for I and Q + case CODEC_PROP_GAIN_Q: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + val = _codec_ctrl->get_tx_pga_gain(); + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +void b100_impl::tx_codec_set(const wax::obj &key_, const wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the set request conditioned on the key + switch(key.as()){ + case CODEC_PROP_GAIN_I: //only one gain for I and Q + case CODEC_PROP_GAIN_Q: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + _codec_ctrl->set_tx_pga_gain(val.as()); + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } +} diff --git a/host/lib/usrp/b100/ctrl_packet.hpp b/host/lib/usrp/b100/ctrl_packet.hpp new file mode 100644 index 000000000..f504fc5aa --- /dev/null +++ b/host/lib/usrp/b100/ctrl_packet.hpp @@ -0,0 +1,75 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_CTRL_PACKET_HPP +#define INCLUDED_CTRL_PACKET_HPP + +#include +#include +#include + +typedef std::vector ctrl_data_t; + +/*! + * Control packet operation type + */ +enum ctrl_pkt_op_t { + CTRL_PKT_OP_WRITE = 1, + CTRL_PKT_OP_READ = 2, + CTRL_PKT_OP_READBACK = 3 +}; + +/*! + * Control packet transaction length + */ +const size_t CTRL_PACKET_LENGTH = 32; +const size_t CTRL_PACKET_HEADER_LENGTH = 8; +const size_t CTRL_PACKET_DATA_LENGTH = 24; //=length-header + +/*! + * Control packet header magic value + */ +const boost::uint8_t CTRL_PACKET_HEADER_MAGIC = 0xAA; + +/*! + * Callback triggers for readback operation + */ +//FIXME: these are not real numbers, callbacks aren't implemented yet +const boost::uint16_t CTRL_PACKET_CALLBACK_SPI = 0x0001; +const boost::uint16_t CTRL_PACKET_CALLBACK_I2C = 0x0002; +//and so on + +/*! + * Metadata structure to describe a control packet + */ +struct UHD_API ctrl_pkt_meta_t { + ctrl_pkt_op_t op; + boost::uint8_t callbacks; + boost::uint8_t seq; + boost::uint16_t len; + boost::uint32_t addr; +}; + +/*! + * Full control packet structure + */ +struct UHD_API ctrl_pkt_t { + ctrl_pkt_meta_t pkt_meta; + ctrl_data_t data; +}; + +#endif /* INCLUDED_CTRL_PACKET_HPP */ diff --git a/host/lib/usrp/b100/dboard_iface.cpp b/host/lib/usrp/b100/dboard_iface.cpp new file mode 100644 index 000000000..ec3da6220 --- /dev/null +++ b/host/lib/usrp/b100/dboard_iface.cpp @@ -0,0 +1,298 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "b100_iface.hpp" +#include "b100_regs.hpp" +#include "clock_ctrl.hpp" +#include "codec_ctrl.hpp" +#include +#include +#include +#include + + +using namespace uhd; +using namespace uhd::usrp; +using namespace boost::assign; + +class b100_dboard_iface : public dboard_iface{ +public: + + b100_dboard_iface( + b100_iface::sptr iface, + b100_clock_ctrl::sptr clock, + b100_codec_ctrl::sptr codec + ){ + _iface = iface; + _clock = clock; + _codec = codec; + + //init the clock rate shadows + this->set_clock_rate(UNIT_RX, _clock->get_fpga_clock_rate()); + this->set_clock_rate(UNIT_TX, _clock->get_fpga_clock_rate()); + + _iface->poke16(B100_REG_GPIO_RX_DBG, 0); + _iface->poke16(B100_REG_GPIO_TX_DBG, 0); + } + + ~b100_dboard_iface(void){ + /* NOP */ + } + + special_props_t get_special_props(void){ + special_props_t props; + props.soft_clock_divider = false; + props.mangle_i2c_addrs = false; + return props; + } + + void write_aux_dac(unit_t, aux_dac_t, double); + double read_aux_adc(unit_t, aux_adc_t); + + void _set_pin_ctrl(unit_t, boost::uint16_t); + void _set_atr_reg(unit_t, atr_reg_t, boost::uint16_t); + void _set_gpio_ddr(unit_t, boost::uint16_t); + void _set_gpio_out(unit_t, boost::uint16_t); + void set_gpio_debug(unit_t, int); + boost::uint16_t read_gpio(unit_t); + + void write_i2c(boost::uint8_t, const byte_vector_t &); + byte_vector_t read_i2c(boost::uint8_t, size_t); + + void write_spi( + unit_t unit, + const spi_config_t &config, + boost::uint32_t data, + size_t num_bits + ); + + boost::uint32_t read_write_spi( + unit_t unit, + const spi_config_t &config, + boost::uint32_t data, + size_t num_bits + ); + + void set_clock_rate(unit_t, double); + std::vector get_clock_rates(unit_t); + double get_clock_rate(unit_t); + void set_clock_enabled(unit_t, bool); + double get_codec_rate(unit_t); + +private: + b100_iface::sptr _iface; + b100_clock_ctrl::sptr _clock; + b100_codec_ctrl::sptr _codec; + uhd::dict _clock_rates; +}; + +/*********************************************************************** + * Make Function + **********************************************************************/ +dboard_iface::sptr make_b100_dboard_iface( + b100_iface::sptr iface, + b100_clock_ctrl::sptr clock, + b100_codec_ctrl::sptr codec +){ + return dboard_iface::sptr(new b100_dboard_iface(iface, clock, codec)); +} + +/*********************************************************************** + * Clock Rates + **********************************************************************/ +void b100_dboard_iface::set_clock_rate(unit_t unit, double rate){ + _clock_rates[unit] = rate; + switch(unit){ + case UNIT_RX: return _clock->set_rx_dboard_clock_rate(rate); + case UNIT_TX: return _clock->set_tx_dboard_clock_rate(rate); + } +} + +std::vector b100_dboard_iface::get_clock_rates(unit_t unit){ + switch(unit){ + case UNIT_RX: return _clock->get_rx_dboard_clock_rates(); + case UNIT_TX: return _clock->get_tx_dboard_clock_rates(); + default: UHD_THROW_INVALID_CODE_PATH(); + } +} + +double b100_dboard_iface::get_clock_rate(unit_t unit){ + return _clock_rates[unit]; +} + +void b100_dboard_iface::set_clock_enabled(unit_t unit, bool enb){ + switch(unit){ + case UNIT_RX: return _clock->enable_rx_dboard_clock(enb); + case UNIT_TX: return _clock->enable_tx_dboard_clock(enb); + } +} + +double b100_dboard_iface::get_codec_rate(unit_t){ + return _clock->get_fpga_clock_rate(); +} + +/*********************************************************************** + * GPIO + **********************************************************************/ +void b100_dboard_iface::_set_pin_ctrl(unit_t unit, boost::uint16_t value){ + UHD_ASSERT_THROW(GPIO_SEL_ATR == 1); //make this assumption + switch(unit){ + case UNIT_RX: _iface->poke16(B100_REG_GPIO_RX_SEL, value); return; + case UNIT_TX: _iface->poke16(B100_REG_GPIO_TX_SEL, value); return; + } +} + +void b100_dboard_iface::_set_gpio_ddr(unit_t unit, boost::uint16_t value){ + switch(unit){ + case UNIT_RX: _iface->poke16(B100_REG_GPIO_RX_DDR, value); return; + case UNIT_TX: _iface->poke16(B100_REG_GPIO_TX_DDR, value); return; + } +} + +void b100_dboard_iface::_set_gpio_out(unit_t unit, boost::uint16_t value){ + switch(unit){ + case UNIT_RX: _iface->poke16(B100_REG_GPIO_RX_IO, value); return; + case UNIT_TX: _iface->poke16(B100_REG_GPIO_TX_IO, value); return; + } +} + +boost::uint16_t b100_dboard_iface::read_gpio(unit_t unit){ + switch(unit){ + case UNIT_RX: return _iface->peek16(B100_REG_GPIO_RX_IO); + case UNIT_TX: return _iface->peek16(B100_REG_GPIO_TX_IO); + default: UHD_THROW_INVALID_CODE_PATH(); + } +} + +void b100_dboard_iface::_set_atr_reg(unit_t unit, atr_reg_t atr, boost::uint16_t value){ + //define mapping of unit to atr regs to register address + static const uhd::dict< + unit_t, uhd::dict + > unit_to_atr_to_addr = map_list_of + (UNIT_RX, map_list_of + (ATR_REG_IDLE, B100_REG_ATR_IDLE_RXSIDE) + (ATR_REG_TX_ONLY, B100_REG_ATR_INTX_RXSIDE) + (ATR_REG_RX_ONLY, B100_REG_ATR_INRX_RXSIDE) + (ATR_REG_FULL_DUPLEX, B100_REG_ATR_FULL_RXSIDE) + ) + (UNIT_TX, map_list_of + (ATR_REG_IDLE, B100_REG_ATR_IDLE_TXSIDE) + (ATR_REG_TX_ONLY, B100_REG_ATR_INTX_TXSIDE) + (ATR_REG_RX_ONLY, B100_REG_ATR_INRX_TXSIDE) + (ATR_REG_FULL_DUPLEX, B100_REG_ATR_FULL_TXSIDE) + ) + ; + _iface->poke16(unit_to_atr_to_addr[unit][atr], value); +} + +void b100_dboard_iface::set_gpio_debug(unit_t unit, int which){ + //set this unit to all outputs + this->set_gpio_ddr(unit, 0xffff); + + //calculate the debug selections + boost::uint32_t dbg_sels = 0x0; + int sel = (which == 0)? GPIO_SEL_DEBUG_0 : GPIO_SEL_DEBUG_1; + for(size_t i = 0; i < 16; i++) dbg_sels |= sel << i; + + //set the debug on and which debug selection + switch(unit){ + case UNIT_RX: + _iface->poke16(B100_REG_GPIO_RX_DBG, 0xffff); + _iface->poke16(B100_REG_GPIO_RX_SEL, dbg_sels); + return; + + case UNIT_TX: + _iface->poke16(B100_REG_GPIO_TX_DBG, 0xffff); + _iface->poke16(B100_REG_GPIO_TX_SEL, dbg_sels); + return; + } +} + +/*********************************************************************** + * SPI + **********************************************************************/ +/*! + * Static function to convert a unit type to a spi slave device number. + * \param unit the dboard interface unit type enum + * \return the slave device number + */ +static boost::uint32_t unit_to_otw_spi_dev(dboard_iface::unit_t unit){ + switch(unit){ + case dboard_iface::UNIT_TX: return B100_SPI_SS_TX_DB; + case dboard_iface::UNIT_RX: return B100_SPI_SS_RX_DB; + } + throw std::invalid_argument("unknown unit type"); +} + +void b100_dboard_iface::write_spi( + unit_t unit, + const spi_config_t &config, + boost::uint32_t data, + size_t num_bits +){ + _iface->transact_spi(unit_to_otw_spi_dev(unit), config, data, num_bits, false /*no rb*/); +} + +boost::uint32_t b100_dboard_iface::read_write_spi( + unit_t unit, + const spi_config_t &config, + boost::uint32_t data, + size_t num_bits +){ + return _iface->transact_spi(unit_to_otw_spi_dev(unit), config, data, num_bits, true /*rb*/); +} + +/*********************************************************************** + * I2C + **********************************************************************/ +void b100_dboard_iface::write_i2c(boost::uint8_t addr, const byte_vector_t &bytes){ + return _iface->write_i2c(addr, bytes); +} + +byte_vector_t b100_dboard_iface::read_i2c(boost::uint8_t addr, size_t num_bytes){ + return _iface->read_i2c(addr, num_bytes); +} + +/*********************************************************************** + * Aux DAX/ADC + **********************************************************************/ +void b100_dboard_iface::write_aux_dac(dboard_iface::unit_t, aux_dac_t which, double value){ + //same aux dacs for each unit + static const uhd::dict which_to_aux_dac = map_list_of + (AUX_DAC_A, b100_codec_ctrl::AUX_DAC_A) + (AUX_DAC_B, b100_codec_ctrl::AUX_DAC_B) + (AUX_DAC_C, b100_codec_ctrl::AUX_DAC_C) + (AUX_DAC_D, b100_codec_ctrl::AUX_DAC_D) + ; + _codec->write_aux_dac(which_to_aux_dac[which], value); +} + +double b100_dboard_iface::read_aux_adc(dboard_iface::unit_t unit, aux_adc_t which){ + static const uhd::dict< + unit_t, uhd::dict + > unit_to_which_to_aux_adc = map_list_of + (UNIT_RX, map_list_of + (AUX_ADC_A, b100_codec_ctrl::AUX_ADC_A1) + (AUX_ADC_B, b100_codec_ctrl::AUX_ADC_B1) + ) + (UNIT_TX, map_list_of + (AUX_ADC_A, b100_codec_ctrl::AUX_ADC_A2) + (AUX_ADC_B, b100_codec_ctrl::AUX_ADC_B2) + ) + ; + return _codec->read_aux_adc(unit_to_which_to_aux_adc[unit][which]); +} diff --git a/host/lib/usrp/b100/dboard_impl.cpp b/host/lib/usrp/b100/dboard_impl.cpp new file mode 100644 index 000000000..ba3776728 --- /dev/null +++ b/host/lib/usrp/b100/dboard_impl.cpp @@ -0,0 +1,185 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "b100_impl.hpp" +#include "b100_regs.hpp" +#include +#include +#include +#include +#include +#include "usrp_i2c_addr.h" + +using namespace uhd; +using namespace uhd::usrp; + +/*********************************************************************** + * Dboard Initialization + **********************************************************************/ +void b100_impl::dboard_init(void){ + //read the tx and rx dboard eeproms + _rx_db_eeprom.load(*_iface, I2C_ADDR_RX_A); + _tx_db_eeprom.load(*_iface, I2C_ADDR_TX_A); + _gdb_eeprom.load(*_iface, I2C_ADDR_TX_A ^ 5); + + //create a new dboard interface and manager + _dboard_iface = make_b100_dboard_iface( + _iface, _clock_ctrl, _codec_ctrl + ); + _dboard_manager = dboard_manager::make( + _rx_db_eeprom.id, + ((_gdb_eeprom.id == dboard_id_t::none())? _tx_db_eeprom : _gdb_eeprom).id, + _dboard_iface + ); + + //setup the dboard proxies + _rx_dboard_proxy = wax_obj_proxy::make( + boost::bind(&b100_impl::rx_dboard_get, this, _1, _2), + boost::bind(&b100_impl::rx_dboard_set, this, _1, _2) + ); + _tx_dboard_proxy = wax_obj_proxy::make( + boost::bind(&b100_impl::tx_dboard_get, this, _1, _2), + boost::bind(&b100_impl::tx_dboard_set, this, _1, _2) + ); +} + +/*********************************************************************** + * RX Dboard Get + **********************************************************************/ +void b100_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case DBOARD_PROP_NAME: + val = std::string("b100 dboard (rx unit)"); + return; + + case DBOARD_PROP_SUBDEV: + val = _dboard_manager->get_rx_subdev(key.name); + return; + + case DBOARD_PROP_SUBDEV_NAMES: + val = _dboard_manager->get_rx_subdev_names(); + return; + + case DBOARD_PROP_DBOARD_EEPROM: + val = _rx_db_eeprom; + return; + + case DBOARD_PROP_DBOARD_IFACE: + val = _dboard_iface; + return; + + case DBOARD_PROP_CODEC: + val = _rx_codec_proxy->get_link(); + return; + + case DBOARD_PROP_GAIN_GROUP: + val = make_gain_group( + _rx_db_eeprom.id, + _dboard_manager->get_rx_subdev(key.name), + _rx_codec_proxy->get_link(), + GAIN_GROUP_POLICY_RX + ); + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +/*********************************************************************** + * RX Dboard Set + **********************************************************************/ +void b100_impl::rx_dboard_set(const wax::obj &key, const wax::obj &val){ + switch(key.as()){ + case DBOARD_PROP_DBOARD_EEPROM: + _rx_db_eeprom = val.as(); + _rx_db_eeprom.store(*_iface, I2C_ADDR_RX_A); + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } +} + +/*********************************************************************** + * TX Dboard Get + **********************************************************************/ +void b100_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case DBOARD_PROP_NAME: + val = std::string("b100 dboard (tx unit)"); + return; + + case DBOARD_PROP_SUBDEV: + val = _dboard_manager->get_tx_subdev(key.name); + return; + + case DBOARD_PROP_SUBDEV_NAMES: + val = _dboard_manager->get_tx_subdev_names(); + return; + + case DBOARD_PROP_DBOARD_EEPROM: + val = _tx_db_eeprom; + return; + + case DBOARD_PROP_GBOARD_EEPROM: + val = _gdb_eeprom; + return; + + case DBOARD_PROP_DBOARD_IFACE: + val = _dboard_iface; + return; + + case DBOARD_PROP_CODEC: + val = _tx_codec_proxy->get_link(); + return; + + case DBOARD_PROP_GAIN_GROUP: + val = make_gain_group( + _tx_db_eeprom.id, + _dboard_manager->get_tx_subdev(key.name), + _tx_codec_proxy->get_link(), + GAIN_GROUP_POLICY_TX + ); + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +/*********************************************************************** + * TX Dboard Set + **********************************************************************/ +void b100_impl::tx_dboard_set(const wax::obj &key, const wax::obj &val){ + switch(key.as()){ + case DBOARD_PROP_DBOARD_EEPROM: + _tx_db_eeprom = val.as(); + _tx_db_eeprom.store(*_iface, I2C_ADDR_TX_A); + return; + + case DBOARD_PROP_GBOARD_EEPROM: + _gdb_eeprom = val.as(); + _gdb_eeprom.store(*_iface, I2C_ADDR_TX_A ^ 5); + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } +} diff --git a/host/lib/usrp/b100/dsp_impl.cpp b/host/lib/usrp/b100/dsp_impl.cpp new file mode 100644 index 000000000..c1bf6bedd --- /dev/null +++ b/host/lib/usrp/b100/dsp_impl.cpp @@ -0,0 +1,189 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "b100_impl.hpp" +#include "b100_regs.hpp" +#include +#include +#include +#include + +#define rint boost::math::iround + +using namespace uhd; +using namespace uhd::usrp; + +static const double MASTER_CLOCK_RATE = 64e6; //TODO get from clock control + +/*********************************************************************** + * RX DDC Initialization + **********************************************************************/ +void b100_impl::rx_ddc_init(void){ + _rx_ddc_proxy = wax_obj_proxy::make( + boost::bind(&b100_impl::rx_ddc_get, this, _1, _2), + boost::bind(&b100_impl::rx_ddc_set, this, _1, _2) + ); + + //initial config and update + rx_ddc_set(DSP_PROP_FREQ_SHIFT, double(0)); + rx_ddc_set(DSP_PROP_HOST_RATE, double(16e6)); +} + +/*********************************************************************** + * RX DDC Get + **********************************************************************/ +void b100_impl::rx_ddc_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + switch(key.as()){ + case DSP_PROP_NAME: + val = std::string("USRP-B100 RX DSP"); + return; + + case DSP_PROP_OTHERS: + val = prop_names_t(); //empty + return; + + case DSP_PROP_FREQ_SHIFT: + val = _ddc_freq; + return; + + case DSP_PROP_CODEC_RATE: + val = _clock_ctrl->get_fpga_clock_rate(); + return; + + case DSP_PROP_HOST_RATE: + val = _clock_ctrl->get_fpga_clock_rate()/_ddc_decim; + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +/*********************************************************************** + * RX DDC Set + **********************************************************************/ +void b100_impl::rx_ddc_set(const wax::obj &key_, const wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + switch(key.as()){ + case DSP_PROP_STREAM_CMD: + issue_stream_cmd(val.as()); + return; + + case DSP_PROP_FREQ_SHIFT:{ + double new_freq = val.as(); + _iface->poke32(B100_REG_DSP_RX_FREQ, + dsp_type1::calc_cordic_word_and_update(new_freq, _clock_ctrl->get_fpga_clock_rate()) + ); + _ddc_freq = new_freq; //shadow + } + return; + + case DSP_PROP_HOST_RATE:{ + //set the decimation + _ddc_decim = rint(_clock_ctrl->get_fpga_clock_rate()/val.as()); + _iface->poke32(B100_REG_DSP_RX_DECIM_RATE, dsp_type1::calc_cic_filter_word(_ddc_decim)); + + //set the scaling + static const boost::int16_t default_rx_scale_iq = 1024; + _iface->poke32(B100_REG_DSP_RX_SCALE_IQ, + dsp_type1::calc_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq) + ); + } + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } +} + +/*********************************************************************** + * TX DUC Initialization + **********************************************************************/ +void b100_impl::tx_duc_init(void){ + _tx_duc_proxy = wax_obj_proxy::make( + boost::bind(&b100_impl::tx_duc_get, this, _1, _2), + boost::bind(&b100_impl::tx_duc_set, this, _1, _2) + ); + + //initial config and update + tx_duc_set(DSP_PROP_FREQ_SHIFT, double(0)); + tx_duc_set(DSP_PROP_HOST_RATE, double(16e6)); +} + +/*********************************************************************** + * TX DUC Get + **********************************************************************/ +void b100_impl::tx_duc_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + switch(key.as()){ + case DSP_PROP_NAME: + val = std::string("USRP-B100 TX DSP"); + return; + + case DSP_PROP_OTHERS: + val = prop_names_t(); //empty + return; + + case DSP_PROP_FREQ_SHIFT: + val = _duc_freq; + return; + + case DSP_PROP_CODEC_RATE: + val = _clock_ctrl->get_fpga_clock_rate(); + return; + + case DSP_PROP_HOST_RATE: + val = _clock_ctrl->get_fpga_clock_rate()/_duc_interp; + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +/*********************************************************************** + * TX DUC Set + **********************************************************************/ +void b100_impl::tx_duc_set(const wax::obj &key_, const wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + switch(key.as()){ + + case DSP_PROP_FREQ_SHIFT:{ + double new_freq = val.as(); + _iface->poke32(B100_REG_DSP_TX_FREQ, + dsp_type1::calc_cordic_word_and_update(new_freq, _clock_ctrl->get_fpga_clock_rate()) + ); + _duc_freq = new_freq; //shadow + } + return; + + case DSP_PROP_HOST_RATE:{ + _duc_interp = rint(_clock_ctrl->get_fpga_clock_rate()/val.as()); + + //set the interpolation + _iface->poke32(B100_REG_DSP_TX_INTERP_RATE, dsp_type1::calc_cic_filter_word(_duc_interp)); + + //set the scaling + _iface->poke32(B100_REG_DSP_TX_SCALE_IQ, dsp_type1::calc_iq_scale_word(_duc_interp)); + } + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } +} diff --git a/host/lib/usrp/b100/io_impl.cpp b/host/lib/usrp/b100/io_impl.cpp new file mode 100644 index 000000000..3978bea75 --- /dev/null +++ b/host/lib/usrp/b100/io_impl.cpp @@ -0,0 +1,210 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "../../transport/super_recv_packet_handler.hpp" +#include "../../transport/super_send_packet_handler.hpp" +#include "usrp_commands.h" +#include "b100_impl.hpp" +#include "b100_regs.hpp" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +using namespace uhd; +using namespace uhd::usrp; +using namespace uhd::transport; +namespace asio = boost::asio; + +/*********************************************************************** + * IO Implementation Details + **********************************************************************/ +struct b100_impl::io_impl{ + io_impl(zero_copy_if::sptr data_transport): + data_transport(data_transport) + { + /* NOP */ + } + + ~io_impl(void){ + //drain the rx buffs + //while(data_transport->get_recv_buff().get() != NULL){ + /* NOP */ + //} + } + + zero_copy_if::sptr &data_transport; + + sph::recv_packet_handler recv_handler; + sph::send_packet_handler send_handler; + bool continuous_streaming; +}; + +/*********************************************************************** + * Initialize internals within this file + **********************************************************************/ +void b100_impl::io_init(void){ + _recv_otw_type.width = 16; + _recv_otw_type.shift = 0; + _recv_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN; + + _send_otw_type.width = 16; + _send_otw_type.shift = 0; + _send_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN; + + _iface->reset_gpif(6); + + //reset state machines + _iface->poke32(B100_REG_CTRL_TX_CLEAR_UNDERRUN, 0); + _iface->poke32(B100_REG_CTRL_RX_CLEAR_OVERRUN, 0); + + _io_impl = UHD_PIMPL_MAKE(io_impl, (_data_transport)); + + //setup rx data path + _iface->poke32(B100_REG_CTRL_RX_NSAMPS_PER_PKT, get_max_recv_samps_per_packet()); + UHD_LOGV(always) << "IO: Using " << get_max_recv_samps_per_packet() << " samples per packet" << std::endl; + _iface->poke32(B100_REG_CTRL_RX_NCHANNELS, 1); + _iface->poke32(B100_REG_CTRL_RX_VRT_HEADER, 0 + | (0x1 << 28) //if data with stream id + | (0x1 << 26) //has trailer + | (0x3 << 22) //integer time other + | (0x1 << 20) //fractional time sample count + ); + _iface->poke32(B100_REG_CTRL_RX_VRT_TRAILER, 0); + + //set the streamid to reset the seq num + _iface->poke32(B100_REG_CTRL_TX_REPORT_SID, 0); + //setup the tx policy + _iface->poke32(B100_REG_CTRL_TX_POLICY, B100_FLAG_CTRL_TX_POLICY_NEXT_PACKET); + + //set the expected packet size in USB frames + _iface->poke32(B100_REG_MISC_RX_LEN, 4); + + update_transport_channel_mapping(); +} + +void b100_impl::update_transport_channel_mapping(void){ + if (_io_impl.get() == NULL) return; //not inited yet + + //set all of the relevant properties on the handler + boost::mutex::scoped_lock recv_lock = _io_impl->recv_handler.get_scoped_lock(); + _io_impl->recv_handler.resize(_rx_subdev_spec.size()); + _io_impl->recv_handler.set_vrt_unpacker(&vrt::if_hdr_unpack_le); + _io_impl->recv_handler.set_tick_rate(_clock_ctrl->get_fpga_clock_rate()); + _io_impl->recv_handler.set_samp_rate(_rx_ddc_proxy->get_link()[DSP_PROP_HOST_RATE].as()); + for (size_t chan = 0; chan < _io_impl->recv_handler.size(); chan++){ + _io_impl->recv_handler.set_xport_chan_get_buff(chan, boost::bind( + &uhd::transport::zero_copy_if::get_recv_buff, _io_impl->data_transport, _1 + )); + _io_impl->recv_handler.set_overflow_handler(chan, boost::bind( + &b100_impl::handle_overrun, this, chan + )); + } + _io_impl->recv_handler.set_converter(_recv_otw_type); + + //set all of the relevant properties on the handler + boost::mutex::scoped_lock send_lock = _io_impl->send_handler.get_scoped_lock(); + _io_impl->send_handler.resize(_tx_subdev_spec.size()); + _io_impl->send_handler.set_vrt_packer(&vrt::if_hdr_pack_le); + _io_impl->send_handler.set_tick_rate(_clock_ctrl->get_fpga_clock_rate()); + _io_impl->send_handler.set_samp_rate(_tx_duc_proxy->get_link()[DSP_PROP_HOST_RATE].as()); + for (size_t chan = 0; chan < _io_impl->send_handler.size(); chan++){ + _io_impl->send_handler.set_xport_chan_get_buff(chan, boost::bind( + &uhd::transport::zero_copy_if::get_send_buff, _io_impl->data_transport, _1 + )); + } + _io_impl->send_handler.set_converter(_send_otw_type); + _io_impl->send_handler.set_max_samples_per_packet(get_max_send_samps_per_packet()); +} + +/*********************************************************************** + * Data send + helper functions + **********************************************************************/ +size_t b100_impl::get_max_send_samps_per_packet(void) const { + static const size_t hdr_size = 0 + + vrt::max_if_hdr_words32*sizeof(boost::uint32_t) + - sizeof(vrt::if_packet_info_t().cid) //no class id ever used + ; + static const size_t bpp = 2048 - hdr_size; + return bpp / _send_otw_type.get_sample_size(); +} + +size_t b100_impl::send( + const send_buffs_type &buffs, size_t nsamps_per_buff, + const tx_metadata_t &metadata, const io_type_t &io_type, + send_mode_t send_mode, double timeout +){ + return _io_impl->send_handler.send( + buffs, nsamps_per_buff, + metadata, io_type, + send_mode, timeout + ); +} + +/*********************************************************************** + * Data recv + helper functions + **********************************************************************/ + +size_t b100_impl::get_max_recv_samps_per_packet(void) const { + static const size_t hdr_size = 0 + + vrt::max_if_hdr_words32*sizeof(boost::uint32_t) + + sizeof(vrt::if_packet_info_t().tlr) //forced to have trailer + - sizeof(vrt::if_packet_info_t().cid) //no class id ever used + ; + size_t bpp = 2048 - hdr_size; //limited by FPGA pkt buffer size + return bpp/_recv_otw_type.get_sample_size(); +} + +size_t b100_impl::recv( + const recv_buffs_type &buffs, size_t nsamps_per_buff, + rx_metadata_t &metadata, const io_type_t &io_type, + recv_mode_t recv_mode, double timeout +){ + return _io_impl->recv_handler.recv( + buffs, nsamps_per_buff, + metadata, io_type, + recv_mode, timeout + ); +} + +void b100_impl::issue_stream_cmd(const stream_cmd_t &stream_cmd) +{ + _io_impl->continuous_streaming = (stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_START_CONTINUOUS); + _iface->poke32(B100_REG_CTRL_RX_STREAM_CMD, dsp_type1::calc_stream_cmd_word(stream_cmd)); + _iface->poke32(B100_REG_CTRL_RX_TIME_SECS, boost::uint32_t(stream_cmd.time_spec.get_full_secs())); + _iface->poke32(B100_REG_CTRL_RX_TIME_TICKS, stream_cmd.time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate())); + + if (stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS) { + while(_io_impl->data_transport->get_recv_buff().get() != NULL){ + /* NOP */ + } + } +} + +void b100_impl::handle_overrun(size_t){ + if (_io_impl->continuous_streaming){ + this->issue_stream_cmd(stream_cmd_t::STREAM_MODE_START_CONTINUOUS); + } +} diff --git a/host/lib/usrp/b100/mboard_impl.cpp b/host/lib/usrp/b100/mboard_impl.cpp new file mode 100644 index 000000000..c651ff2a2 --- /dev/null +++ b/host/lib/usrp/b100/mboard_impl.cpp @@ -0,0 +1,246 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "b100_impl.hpp" +#include "usrp_commands.h" +#include "fpga_regs_standard.h" +#include "fpga_regs_common.h" +#include "b100_regs.hpp" +#include "usrp_i2c_addr.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +using namespace uhd; +using namespace uhd::usrp; + +static const bool b100_mboard_verbose = true; + +/*********************************************************************** + * Mboard Initialization + **********************************************************************/ +void b100_impl::mboard_init(void) +{ + _mboard_proxy = wax_obj_proxy::make( + boost::bind(&b100_impl::mboard_get, this, _1, _2), + boost::bind(&b100_impl::mboard_set, this, _1, _2)); + + //set the ticks per seconds into the vita time control + _iface->poke32(B100_REG_TIME64_TPS, + boost::uint32_t(_clock_ctrl->get_fpga_clock_rate()) + ); + + //init the clock config + _clock_config = clock_config_t::internal(); + update_clock_config(); +} + +void b100_impl::update_clock_config(void){ + boost::uint32_t pps_flags = 0; + + //translate pps polarity enums + switch(_clock_config.pps_polarity){ + case clock_config_t::PPS_POS: pps_flags |= B100_FLAG_TIME64_PPS_POSEDGE; break; + case clock_config_t::PPS_NEG: pps_flags |= B100_FLAG_TIME64_PPS_NEGEDGE; break; + default: throw uhd::runtime_error("unhandled clock configuration pps polarity"); + } + + //set the pps flags + _iface->poke32(B100_REG_TIME64_FLAGS, pps_flags); + + //clock source ref 10mhz + switch(_clock_config.ref_source){ + case clock_config_t::REF_AUTO: _clock_ctrl->use_auto_ref(); break; + case clock_config_t::REF_INT: _clock_ctrl->use_internal_ref(); break; + case clock_config_t::REF_SMA: _clock_ctrl->use_auto_ref(); break; + default: throw uhd::runtime_error("unhandled clock configuration ref source"); + } +} + +/*********************************************************************** + * Mboard Get + **********************************************************************/ +void b100_impl::mboard_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case MBOARD_PROP_NAME: + val = std::string("USRP-B100 mboard"); + return; + + case MBOARD_PROP_OTHERS: + val = prop_names_t(); + return; + + case MBOARD_PROP_RX_DBOARD: + UHD_ASSERT_THROW(key.name == ""); + val = _rx_dboard_proxy->get_link(); + return; + + case MBOARD_PROP_RX_DBOARD_NAMES: + val = prop_names_t(1, ""); //vector of size 1 with empty string + return; + + case MBOARD_PROP_TX_DBOARD: + UHD_ASSERT_THROW(key.name == ""); + val = _tx_dboard_proxy->get_link(); + return; + + case MBOARD_PROP_TX_DBOARD_NAMES: + val = prop_names_t(1, ""); //vector of size 1 with empty string + return; + + case MBOARD_PROP_RX_DSP: + UHD_ASSERT_THROW(key.name == ""); + val = _rx_ddc_proxy->get_link(); + return; + + case MBOARD_PROP_RX_DSP_NAMES: + val = prop_names_t(1, ""); + return; + + case MBOARD_PROP_TX_DSP: + UHD_ASSERT_THROW(key.name == ""); + val = _tx_duc_proxy->get_link(); + return; + + case MBOARD_PROP_TX_DSP_NAMES: + val = prop_names_t(1, ""); + return; + + case MBOARD_PROP_CLOCK_CONFIG: + val = _clock_config; + return; + + case MBOARD_PROP_RX_SUBDEV_SPEC: + val = _rx_subdev_spec; + return; + + case MBOARD_PROP_TX_SUBDEV_SPEC: + val = _tx_subdev_spec; + return; + + case MBOARD_PROP_EEPROM_MAP: + val = _iface->mb_eeprom; + return; + + case MBOARD_PROP_TIME_NOW:while(true){ + uint32_t secs = _iface->peek32(B100_REG_RB_TIME_NOW_SECS); + uint32_t ticks = _iface->peek32(B100_REG_RB_TIME_NOW_TICKS); + if (secs != _iface->peek32(B100_REG_RB_TIME_NOW_SECS)) continue; + val = time_spec_t(secs, ticks, _clock_ctrl->get_fpga_clock_rate()); + return; + } + + case MBOARD_PROP_TIME_PPS: while(true){ + uint32_t secs = _iface->peek32(B100_REG_RB_TIME_PPS_SECS); + uint32_t ticks = _iface->peek32(B100_REG_RB_TIME_PPS_TICKS); + if (secs != _iface->peek32(B100_REG_RB_TIME_PPS_SECS)) continue; + val = time_spec_t(secs, ticks, _clock_ctrl->get_fpga_clock_rate()); + return; + } + + case MBOARD_PROP_CLOCK_RATE: + val = _clock_ctrl->get_fpga_clock_rate(); + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +/*********************************************************************** + * Mboard Set + **********************************************************************/ +void b100_impl::mboard_set(const wax::obj &key, const wax::obj &val) +{ + if(key.type() == typeid(std::string)) { + if(key.as() == "load_eeprom") { + std::string b100_eeprom_image = val.as(); + UHD_MSG(status) << "B100 EEPROM image: " << b100_eeprom_image << std::endl; + _fx2_ctrl->usrp_load_eeprom(val.as()); + } + return; + } + + //handle the get request conditioned on the key + switch(key.as()){ + case MBOARD_PROP_TIME_NOW: + case MBOARD_PROP_TIME_PPS:{ + time_spec_t time_spec = val.as(); + _iface->poke32(B100_REG_TIME64_TICKS, time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate())); + boost::uint32_t imm_flags = (key.as() == MBOARD_PROP_TIME_NOW)? 1 : 0; + _iface->poke32(B100_REG_TIME64_IMM, imm_flags); + _iface->poke32(B100_REG_TIME64_SECS, boost::uint32_t(time_spec.get_full_secs())); + } + return; + + case MBOARD_PROP_RX_SUBDEV_SPEC: + _rx_subdev_spec = val.as(); + verify_rx_subdev_spec(_rx_subdev_spec, _mboard_proxy->get_link()); + UHD_ASSERT_THROW(_rx_subdev_spec.size() == 1); + //set the mux + _iface->poke32(B100_REG_DSP_RX_MUX, dsp_type1::calc_rx_mux_word( + _dboard_manager->get_rx_subdev(_rx_subdev_spec.front().sd_name)[SUBDEV_PROP_CONNECTION].as() + )); + return; + + case MBOARD_PROP_TX_SUBDEV_SPEC: + _tx_subdev_spec = val.as(); + verify_tx_subdev_spec(_tx_subdev_spec, _mboard_proxy->get_link()); + UHD_ASSERT_THROW(_tx_subdev_spec.size() == 1); + //set the mux and set the number of tx channels + _iface->poke32(B100_REG_DSP_TX_MUX, dsp_type1::calc_tx_mux_word( + _dboard_manager->get_tx_subdev(_tx_subdev_spec.front().sd_name)[SUBDEV_PROP_CONNECTION].as() + )); + return; + + case MBOARD_PROP_EEPROM_MAP: + // Step1: commit the map, writing only those values set. + // Step2: readback the entire eeprom map into the iface. + val.as().commit(*_iface, mboard_eeprom_t::MAP_B000); + _iface->mb_eeprom = mboard_eeprom_t(*_iface, mboard_eeprom_t::MAP_B000); + return; + + case MBOARD_PROP_CLOCK_CONFIG: + _clock_config = val.as(); + update_clock_config(); + return; + + case MBOARD_PROP_CLOCK_RATE: + UHD_MSG(warning) + << "You are setting the master clock rate from the API.\n" + << "You may want to pass this into the device address as master_clock_rate=.\n" + << "This way, the clock rate is guaranteed to be initialized first.\n" + << "See the application notes for USRP-B100 for further instructions.\n" + ; + _clock_ctrl->set_fpga_clock_rate(val.as()); + update_transport_channel_mapping(); + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } +} diff --git a/host/lib/usrp/usrp_b100/CMakeLists.txt b/host/lib/usrp/usrp_b100/CMakeLists.txt deleted file mode 100644 index f83a10935..000000000 --- a/host/lib/usrp/usrp_b100/CMakeLists.txt +++ /dev/null @@ -1,47 +0,0 @@ -# -# Copyright 2010-2011 Ettus Research LLC -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# - -######################################################################## -# This file included, use CMake directory variables -######################################################################## - -######################################################################## -# Conditionally configure the B100 support -######################################################################## -LIBUHD_REGISTER_COMPONENT("B100" ENABLE_B100 ON "ENABLE_LIBUHD;ENABLE_USB" OFF) - -IF(ENABLE_B100) - LIBUHD_APPEND_SOURCES( - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/clock_ctrl.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/clock_ctrl.hpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/codec_ctrl.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/codec_ctrl.hpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/codec_impl.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/ctrl_packet.hpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/dboard_impl.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/dboard_iface.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/dsp_impl.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/io_impl.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/mboard_impl.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/b100_ctrl.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/b100_ctrl.hpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/b100_iface.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/b100_iface.hpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/b100_impl.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_b100/b100_impl.hpp - ) -ENDIF(ENABLE_B100) diff --git a/host/lib/usrp/usrp_b100/b100_ctrl.cpp b/host/lib/usrp/usrp_b100/b100_ctrl.cpp deleted file mode 100644 index 4d4520e1e..000000000 --- a/host/lib/usrp/usrp_b100/b100_ctrl.cpp +++ /dev/null @@ -1,245 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "../../transport/super_recv_packet_handler.hpp" -#include "b100_ctrl.hpp" -#include "b100_impl.hpp" -#include -#include -#include -#include -#include -#include -#include -#include "ctrl_packet.hpp" -#include -#include - -using namespace uhd::transport; -using namespace uhd; - -bool b100_ctrl_debug = false; - -class b100_ctrl_impl : public b100_ctrl { -public: - b100_ctrl_impl(uhd::transport::usb_zero_copy::sptr ctrl_transport) : - sync_ctrl_fifo(2), - async_msg_fifo(100), - _ctrl_transport(ctrl_transport), - _seq(0) - { - boost::barrier spawn_barrier(2); - viking_marauders.create_thread(boost::bind(&b100_ctrl_impl::viking_marauder_loop, this, boost::ref(spawn_barrier))); - spawn_barrier.wait(); - } - - int write(boost::uint32_t addr, const ctrl_data_t &data); - ctrl_data_t read(boost::uint32_t addr, size_t len); - - ~b100_ctrl_impl(void) { - bbl_out_marauding = false; - viking_marauders.interrupt_all(); - viking_marauders.join_all(); - } - - bool get_ctrl_data(ctrl_data_t &pkt_data, double timeout); - bool recv_async_msg(uhd::async_metadata_t &async_metadata, double timeout); - -private: - int send_pkt(boost::uint16_t *cmd); - - //änd hërë wë gö ä-Vïkïng för äsynchronous control packets - void viking_marauder_loop(boost::barrier &); - bounded_buffer sync_ctrl_fifo; - bounded_buffer async_msg_fifo; - boost::thread_group viking_marauders; - bool bbl_out_marauding; - - uhd::transport::usb_zero_copy::sptr _ctrl_transport; - boost::uint8_t _seq; -}; - -/*********************************************************************** - * helper functions for packing/unpacking control packets - **********************************************************************/ -void pack_ctrl_pkt(boost::uint16_t *pkt_buff, - const ctrl_pkt_t &pkt){ - //first two bits are OP - //next six bits are CALLBACKS - //next 8 bits are SEQUENCE - //next 16 bits are LENGTH (16-bit word) - //next 32 bits are ADDRESS (16-bit word LSW) - //then DATA (28 16-bit words) - pkt_buff[0] = (boost::uint16_t(pkt.pkt_meta.op) << 14) | (boost::uint16_t(pkt.pkt_meta.callbacks) << 8) | pkt.pkt_meta.seq; - pkt_buff[1] = pkt.pkt_meta.len; - pkt_buff[2] = (pkt.pkt_meta.addr & 0x00000FFF); - pkt_buff[3] = 0x0000; //address high bits always 0 on this device - - for(size_t i = 0; i < pkt.data.size(); i++) { - pkt_buff[4+i] = pkt.data[i]; - } -} - -void unpack_ctrl_pkt(const boost::uint16_t *pkt_buff, - ctrl_pkt_t &pkt){ - pkt.pkt_meta.seq = pkt_buff[0] & 0xFF; - pkt.pkt_meta.op = CTRL_PKT_OP_READ; //really this is useless - pkt.pkt_meta.len = pkt_buff[1]; - pkt.pkt_meta.callbacks = 0; //callbacks aren't implemented yet - pkt.pkt_meta.addr = pkt_buff[2] | boost::uint32_t(pkt_buff[3] << 16); - - //let's check this so we don't go pushing 64K of crap onto the pkt - if(pkt.pkt_meta.len > CTRL_PACKET_DATA_LENGTH) { - throw uhd::runtime_error("Received control packet too long"); - } - - for(int i = 4; i < 4+pkt.pkt_meta.len; i++) pkt.data.push_back(pkt_buff[i]); -} - -int b100_ctrl_impl::send_pkt(boost::uint16_t *cmd) { - managed_send_buffer::sptr sbuf = _ctrl_transport->get_send_buff(); - if(!sbuf.get()) { - throw uhd::runtime_error("Control channel send error"); - } - - //FIXME there's a better way to do this - for(size_t i = 0; i < (CTRL_PACKET_LENGTH / sizeof(boost::uint16_t)); i++) { - sbuf->cast()[i] = cmd[i]; - } - sbuf->commit(CTRL_PACKET_LENGTH); //fixed size transaction - return 0; -} - -int b100_ctrl_impl::write(boost::uint32_t addr, const ctrl_data_t &data) { - UHD_ASSERT_THROW(data.size() <= (CTRL_PACKET_DATA_LENGTH / sizeof(boost::uint16_t))); - ctrl_pkt_t pkt; - pkt.data = data; - pkt.pkt_meta.op = CTRL_PKT_OP_WRITE; - pkt.pkt_meta.callbacks = 0; - pkt.pkt_meta.seq = _seq++; - pkt.pkt_meta.len = pkt.data.size(); - pkt.pkt_meta.addr = addr; - boost::uint16_t pkt_buff[CTRL_PACKET_LENGTH / sizeof(boost::uint16_t)]; - - pack_ctrl_pkt(pkt_buff, pkt); - size_t result = send_pkt(pkt_buff); - return result; -} - -ctrl_data_t b100_ctrl_impl::read(boost::uint32_t addr, size_t len) { - UHD_ASSERT_THROW(len <= (CTRL_PACKET_DATA_LENGTH / sizeof(boost::uint16_t))); - - ctrl_pkt_t pkt; - pkt.pkt_meta.op = CTRL_PKT_OP_READ; - pkt.pkt_meta.callbacks = 0; - pkt.pkt_meta.seq = _seq++; - pkt.pkt_meta.len = len; - pkt.pkt_meta.addr = addr; - boost::uint16_t pkt_buff[CTRL_PACKET_LENGTH / sizeof(boost::uint16_t)]; - - pack_ctrl_pkt(pkt_buff, pkt); - send_pkt(pkt_buff); - - //loop around waiting for the response to appear - while(!get_ctrl_data(pkt.data, 0.05)); - - return pkt.data; -} - -/*********************************************************************** - * Viking marauders go pillaging for asynchronous control packets in the - * control response endpoint. Sync packets go in sync_ctrl_fifo, - * async TX error messages go in async_msg_fifo. sync_ctrl_fifo should - * never have more than 1 message in it, since it's expected that we'll - * wait for a control operation to finish before starting another one. - **********************************************************************/ -void b100_ctrl_impl::viking_marauder_loop(boost::barrier &spawn_barrier) { - bbl_out_marauding = true; - spawn_barrier.wait(); - set_thread_priority_safe(); - - while(bbl_out_marauding){ - managed_recv_buffer::sptr rbuf = _ctrl_transport->get_recv_buff(); - if(!rbuf.get()) continue; //that's ok, there are plenty of villages to pillage! - const boost::uint16_t *pkt_buf = rbuf->cast(); - - if(pkt_buf[0] >> 8 == CTRL_PACKET_HEADER_MAGIC) { - //so it's got a control packet header, let's parse it. - ctrl_pkt_t pkt; - unpack_ctrl_pkt(pkt_buf, pkt); - - if(pkt.pkt_meta.seq != boost::uint8_t(_seq - 1)) { - throw uhd::runtime_error("Sequence error on control channel"); - } - if(pkt.pkt_meta.len > (CTRL_PACKET_LENGTH - CTRL_PACKET_HEADER_LENGTH)) { - throw uhd::runtime_error("Control channel packet length too long"); - } - - //push it onto the queue - sync_ctrl_fifo.push_with_wait(pkt.data); - } else { //it's an async status pkt - //extract the vrt header packet info - vrt::if_packet_info_t if_packet_info; - if_packet_info.num_packet_words32 = rbuf->size()/sizeof(boost::uint32_t); - const boost::uint32_t *vrt_hdr = rbuf->cast(); - vrt::if_hdr_unpack_le(vrt_hdr, if_packet_info); - - if( if_packet_info.sid == 0 - and if_packet_info.packet_type != vrt::if_packet_info_t::PACKET_TYPE_DATA){ - //fill in the async metadata - async_metadata_t metadata; - metadata.channel = 0; - metadata.has_time_spec = if_packet_info.has_tsi and if_packet_info.has_tsf; - metadata.time_spec = time_spec_t( - time_t(if_packet_info.tsi), size_t(if_packet_info.tsf), 64e6 //FIXME get from clock_ctrl - ); - metadata.event_code = async_metadata_t::event_code_t(sph::get_context_code(vrt_hdr, if_packet_info)); - //print the famous U, and push the metadata into the message queue - if (metadata.event_code & - ( async_metadata_t::EVENT_CODE_UNDERFLOW - | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET) ) - UHD_MSG(fastpath) << "U"; - - if (metadata.event_code & - ( async_metadata_t::EVENT_CODE_SEQ_ERROR - | async_metadata_t::EVENT_CODE_SEQ_ERROR_IN_BURST) ) - UHD_MSG(fastpath) << "S"; - - async_msg_fifo.push_with_pop_on_full(metadata); - continue; - } - throw uhd::runtime_error("Control: unknown async response"); - } - } -} - -bool b100_ctrl_impl::get_ctrl_data(ctrl_data_t &pkt_data, double timeout){ - boost::this_thread::disable_interruption di; //disable because the wait can throw - return sync_ctrl_fifo.pop_with_timed_wait(pkt_data, timeout); -} - -bool b100_ctrl_impl::recv_async_msg(uhd::async_metadata_t &async_metadata, double timeout) { - boost::this_thread::disable_interruption di; //disable because the wait can throw - return async_msg_fifo.pop_with_timed_wait(async_metadata, timeout); -} - -/*********************************************************************** - * Public make function for b100_ctrl interface - **********************************************************************/ -b100_ctrl::sptr b100_ctrl::make(uhd::transport::usb_zero_copy::sptr ctrl_transport){ - return sptr(new b100_ctrl_impl(ctrl_transport)); -} diff --git a/host/lib/usrp/usrp_b100/b100_ctrl.hpp b/host/lib/usrp/usrp_b100/b100_ctrl.hpp deleted file mode 100644 index ae706dbb4..000000000 --- a/host/lib/usrp/usrp_b100/b100_ctrl.hpp +++ /dev/null @@ -1,69 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#ifndef INCLUDED_B100_CTRL_HPP -#define INCLUDED_B100_CTRL_HPP - -#include -#include -#include -#include -#include -#include -#include "ctrl_packet.hpp" -#include - -class b100_ctrl : boost::noncopyable{ -public: - typedef boost::shared_ptr sptr; - - /*! - * Make a USRP control object from a data transport - * \param ctrl_transport a USB data transport - * \return a new b100 control object - */ - static sptr make(uhd::transport::usb_zero_copy::sptr ctrl_transport); - - /*! - * Write a byte vector to an FPGA register - * \param addr the FPGA register address - * \param bytes the data to write - * \return 0 on success, error code on failure - */ - virtual int write(boost::uint32_t addr, const ctrl_data_t &data) = 0; - - /*! - * Read a byte vector from an FPGA register (blocking read) - * \param addr the FPGA register address - * \param len the length of the read - * \return a vector of bytes from the register(s) in question - */ - virtual ctrl_data_t read(boost::uint32_t addr, size_t len) = 0; - - /*! - * Get a sync ctrl packet (blocking) - * \param the packet data buffer - * \param the timeout value - * \return true if it got something - */ - virtual bool get_ctrl_data(ctrl_data_t &pkt_data, double timeout) = 0; - - virtual bool recv_async_msg(uhd::async_metadata_t &async_metadata, double timeout) = 0; - -}; - -#endif /* INCLUDED_B100_CTRL_HPP */ diff --git a/host/lib/usrp/usrp_b100/b100_iface.cpp b/host/lib/usrp/usrp_b100/b100_iface.cpp deleted file mode 100644 index 17ea2e6ad..000000000 --- a/host/lib/usrp/usrp_b100/b100_iface.cpp +++ /dev/null @@ -1,336 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "b100_iface.hpp" -#include "usrp_commands.h" -#include -#include -#include -#include -#include -#include -#include - -//FOR TESTING ONLY -#include "b100_regs.hpp" -#include -#include "usrp_i2c_addr.h" - -using namespace uhd; -using namespace uhd::usrp; -using namespace uhd::transport; - -/*********************************************************************** - * Constants - **********************************************************************/ -static const bool iface_debug = true; -static const boost::uint16_t USRP_B_FW_COMPAT_NUM = 0x02; -static const boost::uint16_t USRP_B_FPGA_COMPAT_NUM = 0x03; - -/*********************************************************************** - * I2C + FX2 implementation wrapper - **********************************************************************/ -class b100_i2c_fx2_iface : public i2c_iface{ -public: - b100_i2c_fx2_iface(uhd::usrp::fx2_ctrl::sptr fx2_ctrl){ - _fx2_ctrl = fx2_ctrl; - } - - void write_i2c(boost::uint8_t addr, const byte_vector_t &bytes) - { - UHD_ASSERT_THROW(bytes.size() < max_i2c_data_bytes); - - unsigned char buff[max_i2c_data_bytes]; - std::copy(bytes.begin(), bytes.end(), buff); - - int ret = _fx2_ctrl->usrp_i2c_write(addr & 0xff, - buff, - bytes.size()); - - if (iface_debug && (ret < 0)) - uhd::runtime_error("USRP: failed i2c write"); - } - - byte_vector_t read_i2c(boost::uint8_t addr, size_t num_bytes) - { - UHD_ASSERT_THROW(num_bytes < max_i2c_data_bytes); - - unsigned char buff[max_i2c_data_bytes]; - int ret = _fx2_ctrl->usrp_i2c_read(addr & 0xff, - buff, - num_bytes); - - if (iface_debug && ((ret < 0) || (unsigned)ret < (num_bytes))) - uhd::runtime_error("USRP: failed i2c read"); - - byte_vector_t out_bytes; - for (size_t i = 0; i < num_bytes; i++) - out_bytes.push_back(buff[i]); - - return out_bytes; - } - -private: - static const size_t max_i2c_data_bytes = 64; - uhd::usrp::fx2_ctrl::sptr _fx2_ctrl; -}; - -/*********************************************************************** - * USRP-E100 interface implementation - **********************************************************************/ -class b100_iface_impl : public b100_iface{ -public: - /******************************************************************* - * Structors - ******************************************************************/ - b100_iface_impl(uhd::usrp::fx2_ctrl::sptr fx2_ctrl, - b100_ctrl::sptr fpga_ctrl) : - _fx2_i2c_iface(fx2_ctrl), - _fx2_ctrl(fx2_ctrl), - _fpga_ctrl(fpga_ctrl) - { - this->check_fw_compat(); - if (fpga_ctrl.get() != NULL){ - enable_gpif(1); - i2c_init(); - this->check_fpga_compat(); - } - mb_eeprom = mboard_eeprom_t(get_fx2_i2c_iface(), mboard_eeprom_t::MAP_B000); - } - - void check_fw_compat(void){ - unsigned char data[4]; //useless data buffer - const boost::uint16_t fw_compat_num = _fx2_ctrl->usrp_control_read( - VRQ_FW_COMPAT, 0, 0, data, sizeof(data) - ); - if (fw_compat_num != USRP_B_FW_COMPAT_NUM){ - throw uhd::runtime_error(str(boost::format( - "Expected firmware compatibility number 0x%x, but got 0x%x:\n" - "The firmware build is not compatible with the host code build." - ) % USRP_B_FW_COMPAT_NUM % fw_compat_num)); - } - } - - void check_fpga_compat(void){ - const boost::uint16_t fpga_compat_num = this->peek16(B100_REG_MISC_COMPAT); - if (fpga_compat_num != USRP_B_FPGA_COMPAT_NUM){ - throw uhd::runtime_error(str(boost::format( - "Expected FPGA compatibility number 0x%x, but got 0x%x:\n" - "The FPGA build is not compatible with the host code build." - ) % USRP_B_FPGA_COMPAT_NUM % fpga_compat_num)); - } - } - - ~b100_iface_impl(void) - { - /* NOP */ - } - - /******************************************************************* - * Peek and Poke - ******************************************************************/ - - void poke(boost::uint32_t addr, const ctrl_data_t &data) { - boost::mutex::scoped_lock lock(_ctrl_mutex); - _fpga_ctrl->write(addr, data); - } - - ctrl_data_t peek(boost::uint32_t addr, size_t len) { - boost::mutex::scoped_lock lock(_ctrl_mutex); - return _fpga_ctrl->read(addr, len); - } - - void poke16(boost::uint32_t addr, boost::uint16_t value) - { - ctrl_data_t words(1); - words[0] = value; - poke(addr, words); - } - - void poke32(boost::uint32_t addr, boost::uint32_t value) - { - //just a subset of poke() to maintain compatibility - ctrl_data_t words(2); - words[0] = value & 0x0000FFFF; - words[1] = value >> 16; - poke(addr, words); - } - - boost::uint32_t peek32(boost::uint32_t addr) - { - ctrl_data_t words = peek(addr, 2); - return boost::uint32_t((boost::uint32_t(words[1]) << 16) | words[0]); - } - - boost::uint16_t peek16(boost::uint32_t addr) - { - ctrl_data_t words = peek(addr, 1); - return boost::uint16_t(words[0]); - } - - /******************************************************************* - * I2C - ******************************************************************/ - static const boost::uint32_t i2c_datarate = 400000; - static const boost::uint32_t wishbone_clk = 64000000; //FIXME should go somewhere else - - void i2c_init(void) { - //init I2C FPGA interface. - poke16(B100_REG_I2C_CTRL, 0x0000); - //set prescalers to operate at 400kHz: WB_CLK is 64MHz... - boost::uint16_t prescaler = wishbone_clk / (i2c_datarate*5) - 1; - poke16(B100_REG_I2C_PRESCALER_LO, prescaler & 0xFF); - poke16(B100_REG_I2C_PRESCALER_HI, (prescaler >> 8) & 0xFF); - poke16(B100_REG_I2C_CTRL, I2C_CTRL_EN); //enable I2C core - } - - static const size_t max_i2c_data_bytes = 64; - - void i2c_wait_for_xfer(void) - { - while(this->peek16(B100_REG_I2C_CMD_STATUS) & I2C_ST_TIP) - boost::this_thread::sleep(boost::posix_time::milliseconds(10)); - } - - bool wait_chk_ack(void) { - i2c_wait_for_xfer(); - return (this->peek16(B100_REG_I2C_CMD_STATUS) & I2C_ST_RXACK) == 0; - } - - void write_i2c(boost::uint8_t addr, const byte_vector_t &bytes) - { - poke16(B100_REG_I2C_DATA, (addr << 1) | 0); //addr and read bit (0) - poke16(B100_REG_I2C_CMD_STATUS, I2C_CMD_WR | I2C_CMD_START | (bytes.size() == 0 ? I2C_CMD_STOP : 0)); - - //wait for previous transfer to complete - if(!wait_chk_ack()) { - poke16(B100_REG_I2C_CMD_STATUS, I2C_CMD_STOP); - return; - } - - for(size_t i = 0; i < bytes.size(); i++) { - poke16(B100_REG_I2C_DATA, bytes[i]); - poke16(B100_REG_I2C_CMD_STATUS, I2C_CMD_WR | ((i == (bytes.size() - 1)) ? I2C_CMD_STOP : 0)); - if(!wait_chk_ack()) { - poke16(B100_REG_I2C_CMD_STATUS, I2C_CMD_STOP); - return; - } - } - } - - byte_vector_t read_i2c(boost::uint8_t addr, size_t num_bytes) - { - byte_vector_t bytes; - if(num_bytes == 0) return bytes; - - while (peek16(B100_REG_I2C_CMD_STATUS) & I2C_ST_BUSY); - - poke16(B100_REG_I2C_DATA, (addr << 1) | 1); //addr and read bit (1) - poke16(B100_REG_I2C_CMD_STATUS, I2C_CMD_WR | I2C_CMD_START); - //wait for previous transfer to complete - if(!wait_chk_ack()) { - poke16(B100_REG_I2C_CMD_STATUS, I2C_CMD_STOP); - } - - for(; num_bytes > 0; num_bytes--) { - poke16(B100_REG_I2C_CMD_STATUS, I2C_CMD_RD | ((num_bytes == 1) ? (I2C_CMD_STOP | I2C_CMD_NACK) : 0)); - i2c_wait_for_xfer(); - boost::uint8_t readback = peek16(B100_REG_I2C_DATA) & 0xFF; - bytes.push_back(readback); - } - return bytes; - } - - i2c_iface &get_fx2_i2c_iface(void){ - return _fx2_i2c_iface; - } - - /******************************************************************* - * SPI interface - * Eventually this will be replaced with a control-channel system - * to let the firmware do the actual write/readback cycles. - * This keeps the bandwidth on the control channel down. - ******************************************************************/ - - void spi_wait(void) { - while(peek32(B100_REG_SPI_CTRL) & SPI_CTRL_GO_BSY); - } - - boost::uint32_t transact_spi(int which_slave, - const spi_config_t &config, - boost::uint32_t bits, - size_t num_bits, - bool readback) - { - UHD_ASSERT_THROW((num_bits <= 32) && !(num_bits % 8)); - - int edge_flags = ((config.miso_edge==spi_config_t::EDGE_FALL) ? SPI_CTRL_RXNEG : 0) | - ((config.mosi_edge==spi_config_t::EDGE_FALL) ? 0 : SPI_CTRL_TXNEG) - ; - - boost::uint16_t ctrl = SPI_CTRL_ASS | (SPI_CTRL_CHAR_LEN_MASK & num_bits) | edge_flags; - - poke16(B100_REG_SPI_DIV, 0x0001); // = fpga_clk / 4 - poke32(B100_REG_SPI_SS, which_slave & 0xFFFF); - poke32(B100_REG_SPI_TXRX0, bits); - poke16(B100_REG_SPI_CTRL, ctrl); - - poke16(B100_REG_SPI_CTRL, ctrl | SPI_CTRL_GO_BSY); - if(readback) { - spi_wait(); - return peek32(B100_REG_SPI_TXRX0); - } - else { - return 0; - } - } - - void reset_gpif(boost::uint16_t ep) { - _fx2_ctrl->usrp_control_write(VRQ_RESET_GPIF, ep, ep, 0, 0); - } - - void enable_gpif(bool en) { - _fx2_ctrl->usrp_control_write(VRQ_ENABLE_GPIF, en ? 1 : 0, 0, 0, 0); - } - - void clear_fpga_fifo(void) { - _fx2_ctrl->usrp_control_write(VRQ_CLEAR_FPGA_FIFO, 0, 0, 0, 0); - } - - void write_uart(boost::uint8_t, const std::string &) { - throw uhd::not_implemented_error("Unhandled command write_uart()"); - } - - std::string read_uart(boost::uint8_t) { - throw uhd::not_implemented_error("Unhandled command read_uart()"); - } - -private: - b100_i2c_fx2_iface _fx2_i2c_iface; - uhd::usrp::fx2_ctrl::sptr _fx2_ctrl; - b100_ctrl::sptr _fpga_ctrl; - boost::mutex _ctrl_mutex; -}; - -/*********************************************************************** - * Public Make Function - **********************************************************************/ -b100_iface::sptr b100_iface::make(uhd::usrp::fx2_ctrl::sptr fx2_ctrl, - b100_ctrl::sptr fpga_ctrl) -{ - return b100_iface::sptr(new b100_iface_impl(fx2_ctrl, fpga_ctrl)); -} diff --git a/host/lib/usrp/usrp_b100/b100_iface.hpp b/host/lib/usrp/usrp_b100/b100_iface.hpp deleted file mode 100644 index 57ed6a45c..000000000 --- a/host/lib/usrp/usrp_b100/b100_iface.hpp +++ /dev/null @@ -1,73 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#ifndef INCLUDED_B100_IFACE_HPP -#define INCLUDED_B100_IFACE_HPP - -#include -#include -#include -#include -#include -#include "../fx2/fx2_ctrl.hpp" -#include "b100_ctrl.hpp" - -/*! - * The usrp1 interface class: - * Provides a set of functions to implementation layer. - * Including spi, peek, poke, control... - */ -class b100_iface : boost::noncopyable, public uhd::usrp::mboard_iface{ -public: - typedef boost::shared_ptr sptr; - - /*! - * Make a new b100 interface with the control transport. - * \param fx2_ctrl the usrp control object - * \param fpga_ctrl the FPGA interface control object - * \return a new usrp1 interface object - */ - static sptr make(uhd::usrp::fx2_ctrl::sptr fx2_ctrl, - b100_ctrl::sptr fpga_ctrl = b100_ctrl::sptr() - ); - - /*! - * Reset the GPIF interface on the FX2 - * \param which endpoint to reset - * \return - */ - virtual void reset_gpif(boost::uint16_t ep) = 0; - - /*! - * Clear the GPIF FIFOs on the FPGA - * \return - */ - virtual void clear_fpga_fifo(void) = 0; - - /*! - * Enable/disable the GPIF interfaces on the FX2 - * \return - */ - virtual void enable_gpif(bool en) = 0; - - //! Get access to the FX2 I2C interface - virtual uhd::i2c_iface &get_fx2_i2c_iface(void) = 0; - - uhd::usrp::mboard_eeprom_t mb_eeprom; -}; - -#endif /* INCLUDED_USRP1_IFACE_HPP */ diff --git a/host/lib/usrp/usrp_b100/b100_impl.cpp b/host/lib/usrp/usrp_b100/b100_impl.cpp deleted file mode 100644 index 772da8f42..000000000 --- a/host/lib/usrp/usrp_b100/b100_impl.cpp +++ /dev/null @@ -1,277 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "b100_impl.hpp" -#include "b100_ctrl.hpp" -#include "fpga_regs_standard.h" -#include "usrp_spi_defs.h" -#include -#include "ctrl_packet.hpp" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "b100_regs.hpp" - -using namespace uhd; -using namespace uhd::usrp; -using namespace uhd::transport; - -const boost::uint16_t B100_VENDOR_ID = 0x2500; -const boost::uint16_t B100_PRODUCT_ID = 0x0001; -const boost::uint16_t FX2_VENDOR_ID = 0x04b4; -const boost::uint16_t FX2_PRODUCT_ID = 0x8613; - -/*********************************************************************** - * Discovery - **********************************************************************/ -static device_addrs_t b100_find(const device_addr_t &hint) -{ - device_addrs_t b100_addrs; - - //return an empty list of addresses when type is set to non-b100 - if (hint.has_key("type") and hint["type"] != "b100") return b100_addrs; - - //extract the firmware path for the b100 - std::string b100_fw_image; - try{ - b100_fw_image = find_image_path( - hint.has_key("fw")? hint["fw"] : "usrp_b100_fw.ihx" - ); - } - catch(...){ - UHD_MSG(warning) << boost::format( - "Could not locate B100 firmware.\n" - "Please install the images package.\n" - ); - return b100_addrs; - } - - boost::uint16_t vid = hint.has_key("uninit") ? FX2_VENDOR_ID : B100_VENDOR_ID; - boost::uint16_t pid = hint.has_key("uninit") ? FX2_PRODUCT_ID : B100_PRODUCT_ID; - - // Important note: - // The get device list calls are nested inside the for loop. - // This allows the usb guts to decontruct when not in use, - // so that re-enumeration after fw load can occur successfully. - // This requirement is a courtesy of libusb1.0 on windows. - - //find the usrps and load firmware - BOOST_FOREACH(usb_device_handle::sptr handle, usb_device_handle::get_device_list(vid, pid)) { - try { - fx2_ctrl::make(usb_control::make(handle))->usrp_load_firmware(b100_fw_image); - } catch (...) { - UHD_MSG(status) << "Interface claimed, ignoring device" << std::endl; - } - } - - //get descriptors again with serial number, but using the initialized VID/PID now since we have firmware - vid = B100_VENDOR_ID; - pid = B100_PRODUCT_ID; - - BOOST_FOREACH(usb_device_handle::sptr handle, usb_device_handle::get_device_list(vid, pid)) { - device_addr_t new_addr; - new_addr["type"] = "b100"; - - //Attempt to read the name from the EEPROM and perform filtering. - //This operation can throw due to compatibility mismatch. - try{ - usb_control::sptr control = usb_control::make(handle); - b100_iface::sptr iface = b100_iface::make(fx2_ctrl::make(control)); - new_addr["name"] = iface->mb_eeprom["name"]; - new_addr["serial"] = handle->get_serial(); - } - catch(const uhd::exception &){ - //set these values as empty string so the device may still be found - //and the filter's below can still operate on the discovered device - new_addr["name"] = ""; - new_addr["serial"] = ""; - } - - //this is a found b100 when the hint serial and name match or blank - if ( - (not hint.has_key("name") or hint["name"] == new_addr["name"]) and - (not hint.has_key("serial") or hint["serial"] == new_addr["serial"]) - ){ - b100_addrs.push_back(new_addr); - } - } - - return b100_addrs; -} - -/*********************************************************************** - * Make - **********************************************************************/ -static device::sptr b100_make(const device_addr_t &device_addr){ - - //extract the FPGA path for the B100 - std::string b100_fpga_image = find_image_path( - device_addr.has_key("fpga")? device_addr["fpga"] : "usrp_b100_fpga.bin" - ); - - //try to match the given device address with something on the USB bus - std::vector device_list = - usb_device_handle::get_device_list(B100_VENDOR_ID, B100_PRODUCT_ID); - - //locate the matching handle in the device list - usb_device_handle::sptr handle; - BOOST_FOREACH(usb_device_handle::sptr dev_handle, device_list) { - if (dev_handle->get_serial() == device_addr["serial"]){ - handle = dev_handle; - break; - } - } - UHD_ASSERT_THROW(handle.get() != NULL); //better be found - - //create control objects and a data transport - usb_control::sptr fx2_transport = usb_control::make(handle); - fx2_ctrl::sptr fx2_ctrl = fx2_ctrl::make(fx2_transport); - fx2_ctrl->usrp_load_fpga(b100_fpga_image); - - device_addr_t data_xport_args; - data_xport_args["recv_frame_size"] = device_addr.get("recv_frame_size", "16384"); - data_xport_args["num_recv_frames"] = device_addr.get("num_recv_frames", "16"); - data_xport_args["send_frame_size"] = device_addr.get("send_frame_size", "16384"); - data_xport_args["num_send_frames"] = device_addr.get("num_send_frames", "16"); - - usb_zero_copy::sptr data_transport = usb_zero_copy::make_wrapper( - usb_zero_copy::make( - handle, // identifier - 6, // IN endpoint - 2, // OUT endpoint - data_xport_args // param hints - ) - ); - - //create the control transport - device_addr_t ctrl_xport_args; - ctrl_xport_args["recv_frame_size"] = boost::lexical_cast(CTRL_PACKET_LENGTH); - ctrl_xport_args["num_recv_frames"] = "16"; - ctrl_xport_args["send_frame_size"] = boost::lexical_cast(CTRL_PACKET_LENGTH); - ctrl_xport_args["num_send_frames"] = "4"; - - usb_zero_copy::sptr ctrl_transport = usb_zero_copy::make( - handle, - 8, - 4, - ctrl_xport_args - ); - - const double master_clock_rate = device_addr.cast("master_clock_rate", 64e6); - - - //create the b100 implementation guts - return device::sptr(new b100_impl(data_transport, ctrl_transport, fx2_ctrl, master_clock_rate)); -} - -UHD_STATIC_BLOCK(register_b100_device){ - device::register_device(&b100_find, &b100_make); -} - -/*********************************************************************** - * Structors - **********************************************************************/ -b100_impl::b100_impl(uhd::transport::usb_zero_copy::sptr data_transport, - uhd::transport::usb_zero_copy::sptr ctrl_transport, - uhd::usrp::fx2_ctrl::sptr fx2_ctrl, - const double master_clock_rate) - : _data_transport(data_transport), _fx2_ctrl(fx2_ctrl) -{ - //this is the handler object for FPGA control packets - _fpga_ctrl = b100_ctrl::make(ctrl_transport); - - _iface = b100_iface::make(_fx2_ctrl, _fpga_ctrl); - - //create clock interface - _clock_ctrl = b100_clock_ctrl::make(_iface, master_clock_rate); - - //create codec interface - _codec_ctrl = b100_codec_ctrl::make(_iface); - - //initialize the codecs - codec_init(); - - //initialize the mboard - mboard_init(); - - //initialize the dboards - dboard_init(); - - //initialize the dsps - rx_ddc_init(); - - //initialize the dsps - tx_duc_init(); - - //init the subdev specs - this->mboard_set(MBOARD_PROP_RX_SUBDEV_SPEC, subdev_spec_t()); - this->mboard_set(MBOARD_PROP_TX_SUBDEV_SPEC, subdev_spec_t()); - - //initialize the send/recv buffs - io_init(); -} - -b100_impl::~b100_impl(void){ - /* NOP */ -} - -bool b100_impl::recv_async_msg(uhd::async_metadata_t &md, double timeout){ - return _fpga_ctrl->recv_async_msg(md, timeout); -} - -/*********************************************************************** - * Device Get - **********************************************************************/ -void b100_impl::get(const wax::obj &key_, wax::obj &val) -{ - named_prop_t key = named_prop_t::extract(key_); - - //handle the get request conditioned on the key - switch(key.as()){ - case DEVICE_PROP_NAME: - val = std::string("USRP-B100 device"); - return; - - case DEVICE_PROP_MBOARD: - UHD_ASSERT_THROW(key.name == ""); - val = _mboard_proxy->get_link(); - return; - - case DEVICE_PROP_MBOARD_NAMES: - val = prop_names_t(1, ""); //vector of size 1 with empty string - return; - - default: UHD_THROW_PROP_GET_ERROR(); - } -} - -/*********************************************************************** - * Device Set - **********************************************************************/ -void b100_impl::set(const wax::obj &, const wax::obj &) -{ - UHD_THROW_PROP_SET_ERROR(); -} diff --git a/host/lib/usrp/usrp_b100/b100_impl.hpp b/host/lib/usrp/usrp_b100/b100_impl.hpp deleted file mode 100644 index daec70bca..000000000 --- a/host/lib/usrp/usrp_b100/b100_impl.hpp +++ /dev/null @@ -1,204 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "b100_iface.hpp" -#include "b100_ctrl.hpp" -#include "clock_ctrl.hpp" -#include "codec_ctrl.hpp" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifndef INCLUDED_B100_IMPL_HPP -#define INCLUDED_B100_IMPL_HPP - -/*! - * Make a b100 dboard interface. - * \param iface the b100 interface object - * \param clock the clock control interface - * \param codec the codec control interface - * \return a sptr to a new dboard interface - */ -uhd::usrp::dboard_iface::sptr make_b100_dboard_iface( - b100_iface::sptr iface, - b100_clock_ctrl::sptr clock, - b100_codec_ctrl::sptr codec -); - -/*! - * Simple wax obj proxy class: - * Provides a wax obj interface for a set and a get function. - * This allows us to create nested properties structures - * while maintaining flattened code within the implementation. - */ -class wax_obj_proxy : public wax::obj { -public: - typedef boost::function get_t; - typedef boost::function set_t; - typedef boost::shared_ptr sptr; - - static sptr make(const get_t &get, const set_t &set){ - return sptr(new wax_obj_proxy(get, set)); - } - -private: - get_t _get; set_t _set; - wax_obj_proxy(const get_t &get, const set_t &set): _get(get), _set(set) {}; - void get(const wax::obj &key, wax::obj &val) {return _get(key, val);} - void set(const wax::obj &key, const wax::obj &val) {return _set(key, val);} -}; - -/*! - * USRP1 implementation guts: - * The implementation details are encapsulated here. - * Handles properties on the mboard, dboard, dsps... - */ -class b100_impl : public uhd::device { -public: - //structors - b100_impl(uhd::transport::usb_zero_copy::sptr data_transport, - uhd::transport::usb_zero_copy::sptr ctrl_transport, - uhd::usrp::fx2_ctrl::sptr fx2_ctrl, - double master_clock_rate); - - ~b100_impl(void); - - //the io interface - size_t send(const send_buffs_type &, - size_t, - const uhd::tx_metadata_t &, - const uhd::io_type_t &, - send_mode_t, double); - - size_t recv(const recv_buffs_type &, - size_t, uhd::rx_metadata_t &, - const uhd::io_type_t &, - recv_mode_t, double); - - size_t get_max_send_samps_per_packet(void) const; - - size_t get_max_recv_samps_per_packet(void) const; - - bool recv_async_msg(uhd::async_metadata_t &, double); - -private: - //clock control - b100_clock_ctrl::sptr _clock_ctrl; - - //interface to ioctls and file descriptor - b100_iface::sptr _iface; - - //handle io stuff - uhd::transport::zero_copy_if::sptr _data_transport; - UHD_PIMPL_DECL(io_impl) _io_impl; - void update_transport_channel_mapping(void); - void io_init(void); - void issue_stream_cmd(const uhd::stream_cmd_t &stream_cmd); - void handle_overrun(size_t); - - //otw types - uhd::otw_type_t _recv_otw_type; - uhd::otw_type_t _send_otw_type; - - //configuration shadows - uhd::clock_config_t _clock_config; - uhd::usrp::subdev_spec_t _rx_subdev_spec, _tx_subdev_spec; - - //ad9862 codec control interface - b100_codec_ctrl::sptr _codec_ctrl; - - //codec properties interfaces - void codec_init(void); - void rx_codec_get(const wax::obj &, wax::obj &); - void rx_codec_set(const wax::obj &, const wax::obj &); - void tx_codec_get(const wax::obj &, wax::obj &); - void tx_codec_set(const wax::obj &, const wax::obj &); - wax_obj_proxy::sptr _rx_codec_proxy, _tx_codec_proxy; - - //device functions and settings - void get(const wax::obj &, wax::obj &); - void set(const wax::obj &, const wax::obj &); - - //mboard functions and settings - void mboard_init(void); - void mboard_get(const wax::obj &, wax::obj &); - void mboard_set(const wax::obj &, const wax::obj &); - void update_clock_config(void); - wax_obj_proxy::sptr _mboard_proxy; - - /*! - * Make a usrp1 dboard interface. - * \param iface the usrp1 interface object - * \param clock the clock control interface - * \param codec the codec control interface - * \param dboard_slot the slot identifier - * \param rx_dboard_id the db id for the rx board (used for evil dbsrx purposes) - * \return a sptr to a new dboard interface - */ - static uhd::usrp::dboard_iface::sptr make_dboard_iface( - b100_iface::sptr iface, - b100_clock_ctrl::sptr clock, - b100_codec_ctrl::sptr codec, - const uhd::usrp::dboard_id_t &rx_dboard_id - ); - - //xx dboard functions and settings - void dboard_init(void); - uhd::usrp::dboard_manager::sptr _dboard_manager; - uhd::usrp::dboard_iface::sptr _dboard_iface; - - //rx dboard functions and settings - uhd::usrp::dboard_eeprom_t _rx_db_eeprom; - void rx_dboard_get(const wax::obj &, wax::obj &); - void rx_dboard_set(const wax::obj &, const wax::obj &); - wax_obj_proxy::sptr _rx_dboard_proxy; - - //tx dboard functions and settings - uhd::usrp::dboard_eeprom_t _tx_db_eeprom, _gdb_eeprom; - void tx_dboard_get(const wax::obj &, wax::obj &); - void tx_dboard_set(const wax::obj &, const wax::obj &); - wax_obj_proxy::sptr _tx_dboard_proxy; - - //rx ddc functions and settings - void rx_ddc_init(void); - void rx_ddc_get(const wax::obj &, wax::obj &); - void rx_ddc_set(const wax::obj &, const wax::obj &); - double _ddc_freq; size_t _ddc_decim; - wax_obj_proxy::sptr _rx_ddc_proxy; - - //tx duc functions and settings - void tx_duc_init(void); - void tx_duc_get(const wax::obj &, wax::obj &); - void tx_duc_set(const wax::obj &, const wax::obj &); - double _duc_freq; size_t _duc_interp; - wax_obj_proxy::sptr _tx_duc_proxy; - - //transports - b100_ctrl::sptr _fpga_ctrl; - uhd::usrp::fx2_ctrl::sptr _fx2_ctrl; - -}; - -#endif /* INCLUDED_b100_IMPL_HPP */ diff --git a/host/lib/usrp/usrp_b100/b100_regs.hpp b/host/lib/usrp/usrp_b100/b100_regs.hpp deleted file mode 100644 index 010df283e..000000000 --- a/host/lib/usrp/usrp_b100/b100_regs.hpp +++ /dev/null @@ -1,264 +0,0 @@ - - -//////////////////////////////////////////////////////////////// -// -// Memory map for wishbone bus -// -//////////////////////////////////////////////////////////////// - -// All addresses are byte addresses. All accesses are word (16-bit) accesses. -// This means that address bit 0 is usually 0. -// There are 11 bits of address for the control. - -#ifndef __B100_REGS_H -#define __B100_REGS_H - -///////////////////////////////////////////////////// -// Slave pointers - -#define B100_REG_SLAVE(n) ((n)<<7) -#define B100_REG_SR_ADDR(n) ((B100_REG_SETTINGS_BASE) + (4*(n))) - -///////////////////////////////////////////////////// -// Slave 0 -- Misc Regs - -#define B100_REG_MISC_BASE B100_REG_SLAVE(0) - -#define B100_REG_MISC_LED B100_REG_MISC_BASE + 0 -#define B100_REG_MISC_SW B100_REG_MISC_BASE + 2 -#define B100_REG_MISC_CGEN_CTRL B100_REG_MISC_BASE + 4 -#define B100_REG_MISC_CGEN_ST B100_REG_MISC_BASE + 6 -#define B100_REG_MISC_TEST B100_REG_MISC_BASE + 8 -#define B100_REG_MISC_RX_LEN B100_REG_MISC_BASE + 10 -#define B100_REG_MISC_TX_LEN B100_REG_MISC_BASE + 12 -#define B100_REG_MISC_XFER_RATE B100_REG_MISC_BASE + 14 -#define B100_REG_MISC_COMPAT B100_REG_MISC_BASE + 16 - -///////////////////////////////////////////////////// -// Slave 1 -- UART -// CLKDIV is 16 bits, others are only 8 - -#define B100_REG_UART_BASE B100_REG_SLAVE(1) - -#define B100_REG_UART_CLKDIV B100_REG_UART_BASE + 0 -#define B100_REG_UART_TXLEVEL B100_REG_UART_BASE + 2 -#define B100_REG_UART_RXLEVEL B100_REG_UART_BASE + 4 -#define B100_REG_UART_TXCHAR B100_REG_UART_BASE + 6 -#define B100_REG_UART_RXCHAR B100_REG_UART_BASE + 8 - -///////////////////////////////////////////////////// -// Slave 2 -- SPI Core -//these are 32-bit registers mapped onto the 16-bit Wishbone bus. -//Using peek32/poke32 should allow transparent use of these registers. -#define B100_REG_SPI_BASE B100_REG_SLAVE(2) -#define B100_REG_SPI_TXRX0 B100_REG_SPI_BASE + 0 -#define B100_REG_SPI_TXRX1 B100_REG_SPI_BASE + 4 -#define B100_REG_SPI_TXRX2 B100_REG_SPI_BASE + 8 -#define B100_REG_SPI_TXRX3 B100_REG_SPI_BASE + 12 -#define B100_REG_SPI_CTRL B100_REG_SPI_BASE + 16 -#define B100_REG_SPI_DIV B100_REG_SPI_BASE + 20 -#define B100_REG_SPI_SS B100_REG_SPI_BASE + 24 - -//spi slave constants -#define B100_SPI_SS_AD9862 (1 << 2) -#define B100_SPI_SS_TX_DB (1 << 1) -#define B100_SPI_SS_RX_DB (1 << 0) - -//spi ctrl register bit definitions -#define SPI_CTRL_ASS (1<<13) -#define SPI_CTRL_IE (1<<12) -#define SPI_CTRL_LSB (1<<11) -#define SPI_CTRL_TXNEG (1<<10) //mosi edge, push on falling edge when 1 -#define SPI_CTRL_RXNEG (1<< 9) //miso edge, latch on falling edge when 1 -#define SPI_CTRL_GO_BSY (1<< 8) -#define SPI_CTRL_CHAR_LEN_MASK 0x7F - -//////////////////////////////////////////////// -// Slave 3 -- I2C Core - -#define B100_REG_I2C_BASE B100_REG_SLAVE(3) -#define B100_REG_I2C_PRESCALER_LO B100_REG_I2C_BASE + 0 -#define B100_REG_I2C_PRESCALER_HI B100_REG_I2C_BASE + 2 -#define B100_REG_I2C_CTRL B100_REG_I2C_BASE + 4 -#define B100_REG_I2C_DATA B100_REG_I2C_BASE + 6 -#define B100_REG_I2C_CMD_STATUS B100_REG_I2C_BASE + 8 - -//and while we're here... - -// -// STA, STO, RD, WR, and IACK bits are cleared automatically -// - -#define I2C_CTRL_EN (1 << 7) // core enable -#define I2C_CTRL_IE (1 << 6) // interrupt enable - -#define I2C_CMD_START (1 << 7) // generate (repeated) start condition -#define I2C_CMD_STOP (1 << 6) // generate stop condition -#define I2C_CMD_RD (1 << 5) // read from slave -#define I2C_CMD_WR (1 << 4) // write to slave -#define I2C_CMD_NACK (1 << 3) // when a rcvr, send ACK (ACK=0) or NACK (ACK=1) -#define I2C_CMD_RSVD_2 (1 << 2) // reserved -#define I2C_CMD_RSVD_1 (1 << 1) // reserved -#define I2C_CMD_IACK (1 << 0) // set to clear pending interrupt - -#define I2C_ST_RXACK (1 << 7) // Received acknowledgement from slave (1 = NAK, 0 = ACK) -#define I2C_ST_BUSY (1 << 6) // 1 after START signal detected; 0 after STOP signal detected -#define I2C_ST_AL (1 << 5) // Arbitration lost. 1 when core lost arbitration -#define I2C_ST_RSVD_4 (1 << 4) // reserved -#define I2C_ST_RSVD_3 (1 << 3) // reserved -#define I2C_ST_RSVD_2 (1 << 2) // reserved -#define I2C_ST_TIP (1 << 1) // Transfer-in-progress -#define I2C_ST_IP (1 << 0) // Interrupt pending - -//////////////////////////////////////////////// -// Slave 4 -- GPIO - -#define B100_REG_GPIO_BASE B100_REG_SLAVE(4) - -#define B100_REG_GPIO_RX_IO B100_REG_GPIO_BASE + 0 -#define B100_REG_GPIO_TX_IO B100_REG_GPIO_BASE + 2 -#define B100_REG_GPIO_RX_DDR B100_REG_GPIO_BASE + 4 -#define B100_REG_GPIO_TX_DDR B100_REG_GPIO_BASE + 6 -#define B100_REG_GPIO_RX_SEL B100_REG_GPIO_BASE + 8 -#define B100_REG_GPIO_TX_SEL B100_REG_GPIO_BASE + 10 -#define B100_REG_GPIO_RX_DBG B100_REG_GPIO_BASE + 12 -#define B100_REG_GPIO_TX_DBG B100_REG_GPIO_BASE + 14 - -//possible bit values for sel when dbg is 0: -#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg -#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic - -//possible bit values for sel when dbg is 1: -#define GPIO_SEL_DEBUG_0 0 // if pin is an output, debug lines from FPGA fabric -#define GPIO_SEL_DEBUG_1 1 // if pin is an output, debug lines from FPGA fabric - -/////////////////////////////////////////////////// -// Slave 6 -- ATR Controller -// 16 regs - -#define B100_REG_ATR_BASE B100_REG_SLAVE(6) - -#define B100_REG_ATR_IDLE_RXSIDE B100_REG_ATR_BASE + 0 -#define B100_REG_ATR_IDLE_TXSIDE B100_REG_ATR_BASE + 2 -#define B100_REG_ATR_INTX_RXSIDE B100_REG_ATR_BASE + 4 -#define B100_REG_ATR_INTX_TXSIDE B100_REG_ATR_BASE + 6 -#define B100_REG_ATR_INRX_RXSIDE B100_REG_ATR_BASE + 8 -#define B100_REG_ATR_INRX_TXSIDE B100_REG_ATR_BASE + 10 -#define B100_REG_ATR_FULL_RXSIDE B100_REG_ATR_BASE + 12 -#define B100_REG_ATR_FULL_TXSIDE B100_REG_ATR_BASE + 14 - -/////////////////////////////////////////////////// -// Slave 7 -- Readback Mux 32 - -#define B100_REG_RB_MUX_32_BASE B100_REG_SLAVE(7) - -#define B100_REG_RB_TIME_NOW_SECS B100_REG_RB_MUX_32_BASE + 0 -#define B100_REG_RB_TIME_NOW_TICKS B100_REG_RB_MUX_32_BASE + 4 -#define B100_REG_RB_TIME_PPS_SECS B100_REG_RB_MUX_32_BASE + 8 -#define B100_REG_RB_TIME_PPS_TICKS B100_REG_RB_MUX_32_BASE + 12 -#define B100_REG_RB_MISC_TEST32 B100_REG_RB_MUX_32_BASE + 16 - -//////////////////////////////////////////////////// -// Slaves 8 & 9 -- Settings Bus -// -// Output-only, no readback, 64 registers total -// Each register must be written 32 bits at a time -// First the address xxx_xx00 and then xxx_xx10 - -#define B100_REG_SETTINGS_BASE_ADDR(n) (B100_REG_SLAVE(8) + (4*(n))) - -#define B100_REG_SR_MISC_TEST32 B100_REG_SETTINGS_BASE_ADDR(52) - -///////////////////////////////////////////////// -// DSP RX Regs -//////////////////////////////////////////////// -#define B100_REG_DSP_RX_ADDR(n) (B100_REG_SETTINGS_BASE_ADDR(16) + (4*(n))) -#define B100_REG_DSP_RX_FREQ B100_REG_DSP_RX_ADDR(0) -#define B100_REG_DSP_RX_SCALE_IQ B100_REG_DSP_RX_ADDR(1) // {scale_i,scale_q} -#define B100_REG_DSP_RX_DECIM_RATE B100_REG_DSP_RX_ADDR(2) // hb and decim rate -#define B100_REG_DSP_RX_DCOFFSET_I B100_REG_DSP_RX_ADDR(3) // Bit 31 high sets fixed offset mode, using lower 14 bits, // otherwise it is automatic -#define B100_REG_DSP_RX_DCOFFSET_Q B100_REG_DSP_RX_ADDR(4) // Bit 31 high sets fixed offset mode, using lower 14 bits -#define B100_REG_DSP_RX_MUX B100_REG_DSP_RX_ADDR(5) - -/////////////////////////////////////////////////// -// VITA RX CTRL regs -/////////////////////////////////////////////////// -// The following 3 are logically a single command register. -// They are clocked into the underlying fifo when time_ticks is written. -#define B100_REG_CTRL_RX_ADDR(n) (B100_REG_SETTINGS_BASE_ADDR(0) + (4*(n))) -#define B100_REG_CTRL_RX_STREAM_CMD B100_REG_CTRL_RX_ADDR(0) // {now, chain, num_samples(30) -#define B100_REG_CTRL_RX_TIME_SECS B100_REG_CTRL_RX_ADDR(1) -#define B100_REG_CTRL_RX_TIME_TICKS B100_REG_CTRL_RX_ADDR(2) -#define B100_REG_CTRL_RX_CLEAR_OVERRUN B100_REG_CTRL_RX_ADDR(3) // write anything to clear overrun -#define B100_REG_CTRL_RX_VRT_HEADER B100_REG_CTRL_RX_ADDR(4) // word 0 of packet. FPGA fills in packet counter -#define B100_REG_CTRL_RX_VRT_STREAM_ID B100_REG_CTRL_RX_ADDR(5) // word 1 of packet. -#define B100_REG_CTRL_RX_VRT_TRAILER B100_REG_CTRL_RX_ADDR(6) -#define B100_REG_CTRL_RX_NSAMPS_PER_PKT B100_REG_CTRL_RX_ADDR(7) -#define B100_REG_CTRL_RX_NCHANNELS B100_REG_CTRL_RX_ADDR(8) // 1 in basic case, up to 4 for vector sources - -///////////////////////////////////////////////// -// DSP TX Regs -//////////////////////////////////////////////// -#define B100_REG_DSP_TX_ADDR(n) (B100_REG_SETTINGS_BASE_ADDR(32) + (4*(n))) -#define B100_REG_DSP_TX_FREQ B100_REG_DSP_TX_ADDR(0) -#define B100_REG_DSP_TX_SCALE_IQ B100_REG_DSP_TX_ADDR(1) // {scale_i,scale_q} -#define B100_REG_DSP_TX_INTERP_RATE B100_REG_DSP_TX_ADDR(2) -#define B100_REG_DSP_TX_UNUSED B100_REG_DSP_TX_ADDR(3) -#define B100_REG_DSP_TX_MUX B100_REG_DSP_TX_ADDR(4) - -///////////////////////////////////////////////// -// VITA TX CTRL regs -//////////////////////////////////////////////// -#define B100_REG_CTRL_TX_ADDR(n) (B100_REG_SETTINGS_BASE_ADDR(24) + (4*(n))) -#define B100_REG_CTRL_TX_NCHANNELS B100_REG_CTRL_TX_ADDR(0) -#define B100_REG_CTRL_TX_CLEAR_UNDERRUN B100_REG_CTRL_TX_ADDR(1) -#define B100_REG_CTRL_TX_REPORT_SID B100_REG_CTRL_TX_ADDR(2) -#define B100_REG_CTRL_TX_POLICY B100_REG_CTRL_TX_ADDR(3) - -#define B100_FLAG_CTRL_TX_POLICY_WAIT (0x1 << 0) -#define B100_FLAG_CTRL_TX_POLICY_NEXT_PACKET (0x1 << 1) -#define B100_FLAG_CTRL_TX_POLICY_NEXT_BURST (0x1 << 2) - -///////////////////////////////////////////////// -// VITA49 64 bit time (write only) -//////////////////////////////////////////////// - /*! - * \brief Time 64 flags - * - * 
-   *
-   *    3                   2                   1
-   *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
-   * +-----------------------------------------------------------+-+-+
-   * |                                                           |S|P|
-   * +-----------------------------------------------------------+-+-+
-   *
-   * P - PPS edge selection (0=negedge, 1=posedge, default=0)
-   * S - Source (0=sma, 1=mimo, 0=default)
-   *
-   *
- */ -#define B100_REG_TIME64_ADDR(n) (B100_REG_SETTINGS_BASE_ADDR(40) + (4*(n))) -#define B100_REG_TIME64_SECS B100_REG_TIME64_ADDR(0) // value to set absolute secs to on next PPS -#define B100_REG_TIME64_TICKS B100_REG_TIME64_ADDR(1) // value to set absolute ticks to on next PPS -#define B100_REG_TIME64_FLAGS B100_REG_TIME64_ADDR(2) // flags - see chart above -#define B100_REG_TIME64_IMM B100_REG_TIME64_ADDR(3) // set immediate (0=latch on next pps, 1=latch immediate, default=0) -#define B100_REG_TIME64_TPS B100_REG_TIME64_ADDR(4) // clock ticks per second (counter rollover) - -//pps flags (see above) -#define B100_FLAG_TIME64_PPS_NEGEDGE (0 << 0) -#define B100_FLAG_TIME64_PPS_POSEDGE (1 << 0) -#define B100_FLAG_TIME64_PPS_SMA (0 << 1) -#define B100_FLAG_TIME64_PPS_MIMO (1 << 1) - -#define B100_FLAG_TIME64_LATCH_NOW 1 -#define B100_FLAG_TIME64_LATCH_NEXT_PPS 0 - -#define B100_REG_CLEAR_RX_FIFO B100_REG_SETTINGS_BASE_ADDR(48) -#define B100_REG_CLEAR_TX_FIFO B100_REG_SETTINGS_BASE_ADDR(49) - -#define B100_REG_GLOBAL_RESET B100_REG_SETTINGS_BASE_ADDR(50) -#define B100_REG_TEST32 B100_REG_SETTINGS_BASE_ADDR(52) - -#endif - diff --git a/host/lib/usrp/usrp_b100/clock_ctrl.cpp b/host/lib/usrp/usrp_b100/clock_ctrl.cpp deleted file mode 100644 index e138242d1..000000000 --- a/host/lib/usrp/usrp_b100/clock_ctrl.cpp +++ /dev/null @@ -1,525 +0,0 @@ -// -// Copyright 2010-2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "clock_ctrl.hpp" -#include "ad9522_regs.hpp" -#include -#include -#include -#include -#include -#include -#include "b100_regs.hpp" //spi slave constants -#include -#include -#include -#include -#include //gcd -#include -#include - -using namespace uhd; - -/*********************************************************************** - * Constants - **********************************************************************/ -static const bool ENABLE_THE_TEST_OUT = true; -static const double REFERENCE_INPUT_RATE = 10e6; - -/*********************************************************************** - * Helpers - **********************************************************************/ -template static void set_clock_divider( - size_t divider, div_type &low, div_type &high, bypass_type &bypass -){ - high = divider/2 - 1; - low = divider - high - 2; - bypass = (divider == 1)? 1 : 0; -} - -/*********************************************************************** - * Clock rate calculation stuff: - * Using the internal VCO between 1400 and 1800 MHz - **********************************************************************/ -struct clock_settings_type{ - size_t ref_clock_doubler, r_counter, a_counter, b_counter, prescaler, vco_divider, chan_divider; - size_t get_n_counter(void) const{return prescaler * b_counter + a_counter;} - double get_ref_rate(void) const{return REFERENCE_INPUT_RATE * ref_clock_doubler;} - double get_vco_rate(void) const{return get_ref_rate()/r_counter * get_n_counter();} - double get_chan_rate(void) const{return get_vco_rate()/vco_divider;} - double get_out_rate(void) const{return get_chan_rate()/chan_divider;} - std::string to_pp_string(void) const{ - return str(boost::format( - " r_counter: %d\n" - " a_counter: %d\n" - " b_counter: %d\n" - " prescaler: %d\n" - " vco_divider: %d\n" - " chan_divider: %d\n" - " vco_rate: %fMHz\n" - " chan_rate: %fMHz\n" - " out_rate: %fMHz\n" - ) - % r_counter - % a_counter - % b_counter - % prescaler - % vco_divider - % chan_divider - % (get_vco_rate()/1e6) - % (get_chan_rate()/1e6) - % (get_out_rate()/1e6) - ); - } -}; - -//! gives the greatest divisor of num between 1 and max inclusive -template static inline T greatest_divisor(T num, T max){ - for (T i = max; i > 1; i--) if (num%i == 0) return i; return 1; -} - -//! gives the least divisor of num between min and num exclusive -template static inline T least_divisor(T num, T min){ - for (T i = min; i < num; i++) if (num%i == 0) return i; return 1; -} - -static clock_settings_type get_clock_settings(double rate){ - clock_settings_type cs; - cs.ref_clock_doubler = 2; //always doubling - cs.prescaler = 8; //set to 8 when input is under 2400 MHz - - //basic formulas used below: - //out_rate*X = ref_rate*Y - //X = i*ref_rate/gcd - //Y = i*out_rate/gcd - //X = chan_div * vco_div * R - //Y = P*B + A - - const boost::uint64_t out_rate = boost::uint64_t(rate); - const boost::uint64_t ref_rate = boost::uint64_t(cs.get_ref_rate()); - const size_t gcd = size_t(boost::math::gcd(ref_rate, out_rate)); - - for (size_t i = 1; i <= 100; i++){ - const size_t X = i*ref_rate/gcd; - const size_t Y = i*out_rate/gcd; - - //determine A and B (P is fixed) - cs.b_counter = Y/cs.prescaler; - cs.a_counter = Y - cs.b_counter*cs.prescaler; - - static const double vco_bound_pad = 100e6; - for ( //calculate an r divider that fits into the bounds of the vco - cs.r_counter = size_t(cs.get_n_counter()*cs.get_ref_rate()/(1800e6 - vco_bound_pad)); - cs.r_counter <= size_t(cs.get_n_counter()*cs.get_ref_rate()/(1400e6 + vco_bound_pad)) - and cs.r_counter > 0; cs.r_counter++ - ){ - - //determine chan_div and vco_div - //and fill in that order of preference - cs.chan_divider = greatest_divisor(X/cs.r_counter, 32); - cs.vco_divider = greatest_divisor(X/cs.chan_divider/cs.r_counter, 6); - - //avoid a vco divider of 1 (if possible) - if (cs.vco_divider == 1){ - cs.vco_divider = least_divisor(cs.chan_divider, 2); - cs.chan_divider /= cs.vco_divider; - } - - UHD_LOGV(always) - << "gcd " << gcd << std::endl - << "X " << X << std::endl - << "Y " << Y << std::endl - << cs.to_pp_string() << std::endl - ; - - //filter limits on the counters - if (cs.vco_divider == 1) continue; - if (cs.r_counter >= (1<<14)) continue; - if (cs.b_counter == 2) continue; - if (cs.b_counter == 1 and cs.a_counter != 0) continue; - if (cs.b_counter >= (1<<13)) continue; - if (cs.a_counter >= (1<<6)) continue; - - UHD_MSG(status) << "USRP-B100 clock control: " << i << std::endl << cs.to_pp_string() << std::endl; - return cs; - } - } - - throw uhd::runtime_error(str(boost::format( - "USRP-B100 clock control: could not calculate settings for clock rate %fMHz" - ) % (rate/1e6))); -} - -/*********************************************************************** - * Clock Control Implementation - **********************************************************************/ -class b100_clock_ctrl_impl : public b100_clock_ctrl{ -public: - b100_clock_ctrl_impl(b100_iface::sptr iface, double master_clock_rate){ - _iface = iface; - _chan_rate = 0.0; - _out_rate = 0.0; - - //init the clock gen registers - _ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO; - _ad9522_regs.enb_stat_eeprom_at_stat_pin = 0; //use status pin - _ad9522_regs.status_pin_control = 0x1; //n divider - _ad9522_regs.ld_pin_control = 0x00; //dld - _ad9522_regs.refmon_pin_control = 0x12; //show ref2 - _ad9522_regs.lock_detect_counter = ad9522_regs_t::LOCK_DETECT_COUNTER_16CYC; - - this->use_internal_ref(); - - this->set_fpga_clock_rate(master_clock_rate); //initialize to something - - this->enable_fpga_clock(true); - this->enable_test_clock(ENABLE_THE_TEST_OUT); - this->enable_rx_dboard_clock(false); - this->enable_tx_dboard_clock(false); - } - - ~b100_clock_ctrl_impl(void){ - UHD_SAFE_CALL( - this->enable_test_clock(ENABLE_THE_TEST_OUT); - this->enable_rx_dboard_clock(false); - this->enable_tx_dboard_clock(false); - //this->enable_fpga_clock(false); //FIXME - ) - } - - /*********************************************************************** - * Clock rate control: - * - set clock rate w/ internal VCO - * - set clock rate w/ external VCXO - **********************************************************************/ - void set_clock_settings_with_internal_vco(double rate){ - const clock_settings_type cs = get_clock_settings(rate); - - //set the rates to private variables so the implementation knows! - _chan_rate = cs.get_chan_rate(); - _out_rate = cs.get_out_rate(); - - _ad9522_regs.enable_clock_doubler = (cs.ref_clock_doubler == 2)? 1 : 0; - - _ad9522_regs.set_r_counter(cs.r_counter); - _ad9522_regs.a_counter = cs.a_counter; - _ad9522_regs.set_b_counter(cs.b_counter); - UHD_ASSERT_THROW(cs.prescaler == 8); //assumes this below: - _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV8_9; - - _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL; - _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA; - - _ad9522_regs.bypass_vco_divider = 0; - switch(cs.vco_divider){ - case 1: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV1; break; - case 2: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV2; break; - case 3: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV3; break; - case 4: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV4; break; - case 5: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5; break; - case 6: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV6; break; - } - _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_VCO; - - //setup fpga master clock - _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; - set_clock_divider(cs.chan_divider, - _ad9522_regs.divider0_low_cycles, - _ad9522_regs.divider0_high_cycles, - _ad9522_regs.divider0_bypass - ); - - //setup codec clock - _ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS; - set_clock_divider(cs.chan_divider, - _ad9522_regs.divider1_low_cycles, - _ad9522_regs.divider1_high_cycles, - _ad9522_regs.divider1_bypass - ); - - this->send_all_regs(); - calibrate_now(); - } - - void set_clock_settings_with_external_vcxo(double rate){ - //set the rates to private variables so the implementation knows! - _chan_rate = rate; - _out_rate = rate; - - _ad9522_regs.enable_clock_doubler = 1; //doubler always on - const double ref_rate = REFERENCE_INPUT_RATE*2; - - //bypass prescaler such that N = B - long gcd = boost::math::gcd(long(ref_rate), long(rate)); - _ad9522_regs.set_r_counter(int(ref_rate/gcd)); - _ad9522_regs.a_counter = 0; - _ad9522_regs.set_b_counter(int(rate/gcd)); - _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV1; - - //setup external vcxo - _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL; - _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA; - _ad9522_regs.bypass_vco_divider = 1; - _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_EXTERNAL; - - //setup fpga master clock - _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; - _ad9522_regs.divider0_bypass = 1; - - //setup codec clock - _ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS; - _ad9522_regs.divider1_bypass = 1; - - this->send_all_regs(); - } - - void set_fpga_clock_rate(double rate){ - if (_out_rate == rate) return; - if (rate == 61.44e6) set_clock_settings_with_external_vcxo(rate); - else set_clock_settings_with_internal_vco(rate); - //clock rate changed! update dboard clocks and FPGA ticks per second - set_rx_dboard_clock_rate(rate); - set_tx_dboard_clock_rate(rate); - _iface->poke32(B100_REG_TIME64_TPS, boost::uint32_t(get_fpga_clock_rate())); - } - - double get_fpga_clock_rate(void){ - return this->_out_rate; - } - - /*********************************************************************** - * FPGA clock enable - **********************************************************************/ - void enable_fpga_clock(bool enb){ - _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; - _ad9522_regs.out0_lvds_power_down = !enb; - this->send_reg(0x0F0); - this->latch_regs(); - } - - /*********************************************************************** - * Special test clock output - **********************************************************************/ - void enable_test_clock(bool enb){ - //setup test clock (same divider as codec clock) - _ad9522_regs.out4_format = ad9522_regs_t::OUT4_FORMAT_CMOS; - _ad9522_regs.out4_cmos_configuration = (enb)? - ad9522_regs_t::OUT4_CMOS_CONFIGURATION_A_ON : - ad9522_regs_t::OUT4_CMOS_CONFIGURATION_OFF; - this->send_reg(0x0F4); - this->latch_regs(); - } - - /*********************************************************************** - * RX Dboard Clock Control (output 9, divider 3) - **********************************************************************/ - void enable_rx_dboard_clock(bool enb){ - _ad9522_regs.out9_format = ad9522_regs_t::OUT9_FORMAT_CMOS; - _ad9522_regs.out9_cmos_configuration = (enb)? - ad9522_regs_t::OUT9_CMOS_CONFIGURATION_B_ON : - ad9522_regs_t::OUT9_CMOS_CONFIGURATION_OFF; - this->send_reg(0x0F9); - this->latch_regs(); - } - - std::vector get_rx_dboard_clock_rates(void){ - std::vector rates; - for(size_t div = 1; div <= 16+16; div++) - rates.push_back(this->_chan_rate/div); - return rates; - } - - void set_rx_dboard_clock_rate(double rate){ - assert_has(get_rx_dboard_clock_rates(), rate, "rx dboard clock rate"); - _rx_clock_rate = rate; - size_t divider = size_t(this->_chan_rate/rate); - //set the divider registers - set_clock_divider(divider, - _ad9522_regs.divider3_low_cycles, - _ad9522_regs.divider3_high_cycles, - _ad9522_regs.divider3_bypass - ); - this->send_reg(0x199); - this->send_reg(0x19a); - this->soft_sync(); - } - - double get_rx_clock_rate(void){ - return _rx_clock_rate; - } - - /*********************************************************************** - * TX Dboard Clock Control (output 6, divider 2) - **********************************************************************/ - void enable_tx_dboard_clock(bool enb){ - _ad9522_regs.out6_format = ad9522_regs_t::OUT6_FORMAT_CMOS; - _ad9522_regs.out6_cmos_configuration = (enb)? - ad9522_regs_t::OUT6_CMOS_CONFIGURATION_B_ON : - ad9522_regs_t::OUT6_CMOS_CONFIGURATION_OFF; - this->send_reg(0x0F6); - this->latch_regs(); - } - - std::vector get_tx_dboard_clock_rates(void){ - return get_rx_dboard_clock_rates(); //same master clock, same dividers... - } - - void set_tx_dboard_clock_rate(double rate){ - assert_has(get_tx_dboard_clock_rates(), rate, "tx dboard clock rate"); - _tx_clock_rate = rate; - size_t divider = size_t(this->_chan_rate/rate); - //set the divider registers - set_clock_divider(divider, - _ad9522_regs.divider2_low_cycles, - _ad9522_regs.divider2_high_cycles, - _ad9522_regs.divider2_bypass - ); - this->send_reg(0x196); - this->send_reg(0x197); - this->soft_sync(); - } - - double get_tx_clock_rate(void){ - return _tx_clock_rate; - } - - /*********************************************************************** - * Clock reference control - **********************************************************************/ - void use_internal_ref(void) { - _ad9522_regs.enable_ref2 = 1; - _ad9522_regs.enable_ref1 = 0; - _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF2; - _ad9522_regs.enb_auto_ref_switchover = ad9522_regs_t::ENB_AUTO_REF_SWITCHOVER_MANUAL; - this->send_reg(0x01C); - this->latch_regs(); - } - - void use_external_ref(void) { - _ad9522_regs.enable_ref2 = 0; - _ad9522_regs.enable_ref1 = 1; - _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF1; - _ad9522_regs.enb_auto_ref_switchover = ad9522_regs_t::ENB_AUTO_REF_SWITCHOVER_MANUAL; - this->send_reg(0x01C); - this->latch_regs(); - } - - void use_auto_ref(void) { - _ad9522_regs.enable_ref2 = 1; - _ad9522_regs.enable_ref1 = 1; - _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF1; - _ad9522_regs.enb_auto_ref_switchover = ad9522_regs_t::ENB_AUTO_REF_SWITCHOVER_AUTO; - this->send_reg(0x01C); - this->latch_regs(); - } - -private: - b100_iface::sptr _iface; - ad9522_regs_t _ad9522_regs; - double _out_rate; //rate at the fpga and codec - double _chan_rate; //rate before final dividers - double _rx_clock_rate, _tx_clock_rate; - - void latch_regs(void){ - _ad9522_regs.io_update = 1; - this->send_reg(0x232); - } - - void send_reg(boost::uint16_t addr){ - boost::uint32_t reg = _ad9522_regs.get_write_reg(addr); - UHD_LOGV(often) << "clock control write reg: " << std::hex << reg << std::endl; - byte_vector_t buf; - buf.push_back(boost::uint8_t(reg >> 16)); - buf.push_back(boost::uint8_t(reg >> 8)); - buf.push_back(boost::uint8_t(reg & 0xff)); - - _iface->get_fx2_i2c_iface().write_i2c(0x5C, buf); - } - - boost::uint8_t read_reg(boost::uint16_t addr){ - byte_vector_t buf; - buf.push_back(boost::uint8_t(addr >> 8)); - buf.push_back(boost::uint8_t(addr & 0xff)); - _iface->get_fx2_i2c_iface().write_i2c(0x5C, buf); - - buf = _iface->get_fx2_i2c_iface().read_i2c(0x5C, 1); - - return boost::uint32_t(buf[0] & 0xFF); - } - - void calibrate_now(void){ - //vco calibration routine: - _ad9522_regs.vco_calibration_now = 0; - this->send_reg(0x18); - this->latch_regs(); - _ad9522_regs.vco_calibration_now = 1; - this->send_reg(0x18); - this->latch_regs(); - //wait for calibration done: - static const boost::uint8_t addr = 0x01F; - for (size_t ms10 = 0; ms10 < 100; ms10++){ - boost::this_thread::sleep(boost::posix_time::milliseconds(10)); - boost::uint32_t reg = read_reg(addr); - _ad9522_regs.set_reg(addr, reg); - if (_ad9522_regs.vco_calibration_finished) goto wait_for_ld; - } - UHD_MSG(error) << "USRP-B100 clock control: VCO calibration timeout" << std::endl; - wait_for_ld: - //wait for digital lock detect: - for (size_t ms10 = 0; ms10 < 100; ms10++){ - boost::this_thread::sleep(boost::posix_time::milliseconds(10)); - boost::uint32_t reg = read_reg(addr); - _ad9522_regs.set_reg(addr, reg); - if (_ad9522_regs.digital_lock_detect) return; - } - UHD_MSG(error) << "USRP-B100 clock control: lock detection timeout" << std::endl; - } - - void soft_sync(void){ - _ad9522_regs.soft_sync = 1; - this->send_reg(0x230); - this->latch_regs(); - _ad9522_regs.soft_sync = 0; - this->send_reg(0x230); - this->latch_regs(); - } - - void send_all_regs(void){ - //setup a list of register ranges to write - typedef std::pair range_t; - static const std::vector ranges = boost::assign::list_of - (range_t(0x000, 0x000)) (range_t(0x010, 0x01F)) - (range_t(0x0F0, 0x0FD)) (range_t(0x190, 0x19B)) - (range_t(0x1E0, 0x1E1)) (range_t(0x230, 0x230)) - ; - - //write initial register values and latch/update - BOOST_FOREACH(const range_t &range, ranges){ - for(boost::uint16_t addr = range.first; addr <= range.second; addr++){ - this->send_reg(addr); - } - } - this->latch_regs(); - } -}; - -/*********************************************************************** - * Clock Control Make - **********************************************************************/ -b100_clock_ctrl::sptr b100_clock_ctrl::make(b100_iface::sptr iface, double master_clock_rate){ - return sptr(new b100_clock_ctrl_impl(iface, master_clock_rate)); -} diff --git a/host/lib/usrp/usrp_b100/clock_ctrl.hpp b/host/lib/usrp/usrp_b100/clock_ctrl.hpp deleted file mode 100644 index 2a2e74024..000000000 --- a/host/lib/usrp/usrp_b100/clock_ctrl.hpp +++ /dev/null @@ -1,118 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#ifndef INCLUDED_B100_CLOCK_CTRL_HPP -#define INCLUDED_B100_CLOCK_CTRL_HPP - -#include "b100_iface.hpp" -#include -#include -#include - -/*! - * The usrp-e clock control: - * - Setup system clocks. - * - Disable/enable clock lines. - */ -class b100_clock_ctrl : boost::noncopyable{ -public: - typedef boost::shared_ptr sptr; - - /*! - * Make a new clock control object. - * \param iface the b100 iface object - * \param master_clock_rate the master FPGA/sample clock rate - * \return the clock control object - */ - static sptr make(b100_iface::sptr iface, double master_clock_rate); - - /*! - * Set the rate of the fpga clock line. - * Throws if rate is not valid. - * \param rate the new rate in Hz - */ - virtual void set_fpga_clock_rate(double rate) = 0; - - /*! - * Get the rate of the fpga clock line. - * \return the fpga clock rate in Hz - */ - virtual double get_fpga_clock_rate(void) = 0; - - /*! - * Get the possible rates of the rx dboard clock. - * \return a vector of clock rates in Hz - */ - virtual std::vector get_rx_dboard_clock_rates(void) = 0; - - /*! - * Get the possible rates of the tx dboard clock. - * \return a vector of clock rates in Hz - */ - virtual std::vector get_tx_dboard_clock_rates(void) = 0; - - /*! - * Set the rx dboard clock rate to a possible rate. - * \param rate the new clock rate in Hz - * \throw exception when rate cannot be achieved - */ - virtual void set_rx_dboard_clock_rate(double rate) = 0; - - /*! - * Set the tx dboard clock rate to a possible rate. - * \param rate the new clock rate in Hz - * \throw exception when rate cannot be achieved - */ - virtual void set_tx_dboard_clock_rate(double rate) = 0; - - /*! - * Enable/disable the FPGA clock. - * \param enb true to enable - */ - - virtual void enable_fpga_clock(bool enb) = 0; - - /*! - * Enable/disable the rx dboard clock. - * \param enb true to enable - */ - virtual void enable_rx_dboard_clock(bool enb) = 0; - - /*! - * Enable/disable the tx dboard clock. - * \param enb true to enable - */ - virtual void enable_tx_dboard_clock(bool enb) = 0; - - /*! - * Use the internal TCXO reference - */ - virtual void use_internal_ref(void) = 0; - - /*! - * Use the external SMA reference - */ - virtual void use_external_ref(void) = 0; - - /*! - * Use external if available, internal otherwise - */ - virtual void use_auto_ref(void) = 0; - -}; - -#endif /* INCLUDED_B100_CLOCK_CTRL_HPP */ diff --git a/host/lib/usrp/usrp_b100/codec_ctrl.cpp b/host/lib/usrp/usrp_b100/codec_ctrl.cpp deleted file mode 100644 index 4d118b68b..000000000 --- a/host/lib/usrp/usrp_b100/codec_ctrl.cpp +++ /dev/null @@ -1,283 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "codec_ctrl.hpp" -#include "ad9862_regs.hpp" -#include -#include -#include -#include -#include -#include -#include -#include -#include "b100_regs.hpp" //spi slave constants -#include - -using namespace uhd; - -const gain_range_t b100_codec_ctrl::tx_pga_gain_range(-20, 0, double(0.1)); -const gain_range_t b100_codec_ctrl::rx_pga_gain_range(0, 20, 1); - -/*********************************************************************** - * Codec Control Implementation - **********************************************************************/ -class b100_codec_ctrl_impl : public b100_codec_ctrl{ -public: - //structors - b100_codec_ctrl_impl(b100_iface::sptr iface); - ~b100_codec_ctrl_impl(void); - - //aux adc and dac control - double read_aux_adc(aux_adc_t which); - void write_aux_dac(aux_dac_t which, double volts); - - //pga gain control - void set_tx_pga_gain(double); - double get_tx_pga_gain(void); - void set_rx_pga_gain(double, char); - double get_rx_pga_gain(char); - -private: - b100_iface::sptr _iface; - ad9862_regs_t _ad9862_regs; - void send_reg(boost::uint8_t addr); - void recv_reg(boost::uint8_t addr); -}; - -/*********************************************************************** - * Codec Control Structors - **********************************************************************/ -b100_codec_ctrl_impl::b100_codec_ctrl_impl(b100_iface::sptr iface){ - _iface = iface; - - //soft reset - _ad9862_regs.soft_reset = 1; - this->send_reg(0); - - //initialize the codec register settings - _ad9862_regs.sdio_bidir = ad9862_regs_t::SDIO_BIDIR_SDIO_SDO; - _ad9862_regs.lsb_first = ad9862_regs_t::LSB_FIRST_MSB; - _ad9862_regs.soft_reset = 0; - - //setup rx side of codec - _ad9862_regs.byp_buffer_a = 1; - _ad9862_regs.byp_buffer_b = 1; - _ad9862_regs.buffer_a_pd = 1; - _ad9862_regs.buffer_b_pd = 1; - _ad9862_regs.mux_out = ad9862_regs_t::MUX_OUT_RX_MUX_MODE; //B100 uses interleaved RX->FPGA - _ad9862_regs.rx_pga_a = 0;//0x1f; //TODO bring under api control - _ad9862_regs.rx_pga_b = 0;//0x1f; //TODO bring under api control - _ad9862_regs.rx_twos_comp = 1; - _ad9862_regs.rx_hilbert = ad9862_regs_t::RX_HILBERT_DIS; - - //setup tx side of codec - _ad9862_regs.two_data_paths = ad9862_regs_t::TWO_DATA_PATHS_BOTH; - _ad9862_regs.interleaved = ad9862_regs_t::INTERLEAVED_INTERLEAVED; - _ad9862_regs.tx_retime = ad9862_regs_t::TX_RETIME_CLKOUT2; - _ad9862_regs.tx_pga_gain = 199; //TODO bring under api control - _ad9862_regs.tx_hilbert = ad9862_regs_t::TX_HILBERT_DIS; - _ad9862_regs.interp = ad9862_regs_t::INTERP_2; - _ad9862_regs.tx_twos_comp = 1; - _ad9862_regs.fine_mode = ad9862_regs_t::FINE_MODE_BYPASS; - _ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_BYPASS; - _ad9862_regs.dac_a_coarse_gain = 0x3; - _ad9862_regs.dac_b_coarse_gain = 0x3; - _ad9862_regs.edges = ad9862_regs_t::EDGES_NORMAL; - - //setup the dll - _ad9862_regs.input_clk_ctrl = ad9862_regs_t::INPUT_CLK_CTRL_EXTERNAL; - _ad9862_regs.dll_mult = ad9862_regs_t::DLL_MULT_2; - _ad9862_regs.dll_mode = ad9862_regs_t::DLL_MODE_FAST; - - //write the register settings to the codec - for (uint8_t addr = 0; addr <= 25; addr++){ - this->send_reg(addr); - } - - //always start conversions for aux ADC - _ad9862_regs.start_a = 1; - _ad9862_regs.start_b = 1; - - //aux adc clock - _ad9862_regs.clk_4 = ad9862_regs_t::CLK_4_1_4; - this->send_reg(34); -} - -b100_codec_ctrl_impl::~b100_codec_ctrl_impl(void){ - UHD_SAFE_CALL( - //set aux dacs to zero - this->write_aux_dac(AUX_DAC_A, 0); - this->write_aux_dac(AUX_DAC_B, 0); - this->write_aux_dac(AUX_DAC_C, 0); - this->write_aux_dac(AUX_DAC_D, 0); - - //power down - _ad9862_regs.all_rx_pd = 1; - this->send_reg(1); - _ad9862_regs.tx_digital_pd = 1; - _ad9862_regs.tx_analog_pd = ad9862_regs_t::TX_ANALOG_PD_BOTH; - this->send_reg(8); - ) -} - -/*********************************************************************** - * Codec Control Gain Control Methods - **********************************************************************/ -static const int mtpgw = 255; //maximum tx pga gain word - -void b100_codec_ctrl_impl::set_tx_pga_gain(double gain){ - int gain_word = int(mtpgw*(gain - tx_pga_gain_range.start())/(tx_pga_gain_range.stop() - tx_pga_gain_range.start())); - _ad9862_regs.tx_pga_gain = uhd::clip(gain_word, 0, mtpgw); - this->send_reg(16); -} - -double b100_codec_ctrl_impl::get_tx_pga_gain(void){ - return (_ad9862_regs.tx_pga_gain*(tx_pga_gain_range.stop() - tx_pga_gain_range.start())/mtpgw) + tx_pga_gain_range.start(); -} - -static const int mrpgw = 0x14; //maximum rx pga gain word - -void b100_codec_ctrl_impl::set_rx_pga_gain(double gain, char which){ - int gain_word = int(mrpgw*(gain - rx_pga_gain_range.start())/(rx_pga_gain_range.stop() - rx_pga_gain_range.start())); - gain_word = uhd::clip(gain_word, 0, mrpgw); - switch(which){ - case 'A': - _ad9862_regs.rx_pga_a = gain_word; - this->send_reg(2); - return; - case 'B': - _ad9862_regs.rx_pga_b = gain_word; - this->send_reg(3); - return; - default: UHD_THROW_INVALID_CODE_PATH(); - } -} - -double b100_codec_ctrl_impl::get_rx_pga_gain(char which){ - int gain_word; - switch(which){ - case 'A': gain_word = _ad9862_regs.rx_pga_a; break; - case 'B': gain_word = _ad9862_regs.rx_pga_b; break; - default: UHD_THROW_INVALID_CODE_PATH(); - } - return (gain_word*(rx_pga_gain_range.stop() - rx_pga_gain_range.start())/mrpgw) + rx_pga_gain_range.start(); -} - -/*********************************************************************** - * Codec Control AUX ADC Methods - **********************************************************************/ -static double aux_adc_to_volts(boost::uint8_t high, boost::uint8_t low){ - return double((boost::uint16_t(high) << 2) | low)*3.3/0x3ff; -} - -double b100_codec_ctrl_impl::read_aux_adc(aux_adc_t which){ - switch(which){ - - case AUX_ADC_A1: - _ad9862_regs.select_a = ad9862_regs_t::SELECT_A_AUX_ADC1; - this->send_reg(34); //start conversion and select mux - this->recv_reg(28); //read the value (2 bytes, 2 reads) - this->recv_reg(29); - return aux_adc_to_volts(_ad9862_regs.aux_adc_a1_9_2, _ad9862_regs.aux_adc_a1_1_0); - case AUX_ADC_A2: - _ad9862_regs.select_a = ad9862_regs_t::SELECT_A_AUX_ADC2; - this->send_reg(34); //start conversion and select mux - this->recv_reg(26); //read the value (2 bytes, 2 reads) - this->recv_reg(27); - return aux_adc_to_volts(_ad9862_regs.aux_adc_a2_9_2, _ad9862_regs.aux_adc_a2_1_0); - - case AUX_ADC_B1: - _ad9862_regs.select_b = ad9862_regs_t::SELECT_B_AUX_ADC1; - this->send_reg(34); //start conversion and select mux - this->recv_reg(32); //read the value (2 bytes, 2 reads) - this->recv_reg(33); - return aux_adc_to_volts(_ad9862_regs.aux_adc_b1_9_2, _ad9862_regs.aux_adc_b1_1_0); - case AUX_ADC_B2: - _ad9862_regs.select_b = ad9862_regs_t::SELECT_B_AUX_ADC2; - this->send_reg(34); //start conversion and select mux - this->recv_reg(30); //read the value (2 bytes, 2 reads) - this->recv_reg(31); - return aux_adc_to_volts(_ad9862_regs.aux_adc_b2_9_2, _ad9862_regs.aux_adc_b2_1_0); - } - UHD_THROW_INVALID_CODE_PATH(); -} - -/*********************************************************************** - * Codec Control AUX DAC Methods - **********************************************************************/ -void b100_codec_ctrl_impl::write_aux_dac(aux_dac_t which, double volts){ - //special case for aux dac d (aka sigma delta word) - if (which == AUX_DAC_D){ - boost::uint16_t dac_word = uhd::clip(boost::math::iround(volts*0xfff/3.3), 0, 0xfff); - _ad9862_regs.sig_delt_11_4 = boost::uint8_t(dac_word >> 4); - _ad9862_regs.sig_delt_3_0 = boost::uint8_t(dac_word & 0xf); - this->send_reg(42); - this->send_reg(43); - return; - } - - //calculate the dac word for aux dac a, b, c - boost::uint8_t dac_word = uhd::clip(boost::math::iround(volts*0xff/3.3), 0, 0xff); - - //setup a lookup table for the aux dac params (reg ref, reg addr) - typedef boost::tuple dac_params_t; - uhd::dict aux_dac_to_params = boost::assign::map_list_of - (AUX_DAC_A, dac_params_t(&_ad9862_regs.aux_dac_a, 36)) - (AUX_DAC_B, dac_params_t(&_ad9862_regs.aux_dac_b, 37)) - (AUX_DAC_C, dac_params_t(&_ad9862_regs.aux_dac_c, 38)) - ; - - //set the aux dac register - UHD_ASSERT_THROW(aux_dac_to_params.has_key(which)); - boost::uint8_t *reg_ref, reg_addr; - boost::tie(reg_ref, reg_addr) = aux_dac_to_params[which]; - *reg_ref = dac_word; - this->send_reg(reg_addr); -} - -/*********************************************************************** - * Codec Control SPI Methods - **********************************************************************/ -void b100_codec_ctrl_impl::send_reg(boost::uint8_t addr){ - boost::uint32_t reg = _ad9862_regs.get_write_reg(addr); - UHD_LOGV(rarely) << "codec control write reg: " << std::hex << reg << std::endl; - _iface->transact_spi( - B100_SPI_SS_AD9862, - spi_config_t::EDGE_RISE, - reg, 16, false /*no rb*/ - ); -} - -void b100_codec_ctrl_impl::recv_reg(boost::uint8_t addr){ - boost::uint32_t reg = _ad9862_regs.get_read_reg(addr); - UHD_LOGV(rarely) << "codec control read reg: " << std::hex << reg << std::endl; - boost::uint32_t ret = _iface->transact_spi( - B100_SPI_SS_AD9862, - spi_config_t::EDGE_RISE, - reg, 16, true /*rb*/ - ); - UHD_LOGV(rarely) << "codec control read ret: " << std::hex << boost::uint16_t(ret & 0xFF) << std::endl; - _ad9862_regs.set_reg(addr, boost::uint8_t(ret&0xff)); -} - -/*********************************************************************** - * Codec Control Make - **********************************************************************/ -b100_codec_ctrl::sptr b100_codec_ctrl::make(b100_iface::sptr iface){ - return sptr(new b100_codec_ctrl_impl(iface)); -} diff --git a/host/lib/usrp/usrp_b100/codec_ctrl.hpp b/host/lib/usrp/usrp_b100/codec_ctrl.hpp deleted file mode 100644 index 1bd579190..000000000 --- a/host/lib/usrp/usrp_b100/codec_ctrl.hpp +++ /dev/null @@ -1,90 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#ifndef INCLUDED_B100_CODEC_CTRL_HPP -#define INCLUDED_B100_CODEC_CTRL_HPP - -#include "b100_iface.hpp" -#include -#include -#include - -/*! - * The usrp-e codec control: - * - Init/power down codec. - * - Read aux adc, write aux dac. - */ -class b100_codec_ctrl : boost::noncopyable{ -public: - typedef boost::shared_ptr sptr; - - static const uhd::gain_range_t tx_pga_gain_range; - static const uhd::gain_range_t rx_pga_gain_range; - - /*! - * Make a new codec control object. - * \param iface the usrp_e iface object - * \return the codec control object - */ - static sptr make(b100_iface::sptr iface); - - //! aux adc identifier constants - enum aux_adc_t{ - AUX_ADC_A2 = 0xA2, - AUX_ADC_A1 = 0xA1, - AUX_ADC_B2 = 0xB2, - AUX_ADC_B1 = 0xB1 - }; - - /*! - * Read an auxiliary adc: - * The internals remember which aux adc was read last. - * Therefore, the aux adc switch is only changed as needed. - * \param which which of the 4 adcs - * \return a value in volts - */ - virtual double read_aux_adc(aux_adc_t which) = 0; - - //! aux dac identifier constants - enum aux_dac_t{ - AUX_DAC_A = 0xA, - AUX_DAC_B = 0xB, - AUX_DAC_C = 0xC, - AUX_DAC_D = 0xD //really the sigma delta output - }; - - /*! - * Write an auxiliary dac. - * \param which which of the 4 dacs - * \param volts the level in in volts - */ - virtual void write_aux_dac(aux_dac_t which, double volts) = 0; - - //! Set the TX PGA gain - virtual void set_tx_pga_gain(double gain) = 0; - - //! Get the TX PGA gain - virtual double get_tx_pga_gain(void) = 0; - - //! Set the RX PGA gain ('A' or 'B') - virtual void set_rx_pga_gain(double gain, char which) = 0; - - //! Get the RX PGA gain ('A' or 'B') - virtual double get_rx_pga_gain(char which) = 0; -}; - -#endif /* INCLUDED_B100_CODEC_CTRL_HPP */ diff --git a/host/lib/usrp/usrp_b100/codec_impl.cpp b/host/lib/usrp/usrp_b100/codec_impl.cpp deleted file mode 100644 index de3ca3a66..000000000 --- a/host/lib/usrp/usrp_b100/codec_impl.cpp +++ /dev/null @@ -1,149 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "b100_impl.hpp" -#include -#include -#include - -using namespace uhd; -using namespace uhd::usrp; - -/*********************************************************************** - * Helper Methods - **********************************************************************/ -void b100_impl::codec_init(void){ - //make proxies - _rx_codec_proxy = wax_obj_proxy::make( - boost::bind(&b100_impl::rx_codec_get, this, _1, _2), - boost::bind(&b100_impl::rx_codec_set, this, _1, _2) - ); - _tx_codec_proxy = wax_obj_proxy::make( - boost::bind(&b100_impl::tx_codec_get, this, _1, _2), - boost::bind(&b100_impl::tx_codec_set, this, _1, _2) - ); -} - -/*********************************************************************** - * RX Codec Properties - **********************************************************************/ -static const std::string ad9862_pga_gain_name = "ad9862 pga"; - -void b100_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - //handle the get request conditioned on the key - switch(key.as()){ - case CODEC_PROP_NAME: - val = std::string("b100 adc - ad9522"); - return; - - case CODEC_PROP_OTHERS: - val = prop_names_t(); - return; - - case CODEC_PROP_GAIN_NAMES: - val = prop_names_t(1, ad9862_pga_gain_name); - return; - - case CODEC_PROP_GAIN_RANGE: - UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); - val = b100_codec_ctrl::rx_pga_gain_range; - return; - - case CODEC_PROP_GAIN_I: - UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); - val = _codec_ctrl->get_rx_pga_gain('A'); - return; - - case CODEC_PROP_GAIN_Q: - UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); - val = _codec_ctrl->get_rx_pga_gain('B'); - return; - - default: UHD_THROW_PROP_GET_ERROR(); - } -} - -void b100_impl::rx_codec_set(const wax::obj &key_, const wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - //handle the set request conditioned on the key - switch(key.as()){ - case CODEC_PROP_GAIN_I: - UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); - _codec_ctrl->set_rx_pga_gain(val.as(), 'A'); - return; - - case CODEC_PROP_GAIN_Q: - UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); - _codec_ctrl->set_rx_pga_gain(val.as(), 'B'); - return; - - default: UHD_THROW_PROP_SET_ERROR(); - } -} - -/*********************************************************************** - * TX Codec Properties - **********************************************************************/ -void b100_impl::tx_codec_get(const wax::obj &key_, wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - //handle the get request conditioned on the key - switch(key.as()){ - case CODEC_PROP_NAME: - val = std::string("b100 dac - ad9522"); - return; - - case CODEC_PROP_OTHERS: - val = prop_names_t(); - return; - - case CODEC_PROP_GAIN_NAMES: - val = prop_names_t(1, ad9862_pga_gain_name); - return; - - case CODEC_PROP_GAIN_RANGE: - UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); - val = b100_codec_ctrl::tx_pga_gain_range; - return; - - case CODEC_PROP_GAIN_I: //only one gain for I and Q - case CODEC_PROP_GAIN_Q: - UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); - val = _codec_ctrl->get_tx_pga_gain(); - return; - - default: UHD_THROW_PROP_GET_ERROR(); - } -} - -void b100_impl::tx_codec_set(const wax::obj &key_, const wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - //handle the set request conditioned on the key - switch(key.as()){ - case CODEC_PROP_GAIN_I: //only one gain for I and Q - case CODEC_PROP_GAIN_Q: - UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); - _codec_ctrl->set_tx_pga_gain(val.as()); - return; - - default: UHD_THROW_PROP_SET_ERROR(); - } -} diff --git a/host/lib/usrp/usrp_b100/ctrl_packet.hpp b/host/lib/usrp/usrp_b100/ctrl_packet.hpp deleted file mode 100644 index f504fc5aa..000000000 --- a/host/lib/usrp/usrp_b100/ctrl_packet.hpp +++ /dev/null @@ -1,75 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#ifndef INCLUDED_CTRL_PACKET_HPP -#define INCLUDED_CTRL_PACKET_HPP - -#include -#include -#include - -typedef std::vector ctrl_data_t; - -/*! - * Control packet operation type - */ -enum ctrl_pkt_op_t { - CTRL_PKT_OP_WRITE = 1, - CTRL_PKT_OP_READ = 2, - CTRL_PKT_OP_READBACK = 3 -}; - -/*! - * Control packet transaction length - */ -const size_t CTRL_PACKET_LENGTH = 32; -const size_t CTRL_PACKET_HEADER_LENGTH = 8; -const size_t CTRL_PACKET_DATA_LENGTH = 24; //=length-header - -/*! - * Control packet header magic value - */ -const boost::uint8_t CTRL_PACKET_HEADER_MAGIC = 0xAA; - -/*! - * Callback triggers for readback operation - */ -//FIXME: these are not real numbers, callbacks aren't implemented yet -const boost::uint16_t CTRL_PACKET_CALLBACK_SPI = 0x0001; -const boost::uint16_t CTRL_PACKET_CALLBACK_I2C = 0x0002; -//and so on - -/*! - * Metadata structure to describe a control packet - */ -struct UHD_API ctrl_pkt_meta_t { - ctrl_pkt_op_t op; - boost::uint8_t callbacks; - boost::uint8_t seq; - boost::uint16_t len; - boost::uint32_t addr; -}; - -/*! - * Full control packet structure - */ -struct UHD_API ctrl_pkt_t { - ctrl_pkt_meta_t pkt_meta; - ctrl_data_t data; -}; - -#endif /* INCLUDED_CTRL_PACKET_HPP */ diff --git a/host/lib/usrp/usrp_b100/dboard_iface.cpp b/host/lib/usrp/usrp_b100/dboard_iface.cpp deleted file mode 100644 index ec3da6220..000000000 --- a/host/lib/usrp/usrp_b100/dboard_iface.cpp +++ /dev/null @@ -1,298 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "b100_iface.hpp" -#include "b100_regs.hpp" -#include "clock_ctrl.hpp" -#include "codec_ctrl.hpp" -#include -#include -#include -#include - - -using namespace uhd; -using namespace uhd::usrp; -using namespace boost::assign; - -class b100_dboard_iface : public dboard_iface{ -public: - - b100_dboard_iface( - b100_iface::sptr iface, - b100_clock_ctrl::sptr clock, - b100_codec_ctrl::sptr codec - ){ - _iface = iface; - _clock = clock; - _codec = codec; - - //init the clock rate shadows - this->set_clock_rate(UNIT_RX, _clock->get_fpga_clock_rate()); - this->set_clock_rate(UNIT_TX, _clock->get_fpga_clock_rate()); - - _iface->poke16(B100_REG_GPIO_RX_DBG, 0); - _iface->poke16(B100_REG_GPIO_TX_DBG, 0); - } - - ~b100_dboard_iface(void){ - /* NOP */ - } - - special_props_t get_special_props(void){ - special_props_t props; - props.soft_clock_divider = false; - props.mangle_i2c_addrs = false; - return props; - } - - void write_aux_dac(unit_t, aux_dac_t, double); - double read_aux_adc(unit_t, aux_adc_t); - - void _set_pin_ctrl(unit_t, boost::uint16_t); - void _set_atr_reg(unit_t, atr_reg_t, boost::uint16_t); - void _set_gpio_ddr(unit_t, boost::uint16_t); - void _set_gpio_out(unit_t, boost::uint16_t); - void set_gpio_debug(unit_t, int); - boost::uint16_t read_gpio(unit_t); - - void write_i2c(boost::uint8_t, const byte_vector_t &); - byte_vector_t read_i2c(boost::uint8_t, size_t); - - void write_spi( - unit_t unit, - const spi_config_t &config, - boost::uint32_t data, - size_t num_bits - ); - - boost::uint32_t read_write_spi( - unit_t unit, - const spi_config_t &config, - boost::uint32_t data, - size_t num_bits - ); - - void set_clock_rate(unit_t, double); - std::vector get_clock_rates(unit_t); - double get_clock_rate(unit_t); - void set_clock_enabled(unit_t, bool); - double get_codec_rate(unit_t); - -private: - b100_iface::sptr _iface; - b100_clock_ctrl::sptr _clock; - b100_codec_ctrl::sptr _codec; - uhd::dict _clock_rates; -}; - -/*********************************************************************** - * Make Function - **********************************************************************/ -dboard_iface::sptr make_b100_dboard_iface( - b100_iface::sptr iface, - b100_clock_ctrl::sptr clock, - b100_codec_ctrl::sptr codec -){ - return dboard_iface::sptr(new b100_dboard_iface(iface, clock, codec)); -} - -/*********************************************************************** - * Clock Rates - **********************************************************************/ -void b100_dboard_iface::set_clock_rate(unit_t unit, double rate){ - _clock_rates[unit] = rate; - switch(unit){ - case UNIT_RX: return _clock->set_rx_dboard_clock_rate(rate); - case UNIT_TX: return _clock->set_tx_dboard_clock_rate(rate); - } -} - -std::vector b100_dboard_iface::get_clock_rates(unit_t unit){ - switch(unit){ - case UNIT_RX: return _clock->get_rx_dboard_clock_rates(); - case UNIT_TX: return _clock->get_tx_dboard_clock_rates(); - default: UHD_THROW_INVALID_CODE_PATH(); - } -} - -double b100_dboard_iface::get_clock_rate(unit_t unit){ - return _clock_rates[unit]; -} - -void b100_dboard_iface::set_clock_enabled(unit_t unit, bool enb){ - switch(unit){ - case UNIT_RX: return _clock->enable_rx_dboard_clock(enb); - case UNIT_TX: return _clock->enable_tx_dboard_clock(enb); - } -} - -double b100_dboard_iface::get_codec_rate(unit_t){ - return _clock->get_fpga_clock_rate(); -} - -/*********************************************************************** - * GPIO - **********************************************************************/ -void b100_dboard_iface::_set_pin_ctrl(unit_t unit, boost::uint16_t value){ - UHD_ASSERT_THROW(GPIO_SEL_ATR == 1); //make this assumption - switch(unit){ - case UNIT_RX: _iface->poke16(B100_REG_GPIO_RX_SEL, value); return; - case UNIT_TX: _iface->poke16(B100_REG_GPIO_TX_SEL, value); return; - } -} - -void b100_dboard_iface::_set_gpio_ddr(unit_t unit, boost::uint16_t value){ - switch(unit){ - case UNIT_RX: _iface->poke16(B100_REG_GPIO_RX_DDR, value); return; - case UNIT_TX: _iface->poke16(B100_REG_GPIO_TX_DDR, value); return; - } -} - -void b100_dboard_iface::_set_gpio_out(unit_t unit, boost::uint16_t value){ - switch(unit){ - case UNIT_RX: _iface->poke16(B100_REG_GPIO_RX_IO, value); return; - case UNIT_TX: _iface->poke16(B100_REG_GPIO_TX_IO, value); return; - } -} - -boost::uint16_t b100_dboard_iface::read_gpio(unit_t unit){ - switch(unit){ - case UNIT_RX: return _iface->peek16(B100_REG_GPIO_RX_IO); - case UNIT_TX: return _iface->peek16(B100_REG_GPIO_TX_IO); - default: UHD_THROW_INVALID_CODE_PATH(); - } -} - -void b100_dboard_iface::_set_atr_reg(unit_t unit, atr_reg_t atr, boost::uint16_t value){ - //define mapping of unit to atr regs to register address - static const uhd::dict< - unit_t, uhd::dict - > unit_to_atr_to_addr = map_list_of - (UNIT_RX, map_list_of - (ATR_REG_IDLE, B100_REG_ATR_IDLE_RXSIDE) - (ATR_REG_TX_ONLY, B100_REG_ATR_INTX_RXSIDE) - (ATR_REG_RX_ONLY, B100_REG_ATR_INRX_RXSIDE) - (ATR_REG_FULL_DUPLEX, B100_REG_ATR_FULL_RXSIDE) - ) - (UNIT_TX, map_list_of - (ATR_REG_IDLE, B100_REG_ATR_IDLE_TXSIDE) - (ATR_REG_TX_ONLY, B100_REG_ATR_INTX_TXSIDE) - (ATR_REG_RX_ONLY, B100_REG_ATR_INRX_TXSIDE) - (ATR_REG_FULL_DUPLEX, B100_REG_ATR_FULL_TXSIDE) - ) - ; - _iface->poke16(unit_to_atr_to_addr[unit][atr], value); -} - -void b100_dboard_iface::set_gpio_debug(unit_t unit, int which){ - //set this unit to all outputs - this->set_gpio_ddr(unit, 0xffff); - - //calculate the debug selections - boost::uint32_t dbg_sels = 0x0; - int sel = (which == 0)? GPIO_SEL_DEBUG_0 : GPIO_SEL_DEBUG_1; - for(size_t i = 0; i < 16; i++) dbg_sels |= sel << i; - - //set the debug on and which debug selection - switch(unit){ - case UNIT_RX: - _iface->poke16(B100_REG_GPIO_RX_DBG, 0xffff); - _iface->poke16(B100_REG_GPIO_RX_SEL, dbg_sels); - return; - - case UNIT_TX: - _iface->poke16(B100_REG_GPIO_TX_DBG, 0xffff); - _iface->poke16(B100_REG_GPIO_TX_SEL, dbg_sels); - return; - } -} - -/*********************************************************************** - * SPI - **********************************************************************/ -/*! - * Static function to convert a unit type to a spi slave device number. - * \param unit the dboard interface unit type enum - * \return the slave device number - */ -static boost::uint32_t unit_to_otw_spi_dev(dboard_iface::unit_t unit){ - switch(unit){ - case dboard_iface::UNIT_TX: return B100_SPI_SS_TX_DB; - case dboard_iface::UNIT_RX: return B100_SPI_SS_RX_DB; - } - throw std::invalid_argument("unknown unit type"); -} - -void b100_dboard_iface::write_spi( - unit_t unit, - const spi_config_t &config, - boost::uint32_t data, - size_t num_bits -){ - _iface->transact_spi(unit_to_otw_spi_dev(unit), config, data, num_bits, false /*no rb*/); -} - -boost::uint32_t b100_dboard_iface::read_write_spi( - unit_t unit, - const spi_config_t &config, - boost::uint32_t data, - size_t num_bits -){ - return _iface->transact_spi(unit_to_otw_spi_dev(unit), config, data, num_bits, true /*rb*/); -} - -/*********************************************************************** - * I2C - **********************************************************************/ -void b100_dboard_iface::write_i2c(boost::uint8_t addr, const byte_vector_t &bytes){ - return _iface->write_i2c(addr, bytes); -} - -byte_vector_t b100_dboard_iface::read_i2c(boost::uint8_t addr, size_t num_bytes){ - return _iface->read_i2c(addr, num_bytes); -} - -/*********************************************************************** - * Aux DAX/ADC - **********************************************************************/ -void b100_dboard_iface::write_aux_dac(dboard_iface::unit_t, aux_dac_t which, double value){ - //same aux dacs for each unit - static const uhd::dict which_to_aux_dac = map_list_of - (AUX_DAC_A, b100_codec_ctrl::AUX_DAC_A) - (AUX_DAC_B, b100_codec_ctrl::AUX_DAC_B) - (AUX_DAC_C, b100_codec_ctrl::AUX_DAC_C) - (AUX_DAC_D, b100_codec_ctrl::AUX_DAC_D) - ; - _codec->write_aux_dac(which_to_aux_dac[which], value); -} - -double b100_dboard_iface::read_aux_adc(dboard_iface::unit_t unit, aux_adc_t which){ - static const uhd::dict< - unit_t, uhd::dict - > unit_to_which_to_aux_adc = map_list_of - (UNIT_RX, map_list_of - (AUX_ADC_A, b100_codec_ctrl::AUX_ADC_A1) - (AUX_ADC_B, b100_codec_ctrl::AUX_ADC_B1) - ) - (UNIT_TX, map_list_of - (AUX_ADC_A, b100_codec_ctrl::AUX_ADC_A2) - (AUX_ADC_B, b100_codec_ctrl::AUX_ADC_B2) - ) - ; - return _codec->read_aux_adc(unit_to_which_to_aux_adc[unit][which]); -} diff --git a/host/lib/usrp/usrp_b100/dboard_impl.cpp b/host/lib/usrp/usrp_b100/dboard_impl.cpp deleted file mode 100644 index ba3776728..000000000 --- a/host/lib/usrp/usrp_b100/dboard_impl.cpp +++ /dev/null @@ -1,185 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "b100_impl.hpp" -#include "b100_regs.hpp" -#include -#include -#include -#include -#include -#include "usrp_i2c_addr.h" - -using namespace uhd; -using namespace uhd::usrp; - -/*********************************************************************** - * Dboard Initialization - **********************************************************************/ -void b100_impl::dboard_init(void){ - //read the tx and rx dboard eeproms - _rx_db_eeprom.load(*_iface, I2C_ADDR_RX_A); - _tx_db_eeprom.load(*_iface, I2C_ADDR_TX_A); - _gdb_eeprom.load(*_iface, I2C_ADDR_TX_A ^ 5); - - //create a new dboard interface and manager - _dboard_iface = make_b100_dboard_iface( - _iface, _clock_ctrl, _codec_ctrl - ); - _dboard_manager = dboard_manager::make( - _rx_db_eeprom.id, - ((_gdb_eeprom.id == dboard_id_t::none())? _tx_db_eeprom : _gdb_eeprom).id, - _dboard_iface - ); - - //setup the dboard proxies - _rx_dboard_proxy = wax_obj_proxy::make( - boost::bind(&b100_impl::rx_dboard_get, this, _1, _2), - boost::bind(&b100_impl::rx_dboard_set, this, _1, _2) - ); - _tx_dboard_proxy = wax_obj_proxy::make( - boost::bind(&b100_impl::tx_dboard_get, this, _1, _2), - boost::bind(&b100_impl::tx_dboard_set, this, _1, _2) - ); -} - -/*********************************************************************** - * RX Dboard Get - **********************************************************************/ -void b100_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - //handle the get request conditioned on the key - switch(key.as()){ - case DBOARD_PROP_NAME: - val = std::string("b100 dboard (rx unit)"); - return; - - case DBOARD_PROP_SUBDEV: - val = _dboard_manager->get_rx_subdev(key.name); - return; - - case DBOARD_PROP_SUBDEV_NAMES: - val = _dboard_manager->get_rx_subdev_names(); - return; - - case DBOARD_PROP_DBOARD_EEPROM: - val = _rx_db_eeprom; - return; - - case DBOARD_PROP_DBOARD_IFACE: - val = _dboard_iface; - return; - - case DBOARD_PROP_CODEC: - val = _rx_codec_proxy->get_link(); - return; - - case DBOARD_PROP_GAIN_GROUP: - val = make_gain_group( - _rx_db_eeprom.id, - _dboard_manager->get_rx_subdev(key.name), - _rx_codec_proxy->get_link(), - GAIN_GROUP_POLICY_RX - ); - return; - - default: UHD_THROW_PROP_GET_ERROR(); - } -} - -/*********************************************************************** - * RX Dboard Set - **********************************************************************/ -void b100_impl::rx_dboard_set(const wax::obj &key, const wax::obj &val){ - switch(key.as()){ - case DBOARD_PROP_DBOARD_EEPROM: - _rx_db_eeprom = val.as(); - _rx_db_eeprom.store(*_iface, I2C_ADDR_RX_A); - return; - - default: UHD_THROW_PROP_SET_ERROR(); - } -} - -/*********************************************************************** - * TX Dboard Get - **********************************************************************/ -void b100_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - //handle the get request conditioned on the key - switch(key.as()){ - case DBOARD_PROP_NAME: - val = std::string("b100 dboard (tx unit)"); - return; - - case DBOARD_PROP_SUBDEV: - val = _dboard_manager->get_tx_subdev(key.name); - return; - - case DBOARD_PROP_SUBDEV_NAMES: - val = _dboard_manager->get_tx_subdev_names(); - return; - - case DBOARD_PROP_DBOARD_EEPROM: - val = _tx_db_eeprom; - return; - - case DBOARD_PROP_GBOARD_EEPROM: - val = _gdb_eeprom; - return; - - case DBOARD_PROP_DBOARD_IFACE: - val = _dboard_iface; - return; - - case DBOARD_PROP_CODEC: - val = _tx_codec_proxy->get_link(); - return; - - case DBOARD_PROP_GAIN_GROUP: - val = make_gain_group( - _tx_db_eeprom.id, - _dboard_manager->get_tx_subdev(key.name), - _tx_codec_proxy->get_link(), - GAIN_GROUP_POLICY_TX - ); - return; - - default: UHD_THROW_PROP_GET_ERROR(); - } -} - -/*********************************************************************** - * TX Dboard Set - **********************************************************************/ -void b100_impl::tx_dboard_set(const wax::obj &key, const wax::obj &val){ - switch(key.as()){ - case DBOARD_PROP_DBOARD_EEPROM: - _tx_db_eeprom = val.as(); - _tx_db_eeprom.store(*_iface, I2C_ADDR_TX_A); - return; - - case DBOARD_PROP_GBOARD_EEPROM: - _gdb_eeprom = val.as(); - _gdb_eeprom.store(*_iface, I2C_ADDR_TX_A ^ 5); - return; - - default: UHD_THROW_PROP_SET_ERROR(); - } -} diff --git a/host/lib/usrp/usrp_b100/dsp_impl.cpp b/host/lib/usrp/usrp_b100/dsp_impl.cpp deleted file mode 100644 index c1bf6bedd..000000000 --- a/host/lib/usrp/usrp_b100/dsp_impl.cpp +++ /dev/null @@ -1,189 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "b100_impl.hpp" -#include "b100_regs.hpp" -#include -#include -#include -#include - -#define rint boost::math::iround - -using namespace uhd; -using namespace uhd::usrp; - -static const double MASTER_CLOCK_RATE = 64e6; //TODO get from clock control - -/*********************************************************************** - * RX DDC Initialization - **********************************************************************/ -void b100_impl::rx_ddc_init(void){ - _rx_ddc_proxy = wax_obj_proxy::make( - boost::bind(&b100_impl::rx_ddc_get, this, _1, _2), - boost::bind(&b100_impl::rx_ddc_set, this, _1, _2) - ); - - //initial config and update - rx_ddc_set(DSP_PROP_FREQ_SHIFT, double(0)); - rx_ddc_set(DSP_PROP_HOST_RATE, double(16e6)); -} - -/*********************************************************************** - * RX DDC Get - **********************************************************************/ -void b100_impl::rx_ddc_get(const wax::obj &key_, wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - switch(key.as()){ - case DSP_PROP_NAME: - val = std::string("USRP-B100 RX DSP"); - return; - - case DSP_PROP_OTHERS: - val = prop_names_t(); //empty - return; - - case DSP_PROP_FREQ_SHIFT: - val = _ddc_freq; - return; - - case DSP_PROP_CODEC_RATE: - val = _clock_ctrl->get_fpga_clock_rate(); - return; - - case DSP_PROP_HOST_RATE: - val = _clock_ctrl->get_fpga_clock_rate()/_ddc_decim; - return; - - default: UHD_THROW_PROP_GET_ERROR(); - } -} - -/*********************************************************************** - * RX DDC Set - **********************************************************************/ -void b100_impl::rx_ddc_set(const wax::obj &key_, const wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - switch(key.as()){ - case DSP_PROP_STREAM_CMD: - issue_stream_cmd(val.as()); - return; - - case DSP_PROP_FREQ_SHIFT:{ - double new_freq = val.as(); - _iface->poke32(B100_REG_DSP_RX_FREQ, - dsp_type1::calc_cordic_word_and_update(new_freq, _clock_ctrl->get_fpga_clock_rate()) - ); - _ddc_freq = new_freq; //shadow - } - return; - - case DSP_PROP_HOST_RATE:{ - //set the decimation - _ddc_decim = rint(_clock_ctrl->get_fpga_clock_rate()/val.as()); - _iface->poke32(B100_REG_DSP_RX_DECIM_RATE, dsp_type1::calc_cic_filter_word(_ddc_decim)); - - //set the scaling - static const boost::int16_t default_rx_scale_iq = 1024; - _iface->poke32(B100_REG_DSP_RX_SCALE_IQ, - dsp_type1::calc_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq) - ); - } - return; - - default: UHD_THROW_PROP_SET_ERROR(); - } -} - -/*********************************************************************** - * TX DUC Initialization - **********************************************************************/ -void b100_impl::tx_duc_init(void){ - _tx_duc_proxy = wax_obj_proxy::make( - boost::bind(&b100_impl::tx_duc_get, this, _1, _2), - boost::bind(&b100_impl::tx_duc_set, this, _1, _2) - ); - - //initial config and update - tx_duc_set(DSP_PROP_FREQ_SHIFT, double(0)); - tx_duc_set(DSP_PROP_HOST_RATE, double(16e6)); -} - -/*********************************************************************** - * TX DUC Get - **********************************************************************/ -void b100_impl::tx_duc_get(const wax::obj &key_, wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - switch(key.as()){ - case DSP_PROP_NAME: - val = std::string("USRP-B100 TX DSP"); - return; - - case DSP_PROP_OTHERS: - val = prop_names_t(); //empty - return; - - case DSP_PROP_FREQ_SHIFT: - val = _duc_freq; - return; - - case DSP_PROP_CODEC_RATE: - val = _clock_ctrl->get_fpga_clock_rate(); - return; - - case DSP_PROP_HOST_RATE: - val = _clock_ctrl->get_fpga_clock_rate()/_duc_interp; - return; - - default: UHD_THROW_PROP_GET_ERROR(); - } -} - -/*********************************************************************** - * TX DUC Set - **********************************************************************/ -void b100_impl::tx_duc_set(const wax::obj &key_, const wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - switch(key.as()){ - - case DSP_PROP_FREQ_SHIFT:{ - double new_freq = val.as(); - _iface->poke32(B100_REG_DSP_TX_FREQ, - dsp_type1::calc_cordic_word_and_update(new_freq, _clock_ctrl->get_fpga_clock_rate()) - ); - _duc_freq = new_freq; //shadow - } - return; - - case DSP_PROP_HOST_RATE:{ - _duc_interp = rint(_clock_ctrl->get_fpga_clock_rate()/val.as()); - - //set the interpolation - _iface->poke32(B100_REG_DSP_TX_INTERP_RATE, dsp_type1::calc_cic_filter_word(_duc_interp)); - - //set the scaling - _iface->poke32(B100_REG_DSP_TX_SCALE_IQ, dsp_type1::calc_iq_scale_word(_duc_interp)); - } - return; - - default: UHD_THROW_PROP_SET_ERROR(); - } -} diff --git a/host/lib/usrp/usrp_b100/io_impl.cpp b/host/lib/usrp/usrp_b100/io_impl.cpp deleted file mode 100644 index 3978bea75..000000000 --- a/host/lib/usrp/usrp_b100/io_impl.cpp +++ /dev/null @@ -1,210 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "../../transport/super_recv_packet_handler.hpp" -#include "../../transport/super_send_packet_handler.hpp" -#include "usrp_commands.h" -#include "b100_impl.hpp" -#include "b100_regs.hpp" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -using namespace uhd; -using namespace uhd::usrp; -using namespace uhd::transport; -namespace asio = boost::asio; - -/*********************************************************************** - * IO Implementation Details - **********************************************************************/ -struct b100_impl::io_impl{ - io_impl(zero_copy_if::sptr data_transport): - data_transport(data_transport) - { - /* NOP */ - } - - ~io_impl(void){ - //drain the rx buffs - //while(data_transport->get_recv_buff().get() != NULL){ - /* NOP */ - //} - } - - zero_copy_if::sptr &data_transport; - - sph::recv_packet_handler recv_handler; - sph::send_packet_handler send_handler; - bool continuous_streaming; -}; - -/*********************************************************************** - * Initialize internals within this file - **********************************************************************/ -void b100_impl::io_init(void){ - _recv_otw_type.width = 16; - _recv_otw_type.shift = 0; - _recv_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN; - - _send_otw_type.width = 16; - _send_otw_type.shift = 0; - _send_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN; - - _iface->reset_gpif(6); - - //reset state machines - _iface->poke32(B100_REG_CTRL_TX_CLEAR_UNDERRUN, 0); - _iface->poke32(B100_REG_CTRL_RX_CLEAR_OVERRUN, 0); - - _io_impl = UHD_PIMPL_MAKE(io_impl, (_data_transport)); - - //setup rx data path - _iface->poke32(B100_REG_CTRL_RX_NSAMPS_PER_PKT, get_max_recv_samps_per_packet()); - UHD_LOGV(always) << "IO: Using " << get_max_recv_samps_per_packet() << " samples per packet" << std::endl; - _iface->poke32(B100_REG_CTRL_RX_NCHANNELS, 1); - _iface->poke32(B100_REG_CTRL_RX_VRT_HEADER, 0 - | (0x1 << 28) //if data with stream id - | (0x1 << 26) //has trailer - | (0x3 << 22) //integer time other - | (0x1 << 20) //fractional time sample count - ); - _iface->poke32(B100_REG_CTRL_RX_VRT_TRAILER, 0); - - //set the streamid to reset the seq num - _iface->poke32(B100_REG_CTRL_TX_REPORT_SID, 0); - //setup the tx policy - _iface->poke32(B100_REG_CTRL_TX_POLICY, B100_FLAG_CTRL_TX_POLICY_NEXT_PACKET); - - //set the expected packet size in USB frames - _iface->poke32(B100_REG_MISC_RX_LEN, 4); - - update_transport_channel_mapping(); -} - -void b100_impl::update_transport_channel_mapping(void){ - if (_io_impl.get() == NULL) return; //not inited yet - - //set all of the relevant properties on the handler - boost::mutex::scoped_lock recv_lock = _io_impl->recv_handler.get_scoped_lock(); - _io_impl->recv_handler.resize(_rx_subdev_spec.size()); - _io_impl->recv_handler.set_vrt_unpacker(&vrt::if_hdr_unpack_le); - _io_impl->recv_handler.set_tick_rate(_clock_ctrl->get_fpga_clock_rate()); - _io_impl->recv_handler.set_samp_rate(_rx_ddc_proxy->get_link()[DSP_PROP_HOST_RATE].as()); - for (size_t chan = 0; chan < _io_impl->recv_handler.size(); chan++){ - _io_impl->recv_handler.set_xport_chan_get_buff(chan, boost::bind( - &uhd::transport::zero_copy_if::get_recv_buff, _io_impl->data_transport, _1 - )); - _io_impl->recv_handler.set_overflow_handler(chan, boost::bind( - &b100_impl::handle_overrun, this, chan - )); - } - _io_impl->recv_handler.set_converter(_recv_otw_type); - - //set all of the relevant properties on the handler - boost::mutex::scoped_lock send_lock = _io_impl->send_handler.get_scoped_lock(); - _io_impl->send_handler.resize(_tx_subdev_spec.size()); - _io_impl->send_handler.set_vrt_packer(&vrt::if_hdr_pack_le); - _io_impl->send_handler.set_tick_rate(_clock_ctrl->get_fpga_clock_rate()); - _io_impl->send_handler.set_samp_rate(_tx_duc_proxy->get_link()[DSP_PROP_HOST_RATE].as()); - for (size_t chan = 0; chan < _io_impl->send_handler.size(); chan++){ - _io_impl->send_handler.set_xport_chan_get_buff(chan, boost::bind( - &uhd::transport::zero_copy_if::get_send_buff, _io_impl->data_transport, _1 - )); - } - _io_impl->send_handler.set_converter(_send_otw_type); - _io_impl->send_handler.set_max_samples_per_packet(get_max_send_samps_per_packet()); -} - -/*********************************************************************** - * Data send + helper functions - **********************************************************************/ -size_t b100_impl::get_max_send_samps_per_packet(void) const { - static const size_t hdr_size = 0 - + vrt::max_if_hdr_words32*sizeof(boost::uint32_t) - - sizeof(vrt::if_packet_info_t().cid) //no class id ever used - ; - static const size_t bpp = 2048 - hdr_size; - return bpp / _send_otw_type.get_sample_size(); -} - -size_t b100_impl::send( - const send_buffs_type &buffs, size_t nsamps_per_buff, - const tx_metadata_t &metadata, const io_type_t &io_type, - send_mode_t send_mode, double timeout -){ - return _io_impl->send_handler.send( - buffs, nsamps_per_buff, - metadata, io_type, - send_mode, timeout - ); -} - -/*********************************************************************** - * Data recv + helper functions - **********************************************************************/ - -size_t b100_impl::get_max_recv_samps_per_packet(void) const { - static const size_t hdr_size = 0 - + vrt::max_if_hdr_words32*sizeof(boost::uint32_t) - + sizeof(vrt::if_packet_info_t().tlr) //forced to have trailer - - sizeof(vrt::if_packet_info_t().cid) //no class id ever used - ; - size_t bpp = 2048 - hdr_size; //limited by FPGA pkt buffer size - return bpp/_recv_otw_type.get_sample_size(); -} - -size_t b100_impl::recv( - const recv_buffs_type &buffs, size_t nsamps_per_buff, - rx_metadata_t &metadata, const io_type_t &io_type, - recv_mode_t recv_mode, double timeout -){ - return _io_impl->recv_handler.recv( - buffs, nsamps_per_buff, - metadata, io_type, - recv_mode, timeout - ); -} - -void b100_impl::issue_stream_cmd(const stream_cmd_t &stream_cmd) -{ - _io_impl->continuous_streaming = (stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_START_CONTINUOUS); - _iface->poke32(B100_REG_CTRL_RX_STREAM_CMD, dsp_type1::calc_stream_cmd_word(stream_cmd)); - _iface->poke32(B100_REG_CTRL_RX_TIME_SECS, boost::uint32_t(stream_cmd.time_spec.get_full_secs())); - _iface->poke32(B100_REG_CTRL_RX_TIME_TICKS, stream_cmd.time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate())); - - if (stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS) { - while(_io_impl->data_transport->get_recv_buff().get() != NULL){ - /* NOP */ - } - } -} - -void b100_impl::handle_overrun(size_t){ - if (_io_impl->continuous_streaming){ - this->issue_stream_cmd(stream_cmd_t::STREAM_MODE_START_CONTINUOUS); - } -} diff --git a/host/lib/usrp/usrp_b100/mboard_impl.cpp b/host/lib/usrp/usrp_b100/mboard_impl.cpp deleted file mode 100644 index c651ff2a2..000000000 --- a/host/lib/usrp/usrp_b100/mboard_impl.cpp +++ /dev/null @@ -1,246 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "b100_impl.hpp" -#include "usrp_commands.h" -#include "fpga_regs_standard.h" -#include "fpga_regs_common.h" -#include "b100_regs.hpp" -#include "usrp_i2c_addr.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -using namespace uhd; -using namespace uhd::usrp; - -static const bool b100_mboard_verbose = true; - -/*********************************************************************** - * Mboard Initialization - **********************************************************************/ -void b100_impl::mboard_init(void) -{ - _mboard_proxy = wax_obj_proxy::make( - boost::bind(&b100_impl::mboard_get, this, _1, _2), - boost::bind(&b100_impl::mboard_set, this, _1, _2)); - - //set the ticks per seconds into the vita time control - _iface->poke32(B100_REG_TIME64_TPS, - boost::uint32_t(_clock_ctrl->get_fpga_clock_rate()) - ); - - //init the clock config - _clock_config = clock_config_t::internal(); - update_clock_config(); -} - -void b100_impl::update_clock_config(void){ - boost::uint32_t pps_flags = 0; - - //translate pps polarity enums - switch(_clock_config.pps_polarity){ - case clock_config_t::PPS_POS: pps_flags |= B100_FLAG_TIME64_PPS_POSEDGE; break; - case clock_config_t::PPS_NEG: pps_flags |= B100_FLAG_TIME64_PPS_NEGEDGE; break; - default: throw uhd::runtime_error("unhandled clock configuration pps polarity"); - } - - //set the pps flags - _iface->poke32(B100_REG_TIME64_FLAGS, pps_flags); - - //clock source ref 10mhz - switch(_clock_config.ref_source){ - case clock_config_t::REF_AUTO: _clock_ctrl->use_auto_ref(); break; - case clock_config_t::REF_INT: _clock_ctrl->use_internal_ref(); break; - case clock_config_t::REF_SMA: _clock_ctrl->use_auto_ref(); break; - default: throw uhd::runtime_error("unhandled clock configuration ref source"); - } -} - -/*********************************************************************** - * Mboard Get - **********************************************************************/ -void b100_impl::mboard_get(const wax::obj &key_, wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - //handle the get request conditioned on the key - switch(key.as()){ - case MBOARD_PROP_NAME: - val = std::string("USRP-B100 mboard"); - return; - - case MBOARD_PROP_OTHERS: - val = prop_names_t(); - return; - - case MBOARD_PROP_RX_DBOARD: - UHD_ASSERT_THROW(key.name == ""); - val = _rx_dboard_proxy->get_link(); - return; - - case MBOARD_PROP_RX_DBOARD_NAMES: - val = prop_names_t(1, ""); //vector of size 1 with empty string - return; - - case MBOARD_PROP_TX_DBOARD: - UHD_ASSERT_THROW(key.name == ""); - val = _tx_dboard_proxy->get_link(); - return; - - case MBOARD_PROP_TX_DBOARD_NAMES: - val = prop_names_t(1, ""); //vector of size 1 with empty string - return; - - case MBOARD_PROP_RX_DSP: - UHD_ASSERT_THROW(key.name == ""); - val = _rx_ddc_proxy->get_link(); - return; - - case MBOARD_PROP_RX_DSP_NAMES: - val = prop_names_t(1, ""); - return; - - case MBOARD_PROP_TX_DSP: - UHD_ASSERT_THROW(key.name == ""); - val = _tx_duc_proxy->get_link(); - return; - - case MBOARD_PROP_TX_DSP_NAMES: - val = prop_names_t(1, ""); - return; - - case MBOARD_PROP_CLOCK_CONFIG: - val = _clock_config; - return; - - case MBOARD_PROP_RX_SUBDEV_SPEC: - val = _rx_subdev_spec; - return; - - case MBOARD_PROP_TX_SUBDEV_SPEC: - val = _tx_subdev_spec; - return; - - case MBOARD_PROP_EEPROM_MAP: - val = _iface->mb_eeprom; - return; - - case MBOARD_PROP_TIME_NOW:while(true){ - uint32_t secs = _iface->peek32(B100_REG_RB_TIME_NOW_SECS); - uint32_t ticks = _iface->peek32(B100_REG_RB_TIME_NOW_TICKS); - if (secs != _iface->peek32(B100_REG_RB_TIME_NOW_SECS)) continue; - val = time_spec_t(secs, ticks, _clock_ctrl->get_fpga_clock_rate()); - return; - } - - case MBOARD_PROP_TIME_PPS: while(true){ - uint32_t secs = _iface->peek32(B100_REG_RB_TIME_PPS_SECS); - uint32_t ticks = _iface->peek32(B100_REG_RB_TIME_PPS_TICKS); - if (secs != _iface->peek32(B100_REG_RB_TIME_PPS_SECS)) continue; - val = time_spec_t(secs, ticks, _clock_ctrl->get_fpga_clock_rate()); - return; - } - - case MBOARD_PROP_CLOCK_RATE: - val = _clock_ctrl->get_fpga_clock_rate(); - return; - - default: UHD_THROW_PROP_GET_ERROR(); - } -} - -/*********************************************************************** - * Mboard Set - **********************************************************************/ -void b100_impl::mboard_set(const wax::obj &key, const wax::obj &val) -{ - if(key.type() == typeid(std::string)) { - if(key.as() == "load_eeprom") { - std::string b100_eeprom_image = val.as(); - UHD_MSG(status) << "B100 EEPROM image: " << b100_eeprom_image << std::endl; - _fx2_ctrl->usrp_load_eeprom(val.as()); - } - return; - } - - //handle the get request conditioned on the key - switch(key.as()){ - case MBOARD_PROP_TIME_NOW: - case MBOARD_PROP_TIME_PPS:{ - time_spec_t time_spec = val.as(); - _iface->poke32(B100_REG_TIME64_TICKS, time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate())); - boost::uint32_t imm_flags = (key.as() == MBOARD_PROP_TIME_NOW)? 1 : 0; - _iface->poke32(B100_REG_TIME64_IMM, imm_flags); - _iface->poke32(B100_REG_TIME64_SECS, boost::uint32_t(time_spec.get_full_secs())); - } - return; - - case MBOARD_PROP_RX_SUBDEV_SPEC: - _rx_subdev_spec = val.as(); - verify_rx_subdev_spec(_rx_subdev_spec, _mboard_proxy->get_link()); - UHD_ASSERT_THROW(_rx_subdev_spec.size() == 1); - //set the mux - _iface->poke32(B100_REG_DSP_RX_MUX, dsp_type1::calc_rx_mux_word( - _dboard_manager->get_rx_subdev(_rx_subdev_spec.front().sd_name)[SUBDEV_PROP_CONNECTION].as() - )); - return; - - case MBOARD_PROP_TX_SUBDEV_SPEC: - _tx_subdev_spec = val.as(); - verify_tx_subdev_spec(_tx_subdev_spec, _mboard_proxy->get_link()); - UHD_ASSERT_THROW(_tx_subdev_spec.size() == 1); - //set the mux and set the number of tx channels - _iface->poke32(B100_REG_DSP_TX_MUX, dsp_type1::calc_tx_mux_word( - _dboard_manager->get_tx_subdev(_tx_subdev_spec.front().sd_name)[SUBDEV_PROP_CONNECTION].as() - )); - return; - - case MBOARD_PROP_EEPROM_MAP: - // Step1: commit the map, writing only those values set. - // Step2: readback the entire eeprom map into the iface. - val.as().commit(*_iface, mboard_eeprom_t::MAP_B000); - _iface->mb_eeprom = mboard_eeprom_t(*_iface, mboard_eeprom_t::MAP_B000); - return; - - case MBOARD_PROP_CLOCK_CONFIG: - _clock_config = val.as(); - update_clock_config(); - return; - - case MBOARD_PROP_CLOCK_RATE: - UHD_MSG(warning) - << "You are setting the master clock rate from the API.\n" - << "You may want to pass this into the device address as master_clock_rate=.\n" - << "This way, the clock rate is guaranteed to be initialized first.\n" - << "See the application notes for USRP-B100 for further instructions.\n" - ; - _clock_ctrl->set_fpga_clock_rate(val.as()); - update_transport_channel_mapping(); - return; - - default: UHD_THROW_PROP_SET_ERROR(); - } -} -- cgit v1.2.3 From 3fb011a261c76ec02681a44f35bf4882cf6cd71e Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 15 Jun 2011 14:11:18 -0700 Subject: b100: update find to match usrp1 style + features --- host/lib/usrp/b100/b100_impl.cpp | 39 +++++++++++++++++++++------------------ 1 file changed, 21 insertions(+), 18 deletions(-) diff --git a/host/lib/usrp/b100/b100_impl.cpp b/host/lib/usrp/b100/b100_impl.cpp index 772da8f42..7e733ddd9 100644 --- a/host/lib/usrp/b100/b100_impl.cpp +++ b/host/lib/usrp/b100/b100_impl.cpp @@ -54,20 +54,9 @@ static device_addrs_t b100_find(const device_addr_t &hint) //return an empty list of addresses when type is set to non-b100 if (hint.has_key("type") and hint["type"] != "b100") return b100_addrs; - //extract the firmware path for the b100 - std::string b100_fw_image; - try{ - b100_fw_image = find_image_path( - hint.has_key("fw")? hint["fw"] : "usrp_b100_fw.ihx" - ); - } - catch(...){ - UHD_MSG(warning) << boost::format( - "Could not locate B100 firmware.\n" - "Please install the images package.\n" - ); - return b100_addrs; - } + //Return an empty list of addresses when an address is specified, + //since an address is intended for a different, non-USB, device. + if (hint.has_key("addr")) return b100_addrs; boost::uint16_t vid = hint.has_key("uninit") ? FX2_VENDOR_ID : B100_VENDOR_ID; boost::uint16_t pid = hint.has_key("uninit") ? FX2_PRODUCT_ID : B100_PRODUCT_ID; @@ -80,11 +69,25 @@ static device_addrs_t b100_find(const device_addr_t &hint) //find the usrps and load firmware BOOST_FOREACH(usb_device_handle::sptr handle, usb_device_handle::get_device_list(vid, pid)) { - try { - fx2_ctrl::make(usb_control::make(handle))->usrp_load_firmware(b100_fw_image); - } catch (...) { - UHD_MSG(status) << "Interface claimed, ignoring device" << std::endl; + //extract the firmware path for the b100 + std::string b100_fw_image; + try{ + b100_fw_image = find_image_path(hint.get("fw", "usrp_b100_fw.ihx")); } + catch(...){ + UHD_MSG(warning) << boost::format( + "Could not locate B100 firmware.\n" + "Please install the images package.\n" + ); + return b100_addrs; + } + UHD_LOG << "the firmware image: " << b100_fw_image << std::endl; + + usb_control::sptr control; + try{control = usb_control::make(handle);} + catch(const uhd::exception &){continue;} //ignore claimed + + fx2_ctrl::make(control)->usrp_load_firmware(b100_fw_image); } //get descriptors again with serial number, but using the initialized VID/PID now since we have firmware -- cgit v1.2.3 From 27f1622d439ceb787e7dada733d0eb82270c5532 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 15 Jun 2011 14:49:51 -0700 Subject: b100: removed defunct test utilities --- host/utils/usrp1p_gpif_loopback.cpp | 111 ----------------------------- host/utils/usrp1p_poketest.cpp | 134 ------------------------------------ 2 files changed, 245 deletions(-) delete mode 100644 host/utils/usrp1p_gpif_loopback.cpp delete mode 100644 host/utils/usrp1p_poketest.cpp diff --git a/host/utils/usrp1p_gpif_loopback.cpp b/host/utils/usrp1p_gpif_loopback.cpp deleted file mode 100644 index 3b9da4304..000000000 --- a/host/utils/usrp1p_gpif_loopback.cpp +++ /dev/null @@ -1,111 +0,0 @@ -//USB->GPIF->FPGA loopback test for USRP1P -//uses UHD libusb transport - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -//so the goal is to open a USB device to endpoints (2,6), submit a buffer, receive a reply, and compare them. -//use usb_zero_copy::make() to get a usb_zero_copy object and then start submitting. -//need to get a usb dev handle to pass to make -//use static std::vector get_device_list(boost::uint16_t vid, boost::uint16_t pid) to get a device handle -//then get_send_buffer, send, etc. -using namespace uhd; -using namespace uhd::transport; - -const boost::uint16_t data_xfer_size = 32; -const boost::uint16_t ctrl_xfer_size = 32; - -int main(int argc, char *argv[]) { - std::cout << "USRP1+ GPIF loopback test" << std::endl; - //step 1: get a handle on it - std::vector handles = usb_device_handle::get_device_list(0xfffe, 0x0003); - if(handles.size() == 0) { - std::cout << "No USRP1+ found." << std::endl; - return ~0; - } - - bool verbose = false; - if(argc > 1) if(std::string(argv[1]) == "-v") verbose = true; - - usb_device_handle::sptr handle = handles.front(); - - usb_zero_copy::sptr data_transport; - usb_control::sptr ctrl_transport = usb_control::make(handle); //just in case - - data_transport = usb_zero_copy::make( - handle, // identifier - 8, // IN endpoint - 4, // OUT endpoint - uhd::device_addr_t("recv_frame_size=32, num_recv_frames=1, send_frame_size=32, num_send_frames=1") //args - ); - - if(verbose) std::cout << "Made." << std::endl; - - //ok now we're made. time to get a buffer and start sending data. - - boost::uint8_t localbuf[data_xfer_size]; - - managed_send_buffer::sptr sbuf; - managed_recv_buffer::sptr rbuf; - size_t xfercount = 0; - - srand(time(0)); - while(1) { - - if(verbose) std::cout << "Getting send buffer." << std::endl; - sbuf = data_transport->get_send_buff(); - if(sbuf == 0) { - std::cout << "Failed to get a send buffer." << std::endl; - return ~0; - } - for(int i = 0; i < data_xfer_size; i++) { - boost::uint8_t x = rand(); - sbuf->cast()[i] = x; - localbuf[i] = x; - } - - if(verbose) std::cout << "Buffer loaded" << std::endl; - - sbuf->commit(data_xfer_size); - if(verbose) std::cout << "Committed." << std::endl; - - rbuf = data_transport->get_recv_buff(0.3); //timeout - - if(rbuf == 0) { - std::cout << "Failed to get receive buffer (timeout?)" << std::endl; - return ~0; - } - - if(verbose) std::cout << "# " << xfercount << std::endl; - - if(!memcmp(rbuf->cast(), localbuf, data_xfer_size)) { - std::cout << "."; - } else { - if(verbose) { - int i = 0; - for(int j = 0; j < 32; j++) { - std::cout << boost::format("%02X ") % int(rbuf->cast()[i*32+j]); - } - std::cout << std::endl; - } - else std::cout << "x"; - - } - sbuf.reset(); - rbuf.reset(); - xfercount++; - //if(verbose) std::cout << "sptrs reset" << std::endl; - } - - return 0; -} diff --git a/host/utils/usrp1p_poketest.cpp b/host/utils/usrp1p_poketest.cpp deleted file mode 100644 index ca7628e01..000000000 --- a/host/utils/usrp1p_poketest.cpp +++ /dev/null @@ -1,134 +0,0 @@ -//FPGA register poke test for USRP1P -//uses UHD libusb transport - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../lib/usrp/usrp1p/ctrl_packet.hpp" - -//so the goal is to open a USB device to endpoints (2,6), submit a buffer, receive a reply, and compare them. -//use usb_zero_copy::make() to get a usb_zero_copy object and then start submitting. -//need to get a usb dev handle to pass to make -//use static std::vector get_device_list(boost::uint16_t vid, boost::uint16_t pid) to get a device handle -//then get_send_buffer, send, etc. -using namespace uhd; -using namespace uhd::transport; - -const boost::uint16_t ctrl_xfer_size = 32; - -int main(int argc, char *argv[]) { - std::cout << "USRP1+ GPIF poke test" << std::endl; - //step 1: get a handle on it - std::vector handles = usb_device_handle::get_device_list(0xfffe, 0x0003); - if(handles.size() == 0) { - std::cout << "No USRP1+ found." << std::endl; - return ~0; - } - - bool verbose = false; - if(argc > 1) if(std::string(argv[1]) == "-v") verbose = true; - - usb_device_handle::sptr handle = handles.front(); - - usb_zero_copy::sptr data_transport; - usb_control::sptr ctrl_transport = usb_control::make(handle); //just in case - - data_transport = usb_zero_copy::make( - handle, // identifier - 8, // IN endpoint - 4, // OUT endpoint - uhd::device_addr_t("recv_frame_size=32, num_recv_frames=1, send_frame_size=32, num_send_frames=1") //args - ); - - if(verbose) std::cout << "Made." << std::endl; - - //ok now we're made. time to get a buffer and start sending data. - - managed_send_buffer::sptr sbuf; - managed_recv_buffer::sptr rbuf; - size_t xfercount = 0; - - static uint8_t sequence = 0; - //uhd::usrp::ctrl_packet_out_t outpkt; - //memset(outpkt.data, 0x00, sizeof(outpkt.data)); -// outpkt.op = uhd::usrp::CTRL_PACKET_WRITE; -// outpkt.callbacks = 0; -// outpkt.seq = sequence++; -// outpkt.len = 4; -// outpkt.addr = 0x00000000; -// outpkt.data[0] = 0xff; -// outpkt.data[1] = 0xfe; -// outpkt.data[2] = 0xfd; -// outpkt.data[3] = 0xfc; - - boost::uint16_t outpkt[16]; - /* Packet format: - * Command: 2 bits - * Callbacks: 6 bits - * Seq num: 8 bits - * Length: 16 bits - * Addr LSW: 16 bits - * Addr MSW: 16 bits - * Data: 24 bytes/12 words - * Lengths are in lines - * - * readback: - * AA00 LEN(16) SEQ(16) ADDR(32) DATA(16bx12B) - */ - memset(outpkt, 0x00, sizeof(outpkt)); - outpkt[0] = 0x8000; //read cmd + callbacks (0) + seq - outpkt[1] = 0x0001; //len - outpkt[2] = 0x0000; //addr LSW - outpkt[3] = 0x0000; //addr MSW - outpkt[4] = 0x0A0A; //data - outpkt[5] = 0xFFFF; - - - srand(time(0)); -// while(1) { - - if(verbose) std::cout << "Getting send buffer." << std::endl; - sbuf = data_transport->get_send_buff(); - if(sbuf == 0) { - std::cout << "Failed to get a send buffer." << std::endl; - return ~0; - } - - for(int i = 0; i < ctrl_xfer_size; i++) { - sbuf->cast()[i] = ((boost::uint8_t *)&outpkt)[i]; - } - - if(verbose) std::cout << "Buffer loaded" << std::endl; - - sbuf->commit(ctrl_xfer_size); - if(verbose) std::cout << "Committed." << std::endl; - - rbuf = data_transport->get_recv_buff(0.3); //timeout - - if(rbuf == 0) { - std::cout << "Failed to get receive buffer (timeout?)" << std::endl; - return ~0; - } - - for(int j = 0; j < 32; j++) { - std::cout << boost::format("%02X ") % int(rbuf->cast()[j]); - } - std::cout << std::endl; - - sbuf.reset(); - rbuf.reset(); - xfercount++; - //if(verbose) std::cout << "sptrs reset" << std::endl; -// } - - return 0; -} -- cgit v1.2.3