From 1dc61299faa55e13e535fe20a035aed664084b16 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Tue, 22 Dec 2009 10:03:13 -0800
Subject: proper time sync to pps
---
timing/time_64bit.v | 33 +++++++++++++++++++++++++++++----
top/u2_core/u2_core.v | 2 +-
2 files changed, 30 insertions(+), 5 deletions(-)
diff --git a/timing/time_64bit.v b/timing/time_64bit.v
index ab0c12be6..84f79645c 100644
--- a/timing/time_64bit.v
+++ b/timing/time_64bit.v
@@ -6,11 +6,13 @@ module time_64bit
(input clk, input rst,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
input pps,
- output [63:0] vita_time
+ output [63:0] vita_time, output pps_int
);
- localparam NEXT_TICKS = 1;
localparam NEXT_SECS = 0;
+ localparam NEXT_TICKS = 1;
+ localparam PPS_POL = 2;
+
localparam ROLLOVER = TICKS_PER_SEC - 1;
reg [31:0] seconds;
@@ -22,6 +24,7 @@ module time_64bit
wire [31:0] next_seconds_preset;
wire set_on_pps_trig;
reg set_on_next_pps;
+ wire pps_polarity;
setting_reg #(.my_addr(BASE+NEXT_TICKS)) sr_next_ticks
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
@@ -30,13 +33,33 @@ module time_64bit
setting_reg #(.my_addr(BASE+NEXT_SECS)) sr_next_secs
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(next_seconds_preset),.changed(set_on_pps_trig));
+
+ setting_reg #(.my_addr(BASE+PPS_POL)) sr_pps_pol
+ (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(pps_polarity),.changed());
+
+ reg [1:0] pps_del;
+ reg pps_reg_p, pps_reg_n, pps_reg;
+ wire pps_edge;
+
+ always @(posedge clk) pps_reg_p <= pps;
+ always @(negedge clk) pps_reg_n <= pps;
+ always @* pps_reg <= pps_polarity ? pps_reg_p : pps_reg_n;
+
+ always @(posedge clk)
+ if(rst)
+ pps_del <= 2'b00;
+ else
+ pps_del <= {pps_del[0],pps_reg};
+
+ assign pps_edge = pps_del[0] & ~pps_del[1];
always @(posedge clk)
if(rst)
set_on_next_pps <= 0;
else if(set_on_pps_trig)
set_on_next_pps <= 1;
- else if(pps)
+ else if(pps_edge)
set_on_next_pps <= 0;
always @(posedge clk)
@@ -45,7 +68,7 @@ module time_64bit
seconds <= 32'd0;
ticks <= 32'd0;
end
- else if(pps & set_on_next_pps)
+ else if(pps_edge & set_on_next_pps)
begin
seconds <= next_seconds_preset;
ticks <= next_ticks_preset;
@@ -57,5 +80,7 @@ module time_64bit
end
else
ticks <= ticks + 1;
+
+ assign pps_int = pps_edge;
endmodule // time_64bit
diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v
index f9ac07a55..2fa490d26 100644
--- a/top/u2_core/u2_core.v
+++ b/top/u2_core/u2_core.v
@@ -678,7 +678,7 @@ module u2_core
time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
(.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
- .pps(pps_o), .vita_time(vita_time));
+ .pps(pps_o), .vita_time(vita_time), .pps_int());
// /////////////////////////////////////////////////////////////////////////////////////////
// Debug Pins
--
cgit v1.2.3
From 3df028c652bb5e138aeb9cbc3e26bd26ab314120 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 18 Jan 2010 16:07:48 -0800
Subject: allow processor to read back vrt time over readback mux
---
top/u2_core/u2_core.v | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v
index 2fa490d26..8cd150cb6 100644
--- a/top/u2_core/u2_core.v
+++ b/top/u2_core/u2_core.v
@@ -412,8 +412,8 @@ module u2_core
.word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
.word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
- .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0),
- .word11(32'b0),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count)
+ .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]),
+ .word11(vita_time[31:0]),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count)
);
// /////////////////////////////////////////////////////////////////////////
--
cgit v1.2.3
From 7ebcf79e38fabfbf689f1acc43052e635c6ad08d Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 18 Jan 2010 16:08:20 -0800
Subject: allow setting time immediately in cases where there is no external
pps input
---
timing/time_64bit.v | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/timing/time_64bit.v b/timing/time_64bit.v
index 84f79645c..f689d7700 100644
--- a/timing/time_64bit.v
+++ b/timing/time_64bit.v
@@ -25,7 +25,8 @@ module time_64bit
wire set_on_pps_trig;
reg set_on_next_pps;
wire pps_polarity;
-
+ wire set_imm;
+
setting_reg #(.my_addr(BASE+NEXT_TICKS)) sr_next_ticks
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(next_ticks_preset),.changed());
@@ -36,7 +37,7 @@ module time_64bit
setting_reg #(.my_addr(BASE+PPS_POL)) sr_pps_pol
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
- .in(set_data),.out(pps_polarity),.changed());
+ .in(set_data),.out({set_imm,pps_polarity}),.changed());
reg [1:0] pps_del;
reg pps_reg_p, pps_reg_n, pps_reg;
@@ -59,7 +60,7 @@ module time_64bit
set_on_next_pps <= 0;
else if(set_on_pps_trig)
set_on_next_pps <= 1;
- else if(pps_edge)
+ else if(set_imm | pps_edge)
set_on_next_pps <= 0;
always @(posedge clk)
@@ -68,7 +69,7 @@ module time_64bit
seconds <= 32'd0;
ticks <= 32'd0;
end
- else if(pps_edge & set_on_next_pps)
+ else if((set_imm | pps_edge) & set_on_next_pps)
begin
seconds <= next_seconds_preset;
ticks <= next_ticks_preset;
--
cgit v1.2.3
From 89045982438e2fee8bd56b28a55c7b1c9a013a04 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 18 Jan 2010 17:56:55 -0800
Subject: remove time_sync and master_timer.
Master timer replaced with simple_timer which needs new memory map and control
functions. it allows onetime and periodic interrupts. Copied from quad_radio
time_sync functionality will go in time_64bit. Right now it only does
external SMA connector, not mimo connector
---
timing/simple_timer.v | 60 +++++++++++++++++++++++++++++++++++++++++++++++++++
top/u2_core/u2_core.v | 41 ++++++++++++++++++-----------------
top/u2_rev3/Makefile | 3 +--
3 files changed, 82 insertions(+), 22 deletions(-)
create mode 100644 timing/simple_timer.v
diff --git a/timing/simple_timer.v b/timing/simple_timer.v
new file mode 100644
index 000000000..17c7f1c36
--- /dev/null
+++ b/timing/simple_timer.v
@@ -0,0 +1,60 @@
+
+
+module simple_timer
+ #(parameter BASE=0)
+ (input clk, input reset,
+ input set_stb, input [7:0] set_addr, input [31:0] set_data,
+ output reg onetime_int, output reg periodic_int);
+
+ reg [31:0] onetime_ctr;
+ always @(posedge clk)
+ if(reset)
+ begin
+ onetime_int <= 0;
+ onetime_ctr <= 0;
+ end
+ else
+ if(set_stb & (set_addr == BASE))
+ begin
+ onetime_int <= 0;
+ onetime_ctr <= set_data;
+ end
+ else
+ begin
+ if(onetime_ctr == 1)
+ onetime_int <= 1;
+ if(onetime_ctr != 0)
+ onetime_ctr <= onetime_ctr - 1;
+ else
+ onetime_int <= 0;
+ end // else: !if(set_stb & (set_addr == BASE))
+
+ reg [31:0] periodic_ctr, period;
+ always @(posedge clk)
+ if(reset)
+ begin
+ periodic_int <= 0;
+ periodic_ctr <= 0;
+ period <= 0;
+ end
+ else
+ if(set_stb & (set_addr == (BASE+1)))
+ begin
+ periodic_int <= 0;
+ periodic_ctr <= set_data;
+ period <= set_data;
+ end
+ else
+ if(periodic_ctr == 1)
+ begin
+ periodic_int <= 1;
+ periodic_ctr <= period;
+ end
+ else
+ if(periodic_ctr != 0)
+ begin
+ periodic_int <= 0;
+ periodic_ctr <= periodic_ctr - 1;
+ end
+
+endmodule // simple_timer
diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v
index 8cd150cb6..e384e2b93 100644
--- a/top/u2_core/u2_core.v
+++ b/top/u2_core/u2_core.v
@@ -141,6 +141,7 @@ module u2_core
localparam SR_TX_DSP = 208;
localparam SR_TX_CTRL = 224;
localparam SR_TIME64 = 192;
+ localparam SR_SIMTIMER = 198;
wire [7:0] set_addr;
wire [31:0] set_data;
@@ -150,7 +151,8 @@ module u2_core
wire ram_loader_rst, wb_rst, dsp_rst;
wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7;
- wire bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int;
+ wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int;
+ wire proc_int, overrun, underrun, uart_tx_int, uart_rx_int;
wire [31:0] debug_gpio_0, debug_gpio_1;
wire [31:0] atr_lines;
@@ -481,8 +483,8 @@ module u2_core
assign irq= {{8'b0},
{8'b0},
- {4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int},
- {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}};
+ {3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int},
+ {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}};
pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]),
.we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
@@ -491,13 +493,25 @@ module u2_core
// /////////////////////////////////////////////////////////////////////////
// Master Timer, Slave #9
+ // No longer used, replaced with simple_timer below
+ /*
wire [31:0] master_time;
timer timer
(.wb_clk_i(wb_clk),.rst_i(wb_rst),
.cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]),
.we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack),
.sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) );
-
+ */
+ assign s9_ack = 0;
+
+ // /////////////////////////////////////////////////////////////////////////
+ // Simple Timer interrupts
+
+ simple_timer #(.BASE(SR_SIMTIMER)) simple_timer
+ (.clk(wb_clk), .reset(wb_rst),
+ .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+ .onetime_int(onetime_int), .periodic_int(periodic_int));
+
// /////////////////////////////////////////////////////////////////////////
// UART, Slave #10
@@ -525,22 +539,9 @@ module u2_core
// //////////////////////////////////////////////////////////////////////////
// Time Sync, Slave #12
- reg pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1;
- always @(negedge dsp_clk) pps_negedge <= pps_in;
- always @(posedge dsp_clk) pps_posedge <= pps_in;
- always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge;
- always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge;
+ // No longer used, see time_64bit. Still need to handle mimo time, though
+ assign sc_ack = 0;
- wire pps_o;
- time_sync time_sync
- (.wb_clk_i(wb_clk),.rst_i(wb_rst),
- .cyc_i(sc_cyc),.stb_i(sc_stb),.adr_i(sc_adr[4:2]),
- .we_i(sc_we),.dat_i(sc_dat_o),.dat_o(sc_dat_i),.ack_o(sc_ack),
- .sys_clk_i(dsp_clk),.master_time_o(master_time),
- .pps_posedge(pps_posedge),.pps_negedge(pps_negedge),
- .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out),
- .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) );
-
// /////////////////////////////////////////////////////////////////////////
// SD Card Reader / Writer, Slave #13
@@ -678,7 +679,7 @@ module u2_core
time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
(.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
- .pps(pps_o), .vita_time(vita_time), .pps_int());
+ .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int));
// /////////////////////////////////////////////////////////////////////////////////////////
// Debug Pins
diff --git a/top/u2_rev3/Makefile b/top/u2_rev3/Makefile
index 1f8bbe304..57d55106f 100644
--- a/top/u2_rev3/Makefile
+++ b/top/u2_rev3/Makefile
@@ -179,8 +179,7 @@ timing/time_64bit.v \
timing/time_compare.v \
timing/time_receiver.v \
timing/time_sender.v \
-timing/time_sync.v \
-timing/timer.v \
+timing/simple_timer.v \
top/u2_core/u2_core.v \
top/u2_rev3/u2_rev3.ucf \
top/u2_rev3/u2_rev3.v
--
cgit v1.2.3
From 58e218765a67aadb12224bd512f1592ce0736ed6 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 18 Jan 2010 18:01:45 -0800
Subject: moved around regs, added a bit to allow for alternate PPS source
---
timing/time_64bit.v | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/timing/time_64bit.v b/timing/time_64bit.v
index f689d7700..8ccde3f54 100644
--- a/timing/time_64bit.v
+++ b/timing/time_64bit.v
@@ -11,7 +11,8 @@ module time_64bit
localparam NEXT_SECS = 0;
localparam NEXT_TICKS = 1;
- localparam PPS_POL = 2;
+ localparam PPS_POLSRC = 2;
+ localparam PPS_IMM = 3;
localparam ROLLOVER = TICKS_PER_SEC - 1;
@@ -26,7 +27,8 @@ module time_64bit
reg set_on_next_pps;
wire pps_polarity;
wire set_imm;
-
+ wire pps_source;
+
setting_reg #(.my_addr(BASE+NEXT_TICKS)) sr_next_ticks
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(next_ticks_preset),.changed());
@@ -35,9 +37,13 @@ module time_64bit
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(next_seconds_preset),.changed(set_on_pps_trig));
- setting_reg #(.my_addr(BASE+PPS_POL)) sr_pps_pol
+ setting_reg #(.my_addr(BASE+PPS_POLSRC)) sr_pps_polsrc
+ (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out({pps_source,pps_polarity}),.changed());
+
+ setting_reg #(.my_addr(BASE+PPS_IMM)) sr_pps_imm
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
- .in(set_data),.out({set_imm,pps_polarity}),.changed());
+ .in(set_data),.out(set_imm),.changed());
reg [1:0] pps_del;
reg pps_reg_p, pps_reg_n, pps_reg;
--
cgit v1.2.3
From cb3b628f8d096ab2a843a804189037c495532ac9 Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Mon, 18 Jan 2010 20:02:04 -0800
Subject: Added set time and set time at next pps. Removed the old sync pps
commands, they dont make sense to use anymore.
Replaced the mimo config with clock config.
The clock config handles the pps and the reference.
Modified the memory map and internal calls to reflect the fpga changes.
---
top/u2_core/u2_core.v | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v
index e384e2b93..591c10232 100644
--- a/top/u2_core/u2_core.v
+++ b/top/u2_core/u2_core.v
@@ -630,7 +630,7 @@ module u2_core
// ///////////////////////////////////////////////////////////////////////////////////
// SERDES
-/*
+
serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes
(.clk(dsp_clk),.rst(dsp_rst),
.ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
@@ -640,7 +640,7 @@ module u2_core
.tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty),
.rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
.serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) );
-*/
+
// ///////////////////////////////////////////////////////////////////////////////////
// External RAM Interface
--
cgit v1.2.3
From 8d19387a8642caf74179bdcb7eddf1936f473e53 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Tue, 19 Jan 2010 18:08:37 -0800
Subject: speed up timing by ignoring the too_early error. We'll need to FIXME
this later
---
vrt/vita_tx_control.v | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/vrt/vita_tx_control.v b/vrt/vita_tx_control.v
index 6776e26e5..bffc64e52 100644
--- a/vrt/vita_tx_control.v
+++ b/vrt/vita_tx_control.v
@@ -29,10 +29,13 @@ module vita_tx_control
wire sob = sample_fifo_i[66];
wire send_at = sample_fifo_i[67];
wire now, early, late, too_early;
-
+
+ // FIXME ignore too_early for now for timing reasons
+ assign too_early = 0;
time_compare
time_compare (.time_now(vita_time), .trigger_time(send_time), .now(now), .early(early),
- .late(late), .too_early(too_early));
+ .late(late), .too_early());
+// .late(late), .too_early(too_early));
localparam IBS_IDLE = 0;
localparam IBS_RUN = 1; // FIXME do we need this?
--
cgit v1.2.3