summaryrefslogtreecommitdiffstats
path: root/vrt
Commit message (Expand)AuthorAgeFilesLines
* cleaned up the main ibs state machineMatt Ettus2009-12-141-9/+22
* dsp_core_tx now has setting reg base settable from u2_core. underrun bug in ...Matt Ettus2009-12-141-1/+1
* reorder the memory mapMatt Ettus2009-12-112-2/+2
* put new setting reg into the address space in the right placeMatt Ettus2009-12-111-1/+1
* only pull from input fifo when really consuming or pushing into the next fifoMatt Ettus2009-12-111-1/+1
* Add ability to clear state out when there is an underrunMatt Ettus2009-12-111-1/+6
* fixed typo in u2_core.v resulting in unconnected net. added debug pinsMatt Ettus2009-12-112-3/+16
* ignore save filesMatt Ettus2009-12-091-0/+1
* First cut at vita tx, whole thing compilesMatt Ettus2009-12-091-0/+1
* very basic packet sending worksMatt Ettus2009-12-092-140/+50
* seems to correctly deframe packets. now need to consume them.Matt Ettus2009-12-081-12/+23
* progress on vita_tx. it compiles now, need to work on vita_tx_control.Matt Ettus2009-12-083-239/+182
* make the testbench work in this environment, without the crossclock settings busMatt Ettus2009-12-083-5/+8
* be a little more PC about itMatt Ettus2009-11-181-5/+9
* mostly just copied over from the rx side. Still needs a lot of work.Matt Ettus2009-11-183-13/+221
* VITA49 rx (and tx skeleton) copied over from quad radioMatt Ettus2009-11-057-0/+1026
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 18:25:29 +0000