aboutsummaryrefslogtreecommitdiffstats
path: root/usrp2
Commit message (Collapse)AuthorAgeFilesLines
* all: removed old unused fifosMatt Ettus2011-03-0313-1140/+1
|
* all: short fifos on front and back of fifo36_to_fifo19Matt Ettus2011-03-031-15/+33
|
* u2plus: catch up with ethfifo changes which were on u2Matt Ettus2011-03-031-39/+4
|
* u2/u2p: remove duplicated short fifoMatt Ettus2011-03-031-13/+4
|
* u2/u2p: shortfifos in fifo36_to_ll8, no more _n junkMatt Ettus2011-03-032-36/+45
|
* make big tx fifo the one doing the clock crossingMatt Ettus2011-03-032-12/+4
|
* u2/u2p: rxdsp/cpu/err muxing now prioritizes cpu and err over rxdspMatt Ettus2011-03-031-7/+10
|
* u2/u2p: removed unneeded eth rx fifoMatt Ettus2011-03-031-10/+4
|
* u2/u2p: switch over to 36 bit wide ethernet wrapperMatt Ettus2011-03-033-79/+85
|
* Merge branch 'ethfifo_reorg' of ettus.sourcerepo.com:ettus/fpgapriv into ↵Matt Ettus2011-03-031-5/+6
|\ | | | | | | | | | | | | ethfifo_reorg * 'ethfifo_reorg' of ettus.sourcerepo.com:ettus/fpgapriv: ethfifo_reorg: switch buffer int2 lastline to work as a length parameter
| * ethfifo_reorg: switch buffer int2 lastline to work as a length parameterJosh Blum2011-03-031-5/+6
| |
* | u2/u2p: packet realignment moved into the simple_gemac_wrapper19Matt Ettus2011-03-032-13/+10
|/
* u2/u2p: get rid of redeclarationMatt Ettus2011-03-031-1/+0
|
* u2/u2p: ll8 now all active high, removed extra shortfifo from eth wrapperMatt Ettus2011-03-032-29/+10
|
* u2/u2p: short fifos put on both sides of ll8_to_fifo19Matt Ettus2011-03-031-27/+44
|
* u2/u2p: shrunk ETH TX FIFO, further u2/u2p harmonizationMatt Ettus2011-02-213-20/+19
|
* u2/u2p: inserted short fifo into the packet inspector path to help routing ↵Matt Ettus2011-02-171-1/+13
| | | | and timing
* increase compat number for double dsp changeMatt Ettus2011-02-172-2/+2
|
* u2/u2p: reduce unneeded RX DSP bufferingMatt Ettus2011-02-172-2/+2
|
* u2p: 2nd DSP now in u2p as wellMatt Ettus2011-02-171-25/+56
|
* added port_sel param to dsp framerJosh Blum2011-02-172-4/+5
|
* u2/u2p: added 2nd DSP unitMatt Ettus2011-02-171-0/+34
|
* u2/u2p: renamed and split some rx signals to prepare for 2nd DSPMatt Ettus2011-02-171-25/+22
|
* u2/u2p: proper hookup of vita_rx_chainMatt Ettus2011-02-173-12/+12
|
* clean up rx dsp and some other nets in prep for dual dspMatt Ettus2011-02-164-86/+98
|
* register map changes to fit in the 2nd rx dspMatt Ettus2011-02-151-15/+19
|
* packet_router: added support for two dsps into routerJosh Blum2011-02-153-16/+24
|
* separate clear for tx and rx, and add a global reset from the hostMatt Ettus2011-02-021-10/+19
|
* usrp-e100: added missing newfifo files to list, added missing signals for timedJosh Blum2011-01-262-1/+7
|
* usrp-e100: added 32bit test read/write register, fixes to get buildingJosh Blum2011-01-251-7/+17
|
* reorganized u1e register space to make room for 64 settingregsMatt Ettus2011-01-251-12/+15
|
* believed to fix fifo swizzling with partially empty linesMatt Ettus2011-01-213-25/+114
|
* usrp-e100: added readback mux 32 as slave 7 for time readbackJosh Blum2011-01-143-4/+90
| | | | | created new component wb_readback_mux_16LE.v for 16 wide bus connected vita time pps to vita time controller and readbacks
* xbar and valve: fix switching delayed by active signalJosh Blum2011-01-112-9/+12
|
* usrp-n210: added power-on-reset controller, reset all wb perifsJosh Blum2011-01-101-10/+13
|
* usrp-n210: uploaded most recent bootloader rmiJosh Blum2011-01-101-167/+204
|
* usrp-n210: use cpu rst on the wb+icap, uploaded latest bootloader rmiJosh Blum2011-01-092-169/+172
|
* packet_router: tweak mode SR (its only 1 bit)Josh Blum2011-01-071-3/+2
|
* Merge branch 'cordic_policy' into nextJosh Blum2011-01-045-49/+83
|\ | | | | | | | | | | Conflicts: usrp2/top/u2_rev3/u2_core.v usrp2/top/u2plus/u2plus_core.v
| * hook up sampled pps in u2plus, remove unused priority encoder, minor cleanupsMatt Ettus2010-12-302-26/+18
| |
| * processor can read back vita_time at last ppsMatt Ettus2010-12-302-11/+11
| |
| * run should actually turn on now any time in the IBS_RUN stateMatt Ettus2010-12-291-11/+8
| |
| * gyrations to get it to meet timingMatt Ettus2010-12-291-13/+23
| |
| * should keep cordic spinning and the rest of the tx going throughMatt Ettus2010-12-281-4/+33
| | | | | | | | underruns. There is a timeout so it won't go forever.
* | usrp-n210: checked in updated bootloader (from next with fixes)Josh Blum2010-12-311-36/+36
| |
* | usrp2: removed unused changed signal for mode selectionJosh Blum2010-12-291-2/+1
| |
* | packet_router: replace buffers interfaced in packet router with buffer_int2Josh Blum2010-12-283-163/+25
| |
* | now uses 2 rams, one for read, one for writeMatt Ettus2010-12-281-89/+97
| |
* | reformattingMatt Ettus2010-12-281-5/+1
| |
* | first cut at new buffer interface for CPU. Like old buffer_int plusMatt Ettus2010-12-281-0/+169
| | | | | | | | a single buffer.
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 17:33:35 +0000