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* bigger fifo on UDP TX path, to possibly fix overruns on decim=4Matt Ettus2010-03-241-2/+11
* Xilinx ISE is incorrectly parsing the verilog case statement, this is a worka...Matt Ettus2010-03-241-1/+7
* pps and vita time debug pinsMatt Ettus2010-03-231-3/+6
* more debug for fixing E'sMatt Ettus2010-03-102-6/+13
* better debug pins for going after cascading E'sMatt Ettus2010-03-101-1/+5
* copied over from quad radioMatt Ettus2010-02-081-0/+60
* Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udpMatt Ettus2010-01-254-34/+43
* just debug pin changesMatt Ettus2010-01-252-1/+12
* typo caused the tx udp chain to be disconnectedMatt Ettus2010-01-231-1/+1
* moved into subdirJosh Blum2010-01-22653-0/+1558662