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* u2/u2p: moved dsp framer into vita_rx_chainMatt Ettus2011-03-055-55/+26
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* u2/u2p: rework ports againMatt Ettus2011-03-041-3/+3
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* u2/u2p: reworked port names on packet_routerMatt Ettus2011-03-041-3/+3
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* u2/u2p: reworked dsp framer to work more like a fifo, and do vita length ↵Matt Ettus2011-03-041-87/+56
| | | | correction
* u2/u2p: allow cpu to receive or send packets longer than the buffer size.Matt Ettus2011-03-041-7/+10
| | | | on reception, the rest is dropped. On sending, the rest is a repeat of the buffer.
* make fifo36_to_ll8 properly handle partial end lines.Matt Ettus2011-03-042-152/+31
| | | | I could swear I've fixed this before...
* Merge branch 'gpmc_testing' into ethfifo_reorgMatt Ettus2011-03-0314-174/+243
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | * gpmc_testing: timed packet generator : Temporarily use a checksum rather than a crc to validate packet integrity. correct port names fifo36_mux now has shortfifos on the input ports as well as output timed tester : Bring out src/dst flags for rx chain for testing. u1e: hook up tester controls move declarations to before use hook up under/overruns for debug purposes e100: integrate loopback and timed testing into main image Fix endianess for packet length and sequence number for e100 timed image. put these files in the right place. newfifo is long gone.
| * timed packet generator : Temporarily use a checksum rather than a crc to ↵Philip Balister2011-02-261-3/+9
| | | | | | | | validate packet integrity.
| * correct port namesMatt Ettus2011-02-251-2/+2
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| * fifo36_mux now has shortfifos on the input ports as well as outputMatt Ettus2011-02-253-18/+28
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| * timed tester : Bring out src/dst flags for rx chain for testing.Philip Balister2011-02-252-1/+15
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| * u1e: hook up tester controlsMatt Ettus2011-02-172-9/+13
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| * move declarations to before useMatt Ettus2011-02-161-8/+8
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| * hook up under/overruns for debug purposesMatt Ettus2011-02-162-8/+12
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| * e100: integrate loopback and timed testing into main imageMatt Ettus2011-02-165-81/+112
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| * Fix endianess for packet length and sequence number for e100 timed image.Philip Balister2011-02-161-8/+8
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| * put these files in the right place. newfifo is long gone.Matt Ettus2011-02-169-5/+5
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* | remove references to old directoryMatt Ettus2011-03-036-7/+1
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* | all: removed old unused fifosMatt Ettus2011-03-0313-1140/+1
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* | all: short fifos on front and back of fifo36_to_fifo19Matt Ettus2011-03-031-15/+33
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* | u2plus: catch up with ethfifo changes which were on u2Matt Ettus2011-03-031-39/+4
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* | u2/u2p: remove duplicated short fifoMatt Ettus2011-03-031-13/+4
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* | u2/u2p: shortfifos in fifo36_to_ll8, no more _n junkMatt Ettus2011-03-032-36/+45
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* | make big tx fifo the one doing the clock crossingMatt Ettus2011-03-032-12/+4
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* | u2/u2p: rxdsp/cpu/err muxing now prioritizes cpu and err over rxdspMatt Ettus2011-03-031-7/+10
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* | u2/u2p: removed unneeded eth rx fifoMatt Ettus2011-03-031-10/+4
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* | u2/u2p: switch over to 36 bit wide ethernet wrapperMatt Ettus2011-03-033-79/+85
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* | Merge branch 'ethfifo_reorg' of ettus.sourcerepo.com:ettus/fpgapriv into ↵Matt Ettus2011-03-031-5/+6
|\ \ | | | | | | | | | | | | | | | | | | ethfifo_reorg * 'ethfifo_reorg' of ettus.sourcerepo.com:ettus/fpgapriv: ethfifo_reorg: switch buffer int2 lastline to work as a length parameter
| * | ethfifo_reorg: switch buffer int2 lastline to work as a length parameterJosh Blum2011-03-031-5/+6
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* | | u2/u2p: packet realignment moved into the simple_gemac_wrapper19Matt Ettus2011-03-032-13/+10
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* | u2/u2p: get rid of redeclarationMatt Ettus2011-03-031-1/+0
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* | u2/u2p: ll8 now all active high, removed extra shortfifo from eth wrapperMatt Ettus2011-03-032-29/+10
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* | u2/u2p: short fifos put on both sides of ll8_to_fifo19Matt Ettus2011-03-031-27/+44
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* | u2/u2p: shrunk ETH TX FIFO, further u2/u2p harmonizationMatt Ettus2011-02-213-20/+19
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* | u2/u2p: inserted short fifo into the packet inspector path to help routing ↵Matt Ettus2011-02-171-1/+13
| | | | | | | | and timing
* | increase compat number for double dsp changeMatt Ettus2011-02-172-2/+2
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* | u2/u2p: reduce unneeded RX DSP bufferingMatt Ettus2011-02-172-2/+2
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* | u2p: 2nd DSP now in u2p as wellMatt Ettus2011-02-171-25/+56
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* | added port_sel param to dsp framerJosh Blum2011-02-172-4/+5
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* | u2/u2p: added 2nd DSP unitMatt Ettus2011-02-171-0/+34
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* | u2/u2p: renamed and split some rx signals to prepare for 2nd DSPMatt Ettus2011-02-171-25/+22
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* | u2/u2p: proper hookup of vita_rx_chainMatt Ettus2011-02-173-12/+12
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* | clean up rx dsp and some other nets in prep for dual dspMatt Ettus2011-02-164-86/+98
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* | register map changes to fit in the 2nd rx dspMatt Ettus2011-02-151-15/+19
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* | packet_router: added support for two dsps into routerJosh Blum2011-02-153-16/+24
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* separate clear for tx and rx, and add a global reset from the hostMatt Ettus2011-02-021-10/+19
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* usrp-e100: added missing newfifo files to list, added missing signals for timedJosh Blum2011-01-262-1/+7
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* usrp-e100: added 32bit test read/write register, fixes to get buildingJosh Blum2011-01-251-7/+17
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* reorganized u1e register space to make room for 64 settingregsMatt Ettus2011-01-251-12/+15
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* believed to fix fifo swizzling with partially empty linesMatt Ettus2011-01-213-25/+114
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