| Commit message (Collapse) | Author | Age | Files | Lines | |
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| * | added pragmas suggested by Ian Buckley to help ISE12 synthesis | Matt Ettus | 2010-05-18 | 1 | -3/+6 |
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| * | get rid of old CVS linkage | Matt Ettus | 2010-05-18 | 221 | -315/+0 |
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| * | settings bus to dsp_clk now uses clock crossing fifo | Matt Ettus | 2010-05-16 | 2 | -8/+15 |
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| * | remove files for old prototypes, they were confusing people | Matt Ettus | 2010-05-13 | 10 | -2076/+0 |
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| * | revert commit 9899b81f920 which should have improved timing but didn't | Matt Ettus | 2010-05-13 | 1 | -5/+13 |
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| * | remove port which is no longer there | Matt Ettus | 2010-05-11 | 1 | -1/+1 |
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| * | cleaned up the logic, this is copied over from quad radio | Matt Ettus | 2010-05-11 | 1 | -13/+5 |
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| * | allow settings bus to cross to a new clock domain, should help timing, but ↵ | Matt Ettus | 2010-05-11 | 9 | -0/+534 |
| | | | | | not attached yet | ||||
| * | Update config to all eight clock buffers to be used. | Johnathan Corgan | 2010-03-29 | 1 | -1/+1 |
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| * | Added timing constraint for Wishbone clock/dsp_clock skew | Johnathan Corgan | 2010-03-29 | 1 | -0/+2 |
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| * | Merge commit 'upstream/master' | Johnathan Corgan | 2010-03-09 | 1 | -1/+1 |
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| | * | proper initialization of the ram | Matt Ettus | 2010-02-23 | 1 | -1/+1 |
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| * | | Cut debug bus connection to etherenet MAC to make closing timing easier | Ian Buckley | 2010-02-24 | 1 | -2/+7 |
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| * | | Remove some warnings in dsp_core_rx | Johnathan Corgan | 2010-02-23 | 1 | -3/+7 |
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| * | | Fix missing item on sensitivity list | Johnathan Corgan | 2010-02-23 | 1 | -1/+1 |
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| * | | Change bit width of CORDIC constants to remove meaningless warning | Johnathan Corgan | 2010-02-23 | 1 | -24/+24 |
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| * | | Manually assign clk_fpga to BUFG to improve timing | Johnathan Corgan | 2010-02-23 | 1 | -1/+5 |
| |/ | | | | | | | | | | | | | | Starting Router Phase 1: 96908 unrouted; REAL time: 25 secs Phase 2: 85651 unrouted; REAL time: 35 secs Phase 3: 27099 unrouted; REAL time: 49 secs Phase 4: 27099 unrouted; (97405) REAL time: 49 secs Phase 5: 27259 unrouted; (5348) REAL time: 54 secs Phase 6: 27277 unrouted; (0) REAL time: 54 secs Phase 7: 0 unrouted; (0) REAL time: 1 mins 46 secs Phase 8: 0 unrouted; (0) REAL time: 1 mins 56 secs Phase 9: 0 unrouted; (0) REAL time: 2 mins 29 secs | ||||
| * | Moved usrp2 fpga files into usrp2 subdir. | Josh Blum | 2010-01-22 | 633 | -0/+1556369 |
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