uhd - Ettus' UHD Repository

	Commit message (Expand)	Author	Age	Files	Lines
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* \|	Added timing constraint for Wishbone clock/dsp_clock skew	Johnathan Corgan	2010-03-29	1	-0/+2
* \|	Merge commit 'upstream/master'	Johnathan Corgan	2010-03-09	1	-1/+1
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* \| \|	Cut debug bus connection to etherenet MAC to make closing timing easier	Ian Buckley	2010-02-24	1	-2/+7
* \| \|	Remove some warnings in dsp_core_rx	Johnathan Corgan	2010-02-23	1	-3/+7
* \| \|	Fix missing item on sensitivity list	Johnathan Corgan	2010-02-23	1	-1/+1
* \| \|	Change bit width of CORDIC constants to remove meaningless warning	Johnathan Corgan	2010-02-23	1	-24/+24
* \| \|	Manually assign clk_fpga to BUFG to improve timing	Johnathan Corgan	2010-02-23	1	-1/+5
\| \| *	Merge branch 'master' into udp	Matt Ettus	2010-03-25	2	-3/+1
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\| * \|	proper initialization of the ram	Matt Ettus	2010-02-23	1	-1/+1
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* /	Moved usrp2 fpga files into usrp2 subdir.	Josh Blum	2010-01-22	633	-0/+1556369
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*	moved fifos around, now easier to see where they are and how big	Matt Ettus	2010-03-25	2	-17/+30
*	bigger fifo on UDP TX path, to possibly fix overruns on decim=4	Matt Ettus	2010-03-24	1	-2/+11
*	Xilinx ISE is incorrectly parsing the verilog case statement, this is a worka...	Matt Ettus	2010-03-24	1	-1/+7
*	pps and vita time debug pins	Matt Ettus	2010-03-23	1	-3/+6
*	more debug for fixing E's	Matt Ettus	2010-03-10	2	-6/+13
*	better debug pins for going after cascading E's	Matt Ettus	2010-03-10	1	-1/+5
*	copied over from quad radio	Matt Ettus	2010-02-08	1	-0/+60
*	Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udp	Matt Ettus	2010-01-25	4	-34/+43
*	just debug pin changes	Matt Ettus	2010-01-25	2	-1/+12
*	typo caused the tx udp chain to be disconnected	Matt Ettus	2010-01-23	1	-1/+1
*	moved into subdir	Josh Blum	2010-01-22	653	-0/+1558662