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* dsp rework: implement 64 bit ticks no secondsJosh Blum2012-02-0610-111/+57
* B100: External FPGA reset from FX2 reuses fpga_cfg_cclk.Nick Foster2012-02-062-2/+6
* dsp rework: pass vita clears into dsp modules, unified fifo clearsJosh Blum2012-02-0414-81/+76
* b100: timing constraints on GPIF linesJosh Blum2012-02-041-0/+9
* b100: connect all clears for gpifJosh Blum2012-02-033-15/+8
* power_trig: test code for power triggerMatt Ettus2012-02-021-0/+71
* dsp rework: rehash of the custom module stuff and readmeJosh Blum2012-02-0225-259/+494
* power_trig: first cut at power trigger with fixed delayMatt Ettus2012-02-022-2/+115
* dsp_rework: testbench enhancementsMatt Ettus2012-02-021-11/+34
* dsp rework: custom engine module for rx/tx vita chainJosh Blum2012-02-0113-138/+294
* dsp rework: register the sample in vita tx ctrlJosh Blum2012-02-011-2/+11
* Merge branch 'slave_fifo_rebase' into dsp_reworkJosh Blum2012-02-016-35/+509
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| * Fix missing B100 core_compile (poor Git hygeine)Nick Foster2012-01-231-0/+1
| * b100: bumped fpga compat number for slave fifo modeJosh Blum2012-01-121-1/+1
| * Slave FIFO: fix for PKTEND not asserting @ end of RX.Nick Foster2012-01-121-8/+8
| * B100: moar buffering on TX for better performance in bidirectional applicationsNick Foster2012-01-122-5/+5
| * Squashed slave mode changes onto master.Nick Foster2012-01-127-34/+507
* | dsp rework: paramaterize post_engine_bufferingJosh Blum2012-02-013-4/+16
* | dsp_rework: handle longer headersMatt Ettus2012-01-311-2/+8
* | dsp_rework: more thorough testMatt Ettus2012-01-311-8/+20
* | dsp rework: finished engine HEADER_OFFSET stuff, add post_engine_bufferingJosh Blum2012-01-302-8/+13
* | dsp rework: work on 8 to 16 engine (usrp2 ok)Josh Blum2012-01-302-25/+26
* | dsp_engine: work with transport headerMatt Ettus2012-01-301-16/+14
* | dsp rework: integrated dspengine_8to16, some tweaksJosh Blum2012-01-303-8/+8
* | dsp: 8 to 16 bit conversion for tx side. believed to be functionalMatt Ettus2012-01-292-12/+230
* | dsp rework: increase the number of effective bits in the duc scale factorJosh Blum2012-01-281-1/+1
* | dsp rework: added double buffer interface to vita txJosh Blum2012-01-285-12/+41
* | dsp rework: moved scale and round into ddc chainJosh Blum2012-01-287-41/+49
* | dsp rework: top level fixes B100/E100Josh Blum2012-01-274-8/+9
* | dsp rework: integrated custom dsp module shellsJosh Blum2012-01-2718-38/+370
* | dsp rework: implemented dsp changes for other top levelsJosh Blum2012-01-2710-106/+203
* | dsp rework: renamed dsp signals for frontend IOJosh Blum2012-01-275-32/+35
* | dsp rework: u2_core test implementationJosh Blum2012-01-2613-446/+49
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* n2xx: updated bootloader to latest build in uhd masterJosh Blum2012-01-111-377/+377
* usrp2/nseries: restored clock/serdes readbackJosh Blum2011-11-232-4/+4
* need more umph out of correction valuesJosh Blum2011-11-106-8/+8
* remove unused irq to meet timingJosh Blum2011-11-052-21/+7
* convenience makefiles for top level projectsJosh Blum2011-11-052-0/+31
* increase vita rx fifosize to 10, like USRP2, make things workJosh Blum2011-11-042-4/+4
* dsp: remove dsp_buffer and replace with simpler add_routing_header,Matt Ettus2011-11-043-3/+50
* dsp: remove warningsMatt Ettus2011-11-042-4/+6
* u1e: fix unattached nets from copy-paste errorMatt Ettus2011-11-041-3/+3
* b100: fix warnings, complete removal of test codeMatt Ettus2011-11-042-16/+7
* b100: remove test features from GPIF to save spaceMatt Ettus2011-11-042-82/+9
* u1e/u1p: GPIOs switched over to setting regsMatt Ettus2011-10-272-32/+45
* forgot to add gpio atr to makefile source listJosh Blum2011-10-261-0/+1
* 32 bit compat number for E and B seriesJosh Blum2011-10-262-10/+8
* u1e/u1p: removed led setting regMatt Ettus2011-10-262-14/+4
* u1p/u1e: partially redone atr and gpio redoMatt Ettus2011-10-262-33/+11
* u2/u2p: use new setting_reg based gpios, gets it off of wbMatt Ettus2011-10-263-17/+98
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