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| * move declaration ahead of useMatt Ettus2010-07-191-5/+5
| * put run_tx and run_rx on the displayed LEDsMatt Ettus2010-07-191-3/+4
| * remove warningsMatt Ettus2010-07-162-3/+3
| * add mux and demux to buildMatt Ettus2010-07-151-0/+2
| * mux multiple fifo streams into one. Allows priority or round robinMatt Ettus2010-07-151-0/+57
| * split fifo into 2 streams based on first line in each packetMatt Ettus2010-07-151-0/+50
| * Merge branch 'reload' into ise12Matt Ettus2010-07-154-22/+59
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| | * fix to stop endless error packetsMatt Ettus2010-07-091-2/+2
| | * updated tests to match new featuresMatt Ettus2010-07-092-4/+9
| | * error packets are now valid Extension Context packetsMatt Ettus2010-07-081-11/+32
| | * reload bit for vita rx ctrlJosh Blum2010-07-051-5/+16
* | | Regenerated FIFO's for extfifo.Ian Buckley2010-08-1212-728/+19
* | | Edited FIFO instance to delete port that was not regenerated after reconfigur...Ian Buckley2010-08-121-1/+0
* | | Adding in files that probably didn;t exist in the ISE10.1 version of coregenIan Buckley2010-08-125-0/+808
* | | Bringing all coregen files checked in into syncIan Buckley2010-08-1210-137/+60
* | | Merge branch 'ise12_efifo_work' of git@ettus.sourcerepo.com:ettus/fpgapriv in...Ian Buckley2010-08-1218-41/+587
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| * | | checkin of generated coregen filesMatt Ettus2010-08-1118-8/+556
* | | | Found bug due to not accounting for the correct number of possible in flight ...Ian Buckley2010-08-127-49/+113
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* | | External FIFO tested in simulation and on USRP2 from decimation 64->8 with cu...Ian Buckley2010-07-3119-238/+7327
* | | Checkpoint checkin.Ian Buckley2010-07-2913-0/+1507
* | | get it to buildMatt Ettus2010-07-145-5/+309
* | | moved forward from the old branchMatt Ettus2010-07-148-4/+876
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* | Merge branch 'master' into ise12Matt Ettus2010-07-121-4/+5
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| * fix bug which caused serdes fifo to disappearMatt Ettus2010-07-031-4/+5
* | Merge branch 'master' into ise12Matt Ettus2010-06-181-1/+2
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| * proper dependency tracking for the makefileMatt Ettus2010-06-181-1/+2
* | precompute udp checksumsMatt Ettus2010-06-151-5/+14
* | barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but allMatt Ettus2010-06-147-275/+390
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* new make works on ise12Matt Ettus2010-06-141-1/+7
* produces good bin filesMatt Ettus2010-06-114-57/+31
* first attempt at cleaning up the build systemMatt Ettus2010-06-1038-422/+583
* get rid of debug stuff to help timingMatt Ettus2010-06-081-7/+16
* move u2_core into u2_rev3 directory to simplify directory structure and save ...Matt Ettus2010-06-085-46/+2
* allow other clock rates in vita timeMatt Ettus2010-06-081-13/+15
* report ise version in buildMatt Ettus2010-06-071-1/+1
* proper name for directoryMatt Ettus2010-06-071-1/+1
* name build directory with ISE version nameMatt Ettus2010-06-071-1/+1
* non-udp uses a different address for the tx dsp coreMatt Ettus2010-05-271-1/+1
* manual merge to use localparams from udp versionMatt Ettus2010-05-271-4/+23
* from UDP branch, changed names because I want these separate from the non-udp...Matt Ettus2010-05-273-0/+1321
* new files from udp branch added to main MakefileMatt Ettus2010-05-271-1/+19
* Merge branch 'udp' into master_merge_take2Matt Ettus2010-05-2730-67/+2257
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| * better test program for just the tx sideMatt Ettus2010-05-191-163/+63
| * fix typo, no functionality differenceMatt Ettus2010-05-191-1/+1
| * Merge branch 'master' into udpMatt Ettus2010-05-18224-329/+19
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* | get rid of some warnings by declaring setting reg widthMatt Ettus2010-05-181-8/+8
* | added width parameter to avoid warnings (thanks IJB) and default value parameterMatt Ettus2010-05-181-3/+5
* | added pragmas suggested by Ian Buckley to help ISE12 synthesisMatt Ettus2010-05-181-3/+6
* | get rid of old CVS linkageMatt Ettus2010-05-18221-315/+0
* | settings bus to dsp_clk now uses clock crossing fifoMatt Ettus2010-05-162-8/+15
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