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| * | fpga: extract usage summary from map fileJosh Blum2012-03-271-0/+60
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* | Merge branch 'master' into nextJosh Blum2012-03-264-85/+92
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| * B100: port cleanups from b100-txbug to this branchNick Foster2012-03-262-28/+21
| * fpga: fifo_2clock handles widths and sizes in-between corgensJosh Blum2012-03-251-21/+23
| * b100: cleanup redundant logic for slwr and slrdJosh Blum2012-03-251-2/+2
| * b100: extra data pktend cycle for fifo addrJosh Blum2012-03-251-2/+8
| * b100: slave fifo fix for dst/src ready signalsJosh Blum2012-03-242-35/+41
* | spi core: ready logic low one cycle earlierJosh Blum2012-03-161-1/+1
* | fifo ctrl: parameterize having a proto headerJosh Blum2012-03-164-10/+12
* | fifo ctrl: rename fifo ctrl module and add sid ack paramJosh Blum2012-03-164-37/+40
* | fifo ctrl: minor fixes for spi core, swap time defineJosh Blum2012-03-165-10/+10
* | fifo ctrl: simplified perfs, added spi clock idle phaseJosh Blum2012-03-165-333/+341
* | fifo ctrl: minor fixes from last commitJosh Blum2012-03-163-366/+366
* | fifo ctrl: spi core work, fifo ctrl perifs, usrp2 supportJosh Blum2012-03-165-370/+429
* | spi: created simple spi core (sr based)Josh Blum2012-03-164-383/+593
* | fifo ctrl: simplified result packets (no tsf or sid)Josh Blum2012-03-161-16/+7
* | fifo_ctrl: switched to medfifo and separate result fifoJosh Blum2012-03-163-92/+122
* | fifo_ctrl: clear settings reg, and flow controlJosh Blum2012-03-163-10/+17
* | fifo ctrl: added time compare for timed commandsJosh Blum2012-03-161-3/+7
* | srb: created command queue, in and out state machinesJosh Blum2012-03-163-99/+162
* | usrp2: added vrt pack/unpacker to fifo ctrlJosh Blum2012-03-161-40/+107
* | usrp2: first pass implementation of fifo controlJosh Blum2012-03-166-10/+594
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* fpga: force -include_global for custom sourcesJosh Blum2012-03-129-13/+16
* fpga: fix custom defs in some top level makefilesJosh Blum2012-03-084-101/+3
* usrp2/nseries: added churn to meet timingJosh Blum2012-02-182-2/+4
* vita rx: trigger clear after packet tranferJosh Blum2012-02-181-2/+22
* dsp rework: fix dspengine_8to16 to handle padded packetsJosh Blum2012-02-171-4/+3
* dsp_engine: fix for upper/lower swap, and odd length packetsMatt Ettus2012-02-161-16/+20
* dsp rework: added flusher to vita tx chain on clearJosh Blum2012-02-151-8/+16
* dsp rework: minor simplification in vita_tx_deframerJosh Blum2012-02-131-4/+1
* dsp rework: full-rate pipelining in vita tx deframerJosh Blum2012-02-121-37/+51
* dsp rework: pass enables into glue, update power trig, parameterize, fix modu...Josh Blum2012-02-109-103/+145
* dsp rework: implement 64 bit ticks no secondsJosh Blum2012-02-0610-111/+57
* B100: External FPGA reset from FX2 reuses fpga_cfg_cclk.Nick Foster2012-02-062-2/+6
* dsp rework: pass vita clears into dsp modules, unified fifo clearsJosh Blum2012-02-0414-81/+76
* b100: timing constraints on GPIF linesJosh Blum2012-02-041-0/+9
* b100: connect all clears for gpifJosh Blum2012-02-033-15/+8
* power_trig: test code for power triggerMatt Ettus2012-02-021-0/+71
* dsp rework: rehash of the custom module stuff and readmeJosh Blum2012-02-0225-259/+494
* power_trig: first cut at power trigger with fixed delayMatt Ettus2012-02-022-2/+115
* dsp_rework: testbench enhancementsMatt Ettus2012-02-021-11/+34
* dsp rework: custom engine module for rx/tx vita chainJosh Blum2012-02-0113-138/+294
* dsp rework: register the sample in vita tx ctrlJosh Blum2012-02-011-2/+11
* Merge branch 'slave_fifo_rebase' into dsp_reworkJosh Blum2012-02-016-35/+509
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| * Fix missing B100 core_compile (poor Git hygeine)Nick Foster2012-01-231-0/+1
| * b100: bumped fpga compat number for slave fifo modeJosh Blum2012-01-121-1/+1
| * Slave FIFO: fix for PKTEND not asserting @ end of RX.Nick Foster2012-01-121-8/+8
| * B100: moar buffering on TX for better performance in bidirectional applicationsNick Foster2012-01-122-5/+5
| * Squashed slave mode changes onto master.Nick Foster2012-01-127-34/+507
* | dsp rework: paramaterize post_engine_bufferingJosh Blum2012-02-013-4/+16
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