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* spi core: ready logic low one cycle earlierJosh Blum2012-03-161-1/+1
| | | | | | | FIFO ctrl can poke registers every other cycle, the extra time to register not ready for spi core was too long. And it with ~trigger to get the not-ready one cycle earlier, so FIFO ctrl can block on the 2nd potential spi transaction.
* fifo ctrl: parameterize having a proto headerJosh Blum2012-03-164-10/+12
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* fifo ctrl: rename fifo ctrl module and add sid ack paramJosh Blum2012-03-164-37/+40
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* fifo ctrl: minor fixes for spi core, swap time defineJosh Blum2012-03-165-10/+10
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* fifo ctrl: simplified perfs, added spi clock idle phaseJosh Blum2012-03-165-333/+341
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* fifo ctrl: minor fixes from last commitJosh Blum2012-03-163-366/+366
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* fifo ctrl: spi core work, fifo ctrl perifs, usrp2 supportJosh Blum2012-03-165-370/+429
| | | | | | | | Continued work on simple spi core. Added peripherals input to fifo ctrl so perifs can backpressure fifo ctrl. Copied the implementation into usrp2 core.
* spi: created simple spi core (sr based)Josh Blum2012-03-164-383/+593
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* fifo ctrl: simplified result packets (no tsf or sid)Josh Blum2012-03-161-16/+7
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* fifo_ctrl: switched to medfifo and separate result fifoJosh Blum2012-03-163-92/+122
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* fifo_ctrl: clear settings reg, and flow controlJosh Blum2012-03-163-10/+17
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* fifo ctrl: added time compare for timed commandsJosh Blum2012-03-161-3/+7
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* srb: created command queue, in and out state machinesJosh Blum2012-03-163-99/+162
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* usrp2: added vrt pack/unpacker to fifo ctrlJosh Blum2012-03-161-40/+107
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* usrp2: first pass implementation of fifo controlJosh Blum2012-03-166-10/+594
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* fpga: force -include_global for custom sourcesJosh Blum2012-03-129-13/+16
| | | | | | | | ISE will not recognize custom sources as part of the hierarchy, and thus will not compile (unless its the first macro...). Remove custom sources from the source list, and specially add them with the -include_global option.
* fpga: fix custom defs in some top level makefilesJosh Blum2012-03-084-101/+3
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* usrp2/nseries: added churn to meet timingJosh Blum2012-02-182-2/+4
| | | | | Added churn to readback mux on nseries to make n200r4 meet timing. Also added churn to usrp2 for parallelism, but assigned to zero.
* vita rx: trigger clear after packet tranferJosh Blum2012-02-181-2/+22
| | | | | | | To avoid blocking conditions down the pipe, avoid clearing vita rx during packet transfer. Adds state machine to delay the clear until after xfer completes.
* dsp rework: fix dspengine_8to16 to handle padded packetsJosh Blum2012-02-171-4/+3
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* dsp_engine: fix for upper/lower swap, and odd length packetsMatt Ettus2012-02-161-16/+20
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* dsp rework: added flusher to vita tx chain on clearJosh Blum2012-02-151-8/+16
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* dsp rework: minor simplification in vita_tx_deframerJosh Blum2012-02-131-4/+1
| | | | all n-series devices meet timing
* dsp rework: full-rate pipelining in vita tx deframerJosh Blum2012-02-121-37/+51
| | | | | | | | The vita tx deframer can now pass payload at clock rate. This enables TX streaming at interpolations factors of 2. The vector capabilities of TX deframer have been kept in-tact, and should be functional, however, only MAXCHAN=1 has been tested.
* dsp rework: pass enables into glue, update power trig, parameterize, fix ↵Josh Blum2012-02-109-103/+145
| | | | | | | | | | | | module inc DSP enables now pass through the glue and custom modules so it can be user-controlled. Updated power trigger to current spec, and added comments Pass width from dsp into glue, and use width to parameterize wires Fix custom module includes so they will build
* dsp rework: implement 64 bit ticks no secondsJosh Blum2012-02-0610-111/+57
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* B100: External FPGA reset from FX2 reuses fpga_cfg_cclk.Nick Foster2012-02-062-2/+6
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* dsp rework: pass vita clears into dsp modules, unified fifo clearsJosh Blum2012-02-0414-81/+76
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* b100: timing constraints on GPIF linesJosh Blum2012-02-041-0/+9
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* b100: connect all clears for gpifJosh Blum2012-02-033-15/+8
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* power_trig: test code for power triggerMatt Ettus2012-02-021-0/+71
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* dsp rework: rehash of the custom module stuff and readmeJosh Blum2012-02-0225-259/+494
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* power_trig: first cut at power trigger with fixed delayMatt Ettus2012-02-022-2/+115
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* dsp_rework: testbench enhancementsMatt Ettus2012-02-021-11/+34
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* dsp rework: custom engine module for rx/tx vita chainJosh Blum2012-02-0113-138/+294
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* dsp rework: register the sample in vita tx ctrlJosh Blum2012-02-011-2/+11
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* Merge branch 'slave_fifo_rebase' into dsp_reworkJosh Blum2012-02-016-35/+509
|\ | | | | | | | | Conflicts: usrp2/top/B100/u1plus_core.v
| * Fix missing B100 core_compile (poor Git hygeine)Nick Foster2012-01-231-0/+1
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| * b100: bumped fpga compat number for slave fifo modeJosh Blum2012-01-121-1/+1
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| * Slave FIFO: fix for PKTEND not asserting @ end of RX.Nick Foster2012-01-121-8/+8
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| * B100: moar buffering on TX for better performance in bidirectional applicationsNick Foster2012-01-122-5/+5
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| * Squashed slave mode changes onto master.Nick Foster2012-01-127-34/+507
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* | dsp rework: paramaterize post_engine_bufferingJosh Blum2012-02-013-4/+16
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* | dsp_rework: handle longer headersMatt Ettus2012-01-311-2/+8
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* | dsp_rework: more thorough testMatt Ettus2012-01-311-8/+20
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* | dsp rework: finished engine HEADER_OFFSET stuff, add post_engine_bufferingJosh Blum2012-01-302-8/+13
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* | dsp rework: work on 8 to 16 engine (usrp2 ok)Josh Blum2012-01-302-25/+26
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* | dsp_engine: work with transport headerMatt Ettus2012-01-301-16/+14
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* | dsp rework: integrated dspengine_8to16, some tweaksJosh Blum2012-01-303-8/+8
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* | dsp: 8 to 16 bit conversion for tx side. believed to be functionalMatt Ettus2012-01-292-12/+230
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