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* Merge branch 'ise12' into efifo_merge_dcmMatt Ettus2010-10-063-29/+23
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| * fix timing problem on DAC output busMatt Ettus2010-10-011-2/+2
| * clean up DAC inversion and swapping to match schematicsMatt Ettus2010-08-251-3/+6
| * Clean up iq swapping on RX. It is now swapped in the top level.Matt Ettus2010-08-253-27/+18
| * Merge branch 'features' into tx_policyMatt Ettus2010-08-172-3/+6
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* | | Modified phase shift of DCM1 to -64 which is intended to give more timing mar...Ian Buckley2010-09-301-1/+1
* | | Enabled phase offset adjustment on DCM_INST1 which drives the external Fast S...Ian Buckley2010-09-141-12/+12
* | | Added to DCM's and some BUFG's to align the internal 125MHz clock edge with i...Ian Buckley2010-09-014-5/+101
* | | Merge branch 'efifo_merge' of git@ettus.sourcerepo.com:ettus/fpgapriv into ef...Ian Buckley2010-09-015-47/+60
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| * | | hangedddddddextrnal fifo size to use full NoBL SRAMianb2010-08-251-1/+1
| * | | Corrected extfifo code so that all registers that are on SRAM signals are pac...ianb2010-08-255-46/+59
* | | | Enhanced test bench to be more like real world applicationIan Buckley2010-09-012-7/+14
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* | | capacity logic fixMatt Ettus2010-08-191-1/+1
* | | Added capacity to the module pinoutIan Buckley2010-08-191-3/+4
* | | Added a bunch of debug signals.Ian Buckley2010-08-194-9/+19
* | | Merge branch 'ise12_efifo_work' into efifo_mergeMatt Ettus2010-08-198-236/+113
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| * | | Regenerated FIFO with lower trigger level for almost full flag to reflect log...Ian Buckley2010-08-199-238/+115
* | | | Merge branch 'features' into ise12_efifo_mergeMatt Ettus2010-08-162-3/+6
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| * | | added compat number to usrp2 readback muxJosh Blum2010-08-091-2/+5
| * | | makefile dependency fix for second expansionJosh Blum2010-08-091-1/+1
* | | | Matt's attempt at mergingMatt Ettus2010-08-1610-5569/+306
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| * | | rx error context packets should not be marked as errors in the fifoMatt Ettus2010-08-111-1/+1
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| * | provide a way to get out of the error state without processor interventionMatt Ettus2010-07-291-1/+4
| * | sequence number reset upon programming streamidMatt Ettus2010-07-282-5/+11
| * | attempt at avoiding infinite error messagesMatt Ettus2010-07-281-5/+14
| * | implemented "next packet" and "next burst" policiesMatt Ettus2010-07-283-24/+50
| * | sequence errors can happen on start of burst as well.Matt Ettus2010-07-281-1/+1
| * | more informative error codesMatt Ettus2010-07-282-6/+8
| * | cleaner error handlingMatt Ettus2010-07-281-27/+28
| * | introduce new error typesMatt Ettus2010-07-283-34/+80
| * | test mux and gen_context_pktMatt Ettus2010-07-281-3/+22
| * | this is an output file, it shouldn't be checked inMatt Ettus2010-07-281-5506/+0
| * | insert protocol engine flags when requestedMatt Ettus2010-07-281-2/+6
| * | move the streamid so it isn't at the same address as clear_stateMatt Ettus2010-07-282-2/+2
| * | connect the demuxMatt Ettus2010-07-281-1/+1
| * | fix a typoMatt Ettus2010-07-283-4/+4
| * | tx error packets now muxed into the ethernet stream back to the hostMatt Ettus2010-07-284-47/+66
| * | checkpoint. New context packet generator to report underruns and other errorsMatt Ettus2010-07-282-0/+107
* | | Merge branch 'ise12' into ise12_efifo_workMatt Ettus2010-08-1610-33/+180
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| * move declaration ahead of useMatt Ettus2010-07-191-5/+5
| * put run_tx and run_rx on the displayed LEDsMatt Ettus2010-07-191-3/+4
| * remove warningsMatt Ettus2010-07-162-3/+3
| * add mux and demux to buildMatt Ettus2010-07-151-0/+2
| * mux multiple fifo streams into one. Allows priority or round robinMatt Ettus2010-07-151-0/+57
| * split fifo into 2 streams based on first line in each packetMatt Ettus2010-07-151-0/+50
| * Merge branch 'reload' into ise12Matt Ettus2010-07-154-22/+59
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| | * fix to stop endless error packetsMatt Ettus2010-07-091-2/+2
| | * updated tests to match new featuresMatt Ettus2010-07-092-4/+9
| | * error packets are now valid Extension Context packetsMatt Ettus2010-07-081-11/+32
| | * reload bit for vita rx ctrlJosh Blum2010-07-051-5/+16
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