| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | vita rx: trigger clear after packet tranfer | Josh Blum | 2012-02-18 | 1 | -2/+22 |
| * | dsp rework: fix dspengine_8to16 to handle padded packets | Josh Blum | 2012-02-17 | 1 | -4/+3 |
| * | dsp_engine: fix for upper/lower swap, and odd length packets | Matt Ettus | 2012-02-16 | 1 | -16/+20 |
| * | dsp rework: added flusher to vita tx chain on clear | Josh Blum | 2012-02-15 | 1 | -8/+16 |
| * | dsp rework: minor simplification in vita_tx_deframer | Josh Blum | 2012-02-13 | 1 | -4/+1 |
| * | dsp rework: full-rate pipelining in vita tx deframer | Josh Blum | 2012-02-12 | 1 | -37/+51 |
| * | dsp rework: pass enables into glue, update power trig, parameterize, fix modu... | Josh Blum | 2012-02-10 | 9 | -103/+145 |
| * | dsp rework: implement 64 bit ticks no seconds | Josh Blum | 2012-02-06 | 10 | -111/+57 |
| * | B100: External FPGA reset from FX2 reuses fpga_cfg_cclk. | Nick Foster | 2012-02-06 | 2 | -2/+6 |
| * | dsp rework: pass vita clears into dsp modules, unified fifo clears | Josh Blum | 2012-02-04 | 14 | -81/+76 |
| * | b100: timing constraints on GPIF lines | Josh Blum | 2012-02-04 | 1 | -0/+9 |
| * | b100: connect all clears for gpif | Josh Blum | 2012-02-03 | 3 | -15/+8 |
| * | power_trig: test code for power trigger | Matt Ettus | 2012-02-02 | 1 | -0/+71 |
| * | dsp rework: rehash of the custom module stuff and readme | Josh Blum | 2012-02-02 | 25 | -259/+494 |
| * | power_trig: first cut at power trigger with fixed delay | Matt Ettus | 2012-02-02 | 2 | -2/+115 |
| * | dsp_rework: testbench enhancements | Matt Ettus | 2012-02-02 | 1 | -11/+34 |
| * | dsp rework: custom engine module for rx/tx vita chain | Josh Blum | 2012-02-01 | 13 | -138/+294 |
| * | dsp rework: register the sample in vita tx ctrl | Josh Blum | 2012-02-01 | 1 | -2/+11 |
| * | Merge branch 'slave_fifo_rebase' into dsp_rework | Josh Blum | 2012-02-01 | 6 | -35/+509 |
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| | * | Fix missing B100 core_compile (poor Git hygeine) | Nick Foster | 2012-01-23 | 1 | -0/+1 |
| | * | b100: bumped fpga compat number for slave fifo mode | Josh Blum | 2012-01-12 | 1 | -1/+1 |
| | * | Slave FIFO: fix for PKTEND not asserting @ end of RX. | Nick Foster | 2012-01-12 | 1 | -8/+8 |
| | * | B100: moar buffering on TX for better performance in bidirectional applications | Nick Foster | 2012-01-12 | 2 | -5/+5 |
| | * | Squashed slave mode changes onto master. | Nick Foster | 2012-01-12 | 7 | -34/+507 |
| * | | dsp rework: paramaterize post_engine_buffering | Josh Blum | 2012-02-01 | 3 | -4/+16 |
| * | | dsp_rework: handle longer headers | Matt Ettus | 2012-01-31 | 1 | -2/+8 |
| * | | dsp_rework: more thorough test | Matt Ettus | 2012-01-31 | 1 | -8/+20 |
| * | | dsp rework: finished engine HEADER_OFFSET stuff, add post_engine_buffering | Josh Blum | 2012-01-30 | 2 | -8/+13 |
| * | | dsp rework: work on 8 to 16 engine (usrp2 ok) | Josh Blum | 2012-01-30 | 2 | -25/+26 |
| * | | dsp_engine: work with transport header | Matt Ettus | 2012-01-30 | 1 | -16/+14 |
| * | | dsp rework: integrated dspengine_8to16, some tweaks | Josh Blum | 2012-01-30 | 3 | -8/+8 |
| * | | dsp: 8 to 16 bit conversion for tx side. believed to be functional | Matt Ettus | 2012-01-29 | 2 | -12/+230 |
| * | | dsp rework: increase the number of effective bits in the duc scale factor | Josh Blum | 2012-01-28 | 1 | -1/+1 |
| * | | dsp rework: added double buffer interface to vita tx | Josh Blum | 2012-01-28 | 5 | -12/+41 |
| * | | dsp rework: moved scale and round into ddc chain | Josh Blum | 2012-01-28 | 7 | -41/+49 |
| * | | dsp rework: top level fixes B100/E100 | Josh Blum | 2012-01-27 | 4 | -8/+9 |
| * | | dsp rework: integrated custom dsp module shells | Josh Blum | 2012-01-27 | 18 | -38/+370 |
| * | | dsp rework: implemented dsp changes for other top levels | Josh Blum | 2012-01-27 | 10 | -106/+203 |
| * | | dsp rework: renamed dsp signals for frontend IO | Josh Blum | 2012-01-27 | 5 | -32/+35 |
| * | | dsp rework: u2_core test implementation | Josh Blum | 2012-01-26 | 13 | -446/+49 |
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| * | n2xx: updated bootloader to latest build in uhd master | Josh Blum | 2012-01-11 | 1 | -377/+377 |
| * | usrp2/nseries: restored clock/serdes readback | Josh Blum | 2011-11-23 | 2 | -4/+4 |
| * | need more umph out of correction values | Josh Blum | 2011-11-10 | 6 | -8/+8 |
| * | remove unused irq to meet timing | Josh Blum | 2011-11-05 | 2 | -21/+7 |
| * | convenience makefiles for top level projects | Josh Blum | 2011-11-05 | 2 | -0/+31 |
| * | increase vita rx fifosize to 10, like USRP2, make things work | Josh Blum | 2011-11-04 | 2 | -4/+4 |
| * | dsp: remove dsp_buffer and replace with simpler add_routing_header, | Matt Ettus | 2011-11-04 | 3 | -3/+50 |
| * | dsp: remove warnings | Matt Ettus | 2011-11-04 | 2 | -4/+6 |
| * | u1e: fix unattached nets from copy-paste error | Matt Ettus | 2011-11-04 | 1 | -3/+3 |
| * | b100: fix warnings, complete removal of test code | Matt Ettus | 2011-11-04 | 2 | -16/+7 |
