| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge branch 'maint' | Josh Blum | 2012-07-16 | 3 | -43/+6 |
| |\ | | | | | | | | | Conflicts: usrp2/top/E1x0/u1e_core.v | ||||
| | * | e100: offset gpmc to fifo writes by 2 transfers | Josh Blum | 2012-07-15 | 2 | -5/+5 |
| | | | | | | | | | This effectivly works around bus initial transaction issues. | ||||
| | * | e100: reverted commit registering in gpmc | Josh Blum | 2012-07-15 | 1 | -38/+1 |
| | | | | | | | | | There is a subtle bus issue that the last changset did not address. | ||||
| * | | b100: removed unused proto files | Josh Blum | 2012-06-13 | 3 | -390/+0 |
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| * | | fpga: added setting regs based simple_i2c_core | Josh Blum | 2012-05-30 | 2 | -0/+117 |
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| * | | fpga: added some parameterization to settings_fifo_ctrl | Josh Blum | 2012-05-30 | 1 | -3/+6 |
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| * | | fpga: added various models from ISE | Josh Blum | 2012-05-30 | 7 | -0/+4011 |
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| * | | Merge branch 'maint' | Josh Blum | 2012-05-22 | 1 | -1/+38 |
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| | * | Added registers for gpmc-to-fifo interface to address sequence errors for ↵ | Al Fayez | 2012-05-22 | 1 | -1/+38 |
| | | | | | | | | | E100/E110 | ||||
| * | | Merge branch 'maint' | Josh Blum | 2012-05-10 | 2 | -7/+9 |
| |\| | | | | | | | | | Conflicts: usrp2/top/E1x0/u1e_core.v | ||||
| | * | e100: bump compat minor for xclock reader fix | Josh Blum | 2012-05-10 | 1 | -1/+1 |
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| | * | fpga: xclock fix for edge case condition | Josh Blum | 2012-05-08 | 1 | -6/+8 |
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| * | | e100/b100: bumped compat number for timed commands merge | Josh Blum | 2012-04-25 | 2 | -2/+2 |
| | | | | | | | | | | | There were common FPGA changes and an incompatibility. This should have been done before the merge anyhow. | ||||
| * | | slave_fifo: use 2KB FIFO size instead of 1KB | Nick Foster | 2012-04-24 | 1 | -1/+1 |
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| * | | b100: implement packet-end/flush cycle timeout | Josh Blum | 2012-04-24 | 3 | -12/+26 |
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| * | | gpif: removed unused gpif related files | Josh Blum | 2012-04-24 | 8 | -908/+1 |
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| * | | N2x0: updated the bootloader w/ latest from fw | Josh Blum | 2012-04-20 | 1 | -390/+390 |
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| * | | usrp2: remove settings_fifo_ctrl, meets timing | Josh Blum | 2012-04-20 | 1 | -2/+11 |
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| * | | fifo ctrl: Nseries timing meets with a single shortfifo | Josh Blum | 2012-04-17 | 1 | -3/+2 |
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| * | | usrp: work on meeting timing constraints | Josh Blum | 2012-04-10 | 5 | -25/+30 |
| | | | | | | | | | | | | | * fifo ctrl register the vita ticks and use late * vita de/framer make nchans const since we dont change it * simplify readback muxes to minimal usage | ||||
| * | | Merge branch 'master' into next | Josh Blum | 2012-04-09 | 5 | -7/+67 |
| |\ \ | | | | | | | | | | | | | | | | Conflicts: usrp2/top/N2x0/u2plus_core.v usrp2/top/USRP2/u2_core.v | ||||
| | * | | Merge branch 'maint' | Josh Blum | 2012-04-09 | 5 | -6/+6 |
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| | | * | vita: moved clear register to overlap with nchan register | Josh Blum | 2012-04-09 | 5 | -6/+6 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the bug where setting the format clears the vita RX. This is only an issue when the noclear option is set by UHD, because the format register is always so, so it always clears. Note: noclear is there to support the backwards compat API (pre streamer). Now, numchans and clear overlap. This is ok because in the host code, clear and numchans are always used together. All timing meets on N2xx and USRP2. | ||||
| | * | | Merge branch 'maint' | Josh Blum | 2012-04-02 | 2 | -5/+5 |
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| | | * | b100: fix slave fifo data xfer exit condition | Josh Blum | 2012-04-01 | 2 | -5/+5 |
| | | | | | | | | | | | | | | | | | | | | | | When exiting the read/write data state, when the transfer count maxes out/peaks, the fifo read/write signals were getting this condition the cycle after with the state change. | ||||
| | * | | fpga: extract usage summary from map file | Josh Blum | 2012-03-27 | 1 | -0/+60 |
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| * | | Merge branch 'master' into next | Josh Blum | 2012-03-26 | 4 | -85/+92 |
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| | * | B100: port cleanups from b100-txbug to this branch | Nick Foster | 2012-03-26 | 2 | -28/+21 |
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| | * | fpga: fifo_2clock handles widths and sizes in-between corgens | Josh Blum | 2012-03-25 | 1 | -21/+23 |
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| | * | b100: cleanup redundant logic for slwr and slrd | Josh Blum | 2012-03-25 | 1 | -2/+2 |
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| | * | b100: extra data pktend cycle for fifo addr | Josh Blum | 2012-03-25 | 1 | -2/+8 |
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| | * | b100: slave fifo fix for dst/src ready signals | Josh Blum | 2012-03-24 | 2 | -35/+41 |
| | | | | | | | | | | | | | | | | | Some of the changes my be overkill, but the idea is to be more careful about allowing FIFO IO to occur on transitions. The cal app was able to complete successfully. | ||||
| * | | spi core: ready logic low one cycle earlier | Josh Blum | 2012-03-16 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | FIFO ctrl can poke registers every other cycle, the extra time to register not ready for spi core was too long. And it with ~trigger to get the not-ready one cycle earlier, so FIFO ctrl can block on the 2nd potential spi transaction. | ||||
| * | | fifo ctrl: parameterize having a proto header | Josh Blum | 2012-03-16 | 4 | -10/+12 |
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| * | | fifo ctrl: rename fifo ctrl module and add sid ack param | Josh Blum | 2012-03-16 | 4 | -37/+40 |
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| * | | fifo ctrl: minor fixes for spi core, swap time define | Josh Blum | 2012-03-16 | 5 | -10/+10 |
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| * | | fifo ctrl: simplified perfs, added spi clock idle phase | Josh Blum | 2012-03-16 | 5 | -333/+341 |
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| * | | fifo ctrl: minor fixes from last commit | Josh Blum | 2012-03-16 | 3 | -366/+366 |
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| * | | fifo ctrl: spi core work, fifo ctrl perifs, usrp2 support | Josh Blum | 2012-03-16 | 5 | -370/+429 |
| | | | | | | | | | | | | | | | | | Continued work on simple spi core. Added peripherals input to fifo ctrl so perifs can backpressure fifo ctrl. Copied the implementation into usrp2 core. | ||||
| * | | spi: created simple spi core (sr based) | Josh Blum | 2012-03-16 | 4 | -383/+593 |
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| * | | fifo ctrl: simplified result packets (no tsf or sid) | Josh Blum | 2012-03-16 | 1 | -16/+7 |
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| * | | fifo_ctrl: switched to medfifo and separate result fifo | Josh Blum | 2012-03-16 | 3 | -92/+122 |
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| * | | fifo_ctrl: clear settings reg, and flow control | Josh Blum | 2012-03-16 | 3 | -10/+17 |
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| * | | fifo ctrl: added time compare for timed commands | Josh Blum | 2012-03-16 | 1 | -3/+7 |
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| * | | srb: created command queue, in and out state machines | Josh Blum | 2012-03-16 | 3 | -99/+162 |
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| * | | usrp2: added vrt pack/unpacker to fifo ctrl | Josh Blum | 2012-03-16 | 1 | -40/+107 |
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| * | | usrp2: first pass implementation of fifo control | Josh Blum | 2012-03-16 | 6 | -10/+594 |
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| * | fpga: force -include_global for custom sources | Josh Blum | 2012-03-12 | 9 | -13/+16 |
| | | | | | | | | | ISE will not recognize custom sources as part of the hierarchy, and thus will not compile (unless its the first macro...). Remove custom sources from the source list, and specially add them with the -include_global option. | ||||
| * | fpga: fix custom defs in some top level makefiles | Josh Blum | 2012-03-08 | 4 | -101/+3 |
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| * | usrp2/nseries: added churn to meet timing | Josh Blum | 2012-02-18 | 2 | -2/+4 |
| | | | | | | Added churn to readback mux on nseries to make n200r4 meet timing. Also added churn to usrp2 for parallelism, but assigned to zero. | ||||
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