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* zpu: added a zpu + wishbone opencore and integrated into top levelJosh Blum2010-12-0610-10/+1554
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* packet_router: added status readback for mode, incremented compat numberJosh Blum2010-11-242-1/+2
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* packet_router: split the control register into misc, cpu hs out, cpu hs inpJosh Blum2010-11-241-10/+24
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* packet_router: modification for sequence number and vrt header offsetJosh Blum2010-11-231-1/+1
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* packet_router: it makes more sense to connect the control flags this way nowJosh Blum2010-11-231-13/+6
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* packet_router: program the dsp udp port and ip addr through setting registersJosh Blum2010-11-232-32/+34
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* reduce warnings, modernize testbenchMatt Ettus2010-11-236-28/+25
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* packet_router: mux the crossbar input after the protocol framerJosh Blum2010-11-231-2/+12
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* allow any unicast packet through.Matt Ettus2010-11-234-5/+40
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* packet_router: moved udp tx proto machine into packet router, replaced ↵Josh Blum2010-11-232-18/+69
| | | | udp_wrapper in top level with some fifo conversion stuff
* packet_router: moved dsp framer into a module, added clr to splitter and renamedJosh Blum2010-11-234-93/+110
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* packet_router: implemented crossbar and valve module, moved sreg into router ↵Josh Blum2010-11-233-61/+72
| | | | module
* packet valve. will drop incoming data if shut off.Matt Ettus2010-11-231-0/+28
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* abstract out the crossbar functionalityMatt Ettus2010-11-231-0/+40
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* packet_router: transplanted the async error interface, its now sent into the ↵Josh Blum2010-11-232-17/+21
| | | | packet router to be muxed to com out
* packet_router: added a way to program in the ip and mac addrs, and added ↵Josh Blum2010-11-231-2/+17
| | | | inspector check
* packet_router: fixed sof bug for cpu (== 1), some logic tweaks, added debugJosh Blum2010-11-232-10/+44
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* packet_router: registered control flags, added clear to all state machinesJosh Blum2010-11-232-14/+26
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* packet_router: added splitter and mux for slow path stuff (also fixed typo ↵Josh Blum2010-11-232-10/+95
| | | | in crossbar input)
* packet_router: renamed inspector output signals and connected (for now) to ↵Josh Blum2010-11-232-22/+52
| | | | cpu, dsp, crs
* packet_router: use BRAM enables to perform pipelined readsJosh Blum2010-11-231-26/+21
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* packet_router: use control register bit for master mode flagJosh Blum2010-11-231-2/+1
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* packet_router: removed unused status words from readback muxJosh Blum2010-11-231-3/+3
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* packet_router: swapped comm mux for a crossbar, serdes crossbar out now ↵Josh Blum2010-11-231-27/+62
| | | | muxed into the comm output
* packet_router: used registered valid signal for BRAM read cycle delayJosh Blum2010-11-231-16/+15
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* packet_router: created dsp framer for rx pathJosh Blum2010-11-231-6/+100
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* packet_router: added lines for com crossbar and com output muxJosh Blum2010-11-231-13/+35
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* packet_router: fixed swapped connection typo, dsp tx routing worksJosh Blum2010-11-231-2/+3
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* packet_router: collapsed inspector states, fixed terminology for cpu inp vs outJosh Blum2010-11-231-163/+161
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* packet_router: some tweaks, dsp output routing seems to work but has wrong ↵Josh Blum2010-11-231-4/+10
| | | | offset
* packet_router: added all input/output signals to module, created the comm ↵Josh Blum2010-11-232-6/+22
| | | | muxes (in and out)
* packet_router: created com signals (device IO lines that may be ethernet or ↵Josh Blum2010-11-231-79/+100
| | | | serdes)
* packet_router: created inspector and added dsp output (however inspection ↵Josh Blum2010-11-232-4/+134
| | | | logic does not enable it yet)
* packet_router: connected and created CPU read from interface (slow path in ↵Josh Blum2010-11-231-47/+153
| | | | place)
* packet_router: created nearly empty router with eth in attached to mapped memoryJosh Blum2010-11-233-19/+135
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* packets are shorter now, so we need to tell the udp state machine that...Matt Ettus2010-11-231-1/+1
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* no need for second sequence number anymore. Each dsp tx chainMatt Ettus2010-11-212-11/+8
| | | | generates its own flow control packets now.
* shouldn't be executableMatt Ettus2010-11-201-0/+0
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* modernize the testbenchMatt Ettus2010-11-191-18/+30
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* get rid of extraneous U messages when we actually had an ACKMatt Ettus2010-11-182-7/+10
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* fix problem with consecutive timed packets on txMatt Ettus2010-11-181-2/+0
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* simplify time comparison to speed up logic and meet fpga timingMatt Ettus2010-11-132-4/+27
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* we're still on version 12.1Matt Ettus2010-11-132-2/+2
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* Add flow control and other small vrt fixes to u2p, minor cleanupsMatt Ettus2010-11-112-34/+38
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* reset properlyMatt Ettus2010-11-111-0/+1
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* compiles with new file locationsMatt Ettus2010-11-111-1/+1
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* handle zero-length packets properlyMatt Ettus2010-11-113-55/+76
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* clear out the vita tx chain and the tx fifo. need to check the fifoMatt Ettus2010-11-115-24/+25
| | | | reset to make sure it is in the correct clock domain.
* added ability to truly clear out the entire rx chain. also removed old ↵Matt Ettus2010-11-113-29/+27
| | | | style fifo in rx.
* gray code address for emiMatt Ettus2010-11-111-1/+7
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