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* vita49 tx and rx added in, all sample rates now at main system clock rate.Matt Ettus2010-06-014-107/+220
* Merge branch 'udp' into u1e_merge_with_udpMatt Ettus2010-05-274-172/+72
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| * better test program for just the tx sideMatt Ettus2010-05-191-163/+63
| * fix typo, no functionality differenceMatt Ettus2010-05-191-1/+1
| * Merge branch 'master' into udpMatt Ettus2010-05-18224-329/+19
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| * | ignoresMatt Ettus2010-05-181-1/+1
| * | Merge branch 'master' into udp, removes u2_rev1, rev2Matt Ettus2010-05-1310-2076/+0
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| * | | move dsp settings regs to reclocked setting bus. Works, gets us to within 18...Matt Ettus2010-05-122-12/+19
| * | | reverting logic clean up which should have made timing better, but made it wo...Matt Ettus2010-05-111-5/+12
| * | | Merge branch 'master' into udpMatt Ettus2010-05-1111-14/+540
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| * \ \ \ Merge branch 'corgan_fixes' into udp_corganMatt Ettus2010-04-266-32/+47
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* | \ \ \ \ Merge branch 'master' into u1e_merge_with_masterMatt Ettus2010-05-27235-2409/+30
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| * | | | | get rid of some warnings by declaring setting reg widthMatt Ettus2010-05-181-8/+8
| * | | | | added width parameter to avoid warnings (thanks IJB) and default value parameterMatt Ettus2010-05-181-3/+5
| * | | | | added pragmas suggested by Ian Buckley to help ISE12 synthesisMatt Ettus2010-05-181-3/+6
| * | | | | get rid of old CVS linkageMatt Ettus2010-05-18221-315/+0
| * | | | | settings bus to dsp_clk now uses clock crossing fifoMatt Ettus2010-05-162-8/+15
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| * | | | remove files for old prototypes, they were confusing peopleMatt Ettus2010-05-1310-2076/+0
| * | | | revert commit 9899b81f920 which should have improved timing but didn'tMatt Ettus2010-05-131-5/+13
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* | | | test full width packetsMatt Ettus2010-05-241-0/+27
* | | | fifo36_to_ll8 and fifo pacer need a real fifo between them or they deadlock (...Matt Ettus2010-05-211-1/+8
* | | | fix double declarationMatt Ettus2010-05-211-1/+0
* | | | send bigger packets to reduce cpu loadMatt Ettus2010-05-202-3/+3
* | | | put over/underrun on debug bus, remove high order address bitsMatt Ettus2010-05-201-1/+2
* | | | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-201-4/+2
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| * | | | better debug pinsMatt Ettus2010-05-171-6/+4
* | | | | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-203-34/+48
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* | | | moved fifos into gpmc_async, reorganized top level a bit, added in crc packet...Matt Ettus2010-05-126-66/+144
* | | | add missing signal from sensitivity listMatt Ettus2010-05-121-1/+1
* | | | Merge branch 'master' into u1eMatt Ettus2010-05-1217-46/+587
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| * | | remove port which is no longer thereMatt Ettus2010-05-111-1/+1
| * | | cleaned up the logic, this is copied over from quad radioMatt Ettus2010-05-111-13/+5
| * | | allow settings bus to cross to a new clock domain, should help timing, but no...Matt Ettus2010-05-119-0/+534
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| * | Update config to all eight clock buffers to be used.Johnathan Corgan2010-03-291-1/+1
| * | Added timing constraint for Wishbone clock/dsp_clock skewJohnathan Corgan2010-03-291-0/+2
| * | Merge commit 'upstream/master'Johnathan Corgan2010-03-091-1/+1
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| * | | Cut debug bus connection to etherenet MAC to make closing timing easierIan Buckley2010-02-241-2/+7
| * | | Remove some warnings in dsp_core_rxJohnathan Corgan2010-02-231-3/+7
| * | | Fix missing item on sensitivity listJohnathan Corgan2010-02-231-1/+1
| * | | Change bit width of CORDIC constants to remove meaningless warningJohnathan Corgan2010-02-231-24/+24
| * | | Manually assign clk_fpga to BUFG to improve timingJohnathan Corgan2010-02-231-1/+5
* | | | packet generator and verifier, to test gpmc and other data transfer stuffMatt Ettus2010-05-124-0/+153
* | | | switched passthru of cgen_sen_b to gpio127, made a note of it. No more safe_...Matt Ettus2010-05-108-561/+9
* | | | proper signal level for 24 bit dataMatt Ettus2010-05-101-2/+7
* | | | SPI passthru for programming clock gen chip on brand new boardsMatt Ettus2010-05-073-0/+391
* | | | added DAC output pins, and a sine wave generator to test themMatt Ettus2010-05-043-18/+63
* | | | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-042-0/+14
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| * | | | add timing constraints. Just have main clock signal at 64 MHz for now.Matt Ettus2010-05-042-0/+14
* | | | | changed commentMatt Ettus2010-05-041-1/+1
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* | | | have_space and have_packet now stay high even while busy,Matt Ettus2010-05-033-4/+6
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