uhd - Ettus' UHD Repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	Merge branch 'master' into udp	Matt Ettus	2010-03-25	2	-3/+1
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\| *	proper initialization of the ram	Matt Ettus	2010-02-23	1	-1/+1
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\| *	Moved usrp2 fpga files into usrp2 subdir.	Josh Blum	2010-01-22	633	-0/+1556369
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*	moved fifos around, now easier to see where they are and how big	Matt Ettus	2010-03-25	2	-17/+30
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*	bigger fifo on UDP TX path, to possibly fix overruns on decim=4	Matt Ettus	2010-03-24	1	-2/+11
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*	Xilinx ISE is incorrectly parsing the verilog case statement, this is a ↵	Matt Ettus	2010-03-24	1	-1/+7
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*	pps and vita time debug pins	Matt Ettus	2010-03-23	1	-3/+6
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*	more debug for fixing E's	Matt Ettus	2010-03-10	2	-6/+13
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*	better debug pins for going after cascading E's	Matt Ettus	2010-03-10	1	-1/+5
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*	copied over from quad radio	Matt Ettus	2010-02-08	1	-0/+60
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*	Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udp	Matt Ettus	2010-01-25	4	-34/+43
\| \| \| \| \| \| \| \|	Merge latest VRT changes into UDP branch. Merged from 1 behind the head of VRT because the head moved things around and confused git Conflicts: usrp2/timing/time_64bit.v usrp2/top/u2_core/u2_core.v
*	just debug pin changes	Matt Ettus	2010-01-25	2	-1/+12
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*	typo caused the tx udp chain to be disconnected	Matt Ettus	2010-01-23	1	-1/+1
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*	moved into subdir	Josh Blum	2010-01-22	653	-0/+1558662