uhd - Ettus' UHD Repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	dsp: ability to set rx dc offset to a fixed value	Matt Ettus	2011-10-26	1	-1/+2
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*	usrp2: fix typo in top level core files	Josh Blum	2011-10-26	2	-2/+2
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*	connect and map b100 and e100 front-panel leds	Josh Blum	2011-10-11	2	-2/+2
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*	E100: GPSDO serial port level conversion	Nick Foster	2011-09-28	2	-2/+9
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*	B100: use gpif_misc on R2 hw, invert direction of gpif_misc pins	Nick Foster	2011-09-19	1	-2/+2
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*	u1e,u1p: turn off debug pins, misc cleanups	Matt Ettus	2011-09-08	2	-26/+10
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*	u1p: proper format in ucf file	Matt Ettus	2011-09-08	5	-4/+474
\| \| \| \|	u1p: build separate u1plus (prototypes) and B100 (release)
*	u1e: relax GPMC constraints, eases P&R	Matt Ettus	2011-09-02	1	-10/+10
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*	u1e: separate build for E100 and E110, just a different FPGA	Matt Ettus	2011-09-01	2	-1/+102
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*	e100: squashed work on bus implementation on GPMC	Josh Blum	2011-08-29	22	-984/+545
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*	fix warning on dat_o in atr_controller16.v	Josh Blum	2011-08-29	1	-3/+2
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*	fpga: minor tweaks to build system	Josh Blum	2011-08-26	2	-2/+4
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*	fix typo	Matt Ettus	2011-08-26	1	-21/+21
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*	all: tie unused ram inputs to 1 instead of zero, helps routing	Matt Ettus	2011-08-26	2	-22/+22
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*	b100: gpif_rst resynced to gpif_clk	Matt Ettus	2011-08-26	1	-1/+1
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*	dsp: slow down the time constant of the DC offset correction by a factor of ↵	Matt Ettus	2011-08-26	1	-1/+1
\| \| \| \|	16. it may need to be even slower.
*	usrp2: reconnect frontend calibration, timing meets	Josh Blum	2011-08-26	5	-6/+6
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*	e100: continuation of the atr fix to get e100 to build	Josh Blum	2011-08-15	1	-2/+2
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*	usrp2: bump FPGA minor number to 2 for patch release	Josh Blum	2011-08-15	2	-2/+2
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*	connect unused BRAM inputs to 1s to save routing logic	Josh Blum	2011-08-15	1	-1/+1
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*	dsp: clear cic_decim when not enabled	Matt Ettus	2011-08-15	1	-4/+4
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*	N2x0: print constraints summary from makefile	Josh Blum	2011-08-15	1	-0/+1
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*	N2x0: added a Makefile to build all N2x0 projects (make -j4)	Josh Blum	2011-08-15	1	-0/+22
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*	N2x0: delay ADC A inversion so A and B are latched in the same	Josh Blum	2011-08-15	1	-3/+5
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*	B100/E100: fix ATR RX mode pins not connected	Nick Foster	2011-08-10	2	-4/+4
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*	time: register time output to help fpga timing	Matt Ettus	2011-07-28	1	-2/+5
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*	vrt: delay the late signal to help with timing	Matt Ettus	2011-07-28	1	-5/+20
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*	dsp: allow tx iq balance to be removed at compile time	Matt Ettus	2011-07-28	1	-23/+38
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*	dsp: option to remove iq compensation at compile time	Matt Ettus	2011-07-28	1	-35/+40
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*	time64: reverted mimo sync changes to time64	Josh Blum	2011-07-28	1	-3/+1
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*	u2/u2p: speed up time_64, and remove readbacks on simple_gemac wb regs	Matt Ettus	2011-07-28	2	-11/+13
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*	simple_gemac: remove old 19-bit wide wrapper	Matt Ettus	2011-07-28	4	-402/+0
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*	usrp2: remove old unused readback mux value	Josh Blum	2011-07-28	2	-2/+2
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*	usrp2: bump minor version number for changes	Josh Blum	2011-07-28	2	-2/+2
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*	vita_rx_ctrl: use an extra cmd bit to signal stop	Josh Blum	2011-07-28	1	-7/+7
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*	usrp2: fixed swapped tx/rx signals for nsgpio	Josh Blum	2011-07-28	2	-2/+2
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*	simple_gemac: add parameter to allow disabling rx flow control at compile time	Matt Ettus	2011-07-27	1	-6/+10
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*	u2/u2p: apply atr/gpio changes to u2p	Matt Ettus	2011-07-27	2	-14/+7
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*	atr: forgot to delete this line	Matt Ettus	2011-07-27	1	-1/+0
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*	u2: redo the atr gpio pins, remove some old cruft	Matt Ettus	2011-07-27	2	-52/+48
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*	u2p: finish copying over serdes light fix	Matt Ettus	2011-07-22	1	-2/+1
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*	u2/u2p: further qualify the serdes link light	Matt Ettus	2011-07-21	3	-7/+13
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*	usrp2: split inspection logic into each relevant cycle	Josh Blum	2011-07-19	1	-11/+35
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*	appease the ISE gods	Matt Ettus	2011-07-19	5	-2/+5
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*	removed wb readback of ATR, allowing it to be synthesized as luts	Matt Ettus	2011-07-19	2	-4/+10
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*	N200: detailed map report allows you to see what takes up too much space	Matt Ettus	2011-07-19	4	-0/+4
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*	dsp: reduce bitwidth to help timing	Matt Ettus	2011-07-19	1	-4/+6
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*	fpga: print timing report after generate bin file	Josh Blum	2011-07-19	2	-1/+34
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*	dsp: reset the interpolator when the rate changes, to prevent oscillation	Matt Ettus	2011-07-19	1	-7/+8
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*	b100: fix for fpga syntax error on xfer_rate	Josh Blum	2011-07-19	1	-1/+1
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