| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Added timing constraint for Wishbone clock/dsp_clock skew | Johnathan Corgan | 2010-03-29 | 1 | -0/+2 |
| | | |||||
| * | Merge commit 'upstream/master' | Johnathan Corgan | 2010-03-09 | 1 | -1/+1 |
| |\ | |||||
| | * | proper initialization of the ram | Matt Ettus | 2010-02-23 | 1 | -1/+1 |
| | | | |||||
| * | | Cut debug bus connection to etherenet MAC to make closing timing easier | Ian Buckley | 2010-02-24 | 1 | -2/+7 |
| | | | |||||
| * | | Remove some warnings in dsp_core_rx | Johnathan Corgan | 2010-02-23 | 1 | -3/+7 |
| | | | |||||
| * | | Fix missing item on sensitivity list | Johnathan Corgan | 2010-02-23 | 1 | -1/+1 |
| | | | |||||
| * | | Change bit width of CORDIC constants to remove meaningless warning | Johnathan Corgan | 2010-02-23 | 1 | -24/+24 |
| | | | |||||
| * | | Manually assign clk_fpga to BUFG to improve timing | Johnathan Corgan | 2010-02-23 | 1 | -1/+5 |
| |/ | | | | | | | | | | | | | | Starting Router Phase 1: 96908 unrouted; REAL time: 25 secs Phase 2: 85651 unrouted; REAL time: 35 secs Phase 3: 27099 unrouted; REAL time: 49 secs Phase 4: 27099 unrouted; (97405) REAL time: 49 secs Phase 5: 27259 unrouted; (5348) REAL time: 54 secs Phase 6: 27277 unrouted; (0) REAL time: 54 secs Phase 7: 0 unrouted; (0) REAL time: 1 mins 46 secs Phase 8: 0 unrouted; (0) REAL time: 1 mins 56 secs Phase 9: 0 unrouted; (0) REAL time: 2 mins 29 secs | ||||
| * | Moved usrp2 fpga files into usrp2 subdir. | Josh Blum | 2010-01-22 | 633 | -0/+1556369 |
 |
index : uhd | |
| Ettus' UHD Repository |
| summaryrefslogtreecommitdiffstats |