| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | Xilinx ISE is incorrectly parsing the verilog case statement, this is a worka... | Matt Ettus | 2010-03-24 | 1 | -1/+7 | |
| * | pps and vita time debug pins | Matt Ettus | 2010-03-23 | 1 | -3/+6 | |
| * | more debug for fixing E's | Matt Ettus | 2010-03-10 | 2 | -6/+13 | |
| * | better debug pins for going after cascading E's | Matt Ettus | 2010-03-10 | 1 | -1/+5 | |
| * | copied over from quad radio | Matt Ettus | 2010-02-08 | 1 | -0/+60 | |
| * | Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udp | Matt Ettus | 2010-01-25 | 4 | -34/+43 | |
| * | just debug pin changes | Matt Ettus | 2010-01-25 | 2 | -1/+12 | |
| * | typo caused the tx udp chain to be disconnected | Matt Ettus | 2010-01-23 | 1 | -1/+1 | |
| * | moved into subdir | Josh Blum | 2010-01-22 | 653 | -0/+1558662 | |
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| Ettus' UHD Repository |
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