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* the width of the address bus is called DEPTH, not WIDTH...Matt Ettus2010-10-211-2/+2
* address gray codingMatt Ettus2010-10-211-1/+7
* slow slew rate and lower drive to 8ma on RAM_XX signals to reduce emiMatt Ettus2010-10-211-43/+43
* should combine the randomizer with flow_controlMatt Ettus2010-10-215-71/+254
* now handles frames larger than the vita packet (i.e. with padding)Matt Ettus2010-10-121-6/+16
* don't clear out following packets on an eob ackMatt Ettus2010-10-121-1/+1
* don't flag an error on eob ackMatt Ettus2010-10-121-1/+1
* proper triggering for interrupts generated on the dsp_clkMatt Ettus2010-10-121-1/+8
* cleanup for 32 bit seqnumMatt Ettus2010-10-111-4/+3
* increase compatibility number for flow controlMatt Ettus2010-10-111-1/+1
* switch to 32 bit sequence numbers. Will wrap in ~15 hours at max rateMatt Ettus2010-10-113-14/+16
* send message on eob to ack the end of transmissionMatt Ettus2010-10-111-1/+6
* typo which isn't caught by xilinxMatt Ettus2010-10-111-1/+1
* separated flow control and error reporting on tx path. should work with and ...Matt Ettus2010-10-104-25/+43
* go to the correct stateMatt Ettus2010-10-081-3/+3
* add a fifo to the end of the mux to help in timing.Matt Ettus2010-10-081-6/+13
* add trigger to makefileMatt Ettus2010-10-081-0/+1
* assign setting reg addressesMatt Ettus2010-10-081-2/+2
* declarationsMatt Ettus2010-10-081-2/+3
* checkpoint in flow control packet generationMatt Ettus2010-10-085-42/+147
* revert unneeded changes and incorrect commentsMatt Ettus2010-10-073-38/+38
* reconnect GPIOs, remove debug pins, meets timing nowMatt Ettus2010-10-061-5/+3
* Merge branch 'ise12' into efifo_merge_dcmMatt Ettus2010-10-063-29/+23
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| * fix timing problem on DAC output busMatt Ettus2010-10-011-2/+2
| * clean up DAC inversion and swapping to match schematicsMatt Ettus2010-08-251-3/+6
| * Clean up iq swapping on RX. It is now swapped in the top level.Matt Ettus2010-08-253-27/+18
| * Merge branch 'features' into tx_policyMatt Ettus2010-08-172-3/+6
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* | | Modified phase shift of DCM1 to -64 which is intended to give more timing mar...Ian Buckley2010-09-301-1/+1
* | | Enabled phase offset adjustment on DCM_INST1 which drives the external Fast S...Ian Buckley2010-09-141-12/+12
* | | Added to DCM's and some BUFG's to align the internal 125MHz clock edge with i...Ian Buckley2010-09-014-5/+101
* | | Merge branch 'efifo_merge' of git@ettus.sourcerepo.com:ettus/fpgapriv into ef...Ian Buckley2010-09-015-47/+60
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| * | | hangedddddddextrnal fifo size to use full NoBL SRAMianb2010-08-251-1/+1
| * | | Corrected extfifo code so that all registers that are on SRAM signals are pac...ianb2010-08-255-46/+59
* | | | Enhanced test bench to be more like real world applicationIan Buckley2010-09-012-7/+14
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* | | capacity logic fixMatt Ettus2010-08-191-1/+1
* | | Added capacity to the module pinoutIan Buckley2010-08-191-3/+4
* | | Added a bunch of debug signals.Ian Buckley2010-08-194-9/+19
* | | Merge branch 'ise12_efifo_work' into efifo_mergeMatt Ettus2010-08-198-236/+113
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| * | | Regenerated FIFO with lower trigger level for almost full flag to reflect log...Ian Buckley2010-08-199-238/+115
* | | | Merge branch 'features' into ise12_efifo_mergeMatt Ettus2010-08-162-3/+6
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| * | | added compat number to usrp2 readback muxJosh Blum2010-08-091-2/+5
| * | | makefile dependency fix for second expansionJosh Blum2010-08-091-1/+1
* | | | Matt's attempt at mergingMatt Ettus2010-08-1610-5569/+306
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| * | | rx error context packets should not be marked as errors in the fifoMatt Ettus2010-08-111-1/+1
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| * | provide a way to get out of the error state without processor interventionMatt Ettus2010-07-291-1/+4
| * | sequence number reset upon programming streamidMatt Ettus2010-07-282-5/+11
| * | attempt at avoiding infinite error messagesMatt Ettus2010-07-281-5/+14
| * | implemented "next packet" and "next burst" policiesMatt Ettus2010-07-283-24/+50
| * | sequence errors can happen on start of burst as well.Matt Ettus2010-07-281-1/+1
| * | more informative error codesMatt Ettus2010-07-282-6/+8
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