| Commit message (Expand) | Author | Age | Files | Lines |
... | |
* | assign setting reg addresses | Matt Ettus | 2010-11-11 | 1 | -2/+2 |
* | declarations | Matt Ettus | 2010-11-11 | 1 | -2/+3 |
* | checkpoint in flow control packet generation | Matt Ettus | 2010-11-11 | 5 | -42/+147 |
* | these got dropped during the rebase | Matt Ettus | 2010-11-11 | 4 | -31/+37 |
* | Removed 'ifdef for second DCM that was a deign idea for external SRAM on u2pl... | Ian Buckley | 2010-11-11 | 1 | -49/+4 |
* | 1) Created new FIFO IP in Coregen. 512x36 dual clcok FIFO with programable fu... | Ian Buckley | 2010-11-11 | 11 | -11/+555 |
* | 1) u2p has added a new signal from the SRAM to the pinout, RAM_ZZ | Ian Buckley | 2010-11-11 | 4 | -11/+17 |
* | Defaulted all SRAM pins to LVCMOS25 8mA FAST | Ian Buckley | 2010-11-11 | 1 | -67/+67 |
* | Placed 2nd DCM into `ifdef DCM_FOR_RAMCLK which is dissabled by default | Ian Buckley | 2010-11-11 | 2 | -7/+23 |
* | Added external RAM FIFO to u2plus. | Ian Buckley | 2010-11-11 | 20 | -100/+4498 |
* | revert unneeded changes and incorrect comments | Matt Ettus | 2010-11-11 | 2 | -34/+34 |
* | reconnect GPIOs, remove debug pins, meets timing now | Matt Ettus | 2010-11-11 | 1 | -5/+3 |
* | Modified phase shift of DCM1 to -64 which is intended to give more timing mar... | Ian Buckley | 2010-11-11 | 1 | -1/+1 |
* | Enabled phase offset adjustment on DCM_INST1 which drives the external Fast S... | Ian Buckley | 2010-11-11 | 1 | -12/+12 |
* | Added to DCM's and some BUFG's to align the internal 125MHz clock edge with i... | Ian Buckley | 2010-11-11 | 4 | -5/+100 |
* | Enhanced test bench to be more like real world application | Ian Buckley | 2010-11-11 | 2 | -7/+14 |
* | hangedddddddextrnal fifo size to use full NoBL SRAM | ianb | 2010-11-11 | 1 | -1/+1 |
* | Corrected extfifo code so that all registers that are on SRAM signals are pac... | ianb | 2010-11-11 | 5 | -46/+59 |
* | capacity logic fix | Matt Ettus | 2010-11-11 | 1 | -1/+1 |
* | Added capacity to the module pinout | Ian Buckley | 2010-11-11 | 1 | -3/+4 |
* | Added a bunch of debug signals. | Ian Buckley | 2010-11-11 | 4 | -9/+19 |
* | Regenerated FIFO with lower trigger level for almost full flag to reflect log... | Ian Buckley | 2010-11-11 | 8 | -236/+113 |
* | Regenerated FIFO's for extfifo. | Ian Buckley | 2010-11-11 | 11 | -726/+15 |
* | Edited FIFO instance to delete port that was not regenerated after reconfigur... | Ian Buckley | 2010-11-11 | 1 | -1/+0 |
* | Adding in files that probably didn;t exist in the ISE10.1 version of coregen | Ian Buckley | 2010-11-11 | 5 | -0/+808 |
* | Bringing all coregen files checked in into sync | Ian Buckley | 2010-11-11 | 10 | -137/+60 |
* | Found bug due to not accounting for the correct number of possible in flight ... | Ian Buckley | 2010-11-11 | 7 | -52/+110 |
* | checkin of generated coregen files | Matt Ettus | 2010-11-11 | 18 | -8/+556 |
* | External FIFO tested in simulation and on USRP2 from decimation 64->8 with cu... | Ian Buckley | 2010-11-11 | 18 | -236/+7297 |
* | Checkpoint checkin. | Ian Buckley | 2010-11-11 | 13 | -0/+1507 |
* | get it to build | Matt Ettus | 2010-11-11 | 5 | -5/+309 |
* | moved forward from the old branch | Matt Ettus | 2010-11-11 | 8 | -4/+876 |
* | reverting part of the reversion of the spi settings. | Matt Ettus | 2010-11-10 | 1 | -2/+2 |
* | u2p needs the bigger regs for some reason | Matt Ettus | 2010-11-10 | 1 | -4/+4 |
* | need to enable both 16 and 32 bit spi interfaces -- 16 used in u1e, 32 in u2 ... | Matt Ettus | 2010-11-10 | 1 | -0/+1 |
* | occ needs to be 2 bits wide on a 36 bit fifo interface. | Matt Ettus | 2010-11-10 | 1 | -1/+2 |
* | Merge branch 'u1e' into merge_u1e | Matt Ettus | 2010-11-10 | 64 | -215/+3325 |
|\ |
|
| * | invert led signals because they are active low | Matt Ettus | 2010-11-09 | 1 | -1/+1 |
| * | duh | Matt Ettus | 2010-11-04 | 1 | -1/+1 |
| * | allow for CS to rise before, at the same time, or after OE | Matt Ettus | 2010-09-24 | 1 | -7/+6 |
| * | better debug pins | Matt Ettus | 2010-09-23 | 2 | -7/+11 |
| * | watch the ethernet chip select on our debug bus | Matt Ettus | 2010-09-23 | 3 | -6/+8 |
| * | fix timing issue on DAC outputs with rev 2. This puts the whole system on a ... | Matt Ettus | 2010-09-21 | 2 | -50/+25 |
| * | send all gpmc signals to mictor | Matt Ettus | 2010-09-16 | 4 | -0/+201 |
| * | updated pins to match rev2, removed dip switch, etc. seems to compile ok. | Matt Ettus | 2010-09-09 | 3 | -137/+130 |
| * | pins are different on rev2 | Matt Ettus | 2010-09-09 | 1 | -264/+4 |
| * | fixed makefile to compile with our new system | Matt Ettus | 2010-09-07 | 1 | -44/+36 |
| * | add register to tell host about compatibility level and which image we are using | Matt Ettus | 2010-08-30 | 1 | -5/+14 |
| * | move declaration to make loopback compile | Matt Ettus | 2010-08-27 | 1 | -1/+2 |
| * | Merge branch 'tx_policy' into u1e | Matt Ettus | 2010-08-25 | 3 | -29/+23 |
| |\ |
|