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| * | | | | | | | | Merge branch 'master' into u1eMatt Ettus2010-06-083-15/+17
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| * | | | | | | | | | remove double declarationMatt Ettus2010-06-061-1/+1
| * | | | | | | | | | use fifo19 not fifo18 in makefileMatt Ettus2010-06-061-1/+1
| * | | | | | | | | | added little endian capability for gpmc to fifo and fifo to gpmc, since ARM i...Matt Ettus2010-06-064-41/+51
| * | | | | | | | | | get rid of redundant fifo18, since we can just use fifo19 and ignore the occ bitMatt Ettus2010-06-063-44/+6
| * | | | | | | | | | Phil wants gpio #145Matt Ettus2010-06-032-4/+4
| * | | | | | | | | | use same version as usrp2-udp, so regs are same place in memory mapMatt Ettus2010-06-012-2/+2
| * | | | | | | | | | Merge branch 'ise12_exp' into u1eMatt Ettus2010-06-0110-391/+1747
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| | * | | | | | | | | | zero out debug pins. helps timing a little bit.Matt Ettus2010-06-011-9/+11
| | * | | | | | | | | | Merge branch 'new_ramloader' into nocache_plus_newramloader, plus manual merg...Matt Ettus2010-05-284-250/+280
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| | | * | | | | | | | | | experimental mods to make ram loader fully synchronous. Based on IJB's workMatt Ettus2010-05-263-235/+266
| | * | | | | | | | | | | Merge branch 'master_nocache' into master_nocache_post_mergeMatt Ettus2010-05-287-26/+114
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| | | * | | | | | | | | | | change the debug pins, which makes it more reliable. This is unnerving.Matt Ettus2010-05-261-1/+2
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| | | * | | | | | | | | | fixes from IJB from 5/24. Basically connect unconnected wires.Matt Ettus2010-05-242-2/+5
| | | * | | | | | | | | | removes the icache and pipelines the readsMatt Ettus2010-05-205-16/+98
| * | | | | | | | | | | | connect the rx run lines so it doesn't get optimized outMatt Ettus2010-06-011-1/+4
| * | | | | | | | | | | | use DDR regs instead of a 2nd clockMatt Ettus2010-06-011-8/+46
| * | | | | | | | | | | | assign addresses for the settings regsMatt Ettus2010-06-011-5/+6
| * | | | | | | | | | | | vita49 tx and rx added in, all sample rates now at main system clock rate.Matt Ettus2010-06-014-107/+220
| * | | | | | | | | | | | Merge branch 'udp' into u1e_merge_with_udpMatt Ettus2010-05-274-172/+72
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| * \ \ \ \ \ \ \ \ \ \ \ \ Merge branch 'master' into u1e_merge_with_masterMatt Ettus2010-05-27235-2409/+30
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| * | | | | | | | | | | | | test full width packetsMatt Ettus2010-05-241-0/+27
| * | | | | | | | | | | | | fifo36_to_ll8 and fifo pacer need a real fifo between them or they deadlock (...Matt Ettus2010-05-211-1/+8
| * | | | | | | | | | | | | fix double declarationMatt Ettus2010-05-211-1/+0
| * | | | | | | | | | | | | send bigger packets to reduce cpu loadMatt Ettus2010-05-202-3/+3
| * | | | | | | | | | | | | put over/underrun on debug bus, remove high order address bitsMatt Ettus2010-05-201-1/+2
| * | | | | | | | | | | | | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-201-4/+2
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| | * | | | | | | | | | | | | better debug pinsMatt Ettus2010-05-171-6/+4
| * | | | | | | | | | | | | | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-203-34/+48
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| * | | | | | | | | | | | | moved fifos into gpmc_async, reorganized top level a bit, added in crc packet...Matt Ettus2010-05-126-66/+144
| * | | | | | | | | | | | | add missing signal from sensitivity listMatt Ettus2010-05-121-1/+1
| * | | | | | | | | | | | | Merge branch 'master' into u1eMatt Ettus2010-05-1217-46/+587
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| * | | | | | | | | | | | | | packet generator and verifier, to test gpmc and other data transfer stuffMatt Ettus2010-05-124-0/+153
| * | | | | | | | | | | | | | switched passthru of cgen_sen_b to gpio127, made a note of it. No more safe_...Matt Ettus2010-05-108-561/+9
| * | | | | | | | | | | | | | proper signal level for 24 bit dataMatt Ettus2010-05-101-2/+7
| * | | | | | | | | | | | | | SPI passthru for programming clock gen chip on brand new boardsMatt Ettus2010-05-073-0/+391
| * | | | | | | | | | | | | | added DAC output pins, and a sine wave generator to test themMatt Ettus2010-05-043-18/+63
| * | | | | | | | | | | | | | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-042-0/+14
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| | * | | | | | | | | | | | | | add timing constraints. Just have main clock signal at 64 MHz for now.Matt Ettus2010-05-042-0/+14
| * | | | | | | | | | | | | | | changed commentMatt Ettus2010-05-041-1/+1
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| * | | | | | | | | | | | | | have_space and have_packet now stay high even while busy,Matt Ettus2010-05-033-4/+6
| * | | | | | | | | | | | | | separate timed tx and rx instead of loopbackMatt Ettus2010-04-281-3/+51
| * | | | | | | | | | | | | | send bus error to debug pinsMatt Ettus2010-04-261-2/+4
| * | | | | | | | | | | | | | Pass previously unused GPIOs to debug pins to help debug interruptsMatt Ettus2010-04-243-16/+21
| * | | | | | | | | | | | | | Only allow new packets if we can fit the largest possible packet (2KB)Matt Ettus2010-04-231-1/+1
| * | | | | | | | | | | | | | Register outputs to omap to prevent runt pulses from falsely triggering inter...Matt Ettus2010-04-233-7/+20
| * | | | | | | | | | | | | | find time_64bitMatt Ettus2010-04-201-0/+1
| * | | | | | | | | | | | | | added pps and time capabilityMatt Ettus2010-04-153-5/+21
| * | | | | | | | | | | | | | access frame length regs from wishboneMatt Ettus2010-04-152-10/+18
| * | | | | | | | | | | | | | async seems to work with packet lengths now. Still need to do wishbone regs ...Matt Ettus2010-04-155-37/+72
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