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* switch to 32 bit sequence numbers. Will wrap in ~15 hours at max rateMatt Ettus2010-11-113-14/+16
* send message on eob to ack the end of transmissionMatt Ettus2010-11-111-1/+6
* typo which isn't caught by xilinxMatt Ettus2010-11-111-1/+1
* separated flow control and error reporting on tx path. should work with and ...Matt Ettus2010-11-114-25/+43
* go to the correct stateMatt Ettus2010-11-111-3/+3
* add a fifo to the end of the mux to help in timing.Matt Ettus2010-11-111-6/+13
* add trigger to makefileMatt Ettus2010-11-111-0/+1
* assign setting reg addressesMatt Ettus2010-11-111-2/+2
* declarationsMatt Ettus2010-11-111-2/+3
* checkpoint in flow control packet generationMatt Ettus2010-11-115-42/+147
* these got dropped during the rebaseMatt Ettus2010-11-114-31/+37
* Removed 'ifdef for second DCM that was a deign idea for external SRAM on u2pl...Ian Buckley2010-11-111-49/+4
* 1) Created new FIFO IP in Coregen. 512x36 dual clcok FIFO with programable fu...Ian Buckley2010-11-1111-11/+555
* 1) u2p has added a new signal from the SRAM to the pinout, RAM_ZZIan Buckley2010-11-114-11/+17
* Defaulted all SRAM pins to LVCMOS25 8mA FASTIan Buckley2010-11-111-67/+67
* Placed 2nd DCM into `ifdef DCM_FOR_RAMCLK which is dissabled by defaultIan Buckley2010-11-112-7/+23
* Added external RAM FIFO to u2plus.Ian Buckley2010-11-1120-100/+4498
* revert unneeded changes and incorrect commentsMatt Ettus2010-11-112-34/+34
* reconnect GPIOs, remove debug pins, meets timing nowMatt Ettus2010-11-111-5/+3
* Modified phase shift of DCM1 to -64 which is intended to give more timing mar...Ian Buckley2010-11-111-1/+1
* Enabled phase offset adjustment on DCM_INST1 which drives the external Fast S...Ian Buckley2010-11-111-12/+12
* Added to DCM's and some BUFG's to align the internal 125MHz clock edge with i...Ian Buckley2010-11-114-5/+100
* Enhanced test bench to be more like real world applicationIan Buckley2010-11-112-7/+14
* hangedddddddextrnal fifo size to use full NoBL SRAMianb2010-11-111-1/+1
* Corrected extfifo code so that all registers that are on SRAM signals are pac...ianb2010-11-115-46/+59
* capacity logic fixMatt Ettus2010-11-111-1/+1
* Added capacity to the module pinoutIan Buckley2010-11-111-3/+4
* Added a bunch of debug signals.Ian Buckley2010-11-114-9/+19
* Regenerated FIFO with lower trigger level for almost full flag to reflect log...Ian Buckley2010-11-118-236/+113
* Regenerated FIFO's for extfifo.Ian Buckley2010-11-1111-726/+15
* Edited FIFO instance to delete port that was not regenerated after reconfigur...Ian Buckley2010-11-111-1/+0
* Adding in files that probably didn;t exist in the ISE10.1 version of coregenIan Buckley2010-11-115-0/+808
* Bringing all coregen files checked in into syncIan Buckley2010-11-1110-137/+60
* Found bug due to not accounting for the correct number of possible in flight ...Ian Buckley2010-11-117-52/+110
* checkin of generated coregen filesMatt Ettus2010-11-1118-8/+556
* External FIFO tested in simulation and on USRP2 from decimation 64->8 with cu...Ian Buckley2010-11-1118-236/+7297
* Checkpoint checkin.Ian Buckley2010-11-1113-0/+1507
* get it to buildMatt Ettus2010-11-115-5/+309
* moved forward from the old branchMatt Ettus2010-11-118-4/+876
* reverting part of the reversion of the spi settings.Matt Ettus2010-11-101-2/+2
* u2p needs the bigger regs for some reasonMatt Ettus2010-11-101-4/+4
* need to enable both 16 and 32 bit spi interfaces -- 16 used in u1e, 32 in u2 ...Matt Ettus2010-11-101-0/+1
* occ needs to be 2 bits wide on a 36 bit fifo interface.Matt Ettus2010-11-101-1/+2
* Merge branch 'u1e' into merge_u1eMatt Ettus2010-11-1064-215/+3325
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| * invert led signals because they are active lowMatt Ettus2010-11-091-1/+1
| * duhMatt Ettus2010-11-041-1/+1
| * allow for CS to rise before, at the same time, or after OEMatt Ettus2010-09-241-7/+6
| * better debug pinsMatt Ettus2010-09-232-7/+11
| * watch the ethernet chip select on our debug busMatt Ettus2010-09-233-6/+8
| * fix timing issue on DAC outputs with rev 2. This puts the whole system on a ...Matt Ettus2010-09-212-50/+25
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