| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
| |
Loopback is running via the external ZBT SRAM...HOWEVER, its not running well, its stable but the data is corrupted sometimes.
Not clear if its a logic or AC timing/SI issue yet.
|
| |
|
| |
|
| |
|
| |
|
|
|
|
| |
and u2p
|
| |
|
|\
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
* u1e: (130 commits)
invert led signals because they are active low
duh
allow for CS to rise before, at the same time, or after OE
better debug pins
watch the ethernet chip select on our debug bus
fix timing issue on DAC outputs with rev 2. This puts the whole system on a 90 degree phase shift
send all gpmc signals to mictor
updated pins to match rev2, removed dip switch, etc. seems to compile ok.
pins are different on rev2
fixed makefile to compile with our new system
add register to tell host about compatibility level and which image we are using
move declaration to make loopback compile
no need for protocol headers since we're not doing ethernet
match the signal names in this design
debug pins cleanup
properly integrate the new tx chain
catch up with tx_policy
attach run_tx and run_rx to leds
connect atr
delay the q channel to make the channels line up on the AD9862
...
Conflicts:
usrp2/control_lib/Makefile.srcs
|
| | |
|
| | |
|
| | |
|
| | |
|
| | |
|
| |
| |
| |
| | |
90 degree phase shift
|
| | |
|
| | |
|
| | |
|
| | |
|
| | |
|
| | |
|
| |\
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
* tx_policy: (21 commits)
clean up DAC inversion and swapping to match schematics
Clean up iq swapping on RX. It is now swapped in the top level. widened muxes to 4 bits to match tx side and handle more ADCs in future
rx error context packets should not be marked as errors in the fifo
added compat number to usrp2 readback mux
makefile dependency fix for second expansion
provide a way to get out of the error state without processor intervention
sequence number reset upon programming streamid
attempt at avoiding infinite error messages
implemented "next packet" and "next burst" policies
sequence errors can happen on start of burst as well.
more informative error codes
cleaner error handling
introduce new error types
test mux and gen_context_pkt
this is an output file, it shouldn't be checked in
insert protocol engine flags when requested
move the streamid so it isn't at the same address as clear_state
connect the demux
fix a typo
tx error packets now muxed into the ethernet stream back to the host
...
Conflicts:
usrp2/top/u2_rev3/u2_core_udp.v
|
| | | |
|
| | | |
|
| | | |
|
| | | |
|
| | | |
|
| | | |
|
| | | |
|
| | | |
|
| | | |
|
| | | |
|
| | | |
|
| |\ \
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
* ise12:
move declaration ahead of use
put run_tx and run_rx on the displayed LEDs
remove warnings
add mux and demux to build
mux multiple fifo streams into one. Allows priority or round robin
split fifo into 2 streams based on first line in each packet
precompute udp checksums
barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but all seem to work ok
|
| | | | |
|
| |\ \ \
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
* reload:
fix to stop endless error packets
updated tests to match new features
|
| | | | | |
|
| |\ \ \ \
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
* reload:
error packets are now valid Extension Context packets
|
| |\ \ \ \ \
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | | |
* reload:
reload bit for vita rx ctrl
|
| |\ \ \ \ \ \
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | | |
* master:
fix bug which caused serdes fifo to disappear
|
| |\ \ \ \ \ \ \
| | | | | | | | |
| | | | | | | | |
| | | | | | | | |
| | | | | | | | | |
* master:
proper dependency tracking for the makefile
|
| | | | | | | | | |
|
| |\ \ \ \ \ \ \ \
| | | | | | | | | |
| | | | | | | | | |
| | | | | | | | | |
| | | | | | | | | |
| | | | | | | | | |
| | | | | | | | | |
| | | | | | | | | |
| | | | | | | | | |
| | | | | | | | | |
| | | | | | | | | |
| | | | | | | | | |
| | | | | | | | | |
| | | | | | | | | |
| | | | | | | | | |
| | | | | | | | | | |
Made so Makefile changes as well to get it to build
* master:
new make works on ise12
produces good bin files
first attempt at cleaning up the build system
get rid of debug stuff to help timing
move u2_core into u2_rev3 directory to simplify directory structure and save headaches
Conflicts:
usrp2/fifo/fifo36_to_fifo18.v
usrp2/top/u2_rev3/Makefile
usrp2/top/u2_rev3/Makefile.udp
usrp2/top/u2_rev3/u2_core_udp.v
|
| | | | | | | | | | |
|
| | | | | | | | | | |
|
| | | | | | | | | | |
|
| | | | | | | | | | |
|
| | | | | | | | | | |
|
| | | | | | | | | | |
|
| |\ \ \ \ \ \ \ \ \
| | | | | | | | | | |
| | | | | | | | | | |
| | | | | | | | | | |
| | | | | | | | | | |
| | | | | | | | | | |
| | | | | | | | | | |
| | | | | | | | | | | |
* master:
allow other clock rates in vita time
report ise version in build
proper name for directory
name build directory with ISE version name
|
| | | | | | | | | | | |
|