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* use our fancy new debug portsMatt Ettus2010-02-231-0/+3
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* settings bus with 16 bit wishbone interface, put on the main wishbone in u1eMatt Ettus2010-02-223-3/+68
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* remove the #1 delay in all the regs. They just slow down sims.Matt Ettus2010-02-224-96/+90
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* Modified nsgpio.v to support 16 bit little endian bus interface.Matt Ettus2010-02-221-0/+124
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* GPIOs now on the wishbone interfaceMatt Ettus2010-02-224-37/+54
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* added gpio control to the wishboneMatt Ettus2010-02-182-11/+14
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* Added I2C, UART, debug pins, misc wishbone stuffMatt Ettus2010-02-183-48/+187
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* allow default uart clock dividerMatt Ettus2010-02-181-6/+7
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* Fixed paths to help icarus find opencores and xilinx models. Added Xilinx ↵Matt Ettus2010-02-182-4/+7
| | | | global set and reset module.
* speed up the presentation of registered wb data to the gpmcMatt Ettus2010-02-172-13/+20
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* wishbone bridge now with minimal functionality. Need to checkMatt Ettus2010-02-168-11/+121
| | | | timing and handle wait states.
* first cut at gpmc <-> wb bridge, split u1e into core, top, and tbMatt Ettus2010-02-166-34/+159
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* copied over from safe_u1eMatt Ettus2010-02-164-0/+553
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* block ram interface to GPMCMatt Ettus2010-02-161-2/+6
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* basic read support for the GPMC, responds with 16'hBEEFMatt Ettus2010-02-161-2/+8
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* reorg pin defsMatt Ettus2010-02-141-94/+102
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* connect GPMC pins to debug busMatt Ettus2010-02-142-76/+94
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* organized the pins in the ucf by functionMatt Ettus2010-02-091-56/+72
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* builds a successful led blinkerMatt Ettus2010-02-093-2/+4
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* first cut at blinking ledsMatt Ettus2010-02-094-345/+237
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* skeletons that don't work yetMatt Ettus2010-02-092-0/+607
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* Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-22633-0/+1556369