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* reset properlyMatt Ettus2010-11-111-0/+1
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* compiles with new file locationsMatt Ettus2010-11-111-1/+1
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* handle zero-length packets properlyMatt Ettus2010-11-113-55/+76
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* clear out the vita tx chain and the tx fifo. need to check the fifoMatt Ettus2010-11-115-24/+25
| | | | reset to make sure it is in the correct clock domain.
* added ability to truly clear out the entire rx chain. also removed old ↵Matt Ettus2010-11-113-29/+27
| | | | style fifo in rx.
* gray code address for emiMatt Ettus2010-11-111-1/+7
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* fifo randomizer for emiMatt Ettus2010-11-115-4/+108
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* now handles frames larger than the vita packet (i.e. with padding)Matt Ettus2010-11-111-6/+16
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* don't clear out following packets on an eob ackMatt Ettus2010-11-111-1/+1
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* don't flag an error on eob ackMatt Ettus2010-11-111-1/+1
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* proper triggering for interrupts generated on the dsp_clkMatt Ettus2010-11-111-1/+8
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* cleanup for 32 bit seqnumMatt Ettus2010-11-111-4/+3
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* increase compatibility number for flow controlMatt Ettus2010-11-111-1/+1
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* switch to 32 bit sequence numbers. Will wrap in ~15 hours at max rateMatt Ettus2010-11-113-14/+16
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* send message on eob to ack the end of transmissionMatt Ettus2010-11-111-1/+6
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* typo which isn't caught by xilinxMatt Ettus2010-11-111-1/+1
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* separated flow control and error reporting on tx path. should work with and ↵Matt Ettus2010-11-114-25/+43
| | | | without flow control
* go to the correct stateMatt Ettus2010-11-111-3/+3
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* add a fifo to the end of the mux to help in timing.Matt Ettus2010-11-111-6/+13
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* add trigger to makefileMatt Ettus2010-11-111-0/+1
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* assign setting reg addressesMatt Ettus2010-11-111-2/+2
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* declarationsMatt Ettus2010-11-111-2/+3
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* checkpoint in flow control packet generationMatt Ettus2010-11-115-42/+147
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* these got dropped during the rebaseMatt Ettus2010-11-114-31/+37
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* Removed 'ifdef for second DCM that was a deign idea for external SRAM on ↵Ian Buckley2010-11-111-49/+4
| | | | | | u2plus. Hardcoded -90 degree clcok from first DCM as final solution
* 1) Created new FIFO IP in Coregen. 512x36 dual clcok FIFO with programable ↵Ian Buckley2010-11-1111-11/+555
| | | | | | full watermark 2) Put larger FIFO on output of u2plus extramfifo that is compatable with u2_rev3 EMI fixes.
* 1) u2p has added a new signal from the SRAM to the pinout, RAM_ZZIan Buckley2010-11-114-11/+17
| | | | | | | | | | | | | | | which allows the SRAM to be placed in a sleep mode. This pin was erroniously pulled high at the top level rendering the SRAM unusable. 2) Added declaration for extramfifo debug bus which had got deleted at some point in the past 3) Created a debug bundle of signals from extsramfifo to help diagnose problem 1) 4) u2p Rev1 PCB ommits control of any of the SRAM chip selects. Made a code change so that control logic does not rely on the presence of this pin and ensuring that the SRAM is always placed in READ mode in any idle cycles.
* Defaulted all SRAM pins to LVCMOS25 8mA FASTIan Buckley2010-11-111-67/+67
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* Placed 2nd DCM into `ifdef DCM_FOR_RAMCLK which is dissabled by defaultIan Buckley2010-11-112-7/+23
| | | | | Derived RAMCLK from 270degree offset of principle core DCM giving theoretical 2.5nS timing advance on RAM_CLK relative to RAM_* signals.
* Added external RAM FIFO to u2plus.Ian Buckley2010-11-1120-100/+4498
| | | | | | | | | | Added code branch to ext_fifo.v using generate that instantiates different input and out fifo's and touched nobl_fifo code so that it works at 18 and 36bit widths. Added 2nd DCM to top level to generate off chip RAMCLK. Added explicit I/O instances to top level for tristate drivers and changed signals to core as needed. Creted new FIFO's in core gen to replace much larger FIFO's used on u2rev3
* revert unneeded changes and incorrect commentsMatt Ettus2010-11-112-34/+34
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* reconnect GPIOs, remove debug pins, meets timing nowMatt Ettus2010-11-111-5/+3
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* Modified phase shift of DCM1 to -64 which is intended to give more timing ↵Ian Buckley2010-11-111-1/+1
| | | | | | | margin on reads from the SRAM at the expense of Writes to the SRAM. Tested to be at least as stable as a phase shift of 12 and beter looking timing on the logic analyzer. Signals driven by the FPGA are observed changing on the SRAM pins about 4 nS after the rising edge of the RAM clock.
* Enabled phase offset adjustment on DCM_INST1 which drives the external Fast ↵Ian Buckley2010-11-111-12/+12
| | | | | | | | SRAM clock. Set phase shift to -12 after experimentation using logic analyzer to see results. This value gives near optimum 1.5nS setup times on the source sync signals FPGA -> SRAM under lab conditions.
* Added to DCM's and some BUFG's to align the internal 125MHz clock edge with ↵Ian Buckley2010-11-114-5/+100
| | | | | | | its presentation externally at the NoBL SRAM. Since we don't have a board level trace to use to estimate clock propigation delay we just loop through the I/O on the FPGA. This hasn't been verified as working on a USRP2 yet.
* Enhanced test bench to be more like real world applicationIan Buckley2010-11-112-7/+14
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* hangedddddddextrnal fifo size to use full NoBL SRAMianb2010-11-111-1/+1
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* Corrected extfifo code so that all registers that are on SRAM signals are ↵ianb2010-11-115-46/+59
| | | | | | | | packed into IOBs Explcit drives and skews added to GPIO pins Corrected minor error in FIFO logic that showed data avail internally incorrectly
* capacity logic fixMatt Ettus2010-11-111-1/+1
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* Added capacity to the module pinoutIan Buckley2010-11-111-3/+4
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* Added a bunch of debug signals.Ian Buckley2010-11-114-9/+19
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* Regenerated FIFO with lower trigger level for almost full flag to reflect ↵Ian Buckley2010-11-118-236/+113
| | | | | | | | | | | | | logic removed from nobl_fifo. Improved ext_fifo_tb further, try to simulate more combinations of decomation rates and packet arrival patterns. Strip out the logic in nobl_fifo that made it look like a Xilinx fall-through FIFO...it is now very simple logic but a propriatory interface that exposes the high inetrnal latency of reads. Allow the USED size of the external FIFO to be parameterized from the core level. Currently set at only 256 Corrected a bug in vita_tx_deframer.v that can write to a FIFO when its full causing illegal state. Made further edits that are currently commented becuase simulation indicates they cause problems, however suspect a further bug is in this code.
* Regenerated FIFO's for extfifo.Ian Buckley2010-11-1111-726/+15
| | | | | | | | There are problems with certain configurations it seems. It is important that the fifo_xlnx_512x36_2clk_18to36 is generated with the "almost_full" pin even though it is not used in the application. if this pin is omitted the FPGA image doesn't work correctly
* Edited FIFO instance to delete port that was not regenerated after ↵Ian Buckley2010-11-111-1/+0
| | | | reconfiguration
* Adding in files that probably didn;t exist in the ISE10.1 version of coregenIan Buckley2010-11-115-0/+808
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* Bringing all coregen files checked in into syncIan Buckley2010-11-1110-137/+60
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* Found bug due to not accounting for the correct number of possible in flight ↵Ian Buckley2010-11-117-52/+110
| | | | | | | | | READ operations that can be in the extfifo pipeline. Regenerated fifo_xlnx_512x36_2clk_18to36 to include prog_full output triggered at 1017 so that there are 6 empty spaces to accept in flight read data upon completion. Had to generate the FIFO using Coregen from ISE12.1 due to 10.1 verion not working correctly in FPGA Still have to tackle making this simulate in Icarus
* checkin of generated coregen filesMatt Ettus2010-11-1118-8/+556
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* External FIFO tested in simulation and on USRP2 from decimation 64->8 with ↵Ian Buckley2010-11-1118-236/+7297
| | | | | | | | current head UHD code. Apparently operation is "flawless" but more regression and corner case regression could and should be done. Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched.
* Checkpoint checkin.Ian Buckley2010-11-1113-0/+1507
| | | | | Loopback is running via the external ZBT SRAM...HOWEVER, its not running well, its stable but the data is corrupted sometimes. Not clear if its a logic or AC timing/SI issue yet.
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