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* async seems to work with packet lengths now. Still need to do wishbone regs ...Matt Ettus2010-04-155-37/+72
* async gpmc progressMatt Ettus2010-04-154-18/+173
* change time parameters because Xilinx IP has a 1ps timescaleMatt Ettus2010-04-151-14/+27
* add bus error reportingMatt Ettus2010-04-151-3/+9
* correct name of moduleMatt Ettus2010-04-151-2/+2
* progress on synchronous gpmc, but it may not be possible due to the limited n...Matt Ettus2010-04-153-43/+45
* synchronous and asynchronous gpmc modelsMatt Ettus2010-04-153-3/+100
* handle all tri-state in the top level of gpmcMatt Ettus2010-04-153-6/+8
* more sync progress. This is just a skeleton for now, with junk contentMatt Ettus2010-04-141-0/+56
* more progress on synchronous interfaceMatt Ettus2010-04-144-26/+95
* renamed to async. Will be building a sync version for GPMC_CLKMatt Ettus2010-04-142-3/+3
* make timing diagrams for bus transactions. Still need to do readsMatt Ettus2010-04-145-0/+46
* added in a loopback fifoMatt Ettus2010-04-141-4/+11
* probably won't be using this, and it hasn't been testedMatt Ettus2010-04-141-0/+46
* minor changes to get it to synthesizeMatt Ettus2010-04-132-1/+4
* lengthened delay between cycles, added more transactions on the data busMatt Ettus2010-04-121-2/+7
* replaced ram interface with a fifo interface. still need to do rx sideMatt Ettus2010-04-123-120/+117
* split out gpmc to wishbone interface to make gpmc top level cleanerMatt Ettus2010-04-121-0/+57
* added 16-bit wide atr controllerMatt Ettus2010-04-015-47/+117
* 16 bit wide spi coreMatt Ettus2010-03-271-0/+182
* connect up the 16 bit spi coreMatt Ettus2010-03-262-5/+4
* remove timescale junkMatt Ettus2010-03-265-21/+19
* connect 2 clock gen controls and 3 status pins to the wishbone so they can be...Matt Ettus2010-03-263-8/+26
* Merge branch 'udp' into u1eMatt Ettus2010-03-2532-132/+2545
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| * Merge branch 'master' into udpMatt Ettus2010-03-252-3/+1
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| * | moved fifos around, now easier to see where they are and how bigMatt Ettus2010-03-252-17/+30
| * | bigger fifo on UDP TX path, to possibly fix overruns on decim=4Matt Ettus2010-03-241-2/+11
| * | Xilinx ISE is incorrectly parsing the verilog case statement, this is a worka...Matt Ettus2010-03-241-1/+7
| * | pps and vita time debug pinsMatt Ettus2010-03-231-3/+6
| * | more debug for fixing E'sMatt Ettus2010-03-102-6/+13
| * | better debug pins for going after cascading E'sMatt Ettus2010-03-101-1/+5
| * | copied over from quad radioMatt Ettus2010-02-081-0/+60
| * | Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udpMatt Ettus2010-01-254-34/+43
| * | just debug pin changesMatt Ettus2010-01-252-1/+12
| * | typo caused the tx udp chain to be disconnectedMatt Ettus2010-01-231-1/+1
| * | moved into subdirJosh Blum2010-01-22653-0/+1558662
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* | connected spi pins, but the spi core still needs to be redone for 16 bit inte...Matt Ettus2010-03-253-40/+60
* | debug pinsMatt Ettus2010-02-251-2/+3
* | enable was on the wrong address pin, needs to be the highest order oneMatt Ettus2010-02-251-2/+2
* | invert the pushbuttons since they are active lowMatt Ettus2010-02-251-2/+2
* | gpmc debug pinsMatt Ettus2010-02-252-4/+14
* | point to the new filesMatt Ettus2010-02-251-0/+2
* | fix syntax error which icarus allowed (filed a bug with them)Matt Ettus2010-02-251-7/+9
* | loopback and testMatt Ettus2010-02-252-7/+38
* | corrected logicMatt Ettus2010-02-251-17/+7
* | edge sync on done signals so we only fill/empty one bufferMatt Ettus2010-02-252-2/+32
* | Switched xilinx primitives because they order the bits funny in the other oneMatt Ettus2010-02-251-48/+79
* | ISE chokes on the pure verilog version so we use the macroMatt Ettus2010-02-251-4/+49
* | First cut at passing data buffers around on GPMC busMatt Ettus2010-02-256-25/+165
* | Merge branch 'master' into u1eMatt Ettus2010-02-231-1/+1
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