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* Adding in files that probably didn;t exist in the ISE10.1 version of coregenIan Buckley2010-08-125-0/+808
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* Bringing all coregen files checked in into syncIan Buckley2010-08-1210-137/+60
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* Merge branch 'ise12_efifo_work' of git@ettus.sourcerepo.com:ettus/fpgapriv ↵Ian Buckley2010-08-1218-41/+587
|\ | | | | | | | | | | | | | | | | | | | | | | into ise12_efifo_work Conflicts: usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc Resolving conflicts by regenerating files clenly in ISE12.1 coregen
| * checkin of generated coregen filesMatt Ettus2010-08-1118-8/+556
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* | Found bug due to not accounting for the correct number of possible in flight ↵Ian Buckley2010-08-127-49/+113
|/ | | | | | | | | READ operations that can be in the extfifo pipeline. Regenerated fifo_xlnx_512x36_2clk_18to36 to include prog_full output triggered at 1017 so that there are 6 empty spaces to accept in flight read data upon completion. Had to generate the FIFO using Coregen from ISE12.1 due to 10.1 verion not working correctly in FPGA Still have to tackle making this simulate in Icarus
* External FIFO tested in simulation and on USRP2 from decimation 64->8 with ↵Ian Buckley2010-07-3119-238/+7327
| | | | | | | | current head UHD code. Apparently operation is "flawless" but more regression and corner case regression could and should be done. Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched.
* Checkpoint checkin.Ian Buckley2010-07-2913-0/+1507
| | | | | Loopback is running via the external ZBT SRAM...HOWEVER, its not running well, its stable but the data is corrupted sometimes. Not clear if its a logic or AC timing/SI issue yet.
* get it to buildMatt Ettus2010-07-145-5/+309
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* moved forward from the old branchMatt Ettus2010-07-148-4/+876
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* Merge branch 'master' into ise12Matt Ettus2010-07-121-4/+5
|\ | | | | | | | | * master: fix bug which caused serdes fifo to disappear
| * fix bug which caused serdes fifo to disappearMatt Ettus2010-07-031-4/+5
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* | Merge branch 'master' into ise12Matt Ettus2010-06-181-1/+2
|\| | | | | | | | | * master: proper dependency tracking for the makefile
| * proper dependency tracking for the makefileMatt Ettus2010-06-181-1/+2
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* | precompute udp checksumsMatt Ettus2010-06-151-5/+14
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* | barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but allMatt Ettus2010-06-147-275/+390
|/ | | | seem to work ok
* new make works on ise12Matt Ettus2010-06-141-1/+7
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* produces good bin filesMatt Ettus2010-06-114-57/+31
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* first attempt at cleaning up the build systemMatt Ettus2010-06-1038-422/+583
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* get rid of debug stuff to help timingMatt Ettus2010-06-081-7/+16
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* move u2_core into u2_rev3 directory to simplify directory structure and save ↵Matt Ettus2010-06-085-46/+2
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* allow other clock rates in vita timeMatt Ettus2010-06-081-13/+15
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* report ise version in buildMatt Ettus2010-06-071-1/+1
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* proper name for directoryMatt Ettus2010-06-071-1/+1
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* name build directory with ISE version nameMatt Ettus2010-06-071-1/+1
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* non-udp uses a different address for the tx dsp coreMatt Ettus2010-05-271-1/+1
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* manual merge to use localparams from udp versionMatt Ettus2010-05-271-4/+23
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* from UDP branch, changed names because I want these separate from the ↵Matt Ettus2010-05-273-0/+1321
| | | | non-udp versions
* new files from udp branch added to main MakefileMatt Ettus2010-05-271-1/+19
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* Merge branch 'udp' into master_merge_take2Matt Ettus2010-05-2730-67/+2257
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * udp: (67 commits) better test program for just the tx side fix typo, no functionality difference ignores move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing reverting logic clean up which should have made timing better, but made it worse instead moved fifos around, now easier to see where they are and how big bigger fifo on UDP TX path, to possibly fix overruns on decim=4 Xilinx ISE is incorrectly parsing the verilog case statement, this is a workaround pps and vita time debug pins ignore emacs backup files more debug for fixing E's better debug pins for going after cascading E's copy in wrong place copied over from quad radio just debug pin changes typo caused the tx udp chain to be disconnected moved into subdir speed up timing by ignoring the too_early error. We'll need to FIXME this later Added set time and set time at next pps. Removed the old sync pps commands, they dont make sense to use anymore. moved around regs, added a bit to allow for alternate PPS source ...
| * better test program for just the tx sideMatt Ettus2010-05-191-163/+63
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| * fix typo, no functionality differenceMatt Ettus2010-05-191-1/+1
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| * Merge branch 'master' into udpMatt Ettus2010-05-18224-329/+19
| |\ | |/ |/| | | | | | | | | | | Remove CVS files, warning removal on setting reg width, aeMB synthesis pragmas Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
* | get rid of some warnings by declaring setting reg widthMatt Ettus2010-05-181-8/+8
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* | added width parameter to avoid warnings (thanks IJB) and default value parameterMatt Ettus2010-05-181-3/+5
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* | added pragmas suggested by Ian Buckley to help ISE12 synthesisMatt Ettus2010-05-181-3/+6
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* | get rid of old CVS linkageMatt Ettus2010-05-18221-315/+0
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* | settings bus to dsp_clk now uses clock crossing fifoMatt Ettus2010-05-162-8/+15
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| * ignoresMatt Ettus2010-05-181-1/+1
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| * Merge branch 'master' into udp, removes u2_rev1, rev2Matt Ettus2010-05-1310-2076/+0
| |\ | |/ |/| | | | | Conflicts: usrp2/control_lib/settings_bus.v
* | remove files for old prototypes, they were confusing peopleMatt Ettus2010-05-1310-2076/+0
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* | revert commit 9899b81f920 which should have improved timing but didn'tMatt Ettus2010-05-131-5/+13
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| * move dsp settings regs to reclocked setting bus. Works, gets us to within ↵Matt Ettus2010-05-122-12/+19
| | | | | | | | 18ps of passing timing
| * reverting logic clean up which should have made timing better, but made it ↵Matt Ettus2010-05-111-5/+12
| | | | | | | | worse instead
| * Merge branch 'master' into udpMatt Ettus2010-05-1111-14/+540
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* | remove port which is no longer thereMatt Ettus2010-05-111-1/+1
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* | cleaned up the logic, this is copied over from quad radioMatt Ettus2010-05-111-13/+5
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* | allow settings bus to cross to a new clock domain, should help timing, but ↵Matt Ettus2010-05-119-0/+534
| | | | | | | | not attached yet
| * Merge branch 'corgan_fixes' into udp_corganMatt Ettus2010-04-266-32/+47
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* | Update config to all eight clock buffers to be used.Johnathan Corgan2010-03-291-1/+1
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* | Added timing constraint for Wishbone clock/dsp_clock skewJohnathan Corgan2010-03-291-0/+2
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