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* capacity logic fixMatt Ettus2010-11-111-1/+1
* Added capacity to the module pinoutIan Buckley2010-11-111-3/+4
* Added a bunch of debug signals.Ian Buckley2010-11-114-9/+19
* Regenerated FIFO with lower trigger level for almost full flag to reflect log...Ian Buckley2010-11-118-236/+113
* Regenerated FIFO's for extfifo.Ian Buckley2010-11-1111-726/+15
* Edited FIFO instance to delete port that was not regenerated after reconfigur...Ian Buckley2010-11-111-1/+0
* Adding in files that probably didn;t exist in the ISE10.1 version of coregenIan Buckley2010-11-115-0/+808
* Bringing all coregen files checked in into syncIan Buckley2010-11-1110-137/+60
* Found bug due to not accounting for the correct number of possible in flight ...Ian Buckley2010-11-117-52/+110
* checkin of generated coregen filesMatt Ettus2010-11-1118-8/+556
* External FIFO tested in simulation and on USRP2 from decimation 64->8 with cu...Ian Buckley2010-11-1118-236/+7297
* Checkpoint checkin.Ian Buckley2010-11-1113-0/+1507
* get it to buildMatt Ettus2010-11-115-5/+309
* moved forward from the old branchMatt Ettus2010-11-118-4/+876
* reverting part of the reversion of the spi settings.Matt Ettus2010-11-101-2/+2
* u2p needs the bigger regs for some reasonMatt Ettus2010-11-101-4/+4
* need to enable both 16 and 32 bit spi interfaces -- 16 used in u1e, 32 in u2 ...Matt Ettus2010-11-101-0/+1
* occ needs to be 2 bits wide on a 36 bit fifo interface.Matt Ettus2010-11-101-1/+2
* Merge branch 'u1e' into merge_u1eMatt Ettus2010-11-1064-215/+3325
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| * invert led signals because they are active lowMatt Ettus2010-11-091-1/+1
| * duhMatt Ettus2010-11-041-1/+1
| * allow for CS to rise before, at the same time, or after OEMatt Ettus2010-09-241-7/+6
| * better debug pinsMatt Ettus2010-09-232-7/+11
| * watch the ethernet chip select on our debug busMatt Ettus2010-09-233-6/+8
| * fix timing issue on DAC outputs with rev 2. This puts the whole system on a ...Matt Ettus2010-09-212-50/+25
| * send all gpmc signals to mictorMatt Ettus2010-09-164-0/+201
| * updated pins to match rev2, removed dip switch, etc. seems to compile ok.Matt Ettus2010-09-093-137/+130
| * pins are different on rev2Matt Ettus2010-09-091-264/+4
| * fixed makefile to compile with our new systemMatt Ettus2010-09-071-44/+36
| * add register to tell host about compatibility level and which image we are usingMatt Ettus2010-08-301-5/+14
| * move declaration to make loopback compileMatt Ettus2010-08-271-1/+2
| * Merge branch 'tx_policy' into u1eMatt Ettus2010-08-253-29/+23
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| * | no need for protocol headers since we're not doing ethernetMatt Ettus2010-08-241-1/+1
| * | match the signal names in this designMatt Ettus2010-08-231-3/+3
| * | debug pins cleanupMatt Ettus2010-08-231-3/+3
| * | properly integrate the new tx chainMatt Ettus2010-08-191-31/+27
| * | catch up with tx_policyMatt Ettus2010-08-1911-5572/+311
| * | attach run_tx and run_rx to ledsMatt Ettus2010-08-171-1/+1
| * | connect atrMatt Ettus2010-08-171-1/+1
| * | delay the q channel to make the channels line up on the AD9862Matt Ettus2010-08-171-1/+6
| * | this is necessary for some reasonMatt Ettus2010-08-131-1/+2
| * | connect the setting reg to the real clock and resetMatt Ettus2010-08-111-1/+1
| * | enlarge loopback fifoMatt Ettus2010-08-101-4/+1
| * | Merge branch 'ise12' into u1eMatt Ettus2010-07-199-45/+163
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| * | | make loopback compileMatt Ettus2010-07-141-0/+3
| * | | Merge branch 'reload' into u1eMatt Ettus2010-07-092-5/+10
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| * | | | point to new location for fifosMatt Ettus2010-07-091-1/+1
| * | | | Merge branch 'reload' into u1eMatt Ettus2010-07-081-11/+32
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| * \ \ \ \ Merge branch 'reload' into u1eMatt Ettus2010-07-071-5/+16
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| * \ \ \ \ \ Merge branch 'master' into u1eMatt Ettus2010-07-061-4/+5
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