| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| | * | | just debug pin changes | Matt Ettus | 2010-01-25 | 2 | -1/+12 |
| | * | | typo caused the tx udp chain to be disconnected | Matt Ettus | 2010-01-23 | 1 | -1/+1 |
| | * | | moved into subdir | Josh Blum | 2010-01-22 | 653 | -0/+1558662 |
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| * | | connected spi pins, but the spi core still needs to be redone for 16 bit inte... | Matt Ettus | 2010-03-25 | 3 | -40/+60 |
| * | | debug pins | Matt Ettus | 2010-02-25 | 1 | -2/+3 |
| * | | enable was on the wrong address pin, needs to be the highest order one | Matt Ettus | 2010-02-25 | 1 | -2/+2 |
| * | | invert the pushbuttons since they are active low | Matt Ettus | 2010-02-25 | 1 | -2/+2 |
| * | | gpmc debug pins | Matt Ettus | 2010-02-25 | 2 | -4/+14 |
| * | | point to the new files | Matt Ettus | 2010-02-25 | 1 | -0/+2 |
| * | | fix syntax error which icarus allowed (filed a bug with them) | Matt Ettus | 2010-02-25 | 1 | -7/+9 |
| * | | loopback and test | Matt Ettus | 2010-02-25 | 2 | -7/+38 |
| * | | corrected logic | Matt Ettus | 2010-02-25 | 1 | -17/+7 |
| * | | edge sync on done signals so we only fill/empty one buffer | Matt Ettus | 2010-02-25 | 2 | -2/+32 |
| * | | Switched xilinx primitives because they order the bits funny in the other one | Matt Ettus | 2010-02-25 | 1 | -48/+79 |
| * | | ISE chokes on the pure verilog version so we use the macro | Matt Ettus | 2010-02-25 | 1 | -4/+49 |
| * | | First cut at passing data buffers around on GPMC bus | Matt Ettus | 2010-02-25 | 6 | -25/+165 |
| * | | Merge branch 'master' into u1e | Matt Ettus | 2010-02-23 | 1 | -1/+1 |
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| | * | proper initialization of the ram | Matt Ettus | 2010-02-23 | 1 | -1/+1 |
| * | | first cut at making a bidirectional 2 port ram for the gpmc data interface | Matt Ettus | 2010-02-23 | 3 | -6/+63 |
| * | | use our fancy new debug ports | Matt Ettus | 2010-02-23 | 1 | -0/+3 |
| * | | settings bus with 16 bit wishbone interface, put on the main wishbone in u1e | Matt Ettus | 2010-02-22 | 3 | -3/+68 |
| * | | remove the #1 delay in all the regs. They just slow down sims. | Matt Ettus | 2010-02-22 | 4 | -96/+90 |
| * | | Modified nsgpio.v to support 16 bit little endian bus interface. | Matt Ettus | 2010-02-22 | 1 | -0/+124 |
| * | | GPIOs now on the wishbone interface | Matt Ettus | 2010-02-22 | 4 | -37/+54 |
| * | | added gpio control to the wishbone | Matt Ettus | 2010-02-18 | 2 | -11/+14 |
| * | | Added I2C, UART, debug pins, misc wishbone stuff | Matt Ettus | 2010-02-18 | 3 | -48/+187 |
| * | | allow default uart clock divider | Matt Ettus | 2010-02-18 | 1 | -6/+7 |
| * | | Fixed paths to help icarus find opencores and xilinx models. Added Xilinx gl... | Matt Ettus | 2010-02-18 | 2 | -4/+7 |
| * | | speed up the presentation of registered wb data to the gpmc | Matt Ettus | 2010-02-17 | 2 | -13/+20 |
| * | | wishbone bridge now with minimal functionality. Need to check | Matt Ettus | 2010-02-16 | 8 | -11/+121 |
| * | | first cut at gpmc <-> wb bridge, split u1e into core, top, and tb | Matt Ettus | 2010-02-16 | 6 | -34/+159 |
| * | | copied over from safe_u1e | Matt Ettus | 2010-02-16 | 4 | -0/+553 |
| * | | block ram interface to GPMC | Matt Ettus | 2010-02-16 | 1 | -2/+6 |
| * | | basic read support for the GPMC, responds with 16'hBEEF | Matt Ettus | 2010-02-16 | 1 | -2/+8 |
| * | | reorg pin defs | Matt Ettus | 2010-02-14 | 1 | -94/+102 |
| * | | connect GPMC pins to debug bus | Matt Ettus | 2010-02-14 | 2 | -76/+94 |
| * | | organized the pins in the ucf by function | Matt Ettus | 2010-02-09 | 1 | -56/+72 |
| * | | builds a successful led blinker | Matt Ettus | 2010-02-09 | 3 | -2/+4 |
| * | | first cut at blinking leds | Matt Ettus | 2010-02-09 | 4 | -345/+237 |
| * | | skeletons that don't work yet | Matt Ettus | 2010-02-09 | 2 | -0/+607 |
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| * | Moved usrp2 fpga files into usrp2 subdir. | Josh Blum | 2010-01-22 | 633 | -0/+1556369 |
