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* packet generator and verifier, to test gpmc and other data transfer stuffMatt Ettus2010-05-124-0/+153
* switched passthru of cgen_sen_b to gpio127, made a note of it. No more safe_...Matt Ettus2010-05-108-561/+9
* proper signal level for 24 bit dataMatt Ettus2010-05-101-2/+7
* SPI passthru for programming clock gen chip on brand new boardsMatt Ettus2010-05-073-0/+391
* added DAC output pins, and a sine wave generator to test themMatt Ettus2010-05-043-18/+63
* Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-042-0/+14
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| * add timing constraints. Just have main clock signal at 64 MHz for now.Matt Ettus2010-05-042-0/+14
* | changed commentMatt Ettus2010-05-041-1/+1
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* have_space and have_packet now stay high even while busy,Matt Ettus2010-05-033-4/+6
* separate timed tx and rx instead of loopbackMatt Ettus2010-04-281-3/+51
* send bus error to debug pinsMatt Ettus2010-04-261-2/+4
* Pass previously unused GPIOs to debug pins to help debug interruptsMatt Ettus2010-04-243-16/+21
* Only allow new packets if we can fit the largest possible packet (2KB)Matt Ettus2010-04-231-1/+1
* Register outputs to omap to prevent runt pulses from falsely triggering inter...Matt Ettus2010-04-233-7/+20
* find time_64bitMatt Ettus2010-04-201-0/+1
* added pps and time capabilityMatt Ettus2010-04-153-5/+21
* access frame length regs from wishboneMatt Ettus2010-04-152-10/+18
* async seems to work with packet lengths now. Still need to do wishbone regs ...Matt Ettus2010-04-155-37/+72
* async gpmc progressMatt Ettus2010-04-154-18/+173
* change time parameters because Xilinx IP has a 1ps timescaleMatt Ettus2010-04-151-14/+27
* add bus error reportingMatt Ettus2010-04-151-3/+9
* correct name of moduleMatt Ettus2010-04-151-2/+2
* progress on synchronous gpmc, but it may not be possible due to the limited n...Matt Ettus2010-04-153-43/+45
* synchronous and asynchronous gpmc modelsMatt Ettus2010-04-153-3/+100
* handle all tri-state in the top level of gpmcMatt Ettus2010-04-153-6/+8
* more sync progress. This is just a skeleton for now, with junk contentMatt Ettus2010-04-141-0/+56
* more progress on synchronous interfaceMatt Ettus2010-04-144-26/+95
* renamed to async. Will be building a sync version for GPMC_CLKMatt Ettus2010-04-142-3/+3
* make timing diagrams for bus transactions. Still need to do readsMatt Ettus2010-04-145-0/+46
* added in a loopback fifoMatt Ettus2010-04-141-4/+11
* probably won't be using this, and it hasn't been testedMatt Ettus2010-04-141-0/+46
* minor changes to get it to synthesizeMatt Ettus2010-04-132-1/+4
* lengthened delay between cycles, added more transactions on the data busMatt Ettus2010-04-121-2/+7
* replaced ram interface with a fifo interface. still need to do rx sideMatt Ettus2010-04-123-120/+117
* split out gpmc to wishbone interface to make gpmc top level cleanerMatt Ettus2010-04-121-0/+57
* added 16-bit wide atr controllerMatt Ettus2010-04-015-47/+117
* 16 bit wide spi coreMatt Ettus2010-03-271-0/+182
* connect up the 16 bit spi coreMatt Ettus2010-03-262-5/+4
* remove timescale junkMatt Ettus2010-03-265-21/+19
* connect 2 clock gen controls and 3 status pins to the wishbone so they can be...Matt Ettus2010-03-263-8/+26
* Merge branch 'udp' into u1eMatt Ettus2010-03-2532-132/+2545
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| * Merge branch 'master' into udpMatt Ettus2010-03-252-3/+1
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| * | moved fifos around, now easier to see where they are and how bigMatt Ettus2010-03-252-17/+30
| * | bigger fifo on UDP TX path, to possibly fix overruns on decim=4Matt Ettus2010-03-241-2/+11
| * | Xilinx ISE is incorrectly parsing the verilog case statement, this is a worka...Matt Ettus2010-03-241-1/+7
| * | pps and vita time debug pinsMatt Ettus2010-03-231-3/+6
| * | more debug for fixing E'sMatt Ettus2010-03-102-6/+13
| * | better debug pins for going after cascading E'sMatt Ettus2010-03-101-1/+5
| * | copied over from quad radioMatt Ettus2010-02-081-0/+60
| * | Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udpMatt Ettus2010-01-254-34/+43
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