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* new make works on ise12Matt Ettus2010-06-141-1/+7
* produces good bin filesMatt Ettus2010-06-114-57/+31
* first attempt at cleaning up the build systemMatt Ettus2010-06-1038-422/+583
* get rid of debug stuff to help timingMatt Ettus2010-06-081-7/+16
* move u2_core into u2_rev3 directory to simplify directory structure and save ...Matt Ettus2010-06-085-46/+2
* allow other clock rates in vita timeMatt Ettus2010-06-081-13/+15
* report ise version in buildMatt Ettus2010-06-071-1/+1
* proper name for directoryMatt Ettus2010-06-071-1/+1
* name build directory with ISE version nameMatt Ettus2010-06-071-1/+1
* non-udp uses a different address for the tx dsp coreMatt Ettus2010-05-271-1/+1
* manual merge to use localparams from udp versionMatt Ettus2010-05-271-4/+23
* from UDP branch, changed names because I want these separate from the non-udp...Matt Ettus2010-05-273-0/+1321
* new files from udp branch added to main MakefileMatt Ettus2010-05-271-1/+19
* Merge branch 'udp' into master_merge_take2Matt Ettus2010-05-2730-67/+2257
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| * better test program for just the tx sideMatt Ettus2010-05-191-163/+63
| * fix typo, no functionality differenceMatt Ettus2010-05-191-1/+1
| * Merge branch 'master' into udpMatt Ettus2010-05-18224-329/+19
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* | get rid of some warnings by declaring setting reg widthMatt Ettus2010-05-181-8/+8
* | added width parameter to avoid warnings (thanks IJB) and default value parameterMatt Ettus2010-05-181-3/+5
* | added pragmas suggested by Ian Buckley to help ISE12 synthesisMatt Ettus2010-05-181-3/+6
* | get rid of old CVS linkageMatt Ettus2010-05-18221-315/+0
* | settings bus to dsp_clk now uses clock crossing fifoMatt Ettus2010-05-162-8/+15
| * ignoresMatt Ettus2010-05-181-1/+1
| * Merge branch 'master' into udp, removes u2_rev1, rev2Matt Ettus2010-05-1310-2076/+0
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* | remove files for old prototypes, they were confusing peopleMatt Ettus2010-05-1310-2076/+0
* | revert commit 9899b81f920 which should have improved timing but didn'tMatt Ettus2010-05-131-5/+13
| * move dsp settings regs to reclocked setting bus. Works, gets us to within 18...Matt Ettus2010-05-122-12/+19
| * reverting logic clean up which should have made timing better, but made it wo...Matt Ettus2010-05-111-5/+12
| * Merge branch 'master' into udpMatt Ettus2010-05-1111-14/+540
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* | remove port which is no longer thereMatt Ettus2010-05-111-1/+1
* | cleaned up the logic, this is copied over from quad radioMatt Ettus2010-05-111-13/+5
* | allow settings bus to cross to a new clock domain, should help timing, but no...Matt Ettus2010-05-119-0/+534
| * Merge branch 'corgan_fixes' into udp_corganMatt Ettus2010-04-266-32/+47
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* | Update config to all eight clock buffers to be used.Johnathan Corgan2010-03-291-1/+1
* | Added timing constraint for Wishbone clock/dsp_clock skewJohnathan Corgan2010-03-291-0/+2
* | Merge commit 'upstream/master'Johnathan Corgan2010-03-091-1/+1
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* | | Cut debug bus connection to etherenet MAC to make closing timing easierIan Buckley2010-02-241-2/+7
* | | Remove some warnings in dsp_core_rxJohnathan Corgan2010-02-231-3/+7
* | | Fix missing item on sensitivity listJohnathan Corgan2010-02-231-1/+1
* | | Change bit width of CORDIC constants to remove meaningless warningJohnathan Corgan2010-02-231-24/+24
* | | Manually assign clk_fpga to BUFG to improve timingJohnathan Corgan2010-02-231-1/+5
| | * Merge branch 'master' into udpMatt Ettus2010-03-252-3/+1
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| * | proper initialization of the ramMatt Ettus2010-02-231-1/+1
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* / Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-22633-0/+1556369
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* moved fifos around, now easier to see where they are and how bigMatt Ettus2010-03-252-17/+30
* bigger fifo on UDP TX path, to possibly fix overruns on decim=4Matt Ettus2010-03-241-2/+11
* Xilinx ISE is incorrectly parsing the verilog case statement, this is a worka...Matt Ettus2010-03-241-1/+7
* pps and vita time debug pinsMatt Ettus2010-03-231-3/+6
* more debug for fixing E'sMatt Ettus2010-03-102-6/+13
* better debug pins for going after cascading E'sMatt Ettus2010-03-101-1/+5
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