summaryrefslogtreecommitdiffstats
path: root/usrp2
Commit message (Collapse)AuthorAgeFilesLines
* fix typo, no functionality differenceMatt Ettus2010-05-191-1/+1
|
* Merge branch 'master' into udpMatt Ettus2010-05-18224-329/+19
|\ | | | | | | | | | | | | | | Remove CVS files, warning removal on setting reg width, aeMB synthesis pragmas Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
| * get rid of some warnings by declaring setting reg widthMatt Ettus2010-05-181-8/+8
| |
| * added width parameter to avoid warnings (thanks IJB) and default value parameterMatt Ettus2010-05-181-3/+5
| |
| * added pragmas suggested by Ian Buckley to help ISE12 synthesisMatt Ettus2010-05-181-3/+6
| |
| * get rid of old CVS linkageMatt Ettus2010-05-18221-315/+0
| |
| * settings bus to dsp_clk now uses clock crossing fifoMatt Ettus2010-05-162-8/+15
| |
* | ignoresMatt Ettus2010-05-181-1/+1
| |
* | Merge branch 'master' into udp, removes u2_rev1, rev2Matt Ettus2010-05-1310-2076/+0
|\| | | | | | | | | Conflicts: usrp2/control_lib/settings_bus.v
| * remove files for old prototypes, they were confusing peopleMatt Ettus2010-05-1310-2076/+0
| |
| * revert commit 9899b81f920 which should have improved timing but didn'tMatt Ettus2010-05-131-5/+13
| |
* | move dsp settings regs to reclocked setting bus. Works, gets us to within ↵Matt Ettus2010-05-122-12/+19
| | | | | | | | 18ps of passing timing
* | reverting logic clean up which should have made timing better, but made it ↵Matt Ettus2010-05-111-5/+12
| | | | | | | | worse instead
* | Merge branch 'master' into udpMatt Ettus2010-05-1111-14/+540
|\|
| * remove port which is no longer thereMatt Ettus2010-05-111-1/+1
| |
| * cleaned up the logic, this is copied over from quad radioMatt Ettus2010-05-111-13/+5
| |
| * allow settings bus to cross to a new clock domain, should help timing, but ↵Matt Ettus2010-05-119-0/+534
| | | | | | | | not attached yet
* | Merge branch 'corgan_fixes' into udp_corganMatt Ettus2010-04-266-32/+47
|\|
| * Update config to all eight clock buffers to be used.Johnathan Corgan2010-03-291-1/+1
| |
| * Added timing constraint for Wishbone clock/dsp_clock skewJohnathan Corgan2010-03-291-0/+2
| |
| * Merge commit 'upstream/master'Johnathan Corgan2010-03-091-1/+1
| |\
| * | Cut debug bus connection to etherenet MAC to make closing timing easierIan Buckley2010-02-241-2/+7
| | |
| * | Remove some warnings in dsp_core_rxJohnathan Corgan2010-02-231-3/+7
| | |
| * | Fix missing item on sensitivity listJohnathan Corgan2010-02-231-1/+1
| | |
| * | Change bit width of CORDIC constants to remove meaningless warningJohnathan Corgan2010-02-231-24/+24
| | |
| * | Manually assign clk_fpga to BUFG to improve timingJohnathan Corgan2010-02-231-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Starting Router Phase 1: 96908 unrouted; REAL time: 25 secs Phase 2: 85651 unrouted; REAL time: 35 secs Phase 3: 27099 unrouted; REAL time: 49 secs Phase 4: 27099 unrouted; (97405) REAL time: 49 secs Phase 5: 27259 unrouted; (5348) REAL time: 54 secs Phase 6: 27277 unrouted; (0) REAL time: 54 secs Phase 7: 0 unrouted; (0) REAL time: 1 mins 46 secs Phase 8: 0 unrouted; (0) REAL time: 1 mins 56 secs Phase 9: 0 unrouted; (0) REAL time: 2 mins 29 secs
* | | Merge branch 'master' into udpMatt Ettus2010-03-252-3/+1
|\ \ \ | | |/ | |/|
| * | proper initialization of the ramMatt Ettus2010-02-231-1/+1
| |/
| * Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-22633-0/+1556369
|
* moved fifos around, now easier to see where they are and how bigMatt Ettus2010-03-252-17/+30
|
* bigger fifo on UDP TX path, to possibly fix overruns on decim=4Matt Ettus2010-03-241-2/+11
|
* Xilinx ISE is incorrectly parsing the verilog case statement, this is a ↵Matt Ettus2010-03-241-1/+7
| | | | workaround
* pps and vita time debug pinsMatt Ettus2010-03-231-3/+6
|
* more debug for fixing E'sMatt Ettus2010-03-102-6/+13
|
* better debug pins for going after cascading E'sMatt Ettus2010-03-101-1/+5
|
* copied over from quad radioMatt Ettus2010-02-081-0/+60
|
* Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udpMatt Ettus2010-01-254-34/+43
| | | | | | | | Merge latest VRT changes into UDP branch. Merged from 1 behind the head of VRT because the head moved things around and confused git Conflicts: usrp2/timing/time_64bit.v usrp2/top/u2_core/u2_core.v
* just debug pin changesMatt Ettus2010-01-252-1/+12
|
* typo caused the tx udp chain to be disconnectedMatt Ettus2010-01-231-1/+1
|
* moved into subdirJosh Blum2010-01-22653-0/+1558662
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 16:54:50 +0000