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* generate port number headers in the dsp error unitsMatt Ettus2010-12-152-6/+8
* should safely delay the late signal which was causing timing problemsMatt Ettus2010-12-061-2/+16
* packets are shorter now, so we need to tell the udp state machine that...Matt Ettus2010-11-231-1/+1
* no need for second sequence number anymore. Each dsp tx chainMatt Ettus2010-11-212-11/+8
* modernize the testbenchMatt Ettus2010-11-191-18/+30
* get rid of extraneous U messages when we actually had an ACKMatt Ettus2010-11-182-7/+10
* fix problem with consecutive timed packets on txMatt Ettus2010-11-181-2/+0
* simplify time comparison to speed up logic and meet fpga timingMatt Ettus2010-11-131-3/+2
* reset properlyMatt Ettus2010-11-111-0/+1
* compiles with new file locationsMatt Ettus2010-11-111-1/+1
* handle zero-length packets properlyMatt Ettus2010-11-113-55/+76
* clear out the vita tx chain and the tx fifo. need to check the fifoMatt Ettus2010-11-114-13/+13
* added ability to truly clear out the entire rx chain. also removed old style...Matt Ettus2010-11-112-26/+18
* now handles frames larger than the vita packet (i.e. with padding)Matt Ettus2010-11-111-6/+16
* don't clear out following packets on an eob ackMatt Ettus2010-11-111-1/+1
* don't flag an error on eob ackMatt Ettus2010-11-111-1/+1
* cleanup for 32 bit seqnumMatt Ettus2010-11-111-4/+3
* switch to 32 bit sequence numbers. Will wrap in ~15 hours at max rateMatt Ettus2010-11-113-14/+16
* send message on eob to ack the end of transmissionMatt Ettus2010-11-111-1/+6
* typo which isn't caught by xilinxMatt Ettus2010-11-111-1/+1
* separated flow control and error reporting on tx path. should work with and ...Matt Ettus2010-11-113-24/+41
* go to the correct stateMatt Ettus2010-11-111-3/+3
* add trigger to makefileMatt Ettus2010-11-111-0/+1
* assign setting reg addressesMatt Ettus2010-11-111-2/+2
* declarationsMatt Ettus2010-11-111-2/+3
* checkpoint in flow control packet generationMatt Ettus2010-11-115-42/+147
* revert unneeded changes and incorrect commentsMatt Ettus2010-11-111-2/+2
* Added a bunch of debug signals.Ian Buckley2010-11-111-2/+2
* rx error context packets should not be marked as errors in the fifoMatt Ettus2010-08-111-1/+1
* provide a way to get out of the error state without processor interventionMatt Ettus2010-07-291-1/+4
* sequence number reset upon programming streamidMatt Ettus2010-07-282-5/+11
* attempt at avoiding infinite error messagesMatt Ettus2010-07-281-5/+14
* implemented "next packet" and "next burst" policiesMatt Ettus2010-07-283-24/+50
* sequence errors can happen on start of burst as well.Matt Ettus2010-07-281-1/+1
* more informative error codesMatt Ettus2010-07-282-6/+8
* cleaner error handlingMatt Ettus2010-07-281-27/+28
* introduce new error typesMatt Ettus2010-07-283-34/+80
* insert protocol engine flags when requestedMatt Ettus2010-07-281-2/+6
* move the streamid so it isn't at the same address as clear_stateMatt Ettus2010-07-281-1/+1
* fix a typoMatt Ettus2010-07-282-3/+3
* tx error packets now muxed into the ethernet stream back to the hostMatt Ettus2010-07-283-20/+44
* checkpoint. New context packet generator to report underruns and other errorsMatt Ettus2010-07-282-0/+107
* remove warningsMatt Ettus2010-07-161-1/+1
* fix to stop endless error packetsMatt Ettus2010-07-091-2/+2
* updated tests to match new featuresMatt Ettus2010-07-092-4/+9
* error packets are now valid Extension Context packetsMatt Ettus2010-07-081-11/+32
* reload bit for vita rx ctrlJosh Blum2010-07-051-5/+16
* first attempt at cleaning up the build systemMatt Ettus2010-06-101-0/+13
* better test program for just the tx sideMatt Ettus2010-05-191-163/+63
* fix typo, no functionality differenceMatt Ettus2010-05-191-1/+1
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