| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Regenerated FIFO with lower trigger level for almost full flag to reflect ↵ | Ian Buckley | 2010-08-19 | 1 | -2/+2 |
| | | | | | | | | | | | | | | logic removed from nobl_fifo. Improved ext_fifo_tb further, try to simulate more combinations of decomation rates and packet arrival patterns. Strip out the logic in nobl_fifo that made it look like a Xilinx fall-through FIFO...it is now very simple logic but a propriatory interface that exposes the high inetrnal latency of reads. Allow the USED size of the external FIFO to be parameterized from the core level. Currently set at only 256 Corrected a bug in vita_tx_deframer.v that can write to a FIFO when its full causing illegal state. Made further edits that are currently commented becuase simulation indicates they cause problems, however suspect a further bug is in this code. | ||||
| * | first attempt at cleaning up the build system | Matt Ettus | 2010-06-10 | 1 | -0/+13 |
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| * | better test program for just the tx side | Matt Ettus | 2010-05-19 | 1 | -163/+63 |
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| * | fix typo, no functionality difference | Matt Ettus | 2010-05-19 | 1 | -1/+1 |
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| * | Xilinx ISE is incorrectly parsing the verilog case statement, this is a ↵ | Matt Ettus | 2010-03-24 | 1 | -1/+7 |
| | | | | | workaround | ||||
| * | more debug for fixing E's | Matt Ettus | 2010-03-10 | 1 | -1/+1 |
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| * | Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udp | Matt Ettus | 2010-01-25 | 1 | -2/+5 |
| | | | | | | | | | Merge latest VRT changes into UDP branch. Merged from 1 behind the head of VRT because the head moved things around and confused git Conflicts: usrp2/timing/time_64bit.v usrp2/top/u2_core/u2_core.v | ||||
| * | moved into subdir | Josh Blum | 2010-01-22 | 9 | -0/+1138 |
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