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* vita rx: trigger clear after packet tranferJosh Blum2012-02-181-2/+22
| | | | | | | To avoid blocking conditions down the pipe, avoid clearing vita rx during packet transfer. Adds state machine to delay the clear until after xfer completes.
* dsp rework: added flusher to vita tx chain on clearJosh Blum2012-02-151-8/+16
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* dsp rework: minor simplification in vita_tx_deframerJosh Blum2012-02-131-4/+1
| | | | all n-series devices meet timing
* dsp rework: full-rate pipelining in vita tx deframerJosh Blum2012-02-121-37/+51
| | | | | | | | The vita tx deframer can now pass payload at clock rate. This enables TX streaming at interpolations factors of 2. The vector capabilities of TX deframer have been kept in-tact, and should be functional, however, only MAXCHAN=1 has been tested.
* dsp rework: pass enables into glue, update power trig, parameterize, fix ↵Josh Blum2012-02-102-4/+4
| | | | | | | | | | | | module inc DSP enables now pass through the glue and custom modules so it can be user-controlled. Updated power trigger to current spec, and added comments Pass width from dsp into glue, and use width to parameterize wires Fix custom module includes so they will build
* dsp rework: implement 64 bit ticks no secondsJosh Blum2012-02-064-38/+30
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* dsp rework: pass vita clears into dsp modules, unified fifo clearsJosh Blum2012-02-042-5/+5
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* dsp rework: rehash of the custom module stuff and readmeJosh Blum2012-02-025-3/+208
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* dsp rework: custom engine module for rx/tx vita chainJosh Blum2012-02-012-35/+35
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* dsp rework: register the sample in vita tx ctrlJosh Blum2012-02-011-2/+11
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* dsp rework: paramaterize post_engine_bufferingJosh Blum2012-02-011-4/+14
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* dsp rework: finished engine HEADER_OFFSET stuff, add post_engine_bufferingJosh Blum2012-01-301-3/+8
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* dsp rework: work on 8 to 16 engine (usrp2 ok)Josh Blum2012-01-301-1/+1
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* dsp rework: integrated dspengine_8to16, some tweaksJosh Blum2012-01-301-4/+2
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* dsp rework: added double buffer interface to vita txJosh Blum2012-01-281-8/+35
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* dsp rework: implemented dsp changes for other top levelsJosh Blum2012-01-272-3/+9
| | | | added user registers into each toplevel (not used yet)
* dsp rework: renamed dsp signals for frontend IOJosh Blum2012-01-272-2/+2
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* dsp rework: u2_core test implementationJosh Blum2012-01-262-20/+11
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* dsp: remove dsp_buffer and replace with simpler add_routing_header,Matt Ettus2011-11-041-3/+2
| | | | other funcs of dsp_buffer are done by double_buffer and dsp_engine
* dsp_engine fix rst -> reset, default to read addressMatt Ettus2011-10-261-1/+1
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* dspengine: move the register to VITA_RX_CTRL + 9 instead of + 3 which is ↵Matt Ettus2011-10-261-1/+1
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* dspengine: insert into the rx chainMatt Ettus2011-10-261-1/+23
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* vrt: delay the late signal to help with timingMatt Ettus2011-07-281-5/+20
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* vita_rx_ctrl: use an extra cmd bit to signal stopJosh Blum2011-07-281-7/+7
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* dsp: added tx_frontend, instantiated in u2/u2pMatt Ettus2011-06-081-2/+2
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* added copyrightsJosh Blum2011-06-0711-0/+187
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* u2p-rebase: go back to versions on nextMatt Ettus2011-05-261-3/+3
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* u1p: vita packet generator for testing purposesMatt Ettus2011-05-262-0/+43
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* u1p: debug pinsMatt Ettus2011-05-261-3/+3
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* u1e: get dsp_framer36 from u1p so it can skip the protocol headerMatt Ettus2011-05-091-3/+6
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* clean up a bunch of warnings and incorrect bus widthsMatt Ettus2011-03-164-6/+7
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* u2/u2p: proper connections for dsp_framerMatt Ettus2011-03-071-0/+3
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* u2/u2p: moved dsp framer into vita_rx_chainMatt Ettus2011-03-053-14/+15
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* u2/u2p: proper hookup of vita_rx_chainMatt Ettus2011-02-171-2/+2
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* clean up rx dsp and some other nets in prep for dual dspMatt Ettus2011-02-162-0/+34
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* Merge branch 'cordic_policy' into nextJosh Blum2011-01-041-4/+30
|\ | | | | | | | | | | Conflicts: usrp2/top/u2_rev3/u2_core.v usrp2/top/u2plus/u2plus_core.v
| * run should actually turn on now any time in the IBS_RUN stateMatt Ettus2010-12-291-11/+8
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| * should keep cordic spinning and the rest of the tx going throughMatt Ettus2010-12-281-4/+33
| | | | | | | | underruns. There is a timeout so it won't go forever.
* | generate port number headers in the dsp error unitsMatt Ettus2010-12-152-6/+8
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* should safely delay the late signal which was causing timing problemsMatt Ettus2010-12-061-2/+16
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* packets are shorter now, so we need to tell the udp state machine that...Matt Ettus2010-11-231-1/+1
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* no need for second sequence number anymore. Each dsp tx chainMatt Ettus2010-11-212-11/+8
| | | | generates its own flow control packets now.
* modernize the testbenchMatt Ettus2010-11-191-18/+30
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* get rid of extraneous U messages when we actually had an ACKMatt Ettus2010-11-182-7/+10
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* fix problem with consecutive timed packets on txMatt Ettus2010-11-181-2/+0
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* simplify time comparison to speed up logic and meet fpga timingMatt Ettus2010-11-131-3/+2
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* reset properlyMatt Ettus2010-11-111-0/+1
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* compiles with new file locationsMatt Ettus2010-11-111-1/+1
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* handle zero-length packets properlyMatt Ettus2010-11-113-55/+76
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* clear out the vita tx chain and the tx fifo. need to check the fifoMatt Ettus2010-11-114-13/+13
| | | | reset to make sure it is in the correct clock domain.
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