| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | vita rx: trigger clear after packet tranfer | Josh Blum | 2012-02-18 | 1 | -2/+22 |
| * | dsp rework: added flusher to vita tx chain on clear | Josh Blum | 2012-02-15 | 1 | -8/+16 |
| * | dsp rework: minor simplification in vita_tx_deframer | Josh Blum | 2012-02-13 | 1 | -4/+1 |
| * | dsp rework: full-rate pipelining in vita tx deframer | Josh Blum | 2012-02-12 | 1 | -37/+51 |
| * | dsp rework: pass enables into glue, update power trig, parameterize, fix modu... | Josh Blum | 2012-02-10 | 2 | -4/+4 |
| * | dsp rework: implement 64 bit ticks no seconds | Josh Blum | 2012-02-06 | 4 | -38/+30 |
| * | dsp rework: pass vita clears into dsp modules, unified fifo clears | Josh Blum | 2012-02-04 | 2 | -5/+5 |
| * | dsp rework: rehash of the custom module stuff and readme | Josh Blum | 2012-02-02 | 5 | -3/+208 |
| * | dsp rework: custom engine module for rx/tx vita chain | Josh Blum | 2012-02-01 | 2 | -35/+35 |
| * | dsp rework: register the sample in vita tx ctrl | Josh Blum | 2012-02-01 | 1 | -2/+11 |
| * | dsp rework: paramaterize post_engine_buffering | Josh Blum | 2012-02-01 | 1 | -4/+14 |
| * | dsp rework: finished engine HEADER_OFFSET stuff, add post_engine_buffering | Josh Blum | 2012-01-30 | 1 | -3/+8 |
| * | dsp rework: work on 8 to 16 engine (usrp2 ok) | Josh Blum | 2012-01-30 | 1 | -1/+1 |
| * | dsp rework: integrated dspengine_8to16, some tweaks | Josh Blum | 2012-01-30 | 1 | -4/+2 |
| * | dsp rework: added double buffer interface to vita tx | Josh Blum | 2012-01-28 | 1 | -8/+35 |
| * | dsp rework: implemented dsp changes for other top levels | Josh Blum | 2012-01-27 | 2 | -3/+9 |
| * | dsp rework: renamed dsp signals for frontend IO | Josh Blum | 2012-01-27 | 2 | -2/+2 |
| * | dsp rework: u2_core test implementation | Josh Blum | 2012-01-26 | 2 | -20/+11 |
| * | dsp: remove dsp_buffer and replace with simpler add_routing_header, | Matt Ettus | 2011-11-04 | 1 | -3/+2 |
| * | dsp_engine fix rst -> reset, default to read address | Matt Ettus | 2011-10-26 | 1 | -1/+1 |
| * | dspengine: move the register to VITA_RX_CTRL + 9 instead of + 3 which is occu... | Matt Ettus | 2011-10-26 | 1 | -1/+1 |
| * | dspengine: insert into the rx chain | Matt Ettus | 2011-10-26 | 1 | -1/+23 |
| * | vrt: delay the late signal to help with timing | Matt Ettus | 2011-07-28 | 1 | -5/+20 |
| * | vita_rx_ctrl: use an extra cmd bit to signal stop | Josh Blum | 2011-07-28 | 1 | -7/+7 |
| * | dsp: added tx_frontend, instantiated in u2/u2p | Matt Ettus | 2011-06-08 | 1 | -2/+2 |
| * | added copyrights | Josh Blum | 2011-06-07 | 11 | -0/+187 |
| * | u2p-rebase: go back to versions on next | Matt Ettus | 2011-05-26 | 1 | -3/+3 |
| * | u1p: vita packet generator for testing purposes | Matt Ettus | 2011-05-26 | 2 | -0/+43 |
| * | u1p: debug pins | Matt Ettus | 2011-05-26 | 1 | -3/+3 |
| * | u1e: get dsp_framer36 from u1p so it can skip the protocol header | Matt Ettus | 2011-05-09 | 1 | -3/+6 |
| * | clean up a bunch of warnings and incorrect bus widths | Matt Ettus | 2011-03-16 | 4 | -6/+7 |
| * | u2/u2p: proper connections for dsp_framer | Matt Ettus | 2011-03-07 | 1 | -0/+3 |
| * | u2/u2p: moved dsp framer into vita_rx_chain | Matt Ettus | 2011-03-05 | 3 | -14/+15 |
| * | u2/u2p: proper hookup of vita_rx_chain | Matt Ettus | 2011-02-17 | 1 | -2/+2 |
| * | clean up rx dsp and some other nets in prep for dual dsp | Matt Ettus | 2011-02-16 | 2 | -0/+34 |
| * | Merge branch 'cordic_policy' into next | Josh Blum | 2011-01-04 | 1 | -4/+30 |
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| | * | run should actually turn on now any time in the IBS_RUN state | Matt Ettus | 2010-12-29 | 1 | -11/+8 |
| | * | should keep cordic spinning and the rest of the tx going through | Matt Ettus | 2010-12-28 | 1 | -4/+33 |
| * | | generate port number headers in the dsp error units | Matt Ettus | 2010-12-15 | 2 | -6/+8 |
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| * | should safely delay the late signal which was causing timing problems | Matt Ettus | 2010-12-06 | 1 | -2/+16 |
| * | packets are shorter now, so we need to tell the udp state machine that... | Matt Ettus | 2010-11-23 | 1 | -1/+1 |
| * | no need for second sequence number anymore. Each dsp tx chain | Matt Ettus | 2010-11-21 | 2 | -11/+8 |
| * | modernize the testbench | Matt Ettus | 2010-11-19 | 1 | -18/+30 |
| * | get rid of extraneous U messages when we actually had an ACK | Matt Ettus | 2010-11-18 | 2 | -7/+10 |
| * | fix problem with consecutive timed packets on tx | Matt Ettus | 2010-11-18 | 1 | -2/+0 |
| * | simplify time comparison to speed up logic and meet fpga timing | Matt Ettus | 2010-11-13 | 1 | -3/+2 |
| * | reset properly | Matt Ettus | 2010-11-11 | 1 | -0/+1 |
| * | compiles with new file locations | Matt Ettus | 2010-11-11 | 1 | -1/+1 |
| * | handle zero-length packets properly | Matt Ettus | 2010-11-11 | 3 | -55/+76 |
| * | clear out the vita tx chain and the tx fifo. need to check the fifo | Matt Ettus | 2010-11-11 | 4 | -13/+13 |
