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* dspengine: insert into the rx chainMatt Ettus2011-10-261-1/+23
* vrt: delay the late signal to help with timingMatt Ettus2011-07-281-5/+20
* vita_rx_ctrl: use an extra cmd bit to signal stopJosh Blum2011-07-281-7/+7
* dsp: added tx_frontend, instantiated in u2/u2pMatt Ettus2011-06-081-2/+2
* added copyrightsJosh Blum2011-06-0711-0/+187
* u2p-rebase: go back to versions on nextMatt Ettus2011-05-261-3/+3
* u1p: vita packet generator for testing purposesMatt Ettus2011-05-262-0/+43
* u1p: debug pinsMatt Ettus2011-05-261-3/+3
* u1e: get dsp_framer36 from u1p so it can skip the protocol headerMatt Ettus2011-05-091-3/+6
* clean up a bunch of warnings and incorrect bus widthsMatt Ettus2011-03-164-6/+7
* u2/u2p: proper connections for dsp_framerMatt Ettus2011-03-071-0/+3
* u2/u2p: moved dsp framer into vita_rx_chainMatt Ettus2011-03-053-14/+15
* u2/u2p: proper hookup of vita_rx_chainMatt Ettus2011-02-171-2/+2
* clean up rx dsp and some other nets in prep for dual dspMatt Ettus2011-02-162-0/+34
* Merge branch 'cordic_policy' into nextJosh Blum2011-01-041-4/+30
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| * run should actually turn on now any time in the IBS_RUN stateMatt Ettus2010-12-291-11/+8
| * should keep cordic spinning and the rest of the tx going throughMatt Ettus2010-12-281-4/+33
* | generate port number headers in the dsp error unitsMatt Ettus2010-12-152-6/+8
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* should safely delay the late signal which was causing timing problemsMatt Ettus2010-12-061-2/+16
* packets are shorter now, so we need to tell the udp state machine that...Matt Ettus2010-11-231-1/+1
* no need for second sequence number anymore. Each dsp tx chainMatt Ettus2010-11-212-11/+8
* modernize the testbenchMatt Ettus2010-11-191-18/+30
* get rid of extraneous U messages when we actually had an ACKMatt Ettus2010-11-182-7/+10
* fix problem with consecutive timed packets on txMatt Ettus2010-11-181-2/+0
* simplify time comparison to speed up logic and meet fpga timingMatt Ettus2010-11-131-3/+2
* reset properlyMatt Ettus2010-11-111-0/+1
* compiles with new file locationsMatt Ettus2010-11-111-1/+1
* handle zero-length packets properlyMatt Ettus2010-11-113-55/+76
* clear out the vita tx chain and the tx fifo. need to check the fifoMatt Ettus2010-11-114-13/+13
* added ability to truly clear out the entire rx chain. also removed old style...Matt Ettus2010-11-112-26/+18
* now handles frames larger than the vita packet (i.e. with padding)Matt Ettus2010-11-111-6/+16
* don't clear out following packets on an eob ackMatt Ettus2010-11-111-1/+1
* don't flag an error on eob ackMatt Ettus2010-11-111-1/+1
* cleanup for 32 bit seqnumMatt Ettus2010-11-111-4/+3
* switch to 32 bit sequence numbers. Will wrap in ~15 hours at max rateMatt Ettus2010-11-113-14/+16
* send message on eob to ack the end of transmissionMatt Ettus2010-11-111-1/+6
* typo which isn't caught by xilinxMatt Ettus2010-11-111-1/+1
* separated flow control and error reporting on tx path. should work with and ...Matt Ettus2010-11-113-24/+41
* go to the correct stateMatt Ettus2010-11-111-3/+3
* add trigger to makefileMatt Ettus2010-11-111-0/+1
* assign setting reg addressesMatt Ettus2010-11-111-2/+2
* declarationsMatt Ettus2010-11-111-2/+3
* checkpoint in flow control packet generationMatt Ettus2010-11-115-42/+147
* revert unneeded changes and incorrect commentsMatt Ettus2010-11-111-2/+2
* Added a bunch of debug signals.Ian Buckley2010-11-111-2/+2
* rx error context packets should not be marked as errors in the fifoMatt Ettus2010-08-111-1/+1
* provide a way to get out of the error state without processor interventionMatt Ettus2010-07-291-1/+4
* sequence number reset upon programming streamidMatt Ettus2010-07-282-5/+11
* attempt at avoiding infinite error messagesMatt Ettus2010-07-281-5/+14
* implemented "next packet" and "next burst" policiesMatt Ettus2010-07-283-24/+50
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