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* should safely delay the late signal which was causing timing problemsMatt Ettus2010-12-061-2/+16
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* packets are shorter now, so we need to tell the udp state machine that...Matt Ettus2010-11-231-1/+1
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* no need for second sequence number anymore. Each dsp tx chainMatt Ettus2010-11-212-11/+8
| | | | generates its own flow control packets now.
* modernize the testbenchMatt Ettus2010-11-191-18/+30
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* get rid of extraneous U messages when we actually had an ACKMatt Ettus2010-11-182-7/+10
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* fix problem with consecutive timed packets on txMatt Ettus2010-11-181-2/+0
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* simplify time comparison to speed up logic and meet fpga timingMatt Ettus2010-11-131-3/+2
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* reset properlyMatt Ettus2010-11-111-0/+1
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* compiles with new file locationsMatt Ettus2010-11-111-1/+1
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* handle zero-length packets properlyMatt Ettus2010-11-113-55/+76
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* clear out the vita tx chain and the tx fifo. need to check the fifoMatt Ettus2010-11-114-13/+13
| | | | reset to make sure it is in the correct clock domain.
* added ability to truly clear out the entire rx chain. also removed old ↵Matt Ettus2010-11-112-26/+18
| | | | style fifo in rx.
* now handles frames larger than the vita packet (i.e. with padding)Matt Ettus2010-11-111-6/+16
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* don't clear out following packets on an eob ackMatt Ettus2010-11-111-1/+1
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* don't flag an error on eob ackMatt Ettus2010-11-111-1/+1
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* cleanup for 32 bit seqnumMatt Ettus2010-11-111-4/+3
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* switch to 32 bit sequence numbers. Will wrap in ~15 hours at max rateMatt Ettus2010-11-113-14/+16
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* send message on eob to ack the end of transmissionMatt Ettus2010-11-111-1/+6
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* typo which isn't caught by xilinxMatt Ettus2010-11-111-1/+1
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* separated flow control and error reporting on tx path. should work with and ↵Matt Ettus2010-11-113-24/+41
| | | | without flow control
* go to the correct stateMatt Ettus2010-11-111-3/+3
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* add trigger to makefileMatt Ettus2010-11-111-0/+1
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* assign setting reg addressesMatt Ettus2010-11-111-2/+2
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* declarationsMatt Ettus2010-11-111-2/+3
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* checkpoint in flow control packet generationMatt Ettus2010-11-115-42/+147
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* revert unneeded changes and incorrect commentsMatt Ettus2010-11-111-2/+2
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* Added a bunch of debug signals.Ian Buckley2010-11-111-2/+2
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* rx error context packets should not be marked as errors in the fifoMatt Ettus2010-08-111-1/+1
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* provide a way to get out of the error state without processor interventionMatt Ettus2010-07-291-1/+4
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* sequence number reset upon programming streamidMatt Ettus2010-07-282-5/+11
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* attempt at avoiding infinite error messagesMatt Ettus2010-07-281-5/+14
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* implemented "next packet" and "next burst" policiesMatt Ettus2010-07-283-24/+50
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* sequence errors can happen on start of burst as well.Matt Ettus2010-07-281-1/+1
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* more informative error codesMatt Ettus2010-07-282-6/+8
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* cleaner error handlingMatt Ettus2010-07-281-27/+28
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* introduce new error typesMatt Ettus2010-07-283-34/+80
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* insert protocol engine flags when requestedMatt Ettus2010-07-281-2/+6
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* move the streamid so it isn't at the same address as clear_stateMatt Ettus2010-07-281-1/+1
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* fix a typoMatt Ettus2010-07-282-3/+3
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* tx error packets now muxed into the ethernet stream back to the hostMatt Ettus2010-07-283-20/+44
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* checkpoint. New context packet generator to report underruns and other errorsMatt Ettus2010-07-282-0/+107
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* remove warningsMatt Ettus2010-07-161-1/+1
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* fix to stop endless error packetsMatt Ettus2010-07-091-2/+2
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* updated tests to match new featuresMatt Ettus2010-07-092-4/+9
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* error packets are now valid Extension Context packetsMatt Ettus2010-07-081-11/+32
| | | | | | | error packets don't have a trailer any more streamid is now optional on data packets, set by header register trailer now has a bit to indicate successful End-of-burst hard-coded some header bits to correct values to ensure valid packets
* reload bit for vita rx ctrlJosh Blum2010-07-051-5/+16
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* first attempt at cleaning up the build systemMatt Ettus2010-06-101-0/+13
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* better test program for just the tx sideMatt Ettus2010-05-191-163/+63
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* fix typo, no functionality differenceMatt Ettus2010-05-191-1/+1
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* Xilinx ISE is incorrectly parsing the verilog case statement, this is a ↵Matt Ettus2010-03-241-1/+7
| | | | workaround
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