uhd - Ettus' UHD Repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	Added a bunch of debug signals.	Ian Buckley	2010-08-19	1	-2/+2
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*	rx error context packets should not be marked as errors in the fifo	Matt Ettus	2010-08-11	1	-1/+1
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*	provide a way to get out of the error state without processor intervention	Matt Ettus	2010-07-29	1	-1/+4
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*	sequence number reset upon programming streamid	Matt Ettus	2010-07-28	2	-5/+11
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*	attempt at avoiding infinite error messages	Matt Ettus	2010-07-28	1	-5/+14
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*	implemented "next packet" and "next burst" policies	Matt Ettus	2010-07-28	3	-24/+50
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*	sequence errors can happen on start of burst as well.	Matt Ettus	2010-07-28	1	-1/+1
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*	more informative error codes	Matt Ettus	2010-07-28	2	-6/+8
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*	cleaner error handling	Matt Ettus	2010-07-28	1	-27/+28
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*	introduce new error types	Matt Ettus	2010-07-28	3	-34/+80
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*	insert protocol engine flags when requested	Matt Ettus	2010-07-28	1	-2/+6
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*	move the streamid so it isn't at the same address as clear_state	Matt Ettus	2010-07-28	1	-1/+1
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*	fix a typo	Matt Ettus	2010-07-28	2	-3/+3
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*	tx error packets now muxed into the ethernet stream back to the host	Matt Ettus	2010-07-28	3	-20/+44
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*	checkpoint. New context packet generator to report underruns and other errors	Matt Ettus	2010-07-28	2	-0/+107
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*	remove warnings	Matt Ettus	2010-07-16	1	-1/+1
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*	fix to stop endless error packets	Matt Ettus	2010-07-09	1	-2/+2
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*	updated tests to match new features	Matt Ettus	2010-07-09	2	-4/+9
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*	error packets are now valid Extension Context packets	Matt Ettus	2010-07-08	1	-11/+32
\| \| \| \| \| \| \|	error packets don't have a trailer any more streamid is now optional on data packets, set by header register trailer now has a bit to indicate successful End-of-burst hard-coded some header bits to correct values to ensure valid packets
*	reload bit for vita rx ctrl	Josh Blum	2010-07-05	1	-5/+16
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*	first attempt at cleaning up the build system	Matt Ettus	2010-06-10	1	-0/+13
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*	better test program for just the tx side	Matt Ettus	2010-05-19	1	-163/+63
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*	fix typo, no functionality difference	Matt Ettus	2010-05-19	1	-1/+1
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*	Xilinx ISE is incorrectly parsing the verilog case statement, this is a ↵	Matt Ettus	2010-03-24	1	-1/+7
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*	more debug for fixing E's	Matt Ettus	2010-03-10	1	-1/+1
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*	Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udp	Matt Ettus	2010-01-25	1	-2/+5
\| \| \| \| \| \| \| \|	Merge latest VRT changes into UDP branch. Merged from 1 behind the head of VRT because the head moved things around and confused git Conflicts: usrp2/timing/time_64bit.v usrp2/top/u2_core/u2_core.v
*	moved into subdir	Josh Blum	2010-01-22	9	-0/+1138