| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | reload bit for vita rx ctrl | Josh Blum | 2010-07-05 | 1 | -5/+16 |
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| * | first attempt at cleaning up the build system | Matt Ettus | 2010-06-10 | 1 | -0/+13 |
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| * | better test program for just the tx side | Matt Ettus | 2010-05-19 | 1 | -163/+63 |
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| * | fix typo, no functionality difference | Matt Ettus | 2010-05-19 | 1 | -1/+1 |
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| * | Xilinx ISE is incorrectly parsing the verilog case statement, this is a ↵ | Matt Ettus | 2010-03-24 | 1 | -1/+7 |
| | | | | | workaround | ||||
| * | more debug for fixing E's | Matt Ettus | 2010-03-10 | 1 | -1/+1 |
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| * | Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udp | Matt Ettus | 2010-01-25 | 1 | -2/+5 |
| | | | | | | | | | Merge latest VRT changes into UDP branch. Merged from 1 behind the head of VRT because the head moved things around and confused git Conflicts: usrp2/timing/time_64bit.v usrp2/top/u2_core/u2_core.v | ||||
| * | moved into subdir | Josh Blum | 2010-01-22 | 9 | -0/+1138 |
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index : uhd | |
| Ettus' UHD Repository |
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