| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | vrt: delay the late signal to help with timing | Matt Ettus | 2011-07-28 | 1 | -5/+20 |
| | | |||||
| * | vita_rx_ctrl: use an extra cmd bit to signal stop | Josh Blum | 2011-07-28 | 1 | -7/+7 |
| | | |||||
| * | added copyrights | Josh Blum | 2011-06-07 | 1 | -0/+17 |
| | | |||||
| * | u2p-rebase: go back to versions on next | Matt Ettus | 2011-05-26 | 1 | -3/+3 |
| | | |||||
| * | u1p: debug pins | Matt Ettus | 2011-05-26 | 1 | -3/+3 |
| | | |||||
| * | u2/u2p: moved dsp framer into vita_rx_chain | Matt Ettus | 2011-03-05 | 1 | -1/+1 |
| | | |||||
| * | handle zero-length packets properly | Matt Ettus | 2010-11-11 | 1 | -15/+24 |
| | | |||||
| * | added ability to truly clear out the entire rx chain. also removed old ↵ | Matt Ettus | 2010-11-11 | 1 | -16/+15 |
| | | | | | style fifo in rx. | ||||
| * | reload bit for vita rx ctrl | Josh Blum | 2010-07-05 | 1 | -5/+16 |
| | | |||||
| * | Xilinx ISE is incorrectly parsing the verilog case statement, this is a ↵ | Matt Ettus | 2010-03-24 | 1 | -1/+7 |
| | | | | | workaround | ||||
| * | moved into subdir | Josh Blum | 2010-01-22 | 1 | -0/+174 |
 |
index : uhd | |
| Ettus' UHD Repository |
| aboutsummaryrefslogtreecommitdiffstats |