| Commit message (Collapse) | Author | Age | Files | Lines |
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Normally high, goes low when pushed
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* ise12:
move declaration ahead of use
put run_tx and run_rx on the displayed LEDs
remove warnings
add mux and demux to build
mux multiple fifo streams into one. Allows priority or round robin
split fifo into 2 streams based on first line in each packet
fix to stop endless error packets
updated tests to match new features
error packets are now valid Extension Context packets error packets don't have a trailer any more streamid is now optional on data packets, set by header register trailer now has a bit to indicate successful End-of-burst hard-coded some header bits to correct values to ensure valid packets
reload bit for vita rx ctrl
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* ise12:
precompute udp checksums
barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but all seem to work ok
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* master:
proper dependency tracking for the makefile
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seem to work ok
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* master:
proper dependency tracking for the makefile
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* master:
new make works on ise12
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* master:
produces good bin files
first attempt at cleaning up the build system
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* master:
get rid of debug stuff to help timing
move u2_core into u2_rev3 directory to simplify directory structure and save headaches
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headaches
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* master:
allow other clock rates in vita time
report ise version in build
proper name for directory
name build directory with ISE version name
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non-udp versions
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* udp: (67 commits)
better test program for just the tx side
fix typo, no functionality difference
ignores
move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing
reverting logic clean up which should have made timing better, but made it worse instead
moved fifos around, now easier to see where they are and how big
bigger fifo on UDP TX path, to possibly fix overruns on decim=4
Xilinx ISE is incorrectly parsing the verilog case statement, this is a workaround
pps and vita time debug pins
ignore emacs backup files
more debug for fixing E's
better debug pins for going after cascading E's
copy in wrong place
copied over from quad radio
just debug pin changes
typo caused the tx udp chain to be disconnected
moved into subdir
speed up timing by ignoring the too_early error. We'll need to FIXME this later
Added set time and set time at next pps. Removed the old sync pps commands, they dont make sense to use anymore.
moved around regs, added a bit to allow for alternate PPS source
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Remove CVS files, warning removal on setting reg width, aeMB synthesis pragmas
Conflicts:
usrp2/control_lib/setting_reg.v
usrp2/top/u2_core/u2_core.v
usrp2/top/u2_rev3/Makefile
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