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* u2/u2p: moved dsp framer into vita_rx_chainMatt Ettus2011-03-051-18/+6
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* Merge branch 'gpmc_testing' into ethfifo_reorgMatt Ettus2011-03-031-81/+18
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | * gpmc_testing: timed packet generator : Temporarily use a checksum rather than a crc to validate packet integrity. correct port names fifo36_mux now has shortfifos on the input ports as well as output timed tester : Bring out src/dst flags for rx chain for testing. u1e: hook up tester controls move declarations to before use hook up under/overruns for debug purposes e100: integrate loopback and timed testing into main image Fix endianess for packet length and sequence number for e100 timed image. put these files in the right place. newfifo is long gone.
| * timed tester : Bring out src/dst flags for rx chain for testing.Philip Balister2011-02-251-0/+4
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| * u1e: hook up tester controlsMatt Ettus2011-02-171-4/+6
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| * hook up under/overruns for debug purposesMatt Ettus2011-02-161-3/+7
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| * e100: integrate loopback and timed testing into main imageMatt Ettus2011-02-161-74/+1
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* | remove references to old directoryMatt Ettus2011-03-036-7/+1
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* | u2plus: catch up with ethfifo changes which were on u2Matt Ettus2011-03-031-39/+4
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* | make big tx fifo the one doing the clock crossingMatt Ettus2011-03-031-11/+3
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* | u2/u2p: removed unneeded eth rx fifoMatt Ettus2011-03-031-10/+4
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* | u2/u2p: switch over to 36 bit wide ethernet wrapperMatt Ettus2011-03-031-19/+6
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* | u2/u2p: packet realignment moved into the simple_gemac_wrapper19Matt Ettus2011-03-031-9/+1
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* | u2/u2p: shrunk ETH TX FIFO, further u2/u2p harmonizationMatt Ettus2011-02-213-20/+19
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* | increase compat number for double dsp changeMatt Ettus2011-02-172-2/+2
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* | u2/u2p: reduce unneeded RX DSP bufferingMatt Ettus2011-02-172-2/+2
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* | u2p: 2nd DSP now in u2p as wellMatt Ettus2011-02-171-25/+56
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* | u2/u2p: added 2nd DSP unitMatt Ettus2011-02-171-0/+34
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* | u2/u2p: renamed and split some rx signals to prepare for 2nd DSPMatt Ettus2011-02-171-25/+22
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* | u2/u2p: proper hookup of vita_rx_chainMatt Ettus2011-02-172-10/+10
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* | clean up rx dsp and some other nets in prep for dual dspMatt Ettus2011-02-162-86/+64
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* | register map changes to fit in the 2nd rx dspMatt Ettus2011-02-151-15/+19
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* | packet_router: added support for two dsps into routerJosh Blum2011-02-152-2/+4
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* separate clear for tx and rx, and add a global reset from the hostMatt Ettus2011-02-021-10/+19
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* usrp-e100: added missing newfifo files to list, added missing signals for timedJosh Blum2011-01-261-1/+2
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* usrp-e100: added 32bit test read/write register, fixes to get buildingJosh Blum2011-01-251-7/+17
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* reorganized u1e register space to make room for 64 settingregsMatt Ettus2011-01-251-12/+15
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* usrp-e100: added readback mux 32 as slave 7 for time readbackJosh Blum2011-01-141-4/+16
| | | | | created new component wb_readback_mux_16LE.v for 16 wide bus connected vita time pps to vita time controller and readbacks
* usrp-n210: added power-on-reset controller, reset all wb perifsJosh Blum2011-01-101-10/+13
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* usrp-n210: uploaded most recent bootloader rmiJosh Blum2011-01-101-167/+204
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* usrp-n210: use cpu rst on the wb+icap, uploaded latest bootloader rmiJosh Blum2011-01-092-169/+172
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* Merge branch 'cordic_policy' into nextJosh Blum2011-01-042-31/+23
|\ | | | | | | | | | | Conflicts: usrp2/top/u2_rev3/u2_core.v usrp2/top/u2plus/u2plus_core.v
| * hook up sampled pps in u2plus, remove unused priority encoder, minor cleanupsMatt Ettus2010-12-302-26/+18
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| * processor can read back vita_time at last ppsMatt Ettus2010-12-301-10/+4
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* | usrp-n210: checked in updated bootloader (from next with fixes)Josh Blum2010-12-311-36/+36
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* | Merge branch 'udp_ports' into nextJosh Blum2010-12-222-2/+4
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| * | generate port number headers in the dsp error unitsMatt Ettus2010-12-152-2/+4
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* | usrp-n210: add missing wires, incr compat, use boot ram as stack spaceJosh Blum2010-12-221-16/+14
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* | usrp-n210: delay reset for boot loader stack pointer to init, copied bl.rmi ↵Josh Blum2010-12-182-187/+173
| | | | | | | | without debug
* | usrp-n210: almost working w/ packet router + zpuJosh Blum2010-12-173-293/+305
| | | | | | | | | | | | | | added stack start signal to zpu removed wb perifs in n210 out of 0-16k added reset controller for main app rewire cpu addr line after booted use 0-16k
* | usrp-n210: integrate zpu and packet router, builds but untestedJosh Blum2010-12-141-72/+77
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* | zpu: working, modified top level sizes, disable interruptJosh Blum2010-12-142-8/+5
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* | Merge branch 'packet_router' into zpuJosh Blum2010-12-128-128/+36
|\ \ | | | | | | | | | | | | Conflicts: usrp2/top/u2_rev3/u2_core.v
| * | Merge branch 'ise12' into packet_routerJosh Blum2010-12-107-30/+34
| |\| | | | | | | | | | | | | | | | Conflicts: usrp2/top/u2_rev3/Makefile usrp2/top/u2_rev3/u2_core.v
| | * time sync on usrp2 as well, added debug pins to time sync.Matt Ettus2010-12-101-1/+5
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| | * Only do udp now, renamed old ports to exp_time_*Matt Ettus2010-12-091-0/+0
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| | * udp is now the defaultMatt Ettus2010-12-092-2/+2
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| | * remove old raw ethernet versionMatt Ettus2010-12-092-882/+0
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| | * reimplemented mimo time transfer to handle 64 bits. Still needsMatt Ettus2010-12-091-1/+2
| | | | | | | | | | | | to sync on the received side.
| | * renamed exp_pps_* to be exp_time_*, which is the mimo synchronization signalMatt Ettus2010-12-095-22/+22
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| | * u2plus: clock lock pin capitalization failNick Foster2010-12-062-2/+2
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