uhd - Ettus' UHD Repository

	Commit message (Expand)	Author	Age	Files	Lines
*	experimental mods to make ram loader fully synchronous. Based on IJB's work	Matt Ettus	2010-05-26	1	-15/+14
*	fixes from IJB from 5/24. Basically connect unconnected wires.	Matt Ettus	2010-05-24	1	-2/+3
*	removes the icache and pipelines the reads	Matt Ettus	2010-05-20	2	-5/+6
*	get rid of some warnings by declaring setting reg width	Matt Ettus	2010-05-18	1	-8/+8
*	settings bus to dsp_clk now uses clock crossing fifo	Matt Ettus	2010-05-16	2	-8/+15
*	remove files for old prototypes, they were confusing people	Matt Ettus	2010-05-13	10	-2076/+0
*	remove port which is no longer there	Matt Ettus	2010-05-11	1	-1/+1
*	Update config to all eight clock buffers to be used.	Johnathan Corgan	2010-03-29	1	-1/+1
*	Added timing constraint for Wishbone clock/dsp_clock skew	Johnathan Corgan	2010-03-29	1	-0/+2
*	Cut debug bus connection to etherenet MAC to make closing timing easier	Ian Buckley	2010-02-24	1	-2/+7
*	Manually assign clk_fpga to BUFG to improve timing	Johnathan Corgan	2010-02-23	1	-1/+5
*	Moved usrp2 fpga files into usrp2 subdir.	Josh Blum	2010-01-22	41	-0/+8275