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| * | | | | | use fifo19 not fifo18 in makefileMatt Ettus2010-06-061-1/+1
| * | | | | | Phil wants gpio #145Matt Ettus2010-06-032-4/+4
| * | | | | | use same version as usrp2-udp, so regs are same place in memory mapMatt Ettus2010-06-012-2/+2
| * | | | | | Merge branch 'ise12_exp' into u1eMatt Ettus2010-06-014-160/+1218
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| | * | | | | | zero out debug pins. helps timing a little bit.Matt Ettus2010-06-011-9/+11
| | * | | | | | Merge branch 'new_ramloader' into nocache_plus_newramloader, plus manual merg...Matt Ettus2010-05-282-30/+28
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| | | * | | | | | experimental mods to make ram loader fully synchronous. Based on IJB's workMatt Ettus2010-05-261-15/+14
| | * | | | | | | Merge branch 'master_nocache' into master_nocache_post_mergeMatt Ettus2010-05-284-15/+20
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| | | * | | | | | | change the debug pins, which makes it more reliable. This is unnerving.Matt Ettus2010-05-261-1/+2
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| | | * | | | | | fixes from IJB from 5/24. Basically connect unconnected wires.Matt Ettus2010-05-241-2/+3
| | | * | | | | | removes the icache and pipelines the readsMatt Ettus2010-05-202-5/+6
| * | | | | | | | connect the rx run lines so it doesn't get optimized outMatt Ettus2010-06-011-1/+4
| * | | | | | | | use DDR regs instead of a 2nd clockMatt Ettus2010-06-011-8/+46
| * | | | | | | | assign addresses for the settings regsMatt Ettus2010-06-011-5/+6
| * | | | | | | | vita49 tx and rx added in, all sample rates now at main system clock rate.Matt Ettus2010-06-014-107/+220
| * | | | | | | | Merge branch 'udp' into u1e_merge_with_udpMatt Ettus2010-05-272-8/+8
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| * \ \ \ \ \ \ \ \ Merge branch 'master' into u1e_merge_with_masterMatt Ettus2010-05-2712-2089/+20
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| * | | | | | | | | send bigger packets to reduce cpu loadMatt Ettus2010-05-201-2/+2
| * | | | | | | | | put over/underrun on debug bus, remove high order address bitsMatt Ettus2010-05-201-1/+2
| * | | | | | | | | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-201-4/+2
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| | * | | | | | | | | better debug pinsMatt Ettus2010-05-171-6/+4
| * | | | | | | | | | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-202-34/+24
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| * | | | | | | | | moved fifos into gpmc_async, reorganized top level a bit, added in crc packet...Matt Ettus2010-05-122-22/+43
| * | | | | | | | | Merge branch 'master' into u1eMatt Ettus2010-05-124-5/+16
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| * | | | | | | | | | switched passthru of cgen_sen_b to gpio127, made a note of it. No more safe_...Matt Ettus2010-05-108-561/+9
| * | | | | | | | | | proper signal level for 24 bit dataMatt Ettus2010-05-101-2/+7
| * | | | | | | | | | SPI passthru for programming clock gen chip on brand new boardsMatt Ettus2010-05-073-0/+391
| * | | | | | | | | | added DAC output pins, and a sine wave generator to test themMatt Ettus2010-05-043-18/+63
| * | | | | | | | | | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-042-0/+14
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| | * | | | | | | | | | add timing constraints. Just have main clock signal at 64 MHz for now.Matt Ettus2010-05-042-0/+14
| * | | | | | | | | | | changed commentMatt Ettus2010-05-041-1/+1
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| * | | | | | | | | | separate timed tx and rx instead of loopbackMatt Ettus2010-04-281-3/+51
| * | | | | | | | | | send bus error to debug pinsMatt Ettus2010-04-261-2/+4
| * | | | | | | | | | Pass previously unused GPIOs to debug pins to help debug interruptsMatt Ettus2010-04-243-16/+21
| * | | | | | | | | | find time_64bitMatt Ettus2010-04-201-0/+1
| * | | | | | | | | | added pps and time capabilityMatt Ettus2010-04-153-5/+21
| * | | | | | | | | | access frame length regs from wishboneMatt Ettus2010-04-151-6/+14
| * | | | | | | | | | async seems to work with packet lengths now. Still need to do wishbone regs ...Matt Ettus2010-04-151-3/+3
| * | | | | | | | | | async gpmc progressMatt Ettus2010-04-152-18/+20
| * | | | | | | | | | synchronous and asynchronous gpmc modelsMatt Ettus2010-04-151-1/+1
| * | | | | | | | | | handle all tri-state in the top level of gpmcMatt Ettus2010-04-151-0/+2
| * | | | | | | | | | more progress on synchronous interfaceMatt Ettus2010-04-141-0/+1
| * | | | | | | | | | renamed to async. Will be building a sync version for GPMC_CLKMatt Ettus2010-04-141-1/+1
| * | | | | | | | | | added in a loopback fifoMatt Ettus2010-04-141-4/+11
| * | | | | | | | | | minor changes to get it to synthesizeMatt Ettus2010-04-131-0/+3
| * | | | | | | | | | replaced ram interface with a fifo interface. still need to do rx sideMatt Ettus2010-04-121-39/+7
| * | | | | | | | | | added 16-bit wide atr controllerMatt Ettus2010-04-012-33/+44
| * | | | | | | | | | connect up the 16 bit spi coreMatt Ettus2010-03-262-5/+4
| * | | | | | | | | | connect 2 clock gen controls and 3 status pins to the wishbone so they can be...Matt Ettus2010-03-263-8/+26
| * | | | | | | | | | Merge branch 'udp' into u1eMatt Ettus2010-03-252-57/+179
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