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| * | | | | | | | | | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-202-34/+24
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| * | | | | | | | | moved fifos into gpmc_async, reorganized top level a bit, added in crc packet...Matt Ettus2010-05-122-22/+43
| * | | | | | | | | Merge branch 'master' into u1eMatt Ettus2010-05-124-5/+16
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| * | | | | | | | | | switched passthru of cgen_sen_b to gpio127, made a note of it. No more safe_...Matt Ettus2010-05-108-561/+9
| * | | | | | | | | | proper signal level for 24 bit dataMatt Ettus2010-05-101-2/+7
| * | | | | | | | | | SPI passthru for programming clock gen chip on brand new boardsMatt Ettus2010-05-073-0/+391
| * | | | | | | | | | added DAC output pins, and a sine wave generator to test themMatt Ettus2010-05-043-18/+63
| * | | | | | | | | | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-042-0/+14
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| | * | | | | | | | | | add timing constraints. Just have main clock signal at 64 MHz for now.Matt Ettus2010-05-042-0/+14
| * | | | | | | | | | | changed commentMatt Ettus2010-05-041-1/+1
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| * | | | | | | | | | separate timed tx and rx instead of loopbackMatt Ettus2010-04-281-3/+51
| * | | | | | | | | | send bus error to debug pinsMatt Ettus2010-04-261-2/+4
| * | | | | | | | | | Pass previously unused GPIOs to debug pins to help debug interruptsMatt Ettus2010-04-243-16/+21
| * | | | | | | | | | find time_64bitMatt Ettus2010-04-201-0/+1
| * | | | | | | | | | added pps and time capabilityMatt Ettus2010-04-153-5/+21
| * | | | | | | | | | access frame length regs from wishboneMatt Ettus2010-04-151-6/+14
| * | | | | | | | | | async seems to work with packet lengths now. Still need to do wishbone regs ...Matt Ettus2010-04-151-3/+3
| * | | | | | | | | | async gpmc progressMatt Ettus2010-04-152-18/+20
| * | | | | | | | | | synchronous and asynchronous gpmc modelsMatt Ettus2010-04-151-1/+1
| * | | | | | | | | | handle all tri-state in the top level of gpmcMatt Ettus2010-04-151-0/+2
| * | | | | | | | | | more progress on synchronous interfaceMatt Ettus2010-04-141-0/+1
| * | | | | | | | | | renamed to async. Will be building a sync version for GPMC_CLKMatt Ettus2010-04-141-1/+1
| * | | | | | | | | | added in a loopback fifoMatt Ettus2010-04-141-4/+11
| * | | | | | | | | | minor changes to get it to synthesizeMatt Ettus2010-04-131-0/+3
| * | | | | | | | | | replaced ram interface with a fifo interface. still need to do rx sideMatt Ettus2010-04-121-39/+7
| * | | | | | | | | | added 16-bit wide atr controllerMatt Ettus2010-04-012-33/+44
| * | | | | | | | | | connect up the 16 bit spi coreMatt Ettus2010-03-262-5/+4
| * | | | | | | | | | connect 2 clock gen controls and 3 status pins to the wishbone so they can be...Matt Ettus2010-03-263-8/+26
| * | | | | | | | | | Merge branch 'udp' into u1eMatt Ettus2010-03-252-57/+179
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| * | | | | | | | | | | connected spi pins, but the spi core still needs to be redone for 16 bit inte...Matt Ettus2010-03-253-40/+60
| * | | | | | | | | | | debug pinsMatt Ettus2010-02-251-2/+3
| * | | | | | | | | | | invert the pushbuttons since they are active lowMatt Ettus2010-02-251-2/+2
| * | | | | | | | | | | gpmc debug pinsMatt Ettus2010-02-251-3/+6
| * | | | | | | | | | | point to the new filesMatt Ettus2010-02-251-0/+2
| * | | | | | | | | | | loopback and testMatt Ettus2010-02-251-2/+32
| * | | | | | | | | | | First cut at passing data buffers around on GPMC busMatt Ettus2010-02-253-10/+24
| * | | | | | | | | | | first cut at making a bidirectional 2 port ram for the gpmc data interfaceMatt Ettus2010-02-231-0/+1
| * | | | | | | | | | | use our fancy new debug portsMatt Ettus2010-02-231-0/+3
| * | | | | | | | | | | settings bus with 16 bit wishbone interface, put on the main wishbone in u1eMatt Ettus2010-02-222-3/+14
| * | | | | | | | | | | GPIOs now on the wishbone interfaceMatt Ettus2010-02-224-37/+54
| * | | | | | | | | | | added gpio control to the wishboneMatt Ettus2010-02-182-11/+14
| * | | | | | | | | | | Added I2C, UART, debug pins, misc wishbone stuffMatt Ettus2010-02-183-48/+187
| * | | | | | | | | | | Fixed paths to help icarus find opencores and xilinx models. Added Xilinx gl...Matt Ettus2010-02-182-4/+7
| * | | | | | | | | | | wishbone bridge now with minimal functionality. Need to checkMatt Ettus2010-02-166-9/+49
| * | | | | | | | | | | first cut at gpmc <-> wb bridge, split u1e into core, top, and tbMatt Ettus2010-02-165-34/+93
| * | | | | | | | | | | copied over from safe_u1eMatt Ettus2010-02-164-0/+553
| * | | | | | | | | | | block ram interface to GPMCMatt Ettus2010-02-161-2/+6
| * | | | | | | | | | | basic read support for the GPMC, responds with 16'hBEEFMatt Ettus2010-02-161-2/+8
| * | | | | | | | | | | reorg pin defsMatt Ettus2010-02-141-94/+102
| * | | | | | | | | | | connect GPMC pins to debug busMatt Ettus2010-02-142-76/+94
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