summaryrefslogtreecommitdiffstats
path: root/usrp2/top
Commit message (Collapse)AuthorAgeFilesLines
* usrp: work on meeting timing constraintsJosh Blum2012-04-102-16/+16
| | | | | | * fifo ctrl register the vita ticks and use late * vita de/framer make nchans const since we dont change it * simplify readback muxes to minimal usage
* Merge branch 'master' into nextJosh Blum2012-04-093-2/+62
|\ | | | | | | | | | | Conflicts: usrp2/top/N2x0/u2plus_core.v usrp2/top/USRP2/u2_core.v
| * Merge branch 'maint'Josh Blum2012-04-094-5/+5
| |\
| | * vita: moved clear register to overlap with nchan registerJosh Blum2012-04-094-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the bug where setting the format clears the vita RX. This is only an issue when the noclear option is set by UHD, because the format register is always so, so it always clears. Note: noclear is there to support the backwards compat API (pre streamer). Now, numchans and clear overlap. This is ok because in the host code, clear and numchans are always used together. All timing meets on N2xx and USRP2.
| * | Merge branch 'maint'Josh Blum2012-04-021-1/+1
| |\|
| | * b100: fix slave fifo data xfer exit conditionJosh Blum2012-04-011-1/+1
| | | | | | | | | | | | | | | | | | | | | When exiting the read/write data state, when the transfer count maxes out/peaks, the fifo read/write signals were getting this condition the cycle after with the state change.
| * | fpga: extract usage summary from map fileJosh Blum2012-03-271-0/+60
| |/
* | Merge branch 'master' into nextJosh Blum2012-03-261-1/+1
|\|
| * b100: slave fifo fix for dst/src ready signalsJosh Blum2012-03-241-1/+1
| | | | | | | | | | | | | | | | Some of the changes my be overkill, but the idea is to be more careful about allowing FIFO IO to occur on transitions. The cal app was able to complete successfully.
* | fifo ctrl: parameterize having a proto headerJosh Blum2012-03-162-2/+2
| |
* | fifo ctrl: rename fifo ctrl module and add sid ack paramJosh Blum2012-03-162-28/+28
| |
* | fifo ctrl: minor fixes for spi core, swap time defineJosh Blum2012-03-163-3/+3
| |
* | fifo ctrl: simplified perfs, added spi clock idle phaseJosh Blum2012-03-163-320/+320
| |
* | fifo ctrl: minor fixes from last commitJosh Blum2012-03-163-366/+366
| |
* | fifo ctrl: spi core work, fifo ctrl perifs, usrp2 supportJosh Blum2012-03-163-351/+394
| | | | | | | | | | | | | | | | Continued work on simple spi core. Added peripherals input to fifo ctrl so perifs can backpressure fifo ctrl. Copied the implementation into usrp2 core.
* | spi: created simple spi core (sr based)Josh Blum2012-03-162-383/+397
| |
* | fifo_ctrl: switched to medfifo and separate result fifoJosh Blum2012-03-162-2/+2
| |
* | fifo_ctrl: clear settings reg, and flow controlJosh Blum2012-03-161-5/+10
| |
* | srb: created command queue, in and out state machinesJosh Blum2012-03-162-4/+2
| |
* | usrp2: first pass implementation of fifo controlJosh Blum2012-03-161-4/+38
|/
* fpga: force -include_global for custom sourcesJosh Blum2012-03-129-13/+16
| | | | | | | | ISE will not recognize custom sources as part of the hierarchy, and thus will not compile (unless its the first macro...). Remove custom sources from the source list, and specially add them with the -include_global option.
* fpga: fix custom defs in some top level makefilesJosh Blum2012-03-084-101/+3
|
* usrp2/nseries: added churn to meet timingJosh Blum2012-02-182-2/+4
| | | | | Added churn to readback mux on nseries to make n200r4 meet timing. Also added churn to usrp2 for parallelism, but assigned to zero.
* dsp rework: implement 64 bit ticks no secondsJosh Blum2012-02-064-4/+4
|
* B100: External FPGA reset from FX2 reuses fpga_cfg_cclk.Nick Foster2012-02-062-2/+6
|
* dsp rework: pass vita clears into dsp modules, unified fifo clearsJosh Blum2012-02-044-62/+51
|
* b100: timing constraints on GPIF linesJosh Blum2012-02-041-0/+9
|
* b100: connect all clears for gpifJosh Blum2012-02-031-1/+1
|
* dsp rework: rehash of the custom module stuff and readmeJosh Blum2012-02-0210-28/+61
|
* dsp rework: custom engine module for rx/tx vita chainJosh Blum2012-02-014-11/+21
|
* Merge branch 'slave_fifo_rebase' into dsp_reworkJosh Blum2012-02-013-20/+27
|\ | | | | | | | | Conflicts: usrp2/top/B100/u1plus_core.v
| * Fix missing B100 core_compile (poor Git hygeine)Nick Foster2012-01-231-0/+1
| |
| * b100: bumped fpga compat number for slave fifo modeJosh Blum2012-01-121-1/+1
| |
| * B100: moar buffering on TX for better performance in bidirectional applicationsNick Foster2012-01-121-2/+2
| |
| * Squashed slave mode changes onto master.Nick Foster2012-01-124-19/+25
| |
* | dsp rework: paramaterize post_engine_bufferingJosh Blum2012-02-012-0/+2
| |
* | dsp rework: added double buffer interface to vita txJosh Blum2012-01-284-4/+6
| |
* | dsp rework: moved scale and round into ddc chainJosh Blum2012-01-284-4/+4
| | | | | | | | 16to8 engine now performs only a clip from 16->8
* | dsp rework: top level fixes B100/E100Josh Blum2012-01-274-8/+9
| |
* | dsp rework: integrated custom dsp module shellsJosh Blum2012-01-2712-22/+46
| |
* | dsp rework: implemented dsp changes for other top levelsJosh Blum2012-01-274-100/+127
| | | | | | | | added user registers into each toplevel (not used yet)
* | dsp rework: renamed dsp signals for frontend IOJosh Blum2012-01-271-11/+11
| |
* | dsp rework: u2_core test implementationJosh Blum2012-01-264-12/+21
|/
* n2xx: updated bootloader to latest build in uhd masterJosh Blum2012-01-111-377/+377
|
* usrp2/nseries: restored clock/serdes readbackJosh Blum2011-11-232-4/+4
|
* need more umph out of correction valuesJosh Blum2011-11-104-4/+4
|
* remove unused irq to meet timingJosh Blum2011-11-052-21/+7
|
* convenience makefiles for top level projectsJosh Blum2011-11-052-0/+31
|
* increase vita rx fifosize to 10, like USRP2, make things workJosh Blum2011-11-042-4/+4
|
* u1e: fix unattached nets from copy-paste errorMatt Ettus2011-11-041-3/+3
|
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-17 20:51:01 +0000